JP5866757B2 - Integrated circuit device and electronic apparatus - Google Patents

Description

  The present invention relates to an integrated circuit device and an electronic apparatus including the integrated circuit device.

  An integrated circuit device that has a crystal oscillation circuit and generates a clock signal using an oscillation clock that is an oscillation output of the crystal oscillation circuit generally includes a power supply of an inverter circuit that constitutes the crystal oscillation circuit as a built-in regulator (voltage generation circuit, It is generated by a constant voltage generation circuit. However, when this type of integrated circuit device is mounted on a portable electronic device, the power source (for example, battery) is switched during normal operation and during backup, thereby reducing power consumption. For this reason, the system power supply voltage VDD in the integrated circuit device may suddenly drop, for example, from 5.5V to 1.6V. This causes a problem that the power supply voltage generated by the regulator is lowered and the oscillation clock generated by the crystal oscillation circuit becomes “missing”. As a result, the count number of the clock signal generated based on the oscillation clock becomes inaccurate, and when the integrated circuit device is used for timing, accurate timing is impossible.

  FIG. 14 shows a configuration example of a general regulator and a crystal oscillation circuit. FIG. 14 also shows a part of a subsequent circuit that shapes the oscillation clock of the crystal oscillation circuit.

  The regulator 10 includes a differential amplifier circuit and an output circuit, and generates an output voltage VOSC using the difference between the system power supply voltage VDD and the system ground voltage VSS as an operating voltage. In the differential amplifier circuit, a reference voltage Vref is supplied to the gate of one transistor constituting the input differential pair, and the voltage of a predetermined node of the output circuit is supplied to the gate of the other transistor constituting the input differential pair. Is applied. The output circuit includes an output control transistor TrA and includes a phase compensation capacitor C1 connected between the gate and drain of the output control transistor TrA. In order to reduce power consumption, the current value of the constant current source of the differential amplifier circuit is set to be quite small.

  The crystal oscillation circuit 20 includes a CMOS (Complementary Metal Oxide Semiconductor) inverter circuit. The CMOS inverter circuit operates using the difference between the output voltage VOSC and the system ground voltage VSS as an operating voltage. A crystal resonator 30 provided outside the integrated circuit device is connected to the input and output of the CMOS inverter circuit via connection terminals TM1 and TM2. The oscillation clock that is the output of the CMOS inverter circuit is supplied to the post-stage circuit 22. A stabilizing capacitor C2 is connected between the output voltage supply line to which the output voltage VOSC of the regulator 10 is supplied and the voltage supply line to which the system ground voltage VSS is supplied. The stabilization capacitor C2 is built in the integrated circuit device (for example, about 10 pF).

  In such an integrated circuit device, when the system power supply voltage VDD rapidly decreases, the potential is held by the phase compensation capacitor C1 and the stabilization capacitor C2 at the node PG that is the gate of the output control transistor TrA. At this time, since the system power supply voltage VDD decreases, the output control transistor TrA is turned off.

  In addition, a parasitic diode is formed between the drain and the substrate of the transistor TrB constituting the current mirror circuit of the differential amplifier circuit. Therefore, when the system power supply voltage VDD decreases and the difference from the voltage at the node PG exceeds the forward voltage of the parasitic diode, the potential at the node PG follows the system power supply voltage VDD via the parasitic diode and decreases. I will go. At this time, the output voltage VOSC decreases by a voltage determined by the voltage drop of the node PG and the capacitance ratio between the phase compensation capacitor C1 and the stabilization capacitor C2.

  Furthermore, since the crystal oscillation operation continues, the CMOS inverter circuit continues to consume current. Here, since the output control transistor TrA is turned off, the potential of the output voltage VOSC gradually decreases due to current consumption.

  When the voltage of the output voltage VOSC falls below a predetermined value in this way, the oscillation clock from the crystal oscillation circuit 20 cannot be propagated to the subsequent circuit 22, and the clock signal generated by the subsequent circuit 22 stops. As a result, when the integrated circuit device is used for timing, the timing is delayed in a period in which the clock signal is stopped, and accurate timing becomes impossible.

  At this time, if the time until the output control transistor TrA is turned on again can be shortened, a decrease in the output voltage VOSC can be suppressed. Therefore, it can be considered to increase the current value of the constant current flowing through the regulator 10, but the current value may be reduced as much as possible to reduce power consumption, and it is practical to increase this current value significantly. is not.

  An integrated circuit device that does not malfunction due to such a steep change in power supply voltage is disclosed in Patent Document 1, for example. This Patent Document 1 shortens the time for charging and discharging the charge of the phase compensation capacitor by increasing the constant current flowing through the transistors constituting the input differential pair of the regulator when the power supply voltage is suddenly lowered. A technique for maintaining the output at a constant constant voltage is disclosed.

JP 2009-3764 A

  However, in the technique disclosed in Patent Document 1, when the power supply voltage is suddenly lowered, a current necessary for the transistors constituting the input differential pair of the regulator is supplied. In order to reduce the power consumption, the regulator is designed on the assumption that the constant current of the regulator is reduced to a very small value and the current flowing through the transistors constituting the input differential pair is small. For this reason, a large current may not be allowed to flow through the transistors constituting the input differential pair due to a rapid drop in the power supply voltage, and the intended effect may not be obtained.

  In the technique disclosed in Patent Document 1, since the current flowing through the transistors constituting the input differential pair is switched, problems such as abnormal oscillation may occur, and a design that considers abnormal oscillation may be required.

  It is desired that the fluctuation of the voltage generated in the voltage generation circuit can be suppressed even when the power supply voltage of the voltage generation circuit such as the regulator is not limited to the regulator that supplies the power supply voltage to the crystal oscillation circuit as described above.

  The present invention has been made in view of the above technical problems. According to some aspects of the present invention, even when the power supply voltage of the voltage generation circuit is lowered, the integrated circuit device and the electronic apparatus capable of suppressing the fluctuation of the voltage generated by the voltage generation circuit without changing the configuration Etc. can be provided.

  (1) In the first aspect of the present invention, the integrated circuit device generates a third voltage using the difference between the first voltage and the second voltage as an operating voltage, and supplies the third voltage as an output voltage. A voltage generation circuit that supplies a voltage to the line; and a voltage fluctuation suppression circuit that draws current into the output voltage supply line or draws current from the output voltage supply line for a given period when the operating voltage drops. including.

  According to this aspect, when the operating voltage of the voltage generation circuit decreases, the current is supplied to or drawn into the output voltage supply line to which the third voltage generated by the voltage generation circuit is supplied for a given period. Thus, the third voltage drop can be prevented. Thus, for example, the third voltage can be prevented from being lowered with a simple configuration without changing the configuration of the voltage generation circuit whose design parameters are sufficiently adjusted to reduce power consumption. Therefore, it is possible to prevent malfunction of the subsequent circuit connected to the output voltage supply line due to the decrease in the third voltage.

  (2) In the integrated circuit device according to the second aspect of the present invention, in the first aspect, the voltage fluctuation suppressing circuit includes a first current source and a drain connected to one end of the first current source. A first transistor gate-controlled by a gate voltage corresponding to the first voltage, and the first current source and the first transistor are supplied with the first voltage. A detection current, which is connected between a voltage supply line and a second voltage supply line to which the second voltage is supplied, is obtained by subtracting the drain current of the first transistor from the current of the first current source. , Flow into the output voltage supply line, or draw from the output voltage supply line.

  According to this aspect, the detection current corresponding to the first voltage is caused to flow into the output voltage supply line or the output voltage supply line with a simple configuration including the first current source and the first transistor. Can be pulled in from. Therefore, it is possible to prevent the third voltage from being lowered with a very simple configuration, and it is possible to prevent the malfunction of the subsequent circuit connected to the output voltage supply line due to the third voltage drop. It becomes possible.

  (3) In the integrated circuit device according to the third aspect of the present invention, in the second aspect, the voltage fluctuation suppressing circuit includes a second current source having one end connected to the first voltage supply line; The second transistor having a drain connected to the other end of the second current source, a source connected to the second voltage supply line, and a gate connected to the gate of the first transistor; And a sensing capacitor inserted between the first voltage supply line and the gate of the first transistor.

  According to this aspect, the detection capacitor inserted between the first voltage supply line and the gate of the first transistor is provided, and the fluctuation of the first voltage is detected by the detection capacitor to obtain the first voltage. A corresponding detection current is generated. Thereby, the configuration of the integrated circuit device having the above effects can be further simplified.

  (4) In the integrated circuit device according to the fourth aspect of the present invention, in the third aspect, when the ratio of the current drive capability of the first transistor to the current drive capability of the second transistor is n, The current value of the first current source is smaller than n times the current value of the second current source.

  According to this aspect, for example, when the first voltage is a normal voltage, almost all of the current of the first current source is supplied to the first transistor, and when the first voltage fluctuates, the first transistor is supplied to the first transistor. It can be generated as a detection current corresponding to the first voltage without passing a current. Therefore, when the operating voltage decreases, it becomes possible to reliably generate a detection current corresponding to the first voltage.

  (5) In the integrated circuit device according to a fifth aspect of the present invention, in any one of the second to fourth aspects, the voltage fluctuation suppression circuit is connected to the second voltage supply line, A first current mirror circuit that mirrors a sense current; and a second current mirror circuit that is connected to the first voltage supply line and mirrors the current mirrored by the first current mirror circuit, The current mirrored by the second current mirror circuit is supplied to the output voltage supply line or drawn from the output voltage supply line.

  According to this aspect, in addition to the above effects, even when the detected current is very small, the current flowing into the output voltage supply line or the current drawn from the output voltage supply line can be realized with a desired current value. It becomes like this.

  (6) An integrated circuit device according to a sixth aspect of the present invention is provided between the first voltage supply line and the output voltage supply line in any one of the first to fifth aspects. Constant current source.

  According to this aspect, since the constant current source that constantly flows current into the output voltage supply line or constantly draws current from the output voltage supply line is provided, the third voltage fluctuation can be further suppressed. .

  (7) An integrated circuit device according to a seventh aspect of the present invention operates in any one of the first to sixth aspects, using a difference between the third voltage and the second voltage as an operating voltage. Including a load circuit.

  According to this aspect, since the load circuit that operates as the operating voltage using the third voltage generated by the voltage generating circuit is further included, the load circuit that does not malfunction even when the operating voltage of the voltage generating circuit decreases is provided. It becomes possible to provide an integrated circuit device having the same.

  (8) In an integrated circuit device according to an eighth aspect of the present invention, in the seventh aspect, the voltage generation circuit generates the third voltage, which is a constant voltage, and the load circuit has its input and It includes an inverter circuit that can be connected to an oscillator at the output.

  According to this aspect, since the inverter circuit capable of connecting the oscillation vibrator is employed as the load circuit, the oscillation clock is “toothless” even if the operating voltage of the voltage generation circuit that generates the power supply of the inverter circuit fluctuates. It becomes possible to provide an integrated circuit device that prevents the In addition, the design is facilitated with respect to variations in the flow of current or the pull-in time caused by the degree of fluctuation of the operating voltage, the consumption current of the inverter circuit, and the like, and the decrease in the third voltage can be suppressed under any conditions. become able to.

  (9) In a ninth aspect of the present invention, the integrated circuit device generates a third voltage that is a constant voltage using the difference between the first voltage and the second voltage as an operating voltage, and the third voltage Generating circuit for supplying an output voltage to the output voltage supply line, and an inverter circuit configured such that the difference between the third voltage and the second voltage is an operating voltage, and an oscillator can be connected to the input and output And a first voltage supply line to which the first voltage is supplied, and a constant current source provided between the output voltage supply line.

  According to this aspect, when the inverter circuit operates using the third voltage supplied from the voltage generation circuit as a power source, the current is always supplied to the output voltage supply line to which the third voltage is supplied or the output voltage supply is performed. Current can always be drawn from the wire. Accordingly, it is possible to provide an integrated circuit device that prevents the oscillation clock from becoming “missing” even when the operating voltage of the voltage generating circuit is lowered.

  (10) In the integrated circuit device according to a tenth aspect of the present invention, in the eighth aspect or the ninth aspect, the current of the constant current source is smaller than a minimum value of current consumption of the inverter circuit.

  According to this aspect, in addition to the above-described effect, it is possible to reliably prevent a situation in which the third voltage rises due to the amount of constant current being larger than the current consumption of the inverter circuit and a malfunction occurs. It becomes like this.

  (11) An integrated circuit device according to an eleventh aspect of the present invention is the integrated circuit device according to any one of the eighth aspect to the tenth aspect, wherein the frequency divider circuit divides the output of the inverter circuit, and the frequency divider circuit And a clock circuit that clocks based on the output.

  According to this aspect, it is possible to provide an integrated circuit device capable of measuring time without malfunction even when the operating voltage of the voltage generating circuit is lowered due to power supply switching or the like.

  (12) In a twelfth aspect of the present invention, the electronic device includes the integrated circuit device according to any one of the first to eleventh aspects.

  According to this aspect, there is provided an electronic apparatus to which an integrated circuit device that suppresses fluctuations in the voltage generated by the voltage generation circuit is applied without changing the configuration even when the power supply voltage of the voltage generation circuit decreases. Will be able to.

1 is a block diagram of a configuration example of an integrated circuit device according to an embodiment of the present invention. 2A and 2B are diagrams illustrating an example of a main configuration of the voltage fluctuation suppression circuit in FIG. 1 is a circuit diagram of a configuration example of a voltage fluctuation suppressing circuit according to a first embodiment of the present invention. FIG. 4 is a circuit diagram of a configuration example of an integrated circuit device to which the voltage variation suppression circuit of FIG. 3 is applied. The circuit diagram of the structural example of the integrated circuit device to which the voltage fluctuation suppression circuit in the 2nd Embodiment of this invention was applied. The circuit diagram of the structural example of the voltage fluctuation suppression circuit in the 3rd Embodiment of this invention. The circuit diagram of the structural example of the voltage fluctuation suppression circuit in the 4th Embodiment of this invention. FIG. 8 is a circuit diagram of a configuration example of an integrated circuit device to which the voltage variation suppression circuit of FIG. 7 is applied. The circuit diagram of the structural example of the voltage fluctuation suppression circuit in the 5th Embodiment of this invention. The circuit diagram of the structural example of the voltage fluctuation suppression circuit in the 6th Embodiment of this invention. The block diagram of the structural example of the integrated circuit device for timepieces concerning this invention. 1 is a block diagram of a hardware configuration example of an electronic device according to the present invention. 13A and 13B are perspective views of a configuration example of the electronic device in FIG. The figure which shows the structural example of a general regulator and a crystal oscillation circuit.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, all of the configurations described below are not necessarily indispensable configuration requirements for solving the problems of the present invention.

  FIG. 1 is a block diagram showing a configuration example of an integrated circuit device according to an embodiment of the present invention.

  The integrated circuit device 100 includes a reference voltage generation circuit 110, a voltage generation circuit 120, a voltage fluctuation suppression circuit 130, and a crystal oscillation circuit 140 as a load circuit. An oscillation clock CLKO which is an oscillation output of the crystal oscillation circuit 140 is supplied to an operation circuit (not shown) (for example, a frequency dividing circuit). In the integrated circuit device 100, the first voltage V1 is supplied to each of the above-described parts via the first voltage supply line PL1, and the second voltage V2 is supplied to the above-described parts via the second voltage supply line PL2. Are supplied to each part of The first voltage V1 and the second voltage V2 are generated outside or inside the integrated circuit device 100.

  The reference voltage generation circuit 110 is connected to the first voltage supply line PL1 and the second voltage supply line PL2 (more specifically, electrically connected; the same applies hereinafter), for example, a reference voltage Vref that is a constant voltage. Is generated. The reference voltage generation circuit 110 may be provided outside the integrated circuit device 100. The voltage generation circuit 120 generates a third voltage V3 using the difference between the first voltage V1 and the second voltage V2 as an operating voltage, and supplies the third voltage V3 to the output voltage supply line PLO. More specifically, the voltage generation circuit 120 generates a third voltage V3, which is a constant voltage, for example, based on the reference voltage Vref. When the operating voltage of the voltage generation circuit 120 changes due to the fluctuation of the first voltage V1 (or the second voltage V2), the voltage fluctuation suppression circuit 130 is a current to the output voltage supply line PLO for a given period. Or the current is drawn from the output voltage supply line PLO. By doing so, the voltage fluctuation suppression circuit 130 can suppress the fluctuation of the third voltage V3 without changing the configuration or control of the voltage generation circuit 120.

  The crystal oscillator circuit 140 is connected to a crystal resonator (oscillator resonator in a broad sense) 150 provided outside via a connection terminal (not shown) of the integrated circuit device 100. The crystal oscillation circuit 140 performs a crystal oscillation operation using the difference between the third voltage V3 and the second voltage V2 as an operation voltage, and outputs an oscillation clock CLKO.

  2A and 2B show an example of a main part of the voltage fluctuation suppression circuit 130 in FIG. FIG. 2A shows an example of a main part of the voltage fluctuation suppressing circuit 130 in the case where an N-type (first conductivity type) MOS transistor is used. FIG. 2B shows an example of a main part of the voltage fluctuation suppressing circuit 130 in the case where a P-type (second conductivity type) MOS transistor is used.

For example, as shown in FIG. 2A, the voltage fluctuation suppression circuit 130 includes a first current source CS and a first transistor Tra that is an N-type MOS transistor. One end of the first current source CS is connected to the first voltage supply line PL1, and the other end is connected to the drain of the first transistor Tra. The source of the first transistor Tra is connected to the second voltage supply line PL2. A gate voltage V _G1 corresponding to the first voltage V1 is supplied to the gate of the first transistor Tra, and the first transistor Tra is gate-controlled based on the gate voltage V _G1 . The first voltage V1 is a voltage on the higher potential side than the second voltage V2. Therefore, the voltage fluctuation suppression circuit 130, a sense current Idr obtained by subtracting the drain current Id1 of the first transistor Tra of the current _{I 0} of the first current source CS, can flow into the output voltage supply line PLO. This means that the voltage fluctuation suppression circuit 130 supplies a positive current to the output voltage supply line PLO.

Further, for example, as shown in FIG. 2B, the voltage fluctuation suppressing circuit 130 includes a first current source CS and a first transistor Trb which is a P-type MOS transistor. One end of the first current source CS is connected to the first voltage supply line PL1, and the other end is connected to the drain of the first transistor Trb. The source of the first transistor Trb is connected to the second voltage supply line PL2. A gate voltage V _G2 corresponding to the first voltage V1 is supplied to the gate of the first transistor Trb, and the first transistor Trb is gate-controlled based on the gate voltage V _G2 . The second voltage V2 is a higher potential side voltage than the first voltage V1. Therefore, the voltage fluctuation suppression circuit 130, a sense current Idr obtained by subtracting the drain current Id2 of the first transistor Trb of the current _{I 0} of the first current source CS, a predetermined period of time, be drawn from the output voltage supply line PLO Can do. This means that the voltage fluctuation suppressing circuit 130 supplies a negative current to the output voltage supply line PLO.

That is, the voltage fluctuation suppression circuit 130 includes a first current source CS, a first transistor whose drain is connected to one end of the first current source CS, and gate-controlled by a gate voltage corresponding to the first voltage V1. Tra (Trb) can be included. The first current source CS and the first transistor Tra (Trb) are connected between the first voltage supply line PL1 and the second voltage supply line PL2. Then, the detection current Idr obtained by subtracting the drain current Id1 (Id2) of the current _{I 0} of the first current source CS first transistor Tra (Trb), the predetermined time period, cast the output voltage supply line PLO or output Pull in from the voltage supply line PLO.

  Thereby, in the integrated circuit device 100, even when the operating voltage of the voltage generation circuit 120 varies, the variation of the third voltage V3 can be suppressed. As a result, the oscillation clock generated by the oscillation operation of the crystal oscillation circuit 140 can continue to be propagated to the subsequent stage, and the oscillation clock can be prevented from becoming “missing”. At this time, the voltage generation circuit 120 can adopt a configuration with the design parameters adjusted to operate with low power consumption without changing the configuration.

Hereinafter, a specific configuration example will be described.
[First Embodiment]
FIG. 3 shows a circuit diagram of a configuration example of the voltage fluctuation suppressing circuit in the first embodiment of the present invention. In FIG. 3, it is assumed that the first voltage V1 is the system power supply voltage VDD, the second voltage V2 is the system ground voltage VSS lower than the system power supply voltage VDD, and the third voltage V3 is the output voltage VOSC. In FIG. 3, the same parts as those in FIG.

  In the integrated circuit device 100 of FIG. 1, the voltage fluctuation suppressing circuit 130 a in the first embodiment can be applied instead of the voltage fluctuation suppressing circuit 130. The voltage fluctuation suppressing circuit 130a includes current sources CS1 and CS2, N-type MOS transistors Tr1 to Tr4, P-type MOS transistors Tr5 and Tr6, and a detection capacitor Cdet. The current source CS2 corresponds to the first current source CS in FIG. 2A, and the MOS transistor Tr2 corresponds to the first transistor Tra in FIG.

  The current source CS1 (second current source) has one end connected to the first voltage supply line PL1 and the other end connected to the drain and gate of the MOS transistor Tr1 (second transistor). The current source CS1 flows a constant current I1. The source of the MOS transistor Tr1 is connected to the second voltage supply line PL2. A detection capacitor Cdet is inserted between the gate of the MOS transistor Tr1 (Tr2) and the first voltage supply line PL1.

  One end of the current source CS2 (first current source) is connected to the first voltage supply line PL1, and the other end is connected to the drain of the MOS transistor Tr2 (first transistor). The current source CS2 flows a constant current I2. The MOS transistor Tr2 has a source connected to the second voltage supply line PL2 and a gate connected to the gate of the MOS transistor Tr1.

  The MOS transistors Tr3 and Tr4 constitute a first current mirror circuit connected to the second voltage supply line PL2. That is, the MOS transistor Tr3 has a gate and a drain connected to the drain of the MOS transistor Tr2, and a source connected to the second voltage supply line PL2. The MOS transistor Tr4 has a source connected to the second voltage supply line PL2 and a gate connected to the gate of the MOS transistor Tr3. Therefore, the first current mirror circuit mirrors the detection current generated as shown in FIG. 2A by the current source CS2 and the MOS transistor Tr2, and allows the drain current of the MOS transistor Tr4 to flow.

  The MOS transistors Tr5 and Tr6 constitute a second current mirror circuit connected to the first voltage supply line PL1. That is, the MOS transistor Tr5 has a gate and a drain connected to the drain of the MOS transistor Tr4 and a source connected to the first voltage supply line PL1. The source of the MOS transistor Tr6 is connected to the first voltage supply line PL1, and the gate is connected to the gate of the MOS transistor Tr5. Accordingly, the drain current of the MOS transistor Tr5 (the current mirrored by the first current mirror circuit) can be mirrored to flow as the drain current of the MOS transistor Tr6, and the current can be flowed into the output voltage supply line PLO.

  In the configuration shown in FIG. 3, the ratio of the current drive capability of the MOS transistor Tr2 to the current drive capability of the MOS transistor Tr1 (second transistor) is n. For example, when the channel width of the MOS transistor Tr1 is W1 and the channel length is L1, the current driving capability β1 of the MOS transistor Tr1 can be expressed as (k × W1 / L1) (k is a constant, the same applies hereinafter). Similarly, when the channel width of the MOS transistor Tr2 is W2 and the channel length is L2, the current driving capability β2 of the MOS transistor Tr2 can be expressed as (k × W2 / L2). At this time, it can be expressed as n = (β2 / β1). In FIG. 3, n is assumed to be 100, for example.

  In a steady state where the system power supply voltage VDD is stable, a current much larger than the constant current I2 of the current source CS2 flows through the MOS transistor Tr2 (for example, 100 times). Further, it is assumed that the current value of the current source CS2 (first current source) is smaller than n times the current value of the current source CS1 (second current source). As a result, almost all of the current I2 of the current source CS2 can flow through the MOS transistor Tr2, as will be described later.

  Here, when the system power supply voltage VDD is stable, almost all the current I2 of the current source CS2 flows to the MOS transistor Tr2, and almost no current flows to the MOS transistor Tr3. Therefore, the detection current Idr is almost 0, and almost no current flows through the MOS transistors Tr4 to Tr6 that mirror the detection current Idr. Therefore, when the system power supply voltage VDD is stable, almost no current is supplied to the output voltage supply line PLO.

  On the other hand, when the system power supply voltage VDD rapidly decreases and the operating voltage, which is the difference between the system power supply voltage VDD and the system ground voltage VSS, decreases, the detection capacitor Cdet causes the gate potentials of the MOS transistors Tr1 and Tr2 ( The potential of the node N1 is decreased. Thereby, the MOS transistors Tr1 and Tr2 are turned off. As a result, the current I2 of the current source CS2 flows through the MOS transistor Tr3 as the detection current Idr. When a current flows through the MOS transistor Tr3, it operates as a current mirror circuit, and a current flows through the MOS transistors Tr4, Tr5, Tr6. Therefore, a current corresponding to the detection current Idr can be supplied to the output voltage supply line PLO.

  When the system power supply voltage VDD is stabilized after the system power supply voltage VDD suddenly decreases in this way, the gate potentials of the MOS transistors Tr1 and Tr2 are increased by the current I1 from the current source CS1. When the gate potentials of the MOS transistors Tr1 and Tr2 rise to a predetermined steady potential, the MOS transistors Tr1 and Tr2 are turned on, and the current supply to the output voltage supply line PLO is made as in the state where the system power supply voltage VDD is stable. Stop. In other words, when the system power supply voltage VDD rapidly decreases (when the operating voltage rapidly decreases), the voltage fluctuation control circuit 130a supplies current to the output voltage supply line PLO only for a certain period thereafter.

(Design example)
Assuming that the ratio of the current drive capability of the MOS transistor Tr4 (β4 = k × W4 / L4) to the current drive capability (β3 = k × W3 / L3) of the MOS transistor Tr3 is A, similarly to the above, A = (β4 / β3). When the ratio of the current drive capability of the MOS transistor Tr6 (β6 = k × W6 / L6) to the current drive capability (β5 = k × W5 / L5) of the MOS transistor Tr5 is B, B = (β6 / β5). Become. At this time, the current supplied to the output voltage supply line PLO is (I2 × A × B). Therefore, if (A × B) is increased, the current value of the current I2 of the current source CS2 can be reduced and a large current can be supplied to the output voltage supply line PLO. Note that the current consumption increases due to the steady currents from the current sources CS1 and CS2, but when the voltage generation circuit 120 is configured by a regulator, only a small amount of current is required compared to increasing the constant current of the regulator.

  For example, W1 = 2 μm (micrometer) for MOS transistor Tr1, L1 = 20 μm, W2 = 20 μm, L2 = 2 μm for MOS transistor Tr2, and W3 = 2 μm and L3 = 8 μm for MOS transistor Tr3. For the MOS transistor Tr4, W4 = 8 μm, L4 = 8 μm, for the MOS transistor Tr5, W5 = 2 μm, L5 = 2 μm, and for the MOS transistor Tr6, W6 = 40 μm and L6 = 2 μm. If the detection capacitance Cdet is 3 pF, the current I1 of the current source CS1 can be 5 nA, and the current of the current source CS2 can be 5 nA.

  Further, by making A and B substantially equal to each other, the design is facilitated, and the area of the entire voltage fluctuation suppressing circuit 130a can be further minimized.

  FIG. 4 shows a circuit diagram of a configuration example of an integrated circuit device to which the voltage fluctuation suppressing circuit 130a of FIG. 3 is applied. In FIG. 4, it is assumed that a regulator is employed as the voltage generation circuit 120. In FIG. 4, the same parts as those in FIG. 1 or FIG.

  The integrated circuit device 100a includes a reference voltage generation circuit 110, a voltage generation circuit 120, a voltage fluctuation suppression circuit 130a, a crystal oscillation circuit 140, and a subsequent circuit 160 as an operation circuit.

  The reference voltage generation circuit 110 includes a current source CS3 and an N-type MOS transistor Tr10. The current source CS3 has one end connected to the first voltage supply line PL1 and the other end connected to the gate and drain of the MOS transistor Tr10. The source of the MOS transistor Tr10 is connected to the second voltage supply line PL2. In such a configuration, the drain voltage (gate voltage) of the MOS transistor Tr10 becomes the reference voltage Vref.

  Voltage generation circuit 120 includes a differential amplifier circuit and an output circuit. The differential amplifier circuit is connected between N-type MOS transistors Tr11 and Tr12 that constitute an input differential pair and whose drains are connected, and between the sources of the MOS transistors Tr11 and Tr12 and the second voltage supply line PL2. Current source CS4. The differential amplifier circuit includes P-type MOS transistors Tr13 and Tr14 that constitute a current mirror circuit and whose gates and sources are connected to each other. The drain of the MOS transistor Tr13 is connected to the drain of the MOS transistor Tr11. The gate and drain of the MOS transistor Tr14 are connected to the drain of the MOS transistor Tr12. The output circuit includes a current source CS5, P-type MOS transistors Tr15 and Tr16, and a phase compensation capacitor C1. The current source CS5 has one end connected to the second voltage supply line PL2 and the other end connected to the gate and drain of the MOS transistor Tr16. The source of the MOS transistor Tr16 is connected to the drain of the MOS transistor Tr15. The source of the MOS transistor Tr15 is connected to the first voltage supply line PL1. The phase compensation capacitor C1 is connected between the gate and drain of the MOS transistor Tr15. In such a configuration, the gate of the MOS transistor Tr11 is connected to the drain of the MOS transistor Tr10. The gate of the MOS transistor Tr12 is connected to the gate and drain of the MOS transistor Tr16. In such a configuration, the drain voltage of the MOS transistor Tr15 becomes the output voltage VOSC.

  In FIG. 4, a configuration in which the stabilization capacitor C2 is omitted is employed. However, the stabilization capacitor C2 may be connected between the output voltage supply line PLO and the second voltage supply line PL2. .

  The crystal oscillation circuit 140 is a CMOS inverter circuit composed of a P-type MOS transistor Tr20 and an N-type MOS transistor Tr21, and operates using the difference between the output voltage VOSC and the system ground voltage VSS as an operating voltage. The gate of the MOS transistor Tr20 and the gate of the MOS transistor Tr21 are connected to the connection terminal TMa of the integrated circuit device 100. The drain of the MOS transistor Tr20 and the drain of the MOS transistor Tr21 are connected to the connection terminal TMb of the integrated circuit device 100 (specifically, connected via a drain resistor). A crystal resonator 150 is provided outside the integrated circuit device 100, and the crystal resonator 150 is connected between the input and output of the CMOS inverter circuit constituting the crystal oscillation circuit 140 via the connection terminals TMa and TMb. Configured to be possible.

Incidentally, although not shown in FIG. 4, the crystal oscillator circuit 140 may further include a feedback resistor Rf, drain resistance _{R D,} the gate capacitance _{C G,} the drain capacitance _{C D.} The feedback resistor Rf is connected between the input and output of the CMOS inverter circuit. The drain resistor _RD is inserted in series between the output of the CMOS inverter circuit and the connection terminal TMb. The gate capacitance C _G is inserted between the connection terminal TMa and the system ground voltage VSS to which one end of the crystal oscillator 150 is connected. Drain capacitance C _D is inserted between the connection terminal TMb and the system ground voltage VSS to the other end of the crystal oscillator 150 is connected. By providing the gate capacitance C _G and the drain capacitance C _D, satisfies the oscillation conditions, so that it is possible to adjust the oscillation frequency.

  The post-stage circuit 160 (an operation circuit in a broad sense) includes at least an inverter circuit that buffers the oscillation clock CLKO from the crystal oscillation circuit 140. This inverter circuit includes a P-type MOS transistor Tr30 and an N-type MOS transistor Tr31, and operates using the difference between the output voltage VOSC and the system ground voltage VSS as an operating voltage.

  In FIG. 4, in the reference voltage generation circuit 110, a constant current from the current source CS3 flows between the drain and source of the MOS transistor Tr10, and the reference voltage Vref is applied to the gate of one MOS transistor Tr11 constituting the input differential pair. Is supplied. The drain of the MOS transistor Tr16 is connected to the gate of the other MOS transistor Tr12 constituting the input differential pair. A constant current from the current source CS5 flows between the drain and source of the MOS transistor Tr16, and a feedback voltage lower than the output voltage VOSC by a constant voltage is supplied to the gate of the MOS transistor Tr12. As a result, the differential amplifier circuit is controlled so that the reference voltage Vref and the feedback voltage are equal, and the output voltage VOSC becomes a constant voltage via the MOS transistor Tr16 in which a constant current flows. By doing so, the output voltage VOSC becomes a constant voltage corresponding to the sum of the potential difference generated in the MOS transistor Tr10 and the potential difference generated in the MOS transistor Tr16 with respect to the system ground voltage VSS.

  Here, when the system power supply voltage VDD decreases, the voltage fluctuation suppressing circuit 130a can supply current to the output voltage supply line PLO even if the MOS transistor Tr15 tries to turn off. Further, even if the operation of the voltage generation circuit 120 is stopped due to a decrease in the system power supply voltage VDD, the voltage variation suppression circuit 130a can supply a current to the output voltage supply line PLO. Therefore, it is possible to suppress a drop in the output voltage VOSC due to the voltage drop of the node PG and the stop of the voltage generation circuit 120 due to a drop in the system power supply voltage VDD.

  Furthermore, even when the system power supply voltage VDD decreases, fluctuations in the output voltage VOSC are suppressed without changing the configuration of the regulator that constitutes the voltage generation circuit 120 whose design parameters are sufficiently adjusted for low power consumption. be able to. Therefore, even when the system power supply voltage VDD decreases, the design of an integrated circuit device capable of suppressing the fluctuation of the output voltage VOSC without causing unintentional oscillation and reducing power consumption can be greatly simplified.

[Second Embodiment]
In the first embodiment, the example in which the voltage fluctuation suppression circuit 130a supplies current to the output voltage supply line with the configuration shown in FIG. 3 has been described, but the present invention is not limited to this.

  FIG. 5 shows a circuit diagram of a configuration example of an integrated circuit device to which the voltage fluctuation suppressing circuit according to the second embodiment of the present invention is applied. In FIG. 5, it is assumed that the first voltage V1 is the system power supply voltage VDD, the second voltage V2 is the system ground voltage VSS lower than the system power supply voltage VDD, and the third voltage V3 is the output voltage VOSC. In FIG. 5, the same parts as those in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The difference between the integrated circuit device 100b in the second embodiment and the integrated circuit device 100a in the first embodiment is the configuration of the voltage fluctuation suppressing circuit. The voltage fluctuation suppressing circuit 130b included in the integrated circuit device 100b includes a constant current source CS6. The constant current source CS6 is connected between the first voltage supply line PL1 and the output voltage supply line PLO. That is, the integrated circuit device 100b includes a voltage generation circuit 120 (constant voltage generation circuit), a CMOS inverter circuit, and a constant current source CS6. The voltage generation circuit 120 generates a third voltage, which is a constant voltage, using the difference between the first voltage and the second voltage as an operating voltage, and supplies the third voltage to the output voltage supply line. The CMOS inverter circuit is configured such that a crystal resonator can be connected to an input and an output of the difference between the third voltage and the second voltage as an operating voltage.

  In such a configuration, in the integrated circuit device 100b, even when the system power supply voltage VDD decreases, the constant current source CS6 can flow a constant current into the output voltage supply line PLO, so that a decrease in the output voltage OSC is suppressed. be able to.

  Note that when the constant current supplied by the constant current source CS6 is larger than the consumption current of the CMOS inverter circuit constituting the crystal oscillation circuit 140, the output voltage VOSC rises higher than the desired voltage. For this reason, since the current consumption of the CMOS inverter circuit varies depending on conditions, the constant current supplied by the constant current source CS6 needs to be smaller than the minimum value of the current consumption of the CMOS inverter circuit.

[Third Embodiment]
In the first embodiment, the example in which the voltage fluctuation suppression circuit 130a supplies current to the output voltage supply line with the configuration shown in FIG. 3 has been described.

  FIG. 6 shows a circuit diagram of a configuration example of a voltage fluctuation suppressing circuit according to the third embodiment of the present invention. In FIG. 6, it is assumed that the first voltage V1 is the system power supply voltage VDD, the second voltage V2 is the system ground voltage VSS lower than the system power supply voltage VDD, and the third voltage V3 is the output voltage VOSC. In FIG. 6, the same parts as those in FIG. 3 or FIG.

  In the integrated circuit device 100 of FIG. 1, the voltage fluctuation suppressing circuit 130 c in the third embodiment can be applied instead of the voltage fluctuation suppressing circuit 130. In addition to the configuration of the voltage fluctuation suppression circuit 130a of FIG. 3, the voltage fluctuation suppression circuit 130c connects the constant current source CS6 of FIG. 5 between the first voltage supply line PL1 and the output voltage supply line PLO. .

  In such a configuration, when the system power supply voltage VDD is stable, almost all the current I2 of the current source CS2 flows through the MOS transistor Tr2, and almost no current flows through the MOS transistor Tr3. Therefore, the detection current Idr is almost 0, and almost no current flows through the MOS transistors Tr4 to Tr6 that mirror the detection current Idr. Therefore, when the system power supply voltage VDD is stable, the current from the constant current source CS6 is supplied to the output voltage supply line PLO.

  On the other hand, when the system power supply voltage VDD rapidly decreases and the operating voltage, which is the difference between the system power supply voltage VDD and the system ground voltage VSS, decreases, the detection capacitor Cdet causes the gate potential ( The potential of the node N1 is decreased. Thereby, the MOS transistors Tr1 and Tr2 are turned off. As a result, the current I2 of the current source CS2 flows as the detection current Idr to the MOS transistor Tr3, and the current flows to the MOS transistors Tr4, Tr5, Tr6. Therefore, a current corresponding to the detected current Idr can be supplied to the output voltage supply line PLO in which a constant current flows from the constant current source CS6.

Thus, the combined use of the configuration shown in FIG. 3 and the constant current source CS6 can suppress a decrease in the output voltage VOSC. According to the configuration shown in FIG. 3, the amount of current supplied to the output voltage supply line PLO can be controlled relatively accurately, but the time for supplying the current depends on the degree of fluctuation of the system power supply voltage VDD. It varies. In addition, the time for the voltage generation circuit 120 operating as a regulator to return to normal operation varies, and it is difficult to accurately control the time for supplying current. Furthermore, the current consumption of the CMOS inverter circuit constituting the crystal oscillation circuit varies depending on conditions. For example, when the gate capacitance C _G and the drain capacitance _CD are small, the current consumption is small. Therefore, if a current larger than the current consumption of the CMOS inverter circuit is supplied to the output voltage supply line PLO, the current supply time becomes too long, the output voltage VOSC becomes higher than the target voltage, and the oscillation clock is also stopped. There are things to do. In contrast, the combined use of the configuration shown in FIG. 3 and the constant current source CS6 facilitates the design for the above-described variation, and can suppress the decrease in the output voltage VOSC under any conditions. become.

[Fourth Embodiment]
In the first to third embodiments, the example of supplying current to the output voltage supply line PLO (example of supplying a sexual current) has been described. However, the present invention is not limited to this.

  FIG. 7 shows a circuit diagram of a configuration example of a voltage fluctuation suppressing circuit according to the fourth embodiment of the present invention. In FIG. 7, it is assumed that the first voltage V1 is the system ground voltage VSS, the second voltage V2 is the system power supply voltage VDD, and the third voltage V3 is the output voltage VOSC. Accordingly, in FIG. 7, the voltage supply line to which the system power supply voltage VDD is supplied is referred to as the second voltage supply line PL2, and the voltage supply line to which the system ground voltage VSS is supplied is illustrated as the first voltage supply line PL1. Yes. In FIG. 7, the same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The configuration of FIG. 7 has a configuration in which the N-type MOS transistor in the configuration of FIG. 3 is replaced with a P-type MOS transistor, and the P-type MOS transistor is replaced with an N-type MOS transistor. Accordingly, the arrangement of the current sources in the configuration of FIG. 3 is also changed, and the corresponding current sources are arranged as shown in FIG.

  The integrated circuit device 100 of FIG. 1 can apply the voltage fluctuation suppressing circuit 130d in the fourth embodiment in place of the voltage fluctuation suppressing circuit 130. The voltage fluctuation suppressing circuit 130d includes current sources CS100 and CS101, P-type MOS transistors Tr100 to Tr103, N-type MOS transistors Tr104 and Tr105, and a detection capacitor Cdet1. The current source CS101 corresponds to the first current source CS in FIG. 2B, and the MOS transistor Tr101 corresponds to the first transistor Trb in FIG.

  One end of the current source CS100 (second current source) is connected to the first voltage supply line PL1, and the other end is connected to the drain and gate of the MOS transistor Tr100 (second transistor). The current source CS100 passes a constant current I10. The source of the MOS transistor Tr100 is connected to the second voltage supply line PL2. A detection capacitor Cdet1 is inserted between the gate of the MOS transistor Tr100 (Tr101) and the first voltage supply line PL1.

  One end of the current source CS101 (first current source) is connected to the first voltage supply line PL1, and the other end is connected to the drain of the MOS transistor Tr101 (first transistor). The current source CS101 passes a constant current I20. The source of the MOS transistor Tr101 is connected to the second voltage supply line PL2, and the gate is connected to the gate of the MOS transistor Tr100.

  The MOS transistors Tr102 and Tr103 constitute a first current mirror circuit connected to the second voltage supply line PL2. That is, the gate and drain of the MOS transistor Tr102 are connected to the drain of the MOS transistor Tr101, and the source is connected to the second voltage supply line PL2. The source of the MOS transistor Tr103 is connected to the second voltage supply line PL2, and the gate is connected to the gate of the MOS transistor Tr102. Therefore, the first current mirror circuit mirrors the detection current generated by the current source CS101 and the MOS transistor Tr101 as shown in FIG. 2B, and allows the drain current of the MOS transistor Tr103 to flow.

  The MOS transistors Tr104 and Tr105 constitute a second current mirror circuit connected to the first voltage supply line PL1. That is, the gate and drain of the MOS transistor Tr104 are connected to the drain of the MOS transistor Tr103, and the source is connected to the first voltage supply line PL1. The source of the MOS transistor Tr105 is connected to the first voltage supply line PL1, and the gate is connected to the gate of the MOS transistor Tr104. Accordingly, the drain current of the MOS transistor Tr104 (the current mirrored by the first current mirror circuit) can be mirrored to flow as the drain current of the MOS transistor Tr105, and the current can be drawn from the output voltage supply line PLO.

  In the configuration of FIG. 7, the ratio of the current drive capability of the MOS transistor Tr101 to the current drive capability of the MOS transistor Tr100 (second transistor) is n. For example, when the channel width of the MOS transistor Tr100 is W1 and the channel length is L1, the current driving capability β1 can be expressed as (k × W1 / L1) (k is a constant, the same applies hereinafter). Similarly, when the channel width of the MOS transistor Tr101 is W2 and the channel length is L2, the current driving capability β2 can be expressed as (k × W2 / L2). At this time, it can be expressed as n = (β2 / β1). In FIG. 7, n is assumed to be 100, for example.

  In a steady state where the system power supply voltage VDD is stable with respect to the system ground voltage VSS, a current much larger than the constant current I20 of the current source CS101 flows through the MOS transistor Tr101 (for example, 100 times). Furthermore, the current value of the current source CS101 (first current source) is assumed to be smaller than n times the current value of the current source CS100 (second current source). Thereby, almost all of the current I20 of the current source CS101 can be passed through the MOS transistor Tr101.

  Therefore, when the system power supply voltage VDD is stable with respect to the system ground voltage VSS, almost all the current I20 of the current source CS101 flows to the MOS transistor Tr101, and almost no current flows to the MOS transistor Tr102. Therefore, the detection current Idr1 is almost 0, and almost no current flows through the MOS transistors Tr103 to Tr105 that mirror the detection current Idr1. Therefore, when the system power supply voltage VDD is stable with respect to the system ground voltage VSS, almost no current is drawn from the output voltage supply line PLO.

  On the other hand, when the system power supply voltage VDD rapidly decreases with the system ground voltage VSS as a reference and the operating voltage decreases, the MOS transistors Tr100 and Tr101 are turned off by the detection capacitor Cdet1. As a result, the current I20 of the current source CS101 flows through the MOS transistor Tr102 as the detection current Idr1. When a current flows through the MOS transistor Tr102, it operates as a current mirror circuit, and a current flows through the MOS transistors Tr103 to Tr105. Therefore, a current corresponding to the detection current Idr1 can be drawn from the output voltage supply line PLO.

  After the system power supply voltage VDD suddenly decreases with the system ground voltage VSS as a reference in this way and the system power supply voltage VDD becomes stable, the MOS transistors Tr100 and Tr101 are turned on by the current I10 from the current source CS100. As a result, similarly to the state where the system power supply voltage VDD is stable, the current drawing from the output voltage supply line PLO is stopped. That is, when the system power supply voltage VDD is suddenly reduced with respect to the system ground voltage VSS (when the operating voltage is suddenly lowered), the voltage fluctuation control circuit 130d is disconnected from the output voltage supply line PLO for a certain period thereafter. It will draw current.

  FIG. 8 shows a circuit diagram of a configuration example of an integrated circuit device to which the voltage fluctuation suppressing circuit 130d of FIG. 7 is applied. In FIG. 8, it is assumed that a regulator is employed as the voltage generation circuit 120. In FIG. 8, the same parts as those in FIG. 1, FIG. 4, or FIG.

  The configuration of FIG. 8 has a configuration in which the N-type MOS transistor in the configuration of FIG. 4 is replaced with a P-type MOS transistor, and the P-type MOS transistor is replaced with an N-type MOS transistor. Accordingly, the arrangement of the current sources in the configuration of FIG. 4 is also changed, and the corresponding current sources are arranged as shown in FIG. Since this point is the same as that of FIG. 7, detailed description is omitted.

  In the configuration of FIG. 8, when the system power supply voltage VDD decreases with the system ground voltage VSS as a reference, the difference voltage between the system ground voltage VSS and the output voltage VOSC tends to decrease. Current can be drawn from the supply line PLO. Further, even if the operation of the voltage generation circuit 120 is stopped due to a decrease in the system power supply voltage VDD with respect to the system ground voltage VSS, the voltage variation suppression circuit 130d can draw a current from the output voltage supply line PLO.

  Further, even when the system power supply voltage VDD decreases with the system ground voltage VSS as a reference, the output voltage is not changed without changing the configuration of the regulator constituting the voltage generation circuit 120 whose design parameters are sufficiently adjusted for low power consumption. Variations in VOSC can be suppressed. Therefore, even when the system power supply voltage VDD decreases with the system ground voltage VSS as a reference, the design of an integrated circuit device capable of suppressing the fluctuation of the output voltage VOSC without causing unintentional oscillation and reducing the power consumption is greatly improved. It can be simplified.

[Fifth Embodiment]
In the fourth embodiment, the example in which the voltage fluctuation suppression circuit 130d draws current from the output voltage supply line with the configuration shown in FIG.

  FIG. 9 is a circuit diagram showing a configuration example of the voltage fluctuation suppressing circuit according to the fifth embodiment of the present invention. In FIG. 9, it is assumed that the first voltage V1 is the system ground voltage VSS, the second voltage V2 is the system power supply voltage VDD, and the third voltage V3 is the output voltage VOSC. In FIG. 9, the same parts as those in FIG.

  The difference between the integrated circuit device 100e in the fifth embodiment and the integrated circuit device 100d in the fourth embodiment is the configuration of the voltage fluctuation suppressing circuit. The voltage fluctuation suppressing circuit 130e included in the integrated circuit device 100e is configured by a constant current source CS7. The constant current source CS7 is connected between the first voltage supply line PL1 and the output voltage supply line PLO. That is, the integrated circuit device 100e includes a voltage generation circuit 120 (constant voltage generation circuit), a CMOS inverter circuit, and a constant current source CS7.

  In such a configuration, in the integrated circuit device 100e, even when the system power supply voltage VDD decreases with respect to the system ground voltage VSS, the constant current can be drawn from the output voltage supply line PLO by the constant current source CS7.

  When the constant current supplied from the constant current source CS7 is larger than the consumption current of the CMOS inverter circuit that constitutes the crystal oscillation circuit 140, the output voltage VOSC falls below a desired voltage. Therefore, since the current consumption of the CMOS inverter circuit varies depending on conditions, the constant current supplied by the constant current source CS7 needs to be smaller than the minimum value of the current consumption of the CMOS inverter circuit.

[Sixth Embodiment]
In the fourth embodiment, the example in which the voltage fluctuation suppression circuit 130d draws current from the output voltage supply line with the configuration shown in FIG.

  FIG. 10 is a circuit diagram showing a configuration example of the voltage fluctuation suppressing circuit according to the sixth embodiment of the present invention. In FIG. 10, it is assumed that the first voltage V1 is the system ground voltage VSS, the second voltage V2 is the system power supply voltage VDD, and the third voltage V3 is the output voltage VOSC. In FIG. 10, the same parts as those in FIG. 7 or FIG.

  In the integrated circuit device 100 of FIG. 1, the voltage fluctuation suppressing circuit 130 f in the sixth embodiment can be applied instead of the voltage fluctuation suppressing circuit 130. In addition to the configuration of the voltage fluctuation suppressing circuit 130d in FIG. 7, the voltage fluctuation suppressing circuit 130f connects the constant current source CS7 in FIG. 9 between the first voltage supply line PL1 and the output voltage supply line PLO. .

  In such a configuration, when the system power supply voltage VDD is stable with respect to the system ground voltage VSS, almost all the current I20 of the current source CS101 flows to the MOS transistor Tr101, and almost no current flows to the MOS transistor Tr102. . Therefore, the detection current Idr1 is almost 0, and almost no current flows through the MOS transistors Tr103 to Tr105 that mirror the detection current Idr1. Therefore, when the system power supply voltage VDD is stable with respect to the system ground voltage VSS, a current is drawn from the output voltage supply line PLO by the constant current source CS7.

  On the other hand, when the system power supply voltage VDD rapidly decreases with the system ground voltage VSS as a reference and the operating voltage decreases, the MOS transistors Tr100 and Tr101 are turned off by the detection capacitor Cdet1. As a result, the current I20 of the current source CS101 flows as the detection current Idr1 to the MOS transistor Tr102, and the current flows to the MOS transistors Tr103 to Tr105. Therefore, a current corresponding to the detected current Idr1 is drawn from the output voltage supply line PLO where the current is always drawn by the constant current source CS6.

  Thus, the combined use of the configuration shown in FIG. 9 and the constant current source CS7 can suppress fluctuations in the output voltage VOSC. This combination can provide the same effects as those of the third embodiment.

[Application example of integrated circuit device]
The integrated circuit device according to any one of the first to sixth embodiments can be applied to a timepiece integrated circuit device that measures time based on a clock signal using an oscillation clock.

  FIG. 11 is a block diagram showing a configuration example of a timepiece integrated circuit device according to the present invention. For example, the integrated circuit device according to any of the first to sixth embodiments has the function of the oscillation circuit 410 illustrated in FIG.

  The watch integrated circuit device 400 includes an oscillation circuit 410 and a timer circuit 420. The oscillation circuit 410 includes the reference voltage generation circuit 110, the voltage generation circuit 120, the voltage fluctuation suppression circuit 130 (any one of the voltage fluctuation suppression circuits 130a to 130f), the crystal oscillation circuit 140, And a crystal resonator 150. The crystal resonator 150 may be provided outside the timepiece integrated circuit device 400. The clock circuit 420 includes a post-stage circuit 422, a clock circuit 424, a control register 426, a clock output circuit 428, and an interrupt generation circuit 430.

  The post-stage circuit 422 divides the oscillation clock from the crystal oscillation circuit 140 constituting the oscillation circuit 410. The clock circuit 424 counts the clock signal generated by dividing the oscillation clock by the post-stage circuit 422, and “year”, “month”, “day”, “day”, “hour”, “minute”. , And measure “seconds”. The clock output circuit 428 has a function of generating a plurality of types of clock signals based on the clock signal from the post-stage circuit 422 and outputting any one of these clock signals to the outside. The interrupt generation circuit 430 generates an interrupt signal based on the time measurement result of the clock circuit 424, and outputs the interrupt signal to the outside. The control register 426 includes a register in which control data for controlling each part of the time measuring circuit 420 is set. For example, the frequency of the clock signal output from the clock output circuit 428 and the interrupt generated by the interrupt generation circuit 430 are set. Conditions are set.

  According to such a timepiece integrated circuit device 400, even when the power supply is switched at the time of backup and the system power supply voltage VDD is reduced with respect to the system ground voltage VSS and the operating voltage is reduced, the oscillation clock is “tooth missing”. It becomes possible to measure time accurately without becoming "." At this time, it is possible to easily realize a reduction in power consumption of a voltage generation circuit including a regulator or the like without performing adjustment of design parameters or the like again.

〔Electronics〕
The watch integrated circuit device 400 can be applied to the following electronic devices.

  FIG. 12 shows a block diagram of a hardware configuration example of an electronic apparatus according to the present invention. 12, parts similar to those in FIG. 11 are given the same reference numerals, and description thereof will be omitted as appropriate.

  The electronic device 500 includes a central processing unit (CPU) 510, an input unit 512, a memory 516, a display unit 518, a power supply unit 520, and a timepiece integrated circuit device 400. The CPU 510, the input unit 512, the memory 516, the display unit 518, the power supply unit 520, and the clock integrated circuit device 400 are connected via a bus 522. The CPU 510 reads out a program stored in the memory 516 via the bus 522 and executes processing corresponding to the program to control each unit constituting the electronic device 500. The input unit 512 receives input data for controlling the electronic device 500. The CPU 510 can change the process according to the input data received by the input unit 512. The display unit 518 displays an image generated by the CPU 510 or the like. The power supply unit 520 generates power to be supplied to each unit constituting the electronic device 500. Such an electronic device 500 operates in synchronization with a clock signal generated by the clock integrated circuit device 400 controlled by the CPU 510. At this time, the CPU 510 performs processing corresponding to the interrupt signal generated by the clock integrated circuit device 400 as timer processing, and the electronic device 500 performs real-time processing.

  FIGS. 13A and 13B are perspective views of a configuration example of the electronic device 500 in FIG. FIG. 13A is a perspective view of a configuration example of a mobile personal computer. FIG. 13B illustrates a perspective view of a structure of a mobile phone.

  A personal computer 800 shown in FIG. 13A, which is one example of the configuration of the electronic device 500 in FIG. 12, includes a main body 810, a display 820, and an operation unit 830. The main body 810 includes the CPU 510, the memory 516, the power supply unit 520, and the like shown in FIG. The display unit 820 corresponds to the display unit 518 in FIG. 12, and its function is realized by, for example, a liquid crystal display panel. The operation unit 830 corresponds to the input unit 512 in FIG. 12, and its function is realized by a keyboard or the like. Such operation information via the operation unit 830 is analyzed by the CPU 510 of the main body unit 810, and an image is displayed on the display unit 820 according to the operation information. This makes it possible to provide a personal computer 800 that operates stably even when the battery is switched, has low power consumption, and is easy to design.

  A cellular phone 900 illustrated in FIG. 13B as one example of a structure of the electronic device 500 in FIG. 12 includes a main body portion 910, a display portion 920, and an operation portion 930. The main body unit 910 includes the CPU 510, the memory 516, the power supply unit 520, and the like shown in FIG. The display unit 920 corresponds to the display unit 518 in FIG. 12, and its function is realized by, for example, a liquid crystal display panel. The operation unit 930 corresponds to the input unit 512 in FIG. 12, and its function is realized by buttons and the like. The operation information via the operation unit 930 is analyzed by the CPU 510 of the main body unit 910, and an image is displayed on the display unit 920 according to the operation information. Accordingly, it is possible to provide the mobile phone 900 that operates stably even when the battery is switched, has low power consumption, and is easy to design.

  Note that the electronic device 500 in FIG. 12 is not limited to the electronic device 500 illustrated in FIGS. 13A and 13B. For example, personal digital assistants (PDAs), digital still cameras, televisions, video cameras, car navigation devices, pagers, electronic notebooks, electronic paper, calculators, word processors, workstations, video phones, POS (Point of sale systems ) Devices such as terminals, printers, scanners, copiers, video players and touch panels.

  As described above, the integrated circuit device and the electronic apparatus according to the present invention have been described based on any one of the above embodiments, but the present invention is not limited to any one of the above embodiments. For example, the present invention can be implemented in various modes without departing from the gist thereof, and the following modifications are possible.

  (1) In the above embodiment, the voltage generation circuit 120 has been described mainly using a regulator that generates a constant voltage as an example, but the present invention is not limited to this. The voltage generation circuit according to the present invention may not generate a constant voltage.

  (2) In any of the embodiments described above, a watch integrated circuit device has been described as an example of the integrated circuit device. However, the present invention is not limited to this. It goes without saying that the integrated circuit device according to the present invention can be applied to uses other than for watches.

  (3) The present invention is not limited to the configuration of the regulator and the configuration of the crystal oscillation circuit described in any of the above embodiments. The present invention is not limited to the configuration of the regulator or the configuration of the crystal oscillation circuit.

  (4) In any of the above embodiments, the phrase “gate” means a gate terminal, a gate region, or a gate electrode. Similarly, the phrase “drain” means a drain terminal, a drain region, or a drain electrode. The phrase “source” means a source terminal, a source region, or a source electrode.

  (5) In any of the above embodiments, the present invention has been described as an integrated circuit device, an electronic device, and the like, but the present invention is not limited to this. For example, the operation voltage fluctuation detection method and the voltage fluctuation suppression method described in any of the above embodiments may be used.

10 ... Regulator, 20, 140 ... Crystal oscillation circuit,
22, 160, 422 ... latter circuit, 30, 150 ... crystal resonator,
100, 100a, 100b, 100d, 100e ... integrated circuit device,
110: Reference voltage generation circuit, 120: Voltage generation circuit,
130, 130a, 130b, 130c, 130d, 130e, 130f ... voltage fluctuation suppression circuit, 400 ... integrated circuit device for a watch,
410 ... oscillator circuit, 420 ... timer circuit, 424 ... clock circuit,
426: Control register, 428: Clock output circuit, 430: Interrupt generation circuit,
500: Electronic equipment 510: CPU, 512: Input unit, 516: Memory,
518, 820, 920 ... display unit, 520 ... power supply unit, 522 ... bus,
800 ... Personal computer, 810, 910 ... Main unit,
830, 930 ... operation unit, 900 ... mobile phone, C1 ... phase compensation capacity,
C2, ... Stabilizing capacitance, CS1, CS2, CS3, CS4, CS5, CS100, CS101 ... Current source, CS6, CS7 ... Constant current source, Cdet, Cdet1 ... Detection capacitance,
CLKO ... oscillation clock, PG, N1 ... node, PL1 ... first voltage supply line,
PL2 ... second voltage supply line, PLO ... output voltage supply line,
TM1, TM2, TMa, TMb ... connection terminals, Tr1-Tr6, Tr10-Tr15, Tr20, Tr21, Tr30, Tr31, Tr100-Tr105 ... MOS transistors, TrA ... output control transistors, TrB ... transistors,
V1 ... first voltage, V2 ... second voltage, V3 ... third voltage,
VDD: System power supply voltage, VOSC: Output voltage, Vref: Reference voltage,
VSS: System ground voltage

Claims (10)

A voltage generation circuit for generating a third voltage using the difference between the first voltage and the second voltage as an operating voltage and supplying the third voltage to the output voltage supply line;
A voltage fluctuation suppressing circuit for flowing a current into the output voltage supply line or drawing a current from the output voltage supply line for a given period when the operating voltage decreases,
The voltage fluctuation suppressing circuit is:
A first current source;
A first transistor having a drain connected to one end of the first current source and gate-controlled by a gate voltage corresponding to the first voltage;
A second current source having one end connected to the first voltage supply line to which the first voltage is supplied ;
The drain is connected to the other end of the second current source, the source is connected to a second voltage supply line to which the second voltage is supplied , and the gate is connected to the gate of the first transistor. A second transistor;
A sensing capacitor inserted between the first voltage supply line and the gate of the first transistor;
The first current source and the first transistor is connected between the front Symbol first voltage supply line and the previous SL second voltage supply line,
An integrated circuit device, wherein a detection current obtained by subtracting a drain current of the first transistor from a current of the first current source is supplied to the output voltage supply line or drawn from the output voltage supply line. In claim 1,
When the ratio of the current drive capability of the first transistor to the current drive capability of the second transistor is n, the current value of the first current source is n times the current value of the second current source. An integrated circuit device characterized by being smaller. In any one of Claims 1 thru | or 2.
The voltage fluctuation suppressing circuit is:
A first current mirror circuit connected to the second voltage supply line and mirroring the detection current;
A second current mirror circuit connected to the first voltage supply line and mirroring a current mirrored by the first current mirror circuit;
An integrated circuit device, wherein the current mirrored by the second current mirror circuit flows into the output voltage supply line or is drawn from the output voltage supply line. In any one of Claims 1 thru | or 3,
An integrated circuit device comprising: a constant current source provided between the first voltage supply line and the output voltage supply line. In any one of Claims 1 thru | or 4,
An integrated circuit device comprising a load circuit that operates using a difference between the third voltage and the second voltage as an operating voltage. In claim 5,
The voltage generation circuit includes:
Generating the third voltage which is a constant voltage;
The load circuit is
An integrated circuit device comprising an inverter circuit configured to allow connection of an oscillation vibrator at its input and output. In any one of Claims 1 thru | or 3,
An inverter circuit configured such that a difference between the third voltage and the second voltage is an operating voltage, and an oscillator can be connected to an input and an output thereof;
An integrated circuit device comprising: the first voltage supply line; and a constant current source provided between the output voltage supply line. In claim 7,
The integrated circuit device according to claim 1, wherein a current of the constant current source is smaller than a minimum value of current consumption of the inverter circuit. In any of claims 6 to 8,
A frequency divider that divides the output of the inverter circuit;
An integrated circuit device comprising: a timing circuit that counts based on an output of the frequency dividing circuit.   An electronic device comprising the integrated circuit device according to claim 1.

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