JP2009222621A - Electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electronic apparatus having high accuracy and consuming low power. <P>SOLUTION: An oscillating means 103 comprises a crystal oscillator 101 and oscillation circuit 102, which are stored in the same airtightly sealed package. In a back stage of the oscillating means 103, an amplitude amplifying means 104 for amplifying the amplitude of a clock signal outputted from the oscillating means 103 and supplying it to a frequency dividing means 105 and a display driving means 106, is provided. In a further back stage, a receiving means of the clock signal outputted from the oscillating means 103 is connected. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to an electronic device.

  An electronic device having a timekeeping function such as an electronic timepiece that is widely used at present is an oscillating means for generating a clock signal as a reference for timekeeping, and a clock signal as a timekeeping unit by dividing the output signal of the oscillating means. A frequency dividing means for generating, a display driving means for outputting a display driving signal based on an output signal of the frequency dividing means, and a display means driven by the display driving means for displaying time.

  The configuration of a conventional electronic device will be described using an electronic timepiece as an example. FIG. 14 is a diagram showing a configuration of an electronic timepiece in a conventional example. The oscillating means 1403 includes a crystal resonator 1401 and an oscillating circuit 1402. The oscillating circuit 1402, the frequency dividing means 1405, and the display driving means 1406 are integrated into a single integrated circuit 1407. The display driver 1406 receives a clock signal as a time unit from the frequency divider 1405. In addition, the hand-type time display 1408 displays and drives a high-frequency clock signal before frequency division for smooth hand movement. Often supplied to the means 1406. In an electronic timepiece having a chronograph mechanism, a high-frequency clock signal is also supplied to the display driving means 1406.

  In an electronic timepiece that must operate continuously for a long time with a battery of a limited capacity, it is important to keep power consumption low. However, the conventional configuration shown in FIG. 14 is extremely effective in reducing power consumption. It is effective for. Since the clock signal having a high frequency output from the oscillation circuit 1402 is not output to the outside of the integrated circuit 1407 but is propagated inside the integrated circuit 1407 having a small parasitic capacitance, wasteful power consumption for charging and discharging the parasitic capacitance is reduced. This is because it can be minimized. For example, Patent Document 1 discloses an electronic apparatus having such a configuration.

  In the conventional configuration, a connection portion between the integrated circuit 1407 and the crystal resonator 1401 is exposed to the outside of the integrated circuit 1407, and an oscillation signal having a high frequency is propagated. However, since the crystal oscillation circuit is configured as a resonance circuit, the parasitic amount added to the connection portion is transferred to the oscillation load capacitance and does not consume power.

JP-A-6-259164

  However, the conventional configuration has the following problems. First, since the connection portion between the oscillation circuit 1402 and the crystal resonator 1401 is exposed to the outside of the integrated circuit 1407, the frequency changes easily due to humidity. Many electronic watch cases have a waterproof structure, but they do not have a hermetically sealed structure that can completely shut out the humidity, so there is a slight change in the load capacity of the oscillation circuit 1402 due to the surrounding humidity. Occurs, leading to time advance and delay.

  In addition, when trying to incorporate temperature compensation means for compensating for the change in the oscillation frequency with respect to the temperature of the quartz crystal 1401 into the electronic timepiece, the oscillation is actually performed under high and low temperature conditions for accurate temperature compensation. It is necessary to expose the means 1403 and collect compensation data at each temperature. However, in the conventional configuration, the oscillation means 1403 cannot be separated from the electronic timepiece main body. did not become.

  Further, since the oscillation circuit 1402 is formed in one integrated circuit 1407 together with the frequency dividing means 1405 and the display driving means 1406, when it is desired to add any new mechanism such as a temperature compensation means to the oscillation circuit 1402, the integrated circuit 1407 There is also a drawback that it has to be redesigned from scratch.

  The above problem can be solved by making the oscillation circuit independent from the integrated circuit and using a so-called crystal oscillator in which the oscillation circuit and the crystal unit are housed in the same hermetically sealed package as the oscillation means. . However, in this case, since a high-frequency clock signal output from the oscillator passes through the outside of the integrated circuit until it is input to the integrated circuit formed by the frequency dividing means and the display driving means, a large amount of parasitic capacitance is required. And a new problem arises in that the power consumption is significantly increased by the current that charges and discharges the parasitic capacitance.

  Therefore, the present invention has been made in view of the above points, and an object of the present invention is to provide an electronic device with high accuracy and low power consumption.

  In order to solve the above problem, an electronic device of the present invention includes at least an oscillation unit that outputs a clock signal and a clock signal reception unit that receives a clock signal output from the oscillation unit, and is output from the oscillation unit. Amplitude reducing means for reducing the amplitude of the clock signal reduced to an amplitude smaller than the minimum required by the clock signal receiving means, and receiving the clock signal amplitude reduced in amplitude by the amplitude reducing means. And amplitude amplifying means for amplifying to the minimum required amplitude by the means and outputting to the clock signal receiving means.

  With such a configuration, it is possible to minimize power consumption due to parasitic capacitance between the oscillation means output and the clock signal receiving means by reducing the amplitude of the clock signal output from the oscillation means, It is possible to achieve low power consumption of electronic devices.

  In the electronic device according to the present invention, the clock signal receiving unit includes a frequency dividing circuit that divides and outputs the clock signal output from the oscillating unit to a signal that is a time unit. Time display means for displaying time information based on the output signal can be provided.

  Furthermore, the electronic device of the present invention can further include a constant voltage supply unit that supplies a constant voltage to the oscillation unit.

  Furthermore, the electronic apparatus according to the present invention can further comprise compensation means for compensating for output frequency fluctuations due to the temperature of the clock signal output from the oscillation means.

  With such a configuration, when acquiring compensation data by changing the temperature, it is possible to acquire data with only the oscillation means alone, so the device can be smaller than when adjusting with the electronic device body, Adjustment can be performed efficiently.

  Furthermore, in the electronic apparatus of the present invention, the oscillation means and the amplitude reduction means can be housed in the same space that is hermetically sealed.

  With such a configuration, it is possible to completely prevent the frequency change due to humidity because the oscillation means is housed in a hermetically sealed package.

  According to the present invention, by reducing the amplitude of the clock signal output from the oscillating means, power consumption due to parasitic capacitance between the oscillating means output and the clock signal receiving means can be minimized, and high accuracy Thus, an electronic device with low power consumption can be provided.

  Hereinafter, the best mode for carrying out the present invention will be specifically described with reference to the drawings.

  FIG. 1 is a configuration diagram illustrating an electronic apparatus according to the present embodiment. An oscillating means 103 for outputting a clock signal includes a crystal resonator 101 and an oscillating circuit 102, and is housed in the same hermetically sealed package. An amplitude amplifying means 104 for amplifying the amplitude of the clock signal output from the oscillating means 103 is provided at the subsequent stage of the oscillating means 103, and the clock signal output from the oscillating means 103 is further provided at the subsequent stage. It comprises a frequency dividing means 105 and a display driving means 106 as receiving means, and is connected to a time display means 108. The amplitude amplifying means 104, the frequency dividing means 105, and the display driving means 106 are formed as an integrated circuit 107.

  Next, the operation of the electronic apparatus of this embodiment will be described. The oscillation means 103 outputs a clock signal having a smaller amplitude than the minimum signal amplitude required for the subsequent frequency dividing means 105 and the display driving means 106 to operate normally. The clock signal outputted from the oscillating means 103 is inputted to the amplitude amplifying means 104, and the inputted small amplitude clock signal is amplified to a necessary amplitude by the amplitude amplifying means 104 and supplied to the subsequent circuit. The clock signal output from the oscillating means 103 consumes a large amount of power due to the charging / discharging current for the parasitic capacitance generated in the wiring pattern or the like. This charging / discharging current is proportional to the effective value of the amplitude of the clock signal. By minimizing the output amplitude of the output clock signal, it is possible to suppress the power consumption due to the charge / discharge current to a small amount.

Hereinafter, each element of the electronic apparatus of the present embodiment will be specifically described.
[Oscillation means]
FIG. 2 is a diagram showing the configuration of the oscillation means of this embodiment. The oscillating means 103 includes a constant voltage supply means 201, and the oscillation circuit 102 is driven by the voltage supplied by the constant voltage supply means 201. By making the supplied voltage very small, the amplitude of the clock signal output from the oscillation circuit 102 can be reduced.

  Although the constant voltage supply means 201 can be provided independently as shown in FIG. 2, it is desirable to form an integrated circuit together with the oscillation circuit 102 from the viewpoint of space efficiency. Further, it can be incorporated into the integrated circuit 107.

  When the supply voltage of the constant voltage supply means 201 is extremely reduced, there is a problem that oscillation of the crystal unit 101 becomes difficult. In that case, an inverter circuit having a gate separation configuration as shown in FIG. 3 is used. Is effective. Normally, by separating the gate of the oscillation inverter circuit with capacitors 301 and 302 and separately applying a bias voltage that maximizes the gate-source voltage of each transistor to each of the PN transistors 303 and 304, Driving with a lower voltage is possible as compared with an oscillation circuit using the inverter.

  FIG. 4 is a diagram showing another configuration of the oscillation means of this embodiment. An amplitude reduction unit 401 is provided, and the amplitude of the clock signal output from the oscillation circuit 102 is reduced by the amplitude reduction unit 401 and output to the outside. It is desirable that the oscillation circuit and the amplitude reduction means are built in the same integrated circuit so that a large parasitic capacitance is not added between the oscillation circuit 102 and the amplitude reduction means 401.

  An example of a specific circuit configuration of the amplitude reducing means is shown in FIG. A constant voltage supply means 501 for supplying a low voltage is provided, and the output inverter circuit 503 is driven by the supply voltage of the constant voltage supply means 501 to reduce the amplitude of the waveform output from the oscillation circuit 101. Is output. In FIG. 5, the oscillation circuit is directly driven by the battery 502 as a power source. However, the oscillation circuit may be driven by another constant voltage supply unit having a higher output voltage than the constant voltage supply unit 501.

  When the supply voltage of the constant voltage supply means 501 is extremely low in the circuit of FIG. 5, the potential between the gate and the source of the P channel transistor of the output inverter circuit 503 is lowered, and a normal waveform is not output. In this case, as in the circuit shown in FIG. 6, the output of the oscillation circuit 102 is cut off by the capacitor 601, and a feedback resistor 602 is provided between the input and output of the inverter circuit 503 so as to apply feedback, thereby bringing the bias potential to the middle point. It is preferable to use a circuit that blocks the input of the P-channel transistor 703 with a capacitor 701 and applies a large bias potential between the gate and the source, such as a circuit to come or a circuit shown in FIG.

  Further, a circuit in which the P-channel transistor is replaced with a resistor 801 as in the circuit shown in FIG. 8 can be driven with a lower voltage than the circuit in FIG.

  FIG. 9 shows a specific circuit configuration of the amplitude reducing means that does not have a dedicated constant voltage supply means. The output amplitude is reduced by inserting one-stage or multistage diodes 901 and 902 in the forward direction into the drains of the transistors of the P channel 903 and N channel 904 constituting the inverter circuit. Since a forward drop voltage of about 0.6 volts is normally generated in the diode, for example, when the output voltage without the diode has an amplitude of 0 to 2 volts, the diode is provided by providing one stage of each diode. Can be reduced to an amplitude of .6 volts-1.4 volts.

  In the circuit of FIG. 9, the power supply voltage of the amplitude reduction means is supplied from the constant voltage supply means 905 that is common to the oscillation circuit, but it is of course possible to supply directly from the battery 502. If the amplitude reduction width may be small, a diode may be inserted in the drain of only one of the PN transistors.

  The various configurations of the amplitude reducing means described above are effective even when used alone, but a greater effect can be obtained by using them in combination.

[Amplitude amplification means]
Next, a specific circuit configuration of the amplitude amplifying unit that amplifies the amplitude of the clock signal with a small amplitude input to the integrated circuit 107 and supplies the amplified signal to the frequency dividing unit 105 and the display driving unit 106 will be described.

  An example of a specific circuit configuration of the amplitude amplifying means is shown in FIG. The small amplitude clock signal input to the watch integrated circuit 107 is DC cut by the capacitor 1001 and input to the inverter circuit 1003. Since the input bias voltage of the inverter circuit 1003 is optimized by connecting the input and output of the inverter circuit 1003 with the high resistance 1002, the amplitude of the input small amplitude clock signal is increased to the required amplitude, and the frequency divider circuit 105 and the display driving circuit 106.

  FIG. 11 shows another circuit configuration of the amplitude amplifying means. The N-channel transistors 1101 and 1102 are driven by the input low-amplitude clock signal, and the P-channel transistors 1103 and 1104 are driven by the output to output the clock signal having the power supply voltage amplitude. The problem that it is difficult to directly drive the P-channel transistor is solved.

  When a single amplitude amplification means in FIGS. 10 and 11 cannot provide a clock signal with sufficient amplitude, a necessary amplitude can be obtained by providing a plurality of stages or by using a combination of circuits. It is possible.

  The integrated circuits shown in FIGS. 10 and 11 are configured to be driven by constant voltage driving means, but can be directly driven by battery voltage.

  Since the oscillation frequency of the quartz crystal varies from several ppm to several tens of ppm depending on the temperature, an electronic device using this as a source oscillation causes a time delay or advance depending on the temperature. Many high-precision electronic devices incorporate temperature compensation means in order to suppress this time lag due to temperature.

  As temperature compensation in conventional electronic devices, there are a method of compensating the oscillation frequency itself of the crystal resonator and a method of compensating the frequency equivalently by increasing or decreasing the number of clocks of the output clock waveform. In either method, in order to perform accurate temperature compensation, it is necessary to adjust the frequency by actually exposing each product in a high and low temperature environment. Since it had to be performed, the adjustment apparatus was increased in size and increased in labor for adjustment.

  FIG. 12 is a diagram illustrating the configuration of the electronic apparatus according to the present embodiment. The difference from the first embodiment is that a temperature compensation means is provided in the oscillation circuit. Since the oscillating means is independent of the integrated circuit 107, the temperature compensation means 1201 is incorporated in the oscillating means 1203 as shown in FIG. It is possible. Since the oscillation means is housed in a single package, it is easy to reduce the size, and the shape is usually a simple rectangular parallelepiped. Adjustments can be made.

  The temperature compensation unit 1201 is integrated with the oscillation circuit 1202 into a single integrated circuit, thereby contributing to downsizing and cost reduction of the oscillation unit.

  FIG. 13 shows a basic configuration example of the temperature compensation means. It comprises a temperature sensor 1302 for measuring the ambient temperature, a memory circuit 1301 for storing compensation data written from the outside, and compensation signal generating means 1303 for generating a compensation signal based on the temperature signal and compensation data. An optimum compensation signal is sent to the oscillation circuit 1202 according to the information and the ambient temperature.

In the main body, the temperature compensation data can be acquired and written to the oscillation unit alone, and then the oscillation unit can be mounted on the electronic device. This makes it much easier to manufacture high-precision electronic devices than in the past. be able to.

The block diagram which shows the electronic device in one Example of this invention. The block diagram of the oscillation means of the electronic device in one Example of this invention. The circuit diagram of the oscillation circuit of the electronic device in one Example of this invention. The block diagram of the oscillation means of the electronic device in one Example of this invention. The circuit diagram of the amplitude reduction means of the electronic device in one Example of this invention. The circuit diagram of the amplitude reduction means of the electronic device in one Example of this invention. The circuit diagram of the amplitude reduction means of the electronic device in one Example of this invention. The circuit diagram of the amplitude reduction means of the electronic device in one Example of this invention. The circuit diagram of the amplitude reduction means of the electronic device in one Example of this invention. The circuit diagram of the amplitude amplification means of the electronic device in one Example of this invention. The circuit diagram of the amplitude amplification means of the electronic device in one Example of this invention. The block diagram which incorporated the temperature compensation means in the electronic device of one Example of this invention. The block diagram of the temperature compensation means of the electronic device in one Example of this invention. The block diagram of the electronic timepiece in a prior art example.

Explanation of symbols

101, 1401: Crystal resonators 102, 1202, 1402: Oscillation circuits 103, 403, 1203, 1403: Oscillation means 104: Amplitude amplification means 105, 1405: Frequency division means 106, 1406: Display drive means 107, 1407: Integrated circuit 108, 1408: Time display means 201, 501, 905, 1005: Constant voltage supply means 202, 502: Battery 401: Amplitude reduction means 1201: Temperature compensation means 1301: Memory circuit 1302: Temperature sensor 1303: Compensation signal generation means

Claims (5)

An electronic device including at least an oscillation unit that outputs a clock signal and a clock signal reception unit that receives a clock signal output from the oscillation unit,
An amplitude reducing means for reducing the amplitude of the clock signal output from the oscillating means to an amplitude smaller than the minimum required by the clock signal receiving means, and the clock signal whose amplitude is reduced by the amplitude reducing means. An electronic apparatus comprising: an amplitude amplifying unit that amplifies an amplitude to a minimum required by the clock signal receiving unit and outputs the amplified amplitude to the clock signal receiving unit.   The clock signal receiving means is composed of a frequency dividing circuit that divides the clock signal output from the oscillating means into a signal that is a timekeeping unit, and outputs the time information based on the output signal of the frequency dividing circuit. The electronic apparatus according to claim 1, further comprising a time display unit that displays the time.   The electronic apparatus according to claim 1, further comprising a constant voltage supply unit that supplies a constant voltage to the oscillation unit.   The electronic apparatus according to claim 1, further comprising a compensation unit that compensates for an output frequency variation due to a temperature of the clock signal output from the oscillation unit.   The electronic device according to claim 1, wherein the oscillating unit and the amplitude reducing unit are housed in the same hermetically sealed space.