JP5846398B2 - Multilayer semiconductor ceramic capacitor with varistor function and manufacturing method thereof - Google Patents

Description

The present invention relates to a multilayer semiconductor ceramic capacitor having a varistor function and a method for manufacturing the same, and more particularly to a multilayer semiconductor ceramic capacitor having a varistor function using an SrTiO ₃ based grain boundary insulating semiconductor ceramic and a method for manufacturing the same.

  With the recent development of electronics technology, portable electronic devices such as mobile phones and laptop computers, and in-vehicle electronic devices mounted on automobiles, etc. have become popular, and electronic devices have become smaller and more multifunctional. Yes.

  On the other hand, semiconductor devices such as various ICs and LSIs are increasingly used in order to realize downsizing and multi-functionalization of electronic devices, and accordingly, noise resistance of electronic devices is decreasing.

  Therefore, conventionally, a film capacitor, a multilayer ceramic capacitor, a semiconductor ceramic capacitor, and the like are provided as bypass capacitors on the power lines of various ICs and LSIs, thereby ensuring noise resistance of electronic devices.

  In particular, in car navigation systems, car audio systems, in-vehicle ECUs, and the like, it is widely performed to connect a capacitor having a capacitance of about 1 nF to an external terminal, thereby absorbing high-frequency noise.

  However, these capacitors exhibit excellent performance in absorbing high frequency noise, but the capacitors themselves do not have a function of absorbing high voltage pulses or static electricity. For this reason, when such a high-voltage pulse or static electricity enters the electronic device, there is a risk of malfunction of the electronic device or damage to the semiconductor element. In particular, when the capacitance is as low as 1 nF, ESD (Electro-Static Discharge) is extremely low (for example, about 2 kV to 4 kV), which may cause damage to the capacitor itself. .

  Therefore, conventionally, as shown in FIG. 2A, a Zener diode 105 is provided in parallel to the capacitor 104 connected to the power supply line 103 that connects the external terminal 101 and the IC 102, or FIG. ), A varistor 106 is provided in parallel with the capacitor 104, thereby ensuring an ESD withstand voltage.

  However, when the Zener diode 105 and the varistor 106 are also provided in parallel with the capacitor 104 as described above, the number of components increases, resulting in an increase in cost, and an installation space must be secured, resulting in an increase in the size of the device. May be incurred.

  Therefore, if the capacitor can have a varistor function, a Zener diode and a varistor are not required, and as shown in FIG. 3, the ESD withstand voltage can be dealt with only by the capacitor, thereby facilitating standardization of the design. It is possible to provide a capacitor having added value.

Patent Document 1 discloses that a semiconductor ceramic is formed of an SrTiO ₃ -based grain boundary insulating type, and a molar ratio m of Sr sites to Ti sites is 1.000 <m ≦ 1.020. The element is dissolved in the crystal grains, and the acceptor element is present in the grain boundary layer in a range of 0.5 mol or less (excluding 0 mol) with respect to 100 mol of the Ti element, and A multilayer semiconductor ceramic capacitor with a varistor function in which the average grain size of crystal grains is 1.0 μm or less has been proposed.

  In this patent document 1, since the semiconductor ceramic has the above-described composition, a multilayer grain boundary insulation type semiconductor ceramic capacitor having a varistor function that has good insulation and ESD withstand voltage and can be thinned and miniaturized is obtained. be able to.

International Publication 2008/004389

  However, the multilayer semiconductor ceramic capacitor with a varistor function disclosed in Patent Document 1 has an ESD withstand voltage of 30 kV or more and a good insulation with a specific resistance logρ of 9.7 or more, but the capacitance is reduced to about 1 nF. As a result, there is a large variation in the insulation performance, resulting in a decrease in product yield and inferior mass productivity.

The present invention has been made in view of such circumstances, and can improve the product yield while ensuring the insulation performance that can withstand practicality, and is suitable for mass production having a good ESD withstand voltage. It is an object of the present invention to provide a _three- system grain boundary insulation type multilayer semiconductor ceramic capacitor with a varistor function and a method for manufacturing the same.

In order to achieve the above-mentioned object, the present inventor conducted intensive studies on SrTiO ₃ -based grain boundary insulating semiconductor ceramics, and found that the mixing molar ratio m of Sr sites and Ti sites was 1.000 ≦ m ≦ 1.020. The mixing molar ratio m of Sr site and Ti site is adjusted so that Zr element is added together with a predetermined amount of acceptor element in the range of 0.15 to 3.0 mol with respect to 100 mol of Ti element and heat-treated. As a result, it has been found that the product yield can be improved while ensuring the insulation performance that can withstand practicality, and a good ESD withstand voltage can be obtained.

The present invention has been made based on these findings, and a multilayer semiconductor ceramic capacitor with a varistor function according to the present invention (hereinafter simply referred to as “multilayer semiconductor ceramic capacitor”) is an SrTiO ₃ -based grain boundary insulation type. A laminated sintered body formed by alternately laminating a plurality of semiconductor ceramic layers and a plurality of internal electrode layers formed of the above-mentioned semiconductor ceramic, and firing the internal electrode layers and the electric electrodes at both ends of the laminated sintered body. A laminated semiconductor ceramic capacitor having externally connected external electrodes, wherein the semiconductor ceramic has a molar ratio m of Sr sites to Ti sites of 1.000 ≦ m ≦ 1.020, and a donor element Is dissolved in the crystal grains, and the acceptor element is in the range of 0.5 mol or less (excluding 0 mol) with respect to 100 mol of the Ti element. In the grain boundary layer, the Zr element is contained in the range of 0.15 mol or more and 3.0 mol or less with respect to 100 mol of the Ti element, and the average particle size of the crystal particles is 1.5 μm or less. It is characterized by that.

  Further, in order to ensure better electrical characteristics and insulation while ensuring a desired ESD withstand voltage, the acceptor element is in a range of 0.3 to 0.5 mol with respect to 100 mol of the Ti element. It is preferably contained.

  That is, in the multilayer semiconductor ceramic capacitor of the present invention, the acceptor element is preferably contained in a range of 0.3 to 0.5 mol with respect to 100 mol of the Ti element.

  In the multilayer semiconductor ceramic capacitor of the present invention, it is preferable that the acceptor element contains at least one element of Mn, Co, Ni, and Cr.

  In the multilayer semiconductor ceramic capacitor of the present invention, the donor element preferably contains at least one element selected from La, Nd, Sm, Dy, Nb, and Ta.

  In the multilayer semiconductor ceramic capacitor of the present invention, the low melting point oxide is preferably contained in a range of 0.1 mol or less with respect to 100 mol of the Ti element.

Furthermore, in the multilayer semiconductor ceramic capacitor of the present invention, it is preferable that the low melting point oxide is SiO ₂ .

In addition, a method for manufacturing a multilayer semiconductor ceramic capacitor according to the present invention is a method for manufacturing a multilayer semiconductor ceramic capacitor with a varistor function using an SrTiO ₃ -based grain boundary insulating semiconductor ceramic, the ceramic element including a donor compound. The raw materials are weighed so that the blending molar ratio m of Sr sites and Ti sites is in the range of 1.000 ≦ m ≦ 1.020, mixed and pulverized, and then calcined to prepare a calcined powder. The acceptor compound is weighed so as to be 0.5 mol or less (excluding 0 mol) with respect to 100 mol of Ti element, and 0.15 mol to 3 mol of Ti element with respect to 100 mol of Ti element. The Zr compound is weighed so as to be less than or equal to 0.0 mol, the Zr compound and the acceptor compound are mixed with the calcined powder, and heat treatment is performed to produce a heat treated powder. A heat treatment powder manufacturing step to be manufactured; a laminate forming step of forming a ceramic green sheet by subjecting the heat treatment powder to a forming process; and then alternately laminating internal electrode layers and ceramic green sheets; and a reducing atmosphere. And a firing step of performing a secondary firing treatment in a weak reducing atmosphere, an air atmosphere, or an oxidizing atmosphere after the laminate is subjected to a primary firing treatment.

  In the method for producing a multilayer semiconductor ceramic capacitor of the present invention, it is preferable that a calcination temperature in the calcination treatment is higher than a calcination temperature in the primary firing treatment.

  According to the multilayer semiconductor ceramic capacitor of the present invention, the semiconductor ceramic forming the semiconductor ceramic layer has a compound molar ratio m of Sr sites to Ti sites of 1.000 ≦ m ≦ 1.020, and the donor element is a crystal. While being dissolved in the particles, the acceptor element is present in the grain boundary layer in the range of 0.5 mol or less (excluding 0 mol) with respect to 100 mol of the Ti element, and the Zr element is Since it is contained in the range of 0.15 mol or more and 3.0 mol or less with respect to 100 mol of Ti and the average particle size of the crystal particles is 1.5 μm or less, the compound molar ratio m of Sr site and Ti site is chemical. Even if the stoichiometric ratio or Sr site is more than the stoichiometric ratio, it is possible to improve the product yield while ensuring the insulation performance that can sufficiently withstand practicality, and has a good ESD withstand voltage. You It is possible to obtain a laminated semiconductor ceramic capacitor which is suitable for mass production.

  Specifically, even if the capacitance is reduced to about 1 nF, it has an ESD withstand voltage of 30 kV or more, an insulation resistance logIR of 8.5 or more, a product yield of 85% or more, and good It is possible to obtain a multilayer semiconductor ceramic capacitor having high reliability and suitable for mass production.

Also, according to the method for manufacturing a multilayer semiconductor ceramic capacitor of the present invention, there is provided a method for manufacturing a multilayer semiconductor ceramic capacitor with a varistor function using a SrTiO ₃ -based grain boundary insulating semiconductor ceramic, the ceramic including a donor compound The raw material is weighed so that the blending molar ratio m of Sr site and Ti site is in the range of 1.000 ≦ m ≦ 1.020, mixed and pulverized, and then calcined to prepare a calcined powder. The calcining powder preparation step and the acceptor compound are weighed so as to be 0.5 mol or less (excluding 0 mol) with respect to 100 mol of Ti element, and at least 0.15 mol with respect to 100 mol of Ti element. The Zr compound is weighed so as to be 3.0 mol or less, the Zr compound and the acceptor compound are mixed with the calcined powder, and heat treatment is performed to obtain the heat treated powder. A heat treatment powder production step to be produced, a laminate forming step in which a molding process is performed on the heat treatment powder to produce a ceramic green sheet, and then an internal electrode layer and a ceramic green sheet are alternately laminated to form a laminate, and a reducing atmosphere And a firing step in which a secondary firing treatment is performed in a weak reducing atmosphere, an air atmosphere, or an oxidizing atmosphere after the laminate is subjected to a primary firing treatment. Even if m is 1.000 ≦ m ≦ 1.020, by performing the heat treatment by adding a Zr compound in the heat treatment powder preparation step, the product yield is good and the insulation performance can sufficiently withstand practicality. In addition, it is possible to manufacture a multilayer semiconductor ceramic capacitor suitable for mass production having a good ESD withstand voltage.

1 is a cross-sectional view schematically showing an embodiment of a multilayer semiconductor ceramic capacitor according to the present invention. It is an electric circuit diagram when a Zener diode or a varistor is provided in parallel with a capacitor. It is an electric circuit diagram when the capacitor has a varistor function.

  Next, an embodiment of the present invention will be described in detail.

  FIG. 1 is a cross-sectional view schematically showing an embodiment of a multilayer semiconductor ceramic capacitor according to the present invention.

  The multilayer semiconductor ceramic capacitor includes a component body 1 and external electrodes 3 a and 3 b formed at both ends of the component body 1.

  The component body 1 is composed of a laminated sintered body in which a plurality of semiconductor ceramic layers 1a to 1g and a plurality of internal electrode layers 2a to 2f are alternately laminated and fired, and one of the internal electrode layers 2a, 2c, and 2e. Is exposed to one end face of the component element body 1 and is electrically connected to one external electrode 3a, and the other internal electrode layers 2b, 2d, and 2f are exposed to the other end face of the component element body 1. At the same time, it is electrically connected to the other external electrode 3b.

  Microscopically, the semiconductor ceramic layers 1a to 1g are composed of a plurality of crystal grains made of a semiconductor and a grain boundary layer formed around the crystal grains (not shown). The electrostatic capacity is formed through. These are connected in series or in parallel between the opposing surfaces of the internal electrode layers 2a, 2c, and 2e and the internal electrode layers 2b, 2d, and 2f, thereby obtaining a desired capacitance as a whole.

The semiconductor ceramic layers 1a to 1g are made of SrTiO ₃ -based grain boundary insulating semiconductor ceramic. In the semiconductor ceramic, the compound molar ratio m (= Sr site / Ti site) of Sr site and Ti site is 1.000 ≦ m ≦ 1.020, and the donor element is dissolved in the crystal particles. At the same time, the acceptor element is present in the grain boundary layer in the range of 0.5 mol or less (excluding 0 mol) with respect to 100 mol of Ti element, and the Zr element is in an amount of 0.005 mol per 100 mol of Ti element. It is contained in the range of 15 mol or more and 3.0 mol or less, and the average particle size of the crystal particles is 1.5 μm or less.

  As a result, it is possible to obtain a multilayer semiconductor ceramic capacitor with a varistor function suitable for mass production, capable of improving the product yield while ensuring sufficient insulation performance that can withstand practicality, and having good ESD withstand voltage. Can do.

  Next, the reason why the mixing molar ratio m, the content of the acceptor element and the Zr element is within the above ranges will be described in detail.

(1) Mixing molar ratio m
By making the content amount of Sr sites more than the stoichiometric composition (= 1.000), it is possible to suppress the crystal grains from coarsening and to prevent the insulation resistance from decreasing. . That is, by adding Sr in excess of the stoichiometric composition, Sr precipitated in the grain boundary layer without being solid-solved in the crystal particles suppresses the grain growth, thereby obtaining fine crystal grains. Such fine crystal grains are considered to facilitate the formation of a Schottky barrier by making oxygen easily reach the grain boundary layer, thereby preventing the insulation resistance from being lowered.

  In addition, when the blending molar ratio m is a stoichiometric composition, there is no substance that suppresses the grain growth of the ceramic in the grain boundary layer. It is possible to suppress the average particle size to 1.5 μm or less while ensuring the above.

  On the other hand, when the blending molar ratio m exceeds 1.020, Sr that is not solid-dissolved in the crystal particles and precipitates in the grain boundary layer becomes excessive, and it is difficult to improve the product yield even if the Zr element described later is contained. It is.

  Therefore, in the present embodiment, the blending molar ratio m is adjusted to be 1.000 ≦ m ≦ 1.020.

(2) Molar content of acceptor element
By allowing the acceptor element to be present in the grain boundary layer, the grain boundary layer forms an electrically activated energy level (grain boundary level) to promote the formation of a Schottky barrier, thereby insulating resistance. As a result, a multilayer semiconductor ceramic capacitor having good insulation can be obtained.

  However, if the content of the acceptor element exceeds 0.5 mol with respect to 100 mol of Ti element, the ESD withstand voltage is lowered, which is not preferable.

  Therefore, in this embodiment, the acceptor element is included in a range of 0.5 mol or less (excluding 0 mol) with respect to 100 mol of Ti element so as not to cause a decrease in ESD, so that the insulating property is reduced. We are trying to improve.

  In order to obtain a desired capacitance and good insulation (insulation resistance) while ensuring a desired ESD withstand voltage, the acceptor element is 0.3 to 0.5 mol per 100 mol of Ti element. It is preferable to contain in the range.

  Such an acceptor element is not particularly limited as long as it acts as an acceptor, and Mn, Co, Ni, Cr, etc. can be used, but Mn is particularly preferred. used.

(3) Content molar amount of Zr element Although the average crystal grain can be reduced to 1.5 μm or less by adjusting the blending molar ratio m to 1.000 ≦ m ≦ 1.020 as described above, If the blending molar ratio m, the product yield may be reduced.

  In other words, when the molar content of Sr sites is excessive than the stoichiometric composition or the stoichiometric composition, a low-capacitance product with a capacitance of about 1 nF causes a large variation in insulation performance between products when mass-produced. As a result, the product yield decreases and the mass productivity is inferior. This is considered to be because Sr precipitated in the grain boundary layer without being solid-dissolved in the crystal grains slightly inhibits the insulation of the grain boundaries, and becomes prominent as the blending molar ratio m increases.

  Therefore, in this embodiment, the product yield is improved by containing 0.15 mol or more and 3.0 mol or less of Zr element with respect to 100 mol of Ti element.

  That is, according to the research results of the present inventors, even when the blending molar ratio m is 1.000 or more and Sr is not dissolved in the crystal particles but is precipitated in the grain boundary layer, the blending molar ratio m is 1. It was found that the product yield was improved by adding Zr element and heat-treating it if it was .020 or less. This is because the synthesized calcined powder is heat-treated by adding Zr element and segregates Zr to the grain boundary layer, so that Sr precipitated in the grain boundary layer is compensated by Zr, and Sr inhibits the grain boundary insulation. It is because it is thought that it can suppress doing. Thus, it is considered that Zr has an action of compensating Sr precipitated in the grain boundary layer, which makes it possible to improve the product yield.

  For this purpose, the molar content of the Zr element is required to be at least 0.15 mol per 100 mol of the Ti element.

  On the other hand, when the content molar amount of the Zr element exceeds 3.0 mol with respect to 100 mol of Ti, the amount of Sr that segregates in the grain boundary layer and contributes to the atomization of the crystal particles is relatively reduced. As a result, the average particle size of the material becomes coarse, and the deterioration of the insulation becomes remarkable, and the ESD withstand voltage also decreases.

  Therefore, in the present embodiment, the Zr element is contained so as to be 0.15 mol or more and 3.0 mol or less with respect to 100 mol of Ti element.

  The ceramic is made into a semiconductor by dissolving a donor element in crystal grains. That is, the donor element is solid-solved in the crystal particles in order to carry out the firing treatment in a reducing atmosphere to make the ceramic a semiconductor, but the content is not particularly limited. However, when the donor element is less than 0.2 mol with respect to 100 mol of Ti element, there is a risk of causing an excessive decrease in capacitance. On the other hand, if the donor element exceeds 1.2 mol with respect to 100 mol of Ti element, the allowable temperature range of the firing temperature may be narrowed.

  Accordingly, the molar content of the donor element is 0.2 to 1.2 mol, preferably 0.4 to 1.0 mol, per 100 mol of Ti element.

  Such a donor element is not particularly limited. For example, when solidifying the donor element at the Sr site, La, Nd, Sm, Dy, etc. can be used. Nb, Ta, or the like can be used when solidifying the Ti site.

  Moreover, it is also preferable to add a low melting point oxide in the range of 0.1 mole or less to 100 moles of Ti element in the semiconductor ceramic, and by adding such a low melting point oxide, sinterability And the segregation of the acceptor element to the grain boundary layer can be promoted.

  The content of the low melting point oxide is within the above range because when the content exceeds 0.1 mol with respect to 100 mol of Ti element, the electrostatic capacity is excessively lowered, and the desired electrical properties are reduced. This is because characteristics may not be obtained.

As the low-melting-point oxide, is not particularly limited, SiO 2, _B and alkali metal element (K, Li, Na, etc.) glass ceramic containing copper - may be used tungsten salt However, SiO ₂ is preferably used.

  In addition, the average particle diameter of the crystal grains of the semiconductor ceramic can be easily reduced to 1.5 μm or less by controlling the production conditions such as the specific surface area of the Ti compound, the calcination temperature, and the firing temperature in combination with the composition range described above. Can be controlled.

  As described above, in the present embodiment, the semiconductor ceramic forming the semiconductor ceramic layers 1a to 1g has a mixing molar ratio m of Sr sites to Ti sites of 1.000 ≦ m ≦ 1.020, and La, Nd, Donor elements such as Sm, Dy, Nb, and Ta are dissolved in crystal grains, and acceptor elements such as Mn, Co, Ni, and Cr are 0.5 mol or less (preferably, 100 mol of Ti element) , 0.3 to 0.5 mol) in the grain boundary layer, the Zr element is contained in the range of 0.15 to 3.0 mol with respect to 100 mol of Ti element, and the average of crystal grains Since the particle size is 1.5 μm or less, it is possible to improve the product yield while ensuring sufficient insulation performance that can withstand practicality, and to have a good ESD withstand voltage and suitable for mass production. Get a capacitor It is possible.

  Specifically, even if the capacitance is reduced to about 1 nF, it has an ESD withstand voltage of 30 kV or more, an insulation resistance logIR of 8.5 or more, a product yield of 85% or more, and good It is possible to obtain a multilayer semiconductor ceramic capacitor having high reliability and suitable for mass production.

  Next, an embodiment of a method for manufacturing the multilayer semiconductor ceramic capacitor will be described.

First, an Sr compound such as SrCO ₃ as a ceramic raw material, a donor compound containing a donor element such as La or Sm, and TiO having a specific surface area of 10 m ² / g or more (average particle size: about 0.1 μm or less), for example. Prepare a fine Ti compound such as _{2 and} weigh a predetermined amount.

  Next, a predetermined amount (for example, 1 to 3 parts by weight) of a dispersant is added to the weighed product, and the mixture is put into a ball mill together with a grinding medium such as PSZ (Partially Stabilized Zirconia) balls and pure water. Then, the slurry is sufficiently wet-mixed in the ball mill.

  Next, this slurry is evaporated to dryness, and then calcined at a predetermined temperature (for example, 1300 ° C. to 1450 ° C.) for about 2 hours in an air atmosphere to produce a calcined powder in which the donor element is dissolved. .

Next, the Zr compound is weighed so that the Zr element is 0.15 to 3.0 mol with respect to 100 mol of the Ti element, and the molar content of the acceptor element such as Mn or Co is 100 mol with respect to the Ti element. The molar amount of the acceptor compound and further the low melting point oxide such as SiO ₂ is 0 to 0 with respect to 100 mol of Ti element so that it is 0.5 mol or less (preferably 0.3 to 0.5 mol). Weigh to 1 mol. Then, these Zr compound, acceptor compound, low melting point oxide, the calcined powder and pure water, and a dispersant as necessary are added, and again put into the ball mill together with the grinding medium, and sufficiently wet in the ball mill. Mix with. Then, it is evaporated to dryness, and heat treatment is performed at a predetermined temperature (for example, 500 to 700 ° C.) for about 5 hours in an air atmosphere to produce heat treated powder.

  Next, an organic solvent such as toluene and alcohol, an organic binder, an antifoaming agent, a cationic surfactant, and the like are appropriately added to the heat-treated powder and mixed sufficiently wet, thereby obtaining a ceramic slurry.

  Next, the ceramic slurry is formed using a forming method such as a doctor blade method, a lip coater method, a die coater method, etc., and the thickness after firing becomes a predetermined thickness (for example, about 1 to 2 μm). A sheet is produced.

  Next, a transfer using a screen printing method, a gravure printing method, a vacuum deposition method, a sputtering method, or the like is performed on the ceramic green sheet using the conductive paste for internal electrodes, and a predetermined pattern is formed on the surface of the ceramic green sheet. The conductive film is formed.

  The conductive material contained in the internal electrode conductive paste is not particularly limited, but a base metal material having good conductivity such as Ni or Cu is preferably used.

  Next, a plurality of ceramic green sheets on which a conductive film is formed are laminated in a predetermined direction, and an outer layer ceramic green sheet on which a conductive film is not formed is laminated. Is made.

Thereafter, the binder removal treatment is performed at a temperature of 300 to 500 ° C. for about 2 hours in an air atmosphere. Next, a firing furnace having a reducing atmosphere is used so that the H ₂ gas and the N ₂ gas have a predetermined flow ratio (for example, H ₂ / N ₂ = 1/1000 to 1/100). Then, primary firing is performed at a temperature of 1200 to 1250 ° C. for about 2 hours, and the stacked body is made into a semiconductor.

  Thus, by making the calcination temperature (1300 to 1450 ° C.) in the calcination treatment higher than the firing temperature (1200 to 1250 ° C.) in the primary calcination treatment, grain growth of crystal grains is promoted in the primary calcination treatment. There is almost nothing, and it can suppress that a crystal grain coarsens. And a calcination process can be controlled at the time of calcination powder preparation so that the average particle diameter of crystal grains may be 1.5 micrometers or less.

  In addition, when it is desired to increase the average particle size of the crystal grains in the range of 1.5 μm or less during the primary firing treatment, it is possible to set the firing temperature of the primary firing treatment to a high temperature within a range of 1200 to 1250 ° C. is there.

  Even when the firing temperature of the primary firing treatment is higher than the calcining temperature, the average particle size of the crystal particles can be suppressed to 1.5 μm or less by making both temperatures as close as possible. Is possible.

  And after making a laminated body into a semiconductor in this way, it is 1 hour at a low temperature of 600-900 degreeC so that internal electrode materials, such as Ni and Cu, may not oxidize in weak reducing atmosphere, air atmosphere, or oxidizing atmosphere. Secondary firing is performed to the extent. Then, the semiconductor ceramic is reoxidized to form a grain boundary insulating layer, whereby the component body 1 made of a laminated sintered body in which the internal electrode 2 is embedded is manufactured.

  Next, a conductive paste for external electrodes is applied to both ends of the component element body 1 and subjected to a baking treatment to form external electrodes 3a and 3b, whereby a multilayer semiconductor ceramic capacitor is manufactured.

  The external electrodes 3a and 3b may be formed by printing, vacuum vapor deposition, sputtering, or the like. Moreover, after applying the conductive paste for external electrodes to both end portions of the unfired laminate, the firing treatment may be performed simultaneously with the laminate.

  The conductive material contained in the conductive paste for external electrodes is not particularly limited, but it is preferable to use a material such as Ga, In, Ni, or Cu. Further, an Ag electrode is provided on these electrodes. It is also possible to form

  As described above, in this embodiment, the ceramic raw material containing the donor compound is weighed and mixed and pulverized so that the blending molar ratio m of the Sr site and Ti site is in the range of 1.000 ≦ m ≦ 1.020. Then, after calcining to prepare a calcined powder, the Zr compound is weighed so as to be 0.15 mol or more and 3.0 mol or less with respect to 100 mol of Ti element, and the calcined together with a predetermined amount of the acceptor compound. Since heat treatment is performed by mixing with powder, even if the mixing molar ratio m of Sr site and Ti site is a stoichiometric ratio or Sr site is more than the stoichiometric ratio, it is sufficiently practical. Thus, it is possible to obtain a multilayer semiconductor ceramic capacitor suitable for mass production having a good ESD withstand voltage while ensuring a good insulating performance.

  The present invention is not limited to the above embodiment. For example, in the above embodiment, the solid solution is produced by the solid phase method, but the production method of the solid solution is not particularly limited. For example, hydrothermal synthesis method, sol-gel method, hydrolysis method, coprecipitation Any method such as a method can be used.

  Next, examples of the present invention will be specifically described.

[Sample preparation]
SrCO ₃ as ceramic raw materials, specific surface area of ^30m ₂ / g: TiO 2 (average particle size about 30 nm), and LaCl _3, SmCl ₃ as a donor compound and was prepared NdCl _3. Then, the donor compound is weighed so that the content of the donor element is as shown in Table 1 with respect to 100 mol of Ti element, and the blending molar ratio m (= Sr site / Ti site) of Sr site and Ti site is shown in Table 1. SrCO ₃ and TiO ₂ were weighed so that Next, after adding 3 parts by weight of a polycarboxylic acid ammonium salt as a dispersing agent to 100 parts by weight of these weighed products, the mixture was put into a ball mill together with PSZ balls having a diameter of 2 mm and pure water as a grinding medium. A slurry was prepared by wet mixing for a period of time.

  Next, this slurry was evaporated to dryness, and then calcined at 1350 ° C. for 2 hours in an air atmosphere to obtain a calcined powder in which the donor element was solid-solved in the crystal particles.

Next, with respect to the calcined powder, ZrO ₂ is added so that the molar content of Zr element with respect to 100 mol of Ti element is as shown in Table 1, and the content of Mn element with respect to 100 mol of Ti element is as shown in Table 1. MnCO ₃ is added to SiO ₂ , and SiO ₂ is added so that the molar content of SiO ₂ with respect to 100 mol of Ti element is 0.1 mol. Further, the dispersant is added so that the dispersant is 1% by weight. did. Then, it was again put into a ball mill together with PSZ balls having a diameter of 2 mm and pure water, and wet mixed in the ball mill for 16 hours. In place of MnCO ₃ , an MnCl ₂ aqueous solution or MnO ₂ sol may be used. Further, tetraethoxysilane (Si (OC ₂ H ₅ ) ₄ ) may be used instead of SiO ₂ .

  Then, it was evaporated to dryness, and heat treatment was performed at 600 ° C. for 5 hours in an air atmosphere to obtain heat treated powder.

  Next, an appropriate amount of an organic solvent such as toluene and alcohol, and a dispersant were added to the heat-treated powder, and the mixture was again put into a ball mill together with PSZ balls having a diameter of 2 mm, and mixed in the ball mill for 16 hours in a wet manner. And after this, polyvinyl bityral (PVB) as an organic binder, dioctyl phthalate (DOP) as a plasticizer, and an appropriate amount of a cationic surfactant are added and mixed for 1.5 hours in a wet manner. A ceramic slurry was prepared.

  Next, a ceramic green sheet is produced by molding the ceramic slurry using a lip coater method, and then a screen is formed on the ceramic green sheet using a conductive paste for internal electrodes mainly composed of Ni. Printing was performed to form a conductive film having a predetermined pattern on the surface of the ceramic green sheet.

  Next, after laminating a plurality of ceramic green sheets with a conductive film in a predetermined direction, a ceramic green sheet for an outer layer without a conductive film is laminated, and then heated so that the thickness becomes about 0.7 mm. A laminated body in which ceramic green sheets and internal electrodes were alternately laminated was obtained by pressure bonding.

Thereafter, the binder removal treatment is performed in a nitrogen atmosphere at a temperature of 375 ° C. for 2 hours, and then in a reducing atmosphere prepared at a flow rate ratio of H ₂ : N ₂ = 1: 100 at a temperature of 1250 ° C. for 2 hours. The laminate was subjected to primary firing to make the laminate a semiconductor. The firing temperature was set to a temperature at which the CR product was maximized for each sample.

  Next, secondary firing was performed for 1 hour at a temperature of 700 ° C. in an air atmosphere to perform reoxidation treatment, and then the end face was polished to prepare a component body (laminated sintered body). Next, sputtering was performed on both end faces of the component element body to form a three-layered external electrode composed of a Ni—Cr layer, a Ni—Cu layer, and an Ag layer. Next, electrolytic plating was performed to sequentially form a Ni film and a Sn film on the surface of the external electrode, thereby preparing samples Nos. 1 to 19. In addition, the outer diameter dimension of each obtained sample was length L: 1.0mm, width W: 0.5mm, thickness T: 0.5mm, and the number of laminations was ten layers.

(Sample evaluation)
Next, for each of the three samples of sample numbers 1 to 19, resin hardening was performed, and polishing was performed in the width direction of each sample. Next, this polished cross section was chemically etched and observed with a scanning electron microscope (SEM), and this SEM photograph was subjected to image analysis. And based on JIS standard (R1670), it converted into an equivalent circle diameter, the average particle diameter of the crystal grain was calculated | required, the average value of three samples was calculated, and it was set as the average crystal grain diameter.

  Further, with respect to 100 samples, an impedance analyzer (manufactured by Agilent Technologies: HP4194A) was used, and the capacitance was measured under conditions of a frequency of 1 kHz and a voltage of 1 V, and an average value of 100 samples was obtained.

  Furthermore, 100 samples were measured according to ESD immunity test standard IEC61000-4-2 (international standard), applied forward and reverse 10 times, contact discharged to measure ESD withstand voltage, and 100 samples were measured. The average value was obtained.

  For 100 samples, a DC voltage of 50 V was applied for 1 minute, and the insulation resistance IR was measured from the leakage current, and the average value was obtained. Further, for 100 samples, the samples having an insulation resistance of 50 MΩ or more were counted to determine the product yield (%).

  Table 1 shows the compositions and measurement results of sample numbers 1 to 19. The insulation resistance IR has an average value represented by a common logarithm (logIR).

In Sample No. 1, the insulation resistance logIR was as good as 8.9, but the product yield was as low as 58%. This is because the blending molar ratio m is 1.020, but ZrO ₂ is not included, so that excessively blended Sr is precipitated in the grain boundary layer, which prevents the grain boundary from being insulated. Conceivable.

Sample No. 2 has a compounding molar ratio m of 1.020, but the content of ZrO ₂ is as small as 0.10 mol with respect to 100 mol of Ti element. Therefore, for the same reason as Sample No. 1, the insulation resistance logIR Was as good as 8.8, but the product yield was as low as 61%.

Sample No. 6 has an excess of ZrO ₂ content of 3.5 moles with respect to 100 moles of Ti element, so the average crystal grain size is as large as 1.75 μm, so the insulation resistance logIR is reduced to 7.8. In addition, the ESD withstand voltage also deteriorated. This seems to be because Sr precipitated in the crystal layer contributes less to the miniaturization of crystal grains because the molar amount of ZrO ₂ is excessive. In this case, the product yield was also reduced to 51%.

  Sample No. 7 had a blending molar ratio m of 1.025 and exceeded 1.020. Therefore, the insulation resistance logIR was as good as 8.5, but the product yield was as low as 59%. This seems to be because although the Zr element is contained in an amount of 1.5 mol per 100 mol of the Ti element, the compound molar ratio m exceeds 1.020, so that Sr cannot be compensated for by Zr.

Sample No. 8 has a compounding molar ratio m of 1.010, but does not contain ZrO _{2, and} therefore, for the same reason as Sample No. 1, the insulation resistance logIR is as good as 8.9, but the product yield. Was as low as 60%.

  In Sample No. 10, since the Mn element was not included, the insulation resistance logIR was lowered to 7.5, and the product yield was lowered to 48%.

Sample No. 11 had a blending molar ratio m of 1.000 but no ZrO _2, so that the insulation resistance logIR was as good as 8.6, but the product yield was as low as 65%.

  In Sample No. 15, since the molar amount of Mn element was 0.7 mol per 100 mol of Ti element, the ESD withstand voltage was reduced to 10 kV. In this case, the average crystal grain size was as large as 1.81 μm, so that the insulation resistance logIR was reduced to 7.4 and the product yield was also reduced to 49%.

  Sample No. 19 was coarsened with an average crystal grain size of 1.71 μm, the insulation resistance logIR was reduced to 7.6, and the ESD withstand voltage was also reduced to 10 kV. This is probably because Sr that contributes to miniaturization of crystal grains no longer precipitates in the grain boundary layer because the blending molar ratio m is less than 0.995 and 1.000. In this case, the product yield was also reduced to 47%.

  On the other hand, sample numbers 3-5, 9, 12-14, and 16-18 have a molar ratio m of 1.000 to 1.020, and the content of Mn element as an acceptor element is 100 mol of Ti element. 0.3 to 0.5 mol, the content of Zr element is 0.15 to 3.0 mol with respect to 100 mol of Ti element, and the average crystal grain size is 1.50 μm or less, both within the scope of the present invention. Therefore, while the capacitance is a low capacitance of 1.15 to 1.31 nF, the insulation resistance logIR is 8.5 to 8.9, which can ensure insulation performance that can sufficiently withstand practicality, Moreover, it has been found that a desired multilayer semiconductor ceramic capacitor suitable for mass production having an ESD breakdown voltage of 30 kV or more can be obtained with a dramatic improvement in product yield of 85 to 92%.

  A multilayer semiconductor ceramic capacitor with a varistor function suitable for mass production having a good ESD withstand voltage can be achieved while ensuring insulation performance that can withstand practicality.

1 Component body (laminated sintered body)
1a to 1g Semiconductor ceramic layer 2, 2a to 2f Internal electrode 3a, 3b External electrode

Claims (8)

A laminated sintered body formed by alternately laminating a plurality of semiconductor ceramic layers and a plurality of internal electrode layers formed of SrTiO ₃ -based grain boundary insulating semiconductor ceramic, and both ends of the laminated sintered body A multilayer semiconductor ceramic capacitor with a varistor function having an external electrode electrically connected to the internal electrode layer,
In the semiconductor ceramic, the blending molar ratio m of Sr site and Ti site is 1.000 ≦ m ≦ 1.020, the donor element is dissolved in the crystal particles, and the acceptor element is the Ti element 100 Present in the grain boundary layer in a range of 0.5 mol or less (excluding 0 mol) with respect to mol,
Zr element is contained in the range of 0.15 mol or more and 3.0 mol or less with respect to 100 mol of Ti element, and the average particle size of crystal particles is 1.5 μm or less, and the laminate with varistor function Type semiconductor ceramic capacitor.   2. The multilayer semiconductor ceramic capacitor with a varistor function according to claim 1, wherein the acceptor element is contained in a range of 0.3 to 0.5 mol with respect to 100 mol of the Ti element.   3. The multilayer semiconductor ceramic capacitor with a varistor function according to claim 1, wherein the acceptor element contains at least one element selected from the group consisting of Mn, Co, Ni, and Cr.   4. The varistor function according to claim 1, wherein the donor element includes at least one element selected from La, Nd, Sm, Dy, Nb, and Ta. 5. Multilayer semiconductor ceramic capacitor.   The multilayer semiconductor ceramic with a varistor function according to any one of claims 1 to 4, wherein the low melting point oxide is contained in an amount of 0.1 mol or less with respect to 100 mol of the Ti element. Capacitor. The low melting point oxide varistor function stacked semiconductor ceramic capacitor according to claim 5, characterized in that the SiO _2. A method of manufacturing a multilayer semiconductor ceramic capacitor with a varistor function using a SrTiO ₃ -based grain boundary insulating semiconductor ceramic,
The ceramic raw material containing the donor compound is weighed so that the blending molar ratio m of Sr site and Ti site is in the range of 1.000 ≦ m ≦ 1.020, mixed and pulverized, and then calcined. A calcined powder production process for producing a calcined powder;
The acceptor compound is weighed so that it is 0.5 mol or less (excluding 0 mol) with respect to 100 mol of Ti element, and is 0.15 mol or more and 3.0 mol or less with respect to 100 mol of Ti element. A Zr compound is weighed, the Zr compound and the acceptor compound are mixed with the calcined powder, and a heat treatment powder is produced by performing a heat treatment,
Forming a ceramic green sheet by performing a molding process on the heat-treated powder, and then laminating the internal electrode layers and the ceramic green sheet alternately to form a laminate,
A laminate having a varistor function, comprising: a firing step of performing a secondary firing treatment in a reducing atmosphere, an air atmosphere, or an oxidizing atmosphere after performing a primary firing treatment on the laminate in a reducing atmosphere. Type semiconductor ceramic capacitor manufacturing method.   The method for producing a multilayer semiconductor ceramic capacitor with a varistor function according to claim 7, wherein a calcining temperature in the calcining treatment is higher than a firing temperature in the primary firing treatment.

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