KR102619449B1 - A method for forming a semiconductor pattern and a method for manufacturing v-mlcc using the same - Google Patents

Abstract

A method for forming a semiconductor pattern is provided. The semiconductor pattern forming method forms a first patterning layer containing a first material and a second material different from the first material on a substrate, and the first and second materials included in the first patterning layer have a eutectic composition. composition), performing a laser annealing process on the first patterning film to form first and second patterns extending in the first direction, and removing the second pattern using a selective etching process.

Description

Semiconductor pattern formation method and multilayer ceramic capacitor manufacturing method using the same {A METHOD FOR FORMING A SEMICONDUCTOR PATTERN AND A METHOD FOR MANUFACTURING V-MLCC USING THE SAME}

The present invention relates to a method of forming a semiconductor pattern and a method of manufacturing a multilayer ceramic capacitor using the semiconductor pattern forming method.

As technology in the semiconductor field continues to develop, miniaturization, high performance, and high reliability of semiconductor devices are required. In order to achieve miniaturization of semiconductor devices, the spacing between semiconductor patterns is increasingly decreasing.

However, currently, forming nanometer-scale semiconductor patterns can be expensive, such as using extreme ultraviolet photo processes. Therefore, there are difficulties in mass producing semiconductor devices using nanometer-level semiconductor patterns.

For example, a multilayer ceramic condenser (V-MLCC: Vertical Multi Layer Ceramic Condenser) is manufactured using a plating method. At this time, the dielectric film of the multilayer ceramic capacitor is formed by firing a powder-type dielectric material. However, since powder-type dielectric materials have a minimum size of hundreds of nanometers, it is difficult to realistically manufacture patterns smaller than 1 micrometer. On the other hand, when reducing the spacing of the semiconductor pattern using liquid or deposition of dielectric material, the process must be performed step-by-step, resulting in significant loss in time and cost.

The technical problem to be solved by the present invention is to provide a method of forming nanometer-scale semiconductor patterns through a simple process.

Another technical problem to be solved by the present invention is to provide a method of manufacturing a multilayer ceramic capacitor with reduced time and cost using the method of forming the semiconductor pattern.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the description below.

A method of forming a semiconductor pattern according to some embodiments of the present invention for achieving the above technical problem includes forming a first patterning film including a first material and a second material different from the first material on a substrate, and forming the first patterning film on a substrate. The first and second materials included have a eutectic composition, and a laser annealing process is performed on the first patterning film to form first and second patterns extending in the first direction and selective etching. and removing the second pattern using a process.

A method of manufacturing a multilayer ceramic capacitor according to some embodiments of the present invention for achieving the above technical problem includes forming a first patterning film including a first material and a second material different from the first material on a substrate, and forming a first patterning film on a substrate. The first and second materials included in the film have a eutectic composition, and a laser annealing process is performed to form first and second patterns extending in the first direction on the first patterning film and selectively etching the first patterning film. Using a process, the second pattern is removed, a part of the first pattern is removed to form a third pattern, a high-k dielectric film is formed to fill the trench formed by removing a part of the first pattern and the second pattern, and a high-k dielectric film is formed to fill the trench formed by removing the part of the first pattern and the second pattern. It includes forming first and second external electrodes spaced apart in one direction and extending in a second direction intersecting the first direction.

Specific details of other embodiments are included in the detailed description and drawings.

1 is a plan view for explaining a semiconductor pattern according to some embodiments.
Figure 2 is a cross-sectional view taken along line AA' in Figure 1.
3 is an example flowchart illustrating a method of forming a semiconductor pattern according to some embodiments.
4 to 8 are intermediate stage diagrams for explaining a method of forming a semiconductor pattern according to some embodiments.
9 is an example flowchart for explaining a method of forming a semiconductor pattern according to some other embodiments.
FIG. 10 is an exemplary diagram for explaining a multilayer ceramic capacitor according to some embodiments.
Figure 11 is a cross-sectional view taken along line BB' in Figure 10.
12 is an example flowchart for explaining a method of manufacturing a multilayer ceramic capacitor according to some embodiments.
13 to 15 are intermediate stage diagrams for explaining a method of manufacturing a multilayer ceramic capacitor according to some embodiments.

1 is a plan view for explaining a semiconductor pattern according to some embodiments. Figure 2 is a cross-sectional view taken along line A-A' in Figure 1.

Referring to FIGS. 1 and 2 , semiconductor patterns according to some embodiments may be formed on the substrate 100 .

The substrate 100 may include a second material. For example, the second material is silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon oxide (SiO ₂ ), silicon nitride (SiN), gallium nitride ( It may include materials such as GaN), gallium arsenide (GaAs), aluminum (Al), aluminum oxide (Al ₂ O ₃ ), ceramic, quartz, or copper (Cu). However, the embodiments are not limited thereto. For example, the substrate 100 may include multiple layers such as germanium on silicon or silicon on insulator (SOI).

In some embodiments, the substrate 100 may be doped with impurities to become a p-type or n-type semiconductor substrate. In the case of a p-type silicon (Si) substrate, the silicon (Si) substrate is doped with a p-type dopant, for example, boron (B), aluminum (Al), gallium (Ga), and indium (In). It may be doped. In the case of an n-type silicon (Si) substrate, the silicon (Si) substrate may be doped with an n-type dopant, such as antimony (Sb), arsenic (As), and phosphorus (P).

A semiconductor pattern according to some embodiments may include a plurality of first patterns P1 and a plurality of trenches T. The width of the first pattern (P1) in the second direction (Y) may be the first width (W1). The width of the trench T in the second direction Y may be the second width W2. For convenience of explanation, the sum of the first width (W1) and the second width (W2) is defined as the pattern width (W). The pattern width (W) may be determined according to the scanning speed of the laser, which will be described later. A detailed explanation will be provided later.

The first pattern P1 may extend in the first direction (X). The first patterns P1 may be spaced apart in the second direction Y. In other words, the first pattern (P1) may be spaced apart in the second direction (Y) at intervals of the second width (W2) and may extend in the first direction (X). In some embodiments, the first direction (X) may be a direction in which a laser is scanned in a laser annealing process to be described later. A detailed explanation will be provided later.

The trench (T) may extend in the first direction (X). The trenches T may be spaced apart in the second direction Y. In other words, the trenches T may be spaced apart in the second direction Y at intervals of the first width W1 and extend in the first direction X.

In other words, the semiconductor pattern according to some embodiments may have a shape in which the first pattern P1 and the trench T are alternately arranged. Using FIGS. 3 to 8 , a method of forming a semiconductor pattern according to some embodiments will be described.

3 is an example flowchart illustrating a method of forming a semiconductor pattern according to some embodiments. 4 to 8 are intermediate stage diagrams for explaining a method of forming a semiconductor pattern according to some embodiments.

Referring to FIGS. 3 and 4 , the first metal film 110 may be formed on the substrate 100 (S310). The first metal film 110 may be formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. , the embodiments are not limited thereto. When describing the method of forming a semiconductor pattern with reference to FIGS. 3 to 8 , for convenience of explanation, the substrate 100 is described as a silicon (Si) substrate.

According to some embodiments, the first metal film 110 may include a first material. The first material may include at least one of tungsten (W), titanium (Ti), nickel (Ni), platinum (Pt), iridium (Ir), gold (Au), and silver (Ag). For example, the first metal film 110 may include nickel (Ni). For another example, the first metal film 110 may include nickel (Ni) and platinum (Pt). Hereinafter, the description will be made assuming that the first metal film 110 contains nickel (Ni), but the embodiments are not limited thereto. For example, the first metal film 110 may include other metals not mentioned in this specification.

According to some embodiments, the first metal film 110 may be formed to have a first thickness T1. In some embodiments, the height of the first pattern P1 (T4 in FIG. 8) can be adjusted by adjusting the thickness of the first metal film 110, that is, the first thickness T1. A detailed explanation will be provided later.

Referring to FIGS. 3 and 5 , a first heat treatment process may be performed on the first metal film 110 to form the first patterning film 120 (S320).

According to some embodiments, the process temperature of the first heat treatment process may be the first temperature. This may be smaller than the second temperature, which is the process temperature of the second heat treatment process to be described later. A detailed explanation will be provided later.

According to some embodiments, the first patterning layer 120 may include both a first material included in the first metal layer 110 and a second material included in the substrate 100 . In some embodiments, the first patterning layer 120 may have a metal-rich structure. In other words, among the first and second materials included in the first patterning layer 120, the content of the first material may be greater than the content of the second material. For example, the first patterning layer 120 may include Ni ₂ Si, but embodiments are not limited thereto.

The first patterning layer 120 may be formed to have a second thickness T2. The second thickness T2 may be greater than the first thickness (T1 in FIG. 4). In other words, the first patterning layer 120 may be thicker than the first metal layer 110. This means that, through the first heat treatment process, a part of the second material included in the substrate 100 moves to the first metal film 110, forming the first patterning film 120 containing the first material and the second material. This may be because it is formed.

Referring to FIGS. 3 and 6 , a second heat treatment process may be performed on the first patterning film 120 to form the second patterning film 130 (S330).

According to some embodiments, the process temperature of the second heat treatment process may be the second temperature. As described above, the second temperature of the second heat treatment process may be higher than the first temperature of the first heat treatment process. In some embodiments, a heat treatment process is performed on the first metal film 110 at different first and second temperatures to change the surface roughness of the second patterning film 130, such as the surface roughness of the second patterning film 130. Characteristics can be improved. In other words, the second patterning film 130 formed by performing only the second heat treatment process at the second temperature on the first metal film 110 is formed by performing the first heat treatment process at the first temperature and the second heat treatment process at the second temperature. The surface may be rougher than the formed second patterning layer 130.

According to some embodiments, the second patterning layer 130 may include both the first material included in the first metal layer 110 and the second material included in the substrate 100 . In some embodiments, the first and second materials included in the second patterning layer 130 may have a eutectic composition. In other words, the first metal film 110 can form a second patterning film 130 in which the first and second materials have a eutectic composition through a first heat treatment process and a second heat treatment process.

In some embodiments, the second patterning layer 130 may be formed to have a third thickness T3. The third thickness T3 may be greater than the second thickness (T2 in FIG. 5). In other words, the second patterning layer 130 may be thicker than the first patterning layer 120. This is because, through the second heat treatment process, a portion of the second material included in the substrate 100 moves to the first patterning layer 120, and the first and second materials form a second patterning layer 130 having a eutectic composition. ) may be due to the formation of

In some embodiments, forming the second patterning layer 130 through the first and second heat treatment processes has been described, but the embodiments are not limited thereto. For example, the second patterning film 130 can be formed by performing a one-time heat treatment process on the first metal film 110. For another example, the second patterning layer 130 may be formed by performing three or more heat treatment processes on the first metal layer 110. At this time, the process temperature of each heat treatment process may be different. Depending on the number of times the heat treatment process is performed and the process temperature, the surface characteristics of the second patterning layer 130 may change.

Referring to FIGS. 3, 7, and 8, a laser annealing process may be performed on the second patterning film 130 to form a first pattern (P1) and a second pattern (P2) (S340).

In some embodiments, a laser annealing process may be performed by irradiating a laser along the first direction (X) on the second patterning layer 130. The process temperature of the laser annealing process may be a third temperature. The third temperature may be greater than the melting point of the second patterning layer 130. Additionally, the third temperature may be smaller than the melting point of the substrate 100.

In some embodiments, the second patterning layer 130, which has a eutectic composition of the first material and the second material, may be temporarily melted by a laser annealing process. Thereafter, as the temperature of the melted second patterning layer 130 decreases, the second patterning layer 130 may be separated into the first pattern (P1) and the second pattern (P2). The first pattern P1 and the second pattern P2 may extend in the first direction (X). In other words, the first pattern (P1) and the second pattern (P2) may extend along the direction (X) in which the laser is irradiated.

In some embodiments, the first pattern P1 may be formed to have a first width W1, and the second pattern P2 may be formed to have a second width W2. The pattern width (W) may be determined depending on the speed at which the laser is irradiated, that is, the laser scanning speed. In other words, a person skilled in the art can adjust the laser scanning speed to form the first and second patterns (P1, P2) having a desired pattern width (W).

In some embodiments, the first and second patterns P1 and P2 may include first and second materials. In some embodiments, the first and second materials included in the first pattern P1 may have a first composition, and the first and second materials included in the second pattern P2 may have a second composition. The first composition and the second composition may be different from each other. For example, the composition ratio of the second material included in the first pattern P1 may be greater than the composition ratio of the second material included in the second pattern P2. Conversely, the composition ratio of the first material included in the first pattern P1 may be greater than the composition ratio of the first material included in the second pattern P2. For example, the chemical formula of the first pattern (P1) may be NiSi, and the chemical formula of the second pattern (P2) may be NiSi ₂ . For another example, the chemical formula of the first pattern (P1) may be NiSi ₂ and the chemical formula of the second pattern (P2) may be NiSi.

In some embodiments, the first pattern P1 and the second pattern P2 may be formed to have a fourth thickness T4. In some embodiments, the fourth thickness T4 may be greater than the third thickness T3. In other words, the first pattern (P1) and the second pattern (P2) may be thicker than the second patterning layer 130. This may be because part of the second material included in the substrate 100 moves to the second patterning film 130 melted by the laser annealing process, forming the first pattern (P1) and the second pattern (P2). there is. However, the embodiments are not limited thereto. For example, the fourth thickness T4 may be substantially the same as the third thickness T3.

In some embodiments, the fourth thickness T4 may be adjusted by adjusting the first thickness T1 of the first metal film 110. Additionally, in some embodiments, when performing a laser annealing process, the fourth thickness T4 may be adjusted by adjusting the intensity of the laser. In other words, a person skilled in the art of the present invention can adjust the first thickness T1 of the first metal film 110 or adjust the intensity of the laser to create first and second patterns having desired thicknesses. (P1, P2) can be formed.

Referring to FIGS. 2, 3, and 8, in some embodiments, the second pattern P2 may be removed using a selective etching process (S350). In other words, the trench T may be formed by removing the second pattern P2 through a selective etching process. The selective etching process may include a dry etching process, a wet etching process, or a combination thereof. Since the trench T is formed by removing the second pattern P2, the trench T may extend in the first direction X. Accordingly, through the above method, the first pattern P1 extending in the first direction (X) and spaced apart in the second direction (Y) can be formed on the substrate 100.

In some embodiments, the pattern width (W) may be in nanometers (nm). For example, the first width W1 may be 20 nanometers (nm) or less, and the second width W2 may be 35 nanometers (nm) or less, but embodiments are not limited thereto. As described above, those skilled in the art can adjust the pattern width (W) by adjusting the laser scanning speed when performing a laser annealing process according to some embodiments.

With reference to FIGS. 2 and 6 to 9 , a method of forming a semiconductor pattern according to some other embodiments will be described.

9 is an example flowchart for explaining a method of forming a semiconductor pattern according to some other embodiments. For convenience of explanation, redundant content is omitted or briefly explained.

Referring to FIGS. 2 and 6 to 9 , a second patterning layer 130 including a first material and a second material may be formed on the substrate 100 (S910).

In some embodiments, the second patterning layer 130 may be formed using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. At this time, the first material and the second material may have a eutectic composition. In other words, the second patterning film 130 is formed by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process so that the first material and the second material have a eutectic composition. can be formed.

In some embodiments, the second patterning layer 130 may be formed to have a third thickness T3. In other words, the second patterning layer 130 of the third thickness T3 may be formed through a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process. . In some embodiments, the thickness T4 of the first and second patterns P1 and P2 may be adjusted by adjusting the thickness T3 at which the second patterning layer 130 is formed. In other words, those skilled in the art can form the first and second patterns P1 and P2 of desired thickness by adjusting the thickness of the second patterning film 130.

In some embodiments, substrate 100 may be formed of a material different from the second material. For example, when the second material is silicon (Si), the substrate 100 is made of germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon oxide (SiO ₂ ), and silicon nitride ( It may be composed of SiN), gallium nitride (GaN), gallium arsenide (GaAs), aluminum (Al), aluminum oxide (Al ₂ O ₃ ), ceramic, quartz, or copper (Cu), but embodiments are Not limited. For example, the substrate 100 may be a silicon (Si) substrate.

Next, a laser annealing process may be performed on the second patterning film 130 to form the first pattern (P1) and the second pattern (P2) (S920). Next, a selective etching process may be performed to remove the second pattern P2 to form a semiconductor pattern (S930).

Unlike the semiconductor pattern forming method described in FIG. 3, the second patterning film 130 is formed so that the first and second materials have eutectic compositions, so the first and second heat treatment processes may not be necessary. Therefore, when using the semiconductor pattern forming method described using FIG. 9, the process time can be reduced, and thus a low-cost semiconductor pattern can be formed.

10 to 15, application examples of semiconductor devices using semiconductor patterns according to some embodiments will be described.

FIG. 10 is an exemplary diagram for explaining a multilayer ceramic capacitor according to some embodiments. Figure 11 is a cross-sectional view taken along line B-B' in Figure 10. 12 is an example flowchart for explaining a method of manufacturing a multilayer ceramic capacitor according to some embodiments. 13 to 15 are intermediate stage diagrams for explaining a method of manufacturing a multilayer ceramic capacitor according to some embodiments. Hereinafter, for convenience of explanation, content that is duplicated or similar to the content described above will be omitted or briefly described.

10 and 11, a multilayer ceramic condenser (V-MLCC: Vertical Multi Layer Ceramic Condenser) according to some embodiments includes an internal electrode 1110, a high-k layer (1120), and a first and It may include second external electrodes 1130 and 1131.

The internal electrode 1110 according to some embodiments may include the first and second materials described above. For example, the internal electrode 1110 may include nickel (Ni) and silicon (Si), but embodiments are not limited thereto.

The width of the internal electrode 1110 according to some embodiments may be the first width W1. Each of the internal electrodes 1110 may be spaced apart by a second width W2 in the second direction Y. A portion of the internal electrode 1110 may extend in the first direction (X) and be connected to the first external electrode 1130. Another part of the internal electrode 1110 may extend in the first direction (X) and be connected to the second external electrode 1131. In other words, the internal electrode 1110 may be connected to only one of the first external electrode 1130 and the second external electrode 1131. In some embodiments, the internal electrode 1110 connected to the first external electrode 1130 and the internal electrode 1110 connected to the second external electrode 1131 are separated by a second width W2 along the second direction Y. They can be spaced apart and placed alternately.

The high-k dielectric layer 1120 according to some embodiments may include a material with a dielectric constant greater than silicon oxide (SiO ₂ ). For example, the high dielectric layer 1120 is made of hafnium oxide (HfO ₂ ), hafnium oxy nitride (HfON), hafnium silicon oxide (HfSiO _x ), lanthanum oxide (La ₂ O ₃ ), and lanthanum aluminum oxide (LaAlO _{3 )} , _{zirconium oxide} ( _{ZrO 2 )} , zirconium silicon _oxide ( _ZrSi oxide (SrTiO ₃ ), yttrium oxide (Y ₂ O ₃ ), aluminum oxide (Al ₂ O ₃ ), lead scandium tantalum oxide (Pb ₂ ScTaO ₆ ), lead zinc niobiumate (Pb(Zn _1/3 Nb) It may include at least one of _2/3 )O ₃ ), and combinations thereof, but the embodiments are not limited thereto.

The width of the high-k dielectric layer 1120 according to some embodiments may be the second width W2. The high dielectric film 1120 may be formed between the internal electrodes 1110, between the internal electrode 1110 and the first external electrode 1130, and between the internal electrode 1110 and the second external electrode 1131. . In other words, the high-dielectric film 1120 may be formed between the internal electrodes 1110. Additionally, the high-k dielectric film 1120 may be formed in a portion where the internal electrode 1110 and the first and second external electrodes 1130 and 1131 are not connected. Next, with reference to FIGS. 11 to 14 , a method of manufacturing a multilayer ceramic capacitor according to some embodiments will be described.

When manufacturing a multilayer ceramic capacitor according to some embodiments, the semiconductor pattern forming method described using FIG. 3 or FIG. 9 may be used.

Referring to FIGS. 12 and 13 , a first pattern (P1) extending in the first direction (X) and a second pattern (P2) extending in the first direction (X) may be formed alternately (S1210). . For example, the first and second patterns P1 and P2 may be formed through steps S310 to S340 of FIG. 3 . For another example, the first and second patterns P1 and P2 may be formed through steps S910 and S920 of FIG. 9 .

Next, the second pattern P2 can be removed using a selective etching process (S1220). In other words, the trench T shown in FIGS. 1 and 2 can be formed by removing the second pattern P2. At this time, the first pattern P1 may extend in the first direction (X) and may be arranged to be spaced apart by a second width (W2) in the second direction (Y). As described above, the selective etching process may include a dry etching process, a wet etching process, or a combination thereof.

Referring to FIGS. 12 and 14 , a portion of the first pattern P1 may be removed to form the third pattern P3. The third pattern P3 may function as an internal electrode 1110 (S1230). In other words, the first trench TR may be formed by alternately removing one side and the other side of the first pattern P1 in the first direction (X). At this time, the first pattern (P1) from which a portion of the side surface in the first direction (X) is removed is defined as the third pattern (P3).

Referring to FIGS. 12 and 15 , a high-k dielectric layer 1120 may be formed to fill the first trench TR (S1240).

Referring to FIGS. 11 and 12 , both side surfaces of the multilayer ceramic capacitor in the first direction (X) may be removed, and first and second external electrodes 1130 and 1131 may be formed (S1250). In other words, a portion of the third pattern P3 and a portion of the high dielectric layer 1120 may be removed to form the first and second external electrodes 1130 and 1131. In some embodiments, the first and second external electrodes 1130 and 1131 may be formed such that the internal electrode 1110 is connected to only one of the first and second external electrodes 1130 and 1131.

In some embodiments, a method of manufacturing a multilayer ceramic capacitor in the order shown in FIG. 12 has been described, but the embodiments are not limited thereto. In some other embodiments, the multilayer ceramic capacitor may be manufactured in a different order than that of FIG. 12. For example, before forming the first and second patterns P1 and P2, the first and second external electrodes 1130 and 1131 may be formed.

Although embodiments of the present invention have been described above with reference to the attached drawings, the present invention is not limited to the above embodiments and can be manufactured in various different forms, and can be manufactured in various different forms by those skilled in the art. It will be understood by those who understand that the present invention can be implemented in other specific forms without changing its technical spirit or essential features. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

100: substrate 110: first metal film
120: first patterning layer 130: second patterning layer
1110: internal electrode 1120: high dielectric film
1130, 1131: first and second external electrodes

Claims (10)

A first patterning layer is formed on a substrate, including a first material and a second material different from the first material, and the first and second materials included in the first patterning layer have a eutectic composition. With
Performing a laser annealing process on the first patterning film to form first and second patterns extending in a first direction,
Including removing the second pattern using a selective etching process,
A method of forming a semiconductor pattern, wherein each of the first pattern and the second pattern includes a silicide material. According to clause 1,
Forming a first metal film containing the first material on the substrate,
A method of forming a semiconductor pattern further comprising forming the first patterning layer by performing a heat treatment process on the first metal layer. According to clause 2,
The heat treatment process includes a first heat treatment process of forming the first metal film into a second patterning film, and a second heat treatment process of forming the second patterning film into the first patterning film, and a process of the first heat treatment process. A method of forming a semiconductor pattern where the temperature is lower than the process temperature of the second heat treatment process. According to clause 3,
Wherein the first metal film includes at least one of tungsten (W), titanium (Ti), nickel (Ni), platinum (Pt), iridium (Ir), gold (Au), and silver (Ag). . According to clause 1,
The process temperature of the laser annealing process is higher than the melting point of the first patterning film and lower than the melting point of the substrate. According to clause 1,
The laser annealing process includes scanning a laser along the first direction,
A method of forming a semiconductor pattern in which the widths of the first and second patterns are determined according to the scanning speed of the laser. According to clause 1,
The first material includes at least one of tungsten (W), titanium (Ti), nickel (Ni), platinum (Pt), iridium (Ir), gold (Au), and silver (Ag), and the second A method of forming a semiconductor pattern where the material includes silicon (Si). A first patterning layer is formed on a substrate, including a first material and a second material different from the first material, and the first and second materials included in the first patterning layer have a eutectic composition. With
Performing a laser annealing process to form first and second patterns extending in a first direction on the first patterning film,
Using a selective etching process, the second pattern is removed,
Forming a third pattern by removing part of the first pattern,
Forming a high-k dielectric layer that fills a trench formed by removing a portion of the first pattern and the second pattern,
and forming first and second external electrodes spaced apart in the first direction and extending in a second direction intersecting the first direction,
A method of manufacturing a multi-layer ceramic condenser (MLCC), wherein each of the first pattern and the second pattern includes a silicide material. According to clause 8,
Forming a first metal film on the substrate,
A method of manufacturing a multilayer ceramic capacitor further comprising performing a heat treatment process on the first metal film to form the first patterning film. According to clause 9,
The first material includes at least one of tungsten (W), titanium (Ti), nickel (Ni), platinum (Pt), iridium (Ir), gold (Au), and silver (Ag), and the second material A method of manufacturing a multilayer ceramic capacitor where the material includes silicon (Si).