JP5835627B2 - Circuit equipment - Google Patents

Description

  The present invention relates to a circuit device, and more particularly to a circuit device that operates using a plurality of asynchronous clocks.

  Conventionally, in a transmission apparatus that transmits SDH (Synchronous Digital Hierarchy) / SONET (Synchronous Optical NETwork) / ETHERNET (registered trademark) signals, an SDH / SONET system, an ETHERNET system, and a control system using one application specific integrated circuit (ASIC) Several systems are operating. Since these systems have different operating frequencies, a plurality of clocks having different frequencies are input to the ASIC (see, for example, Patent Document 1).

JP 2006-31133 A

  Normally, the ASIC detects an abnormality of the input clock using a clock interruption detection circuit, but it is difficult for the clock interruption detection circuit to detect an abnormality unless the interruption state continues for several clocks. In addition, since the frequency monitoring circuit for detecting an instantaneous interruption of a clock or an instantaneous frequency abnormality of the clock has a large circuit scale, it is difficult to provide a frequency monitoring circuit for each input clock in the ASIC.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a technique capable of easily detecting a clock abnormality in a control circuit that operates using a plurality of asynchronous clocks.

  In order to solve the above problem, a circuit device according to an aspect of the present invention includes a receiving unit that receives a first clock having a first frequency and a second clock having a second frequency that is higher than the first frequency and asynchronous. A counting unit that counts rising or falling edges of the second clock in one high level period or low level period of the first clock, and an abnormality in the first clock and / or the second clock based on the count value of the counting unit And an abnormality detection unit for detecting.

  It should be noted that any combination of the above-described constituent elements and a representation of the present invention converted between an apparatus, a method, a system, a program, a recording medium storing the program, etc. are also effective as an aspect of the present invention.

  According to the present invention, it is possible to easily detect a clock abnormality in a control circuit that operates using a plurality of asynchronous clocks.

It is a figure which shows the structure of the package in which ASIC which concerns on embodiment of this invention was mounted. It is a figure for demonstrating operation | movement of ASIC which concerns on this embodiment. It is a figure for demonstrating the count value m of a count part. FIGS. 4A and 4B are diagrams showing the first clock and the second clock when 1 <f2 / f1 <2. FIGS. 5A and 5B are diagrams showing the first clock and the second clock when 2 ≦ f2 / f1 <3. FIGS. 6A to 6D are diagrams illustrating the first clock and the second clock when 3 ≦ f2 / f1 <4. It is a figure for demonstrating another operation | movement of ASIC which concerns on this embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 shows a configuration of a package 100 on which an ASIC 10 according to an embodiment of the present invention is mounted. The package 100 is inserted into a slot of a shelf (not shown) and performs main signal processing. For example, the package 100 may be a package that processes an ETHERNET signal input from a client line and outputs it as an SDH / SONET signal.

  The package 100 includes an ASIC 10 that processes a main signal, and a first oscillator 21 and a second oscillator 22 that supply an operation clock to the ASIC 10.

  The first oscillator 21 supplies the ASIC 10 with the first clock CLK1 having the first frequency f1 (Hz). The second oscillator 22 supplies the second clock CLK2 having the second frequency f2 (Hz) to the ASIC 10. The first clock CLK1 and the second clock CLK2 are asynchronous. The second frequency f2 of the second clock CLK2 is higher than the first frequency f1 of the first clock CLK1. For example, when the ASIC 10 processes the ETHERNET signal and the SDH / SONET signal, the first oscillator 21 supplies the first clock CLK1 having the first frequency f1 = 155 MHz for processing the SDH / SONET signal, and the second oscillator 22 The second clock CLK2 having the second frequency f2 = 200 MHz is supplied for processing the ETHERNET signal.

  The ASIC 10 includes a reception unit 11, a count unit 12, an abnormality detection unit 13, an alarm unit 14, a reset unit 15, and a main signal processing unit 20.

  The receiving unit 11 receives the first clock CLK1 from the first oscillator 21 and the second clock CLK2 from the second oscillator 22.

  The count unit 12 counts rising edges of the second clock in one high level period of the first clock CLK1. The count value m of the count unit 12 is sent to the abnormality detection unit 13.

  The abnormality detection unit 13 detects an abnormality in the first clock CLK1 and / or the second clock CLK2 based on the count value m of the counting unit 12. More specifically, when the count value m of the count unit 12 is not a predetermined value determined by the first frequency f1 and the second frequency f2, the abnormality detection unit 13 has an abnormality in the first clock CLK1 and / or the second clock CLK2. It is determined that it has occurred.

  The alarm unit 14 issues an alarm to the host device when the abnormality detection unit 13 detects an abnormality of the first clock CLK1 and / or the second clock CLK2.

  The reset unit 15 resets the ASIC 10 when the abnormality detection unit 13 detects an abnormality in the first clock CLK1 and / or the second clock CLK2. When an abnormality such as a momentary interruption occurs in the first clock CLK1 and / or the second clock CLK2, the ASIC 10 may be in a deadlock state. In such a case, resetting the ASIC 10 by the reset unit 15 can prevent the deadlock state from continuing for a long time.

  The main signal processing unit 20 performs a predetermined process on the main signal input from the outside and then outputs it. For example, the main signal processing unit 20 may process an input ETHERNET signal and output it as an SDH / SONET signal. The main signal processing unit 20 performs main signal processing using the first clock CLK1 and the second clock CLK2 received by the receiving unit 11 as operation clocks.

  FIG. 2 is a diagram for explaining the operation of the ASIC 10 according to the present embodiment. As shown in FIG. 2, the count unit 12 counts rising edges of the second clock in one high level period of the first clock CLK1. Even if the first clock CLK1 and the second clock CLK2 are asynchronous, since the first frequency f1 and the second frequency f2 are determined by each oscillator, the count value m of the count unit 12 is the first frequency f1 and the second frequency f2. The predetermined value is determined by the frequency f2. Therefore, if the count value m of the count unit 12 is a predetermined value, it can be determined that no abnormality such as a momentary interruption has occurred in the first clock CLK1 and the second clock CLK2. On the other hand, when the count value m of the count unit 12 is not a predetermined value, it can be determined that an abnormality such as a momentary interruption has occurred in the first clock CLK1 and / or the second clock CLK2.

  FIG. 3 is a diagram for explaining the count value m of the count unit 12. In this embodiment, since the first clock CLK1 and the second clock CLK2 are asynchronous, the timing of the rising edge of the first clock CLK1 and the timing of the rising edge of the second clock CLK2 may match as shown in FIG. is there. In such a case, the level of the first clock CLK1 becomes unstable at the rising edge of the second clock CLK2. That is, it cannot be determined whether the first clock CLK1 is at the high level or the low level at the rising edge of the second clock CLK2. The same thing occurs when the timing of the falling edge of the first clock CLK1 coincides with the timing of the rising edge of the second clock CLK2. Therefore, the count value m of the count unit 12 increases or decreases depending on the phase relationship between the first clock CLK1 and the second clock CLK2.

  Therefore, in the ASIC 10 according to the present embodiment, a clock abnormality determination is performed as follows. First, the abnormality detection unit 13 calculates f2 / f1-1 (truncated after the decimal point) (this is assumed to be X). Then, the abnormality detection unit 13 considers the increase / decrease in the count value m caused by the level indefinite region, and when the count value m is any one of X, X-1, and X + 1, the first clock CLK1 and the second clock It is determined that CLK2 is normal. On the other hand, the abnormality detection unit 13 determines that an abnormality has occurred in the first clock CLK1 and / or the second clock CLK2 when the count value m is not any of X, X-1, and X + 1. By using such a determination method, the determination accuracy of clock abnormality can be improved.

  However, when the first frequency f1 and the second frequency f2 are close, the number of rising edges of the second clock CLK2 that can be counted in one high level period of the first clock CLK1 is limited. Judgment may not be possible. This point will be described below.

  FIGS. 4A and 4B show the first clock CLK1 and the second clock CLK2 when 1 <f2 / f1 <2. Here, the first frequency f1 = 155 MHz and the second frequency f2 = 200 MHz. In this case, since f2 / f1-1 = 200 / 155-1≈0.2903, when the decimal part is rounded down, X = 0. Therefore, in the above determination method, if the count value m is -1, 0, 1, it is normal, and if the count value m is not -1, 0, 1, it is abnormal.

  FIG. 4A shows a case where the first clock CLK1 and the second clock CLK2 are normal. In this case, as shown in FIG. 4A, the number of rising edges of the second clock CLK2 counted during one high level period of the first clock CLK1 is 0 or 1. When the above-described method is used, it is determined that the first clock CLK1 and the second clock CLK2 are normal.

  FIG. 4B shows a case where one clock loss has occurred in the first clock CLK1. Also in this case, the number of rising edges of the second clock CLK2 counted during one high level period of the first clock CLK1 is 0 or 1. Therefore, when the above-described method is used, it is determined that the first clock CLK1 and the second clock CLK2 are normal despite the occurrence of clock omission in the second clock CLK2. Thus, when 1 <f2 / f1 <2, the above determination method cannot be used.

  FIGS. 5A and 5B show the first clock CLK1 and the second clock CLK2 when 2 ≦ f2 / f1 <3. Here, the first frequency f1 = 155 MHz and the second frequency f2 = 400 MHz. In this case, since f2 / f1-1 = 400 / 155-1≈1.5806, if the decimal part is rounded down, X = 1. Therefore, when the above determination method is used, it is normal if the count value m is 0, 1, or 2, and it is abnormal if the count value m is 0, 1, or 2.

  FIG. 5A shows a case where the first clock CLK1 and the second clock CLK2 are normal. In this case, as shown in FIG. 5A, the number of rising edges of the second clock CLK2 counted during one high level period of the first clock CLK1 is one or two. When the above-described method is used, it is determined that the first clock CLK1 and the second clock CLK2 are normal.

  FIG. 5B shows a case where one clock is lost in the first clock CLK1. Also in this case, the number of rising edges of the second clock CLK2 counted during one high level period of the first clock CLK1 is either 0, 1, or 2. Therefore, when the above-described method is used, it is determined that the first clock CLK1 and the second clock CLK2 are normal despite the occurrence of clock omission in the second clock CLK2. Thus, when 2 ≦ f2 / f1 <3, the above determination method cannot be used.

  6A to 6D show the first clock CLK1 and the second clock CLK2 when 3 ≦ f2 / f1 <4. Here, the first frequency f1 = 155 MHz and the second frequency f2 = 600 MHz. In this case, since f2 / f1-1 = 600 / 155-1≈2.8709, when the decimal part is rounded down, X = 2. Therefore, when the above determination method is used, it is normal if the count value m is 1, 2 or 3, and it is abnormal if the count value m is 1, 2, or 3.

  FIG. 6A shows a case where the first clock CLK1 and the second clock CLK2 are normal. In FIG. 6A, the number of rising edges of the second clock CLK2 counted during one high level period of the first clock CLK1 is two. FIG. 6B also shows a case where the first clock CLK1 and the second clock CLK2 are normal. FIG. 6B is different from FIG. 6A in the phase relationship between the first clock CLK1 and the second clock CLK2. In FIG. 6B, the rising edge of the first clock CLK1 matches the rising edge of the second clock CLK2, and the falling edge of the first clock CLK1 matches the rising edge of the second clock CLK2. In this case, since it is uncertain whether the rising edge and the falling edge of the first clock CLK1 are determined as high level or low level, the second clock CLK2 counted during one high level period of the first clock CLK1. The number of rising edges is 1, 2, or 3. When the above-described method is used in FIGS. 6A and 6B, it is determined that the first clock CLK1 and the second clock CLK2 are normal.

  FIG. 6C shows a case where one clock is lost in the first clock CLK1. In FIG. 6C, the number of rising edges of the second clock CLK2 counted during one high level period of the first clock CLK1 is two. FIG. 6D also shows a case where one clock loss occurs in the first clock CLK1. FIG. 6D is different from FIG. 6C in the phase relationship between the first clock CLK1 and the second clock CLK2. In FIG. 6D, the rising edge of the first clock CLK1 matches the rising edge of the second clock CLK2, and the falling edge of the first clock CLK1 matches the rising edge of the second clock CLK2. In this case, the count value m is 0 at the location where the clock loss has occurred. That is, since the number of rising edges of the second clock CLK2 counted during one high level period of the first clock CLK1 does not become one of 1, 2, or 3, the abnormality of the first clock CLK1 can be detected.

  As described above, the range of 1 <f2 / f1 <3 has been considered, but the above determination method is also effective for the range of 4 ≦ f2 / f1. Therefore, in summary, the above determination method is effective when f2 / f1 is 3 or more.

  In the above description, the case where one clock omission occurs in the first clock CLK1 has been described, but an abnormality can be detected in the same manner when a plurality of omissions occur in the first clock CLK1. In addition, even when the second clock CLK2 is missing, the count value m is different from any of X, X-1, and X + 1, so that an abnormality can be detected.

  In the present embodiment, when f2 / f1 is less than 3, the count unit 12 divides the first clock CLK1 so that f2 / f1 is 3 or more, and one high frequency of the divided first clock CLK1. The rising edge of the second clock CLK2 in the level period is counted. Thereby, the abnormality detection part 13 can determine the abnormality of a clock suitably using said determination method.

  Further, when f2 / f1 is less than 3, the count unit 12 multiplies the second clock CLK2 so that f2 / f1 is 3 or more, and the multiplied second clock CLK1 is multiplied in one high level period. The rising edges of the two clocks CLK2 may be counted. Also in this case, the abnormality detection unit 13 can preferably determine the clock abnormality using the above-described determination method.

  When f2 / f1 is less than 3, the count unit 12 divides the first clock CLK1 and multiplies the second clock CLK2 so that f2 / f1 is 3 or more, and the divided first clock The rising edge of the multiplied second clock in one high level period of CLK1 may be counted.

  FIG. 7 is a diagram for explaining another operation of the ASIC 10 according to the present embodiment. As shown in FIG. 7, the counting unit 12 may count the falling edge of the second clock in one high level period of the first clock CLK1. Also in this case, the abnormality of the first clock CLK1 and / or the second clock CLK2 can be determined by determining whether the count value n of the count unit 12 is any of X, X-1, and X + 1.

  Further, the count unit 12 may count the falling edge or the rising edge of the second clock in one low level period of the first clock CLK1. Similarly to the above, the abnormality of the first clock CLK1 and / or the second clock CLK2 can be determined.

  As described above, the ASIC 10 according to the present embodiment has a simple configuration that only counts the rising or falling edge of the second clock CLK2 in one high level period or low level period of the first clock CLK1. The abnormality of the first clock CLK1 and / or the second clock CLK2 can be detected. When a clock abnormality is detected, the ASIC 10 is reset by the reset unit 15, so that the deadlock state can be avoided for a long time, and the package 100 can be operated stably.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications are possible depending on the combination of each component and each processing process, and such modifications are within the scope of the present invention. is there.

  For example, in the above-described embodiment, there are two input clocks, but a plurality of asynchronous clocks may be input to the ASIC.

    10 ASIC, 11 receiving unit, 12 counting unit, 13 abnormality detecting unit, 14 alarm unit, 15 reset unit, 20 main signal processing unit, 21 first oscillator, 22 second oscillator, 100 package.

Claims (6)

A receiving unit that receives a first clock of a first frequency and a second clock of a second frequency that is higher than the first frequency and asynchronous;
A counting unit for counting rising or falling edges of the second clock in one high level period or low level period of the first clock;
An abnormality detection unit that detects an abnormality of the first clock and / or the second clock based on a count value of the counting unit;
Equipped with a,
The abnormality detecting unit determines that an abnormality has occurred in the first clock and / or the second clock when the count value of the counting unit is not a predetermined value determined by the first frequency and the second frequency;
When the first frequency is f1, the second frequency is f2, and f2 / f1-1 (truncated after the decimal point) is X,
The abnormality detecting unit determines that an abnormality has occurred in the first clock and / or the second clock when the count value of the counting unit is not any of X, X-1, and X + 1. Circuit device. When the f2 / f1 is less than 3, the count unit divides the first clock so that f2 / f1 is 3 or more, and one high level period or a low level of the divided first clock. 2. The circuit device according to claim 1 , wherein a rising edge or a falling edge of the second clock in a level period is counted. When f2 / f1 is less than 3, the counting unit multiplies the second clock so that f2 / f1 is 3 or more, and multiplies in one high level period or low level period of the first clock. 2. The circuit device according to claim 1 , wherein a rising edge or a falling edge of the second clock is counted. When f2 / f1 is less than 3, the count unit divides the first clock and multiplies the second clock so that f2 / f1 is 3 or more, and the divided first clock is divided. 2. The circuit device according to claim 1 , wherein the rising or falling edge of the second clock multiplied in one high level period or low level period is counted. If an abnormality of the first clock and / or said second clock is detected by the abnormality detection unit, according to claims 1, further comprising a reset unit for resetting the circuit arrangement in any one of the 4 Circuit device. If the abnormality by the detection unit of the first clock and / or said second clock abnormality is detected, the circuit according to any of claims 1 5, characterized in that it comprises further an alarm unit to issue an alarm apparatus.

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