JP5823515B2 - 圧縮されたスーパータイル画像をディスプレイすること - Google Patents

圧縮されたスーパータイル画像をディスプレイすること Download PDF

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JP5823515B2
JP5823515B2 JP2013520236A JP2013520236A JP5823515B2 JP 5823515 B2 JP5823515 B2 JP 5823515B2 JP 2013520236 A JP2013520236 A JP 2013520236A JP 2013520236 A JP2013520236 A JP 2013520236A JP 5823515 B2 JP5823515 B2 JP 5823515B2
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frame
supertile
tile
frames
super
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Japanese (ja)
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JP2013541746A (ja
JP2013541746A5 (enExample
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グレン デイビッド
グレン デイビッド
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ATI Technologies ULC
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ATI Technologies ULC
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/363—Graphics controllers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T15/00—3D [Three Dimensional] image rendering
    • G06T15/005—General purpose rendering architectures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T9/00—Image coding
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2340/00—Aspects of display data processing
    • G09G2340/02—Handling of images in compressed format, e.g. JPEG, MPEG
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/06—Use of more than one graphics processor to process data before displaying to one or more screens
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/122—Tiling
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
    • H04N19/59—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Computer Graphics (AREA)
  • Multimedia (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
  • Image Generation (AREA)
JP2013520236A 2010-07-19 2011-07-19 圧縮されたスーパータイル画像をディスプレイすること Active JP5823515B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US36570610P 2010-07-19 2010-07-19
US61/365,706 2010-07-19
PCT/IB2011/002209 WO2012010968A1 (en) 2010-07-19 2011-07-19 Displaying compressed supertile images

Publications (3)

Publication Number Publication Date
JP2013541746A JP2013541746A (ja) 2013-11-14
JP2013541746A5 JP2013541746A5 (enExample) 2014-09-11
JP5823515B2 true JP5823515B2 (ja) 2015-11-25

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JP2013520236A Active JP5823515B2 (ja) 2010-07-19 2011-07-19 圧縮されたスーパータイル画像をディスプレイすること

Country Status (6)

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US (1) US9064468B2 (enExample)
EP (1) EP2596491B1 (enExample)
JP (1) JP5823515B2 (enExample)
KR (1) KR101692460B1 (enExample)
CN (1) CN103026402B (enExample)
WO (1) WO2012010968A1 (enExample)

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US10163180B2 (en) * 2015-04-29 2018-12-25 Qualcomm Incorporated Adaptive memory address scanning based on surface format for graphics processing
US11150943B2 (en) * 2017-04-10 2021-10-19 Intel Corporation Enabling a single context hardware system to operate as a multi-context system
US10950305B1 (en) * 2018-11-02 2021-03-16 Facebook Technologies, Llc Selective pixel output
CN114651304A (zh) * 2019-09-13 2022-06-21 光场实验室公司 光场显示系统
US11127107B2 (en) * 2019-09-30 2021-09-21 Intel Corporation Apparatus and method for real time graphics processing using local and cloud-based graphics processing resources
US12112394B2 (en) 2020-02-03 2024-10-08 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against screen regions using configurable shaders
EP4100922A1 (en) * 2020-02-03 2022-12-14 Sony Interactive Entertainment Inc. System and method for efficient multi-gpu rendering of geometry by pretesting against interleaved screen regions before rendering
US11170461B2 (en) 2020-02-03 2021-11-09 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by performing geometry analysis while rendering
US11080814B1 (en) 2020-02-03 2021-08-03 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against screen regions using prior frame information
US11514549B2 (en) 2020-02-03 2022-11-29 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by generating information in one rendering phase for use in another rendering phase
CN117618883B (zh) * 2020-02-03 2025-04-11 索尼互动娱乐股份有限公司 用于图形处理的方法、计算机可读介质及计算机系统
US11508110B2 (en) 2020-02-03 2022-11-22 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by performing geometry analysis before rendering
US11120522B2 (en) 2020-02-03 2021-09-14 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by subdividing geometry
US11321800B2 (en) 2020-02-03 2022-05-03 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by region testing while rendering
US11263718B2 (en) 2020-02-03 2022-03-01 Sony Interactive Entertainment Inc. System and method for efficient multi-GPU rendering of geometry by pretesting against in interleaved screen regions before rendering
EP4100923A1 (en) * 2020-02-03 2022-12-14 Sony Interactive Entertainment Inc. System and method for efficient multi-gpu rendering of geometry by geometry analysis while rendering
US20250022095A1 (en) * 2023-07-12 2025-01-16 Microsoft Technology Licensing, Llc Upscaling video data

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JPH04245865A (ja) * 1991-01-31 1992-09-02 Toshiba Corp 画像処理装置
JP3238584B2 (ja) * 1993-12-16 2001-12-17 松下電器産業株式会社 マルチウィンドウ装置
US6630933B1 (en) * 2000-09-01 2003-10-07 Ati Technologies Inc. Method and apparatus for compression and decompression of Z data
JP2003143599A (ja) * 2001-10-30 2003-05-16 Mitsubishi Electric Corp 画像伝送装置および画像伝送方法
US8933945B2 (en) 2002-11-27 2015-01-13 Ati Technologies Ulc Dividing work among multiple graphics pipelines using a super-tiling technique
US9108107B2 (en) * 2002-12-10 2015-08-18 Sony Computer Entertainment America Llc Hosting and broadcasting virtual events using streaming interactive video
US8111928B2 (en) * 2003-02-13 2012-02-07 Ati Technologies Ulc Method and apparatus for compression of multi-sampled anti-aliasing color data
CN1472704A (zh) * 2003-06-27 2004-02-04 上海龙贝信息科技有限公司 二维条形码数字图像信息的增强方法
US7075541B2 (en) 2003-08-18 2006-07-11 Nvidia Corporation Adaptive load balancing in a multi-processor graphics processing system
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Also Published As

Publication number Publication date
EP2596491A4 (en) 2015-03-04
CN103026402B (zh) 2017-03-29
CN103026402A (zh) 2013-04-03
EP2596491B1 (en) 2017-08-30
US9064468B2 (en) 2015-06-23
KR20130132752A (ko) 2013-12-05
KR101692460B1 (ko) 2017-01-03
JP2013541746A (ja) 2013-11-14
US20120162250A1 (en) 2012-06-28
WO2012010968A1 (en) 2012-01-26
EP2596491A1 (en) 2013-05-29

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