JP5817860B2 - Multi-core processor system, multi-core processor system control method, and multi-core processor system control program - Google Patents

Description

  The present invention relates to a multi-core processor system for controlling a memory controller, a control method for the multi-core processor system, and a control program for the multi-core processor system.

  2. Description of the Related Art Conventionally, as a memory accessed from a plurality of CPUs (Central Processing Units), a technology of a multi-port memory having a plurality of memory banks capable of storing data and a plurality of input / output ports enabling data input / output It has been known. A technique using a memory controller is also known as a device for controlling a memory when the CPU reads and writes data in the memory. As a function of the memory controller, there is a technology that provides a buffer mechanism between the memory and the bus or between the CPU and the bus, temporarily holds data in the buffer, and has a function of automatically branching to the branch destination port (See, for example, Patent Document 1 below).

  In addition, there is a technology that allows the CPU to move immediately to the next processing by separating the request and response paths to the memory, and in response to a request from the CPU, the memory controller that controls the multiport memory returns a dummy response immediately. (See, for example, Patent Document 2 below).

  In addition, as a technology that uses multiports, a technology that divides the address space into function types and prepares a port for each divided address space, so that multiple functions can be executed simultaneously and processing can be executed at high speed. Is disclosed (for example, see Patent Document 3 below).

Japanese National Patent Publication No. 11-510285 JP 2008-117109 A JP 2003-114797 A

  However, in the above-described conventional technique, in the technique according to Patent Document 1, latency on the path can be minimized by setting a high clock between the memory and the buffer and between the bus and the buffer. However, the technique according to Patent Document 1 has a problem that the power consumption is increased by using a high clock. Further, the technology according to Patent Document 2 has a problem that access contention continues even if the request and response paths are separated. Further, similarly to the technique according to Patent Document 1, there is a problem in that power consumption increases because a high clock is generated between the bus and the buffer.

  Further, the technique according to Patent Document 3 has a problem that access conflict occurs when two pieces of software having different functions access the same address space. Further, it is necessary to prepare a port for each function type, and as the function type increases, the number of ports also increases, resulting in a problem that power consumption increases.

  An object of the present invention is to provide a multi-core processor system, a control method for a multi-core processor system, and a control program for a multi-core processor system that can avoid access contention in order to solve the above-described problems caused by the prior art.

  According to one embodiment of the present embodiment, a plurality of cores, a memory controller having a plurality of ports corresponding to the plurality of cores, and a physical address space allocated to each of the plurality of ports, A multi-core processor system having a shared memory for storing correspondence information between software to be executed and the number of cores to which the software is assigned, wherein the first core of the plurality of cores is the execution target software of the plurality of cores. Execution cores to be executed are assigned based on the corresponding information and the processing load of each of the multiple cores. The address space is set in the memory controller, and the first core has a plurality of excluding execution cores. The connection between the plurality of ports corresponding to the core to provide a multi-core processor system for releasing the memory controller.

  According to the multi-core processor system, the control method for the multi-core processor system, and the control program for the multi-core processor system, the address range accessed by the CPU is different from the address range accessed by another CPU, and an access conflict can be avoided. Play.

It is a block diagram which shows the hardware of the multi-core processor system concerning embodiment. 2 is a block diagram showing a part of hardware and software of the multi-core processor system 100. FIG. It is explanatory drawing which shows the example of the division | segmentation of a physical address space, and the coupling | bonding of a logical address space. FIG. 2 is a block diagram for explaining the relationship between each part in the multi-core processor system 100. 3 is a block diagram of a port connector 203. FIG. It is explanatory drawing which shows an example of an address converter 204 and a setting. It is explanatory drawing which shows an example of the memory content of the parallel degree information table. It is explanatory drawing which shows the state in which distributed software and parallel software were mixedly mounted. It is explanatory drawing which shows the dispatch period pattern of CPU in FIG. It is explanatory drawing which shows the execution state of the software in the timing t1, and the setting state of the memory controller. It is explanatory drawing which shows the state of the memory controller 202 in the timing t1. It is explanatory drawing which shows the execution state of the software in the timing t2, and the setting state of the memory controller. It is explanatory drawing which shows the state of the memory controller 202 in the timing t2. FIG. 6 is an explanatory diagram showing a software execution state and a setting state of a memory controller 202 at a timing t3. It is explanatory drawing which shows the state of the memory controller 202 in the timing t3. It is a flowchart which shows a scheduling process. It is a flowchart which shows an address space conversion process.

  Exemplary embodiments of a multi-core processor system, a multi-core processor system control method, and a multi-core processor system control program according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Multi-core processor system)
FIG. 1 is a block diagram of hardware of the multi-core processor system according to the embodiment. In FIG. 1, a multi-core processor system 100 includes CPUs 101 on which a plurality of CPUs are mounted, a ROM (Read-Only Memory) 102, and a RAM (Random Access Memory) 103. The multi-core processor system 100 includes a flash ROM 104, a flash ROM controller 105, and a flash ROM 106. The multi-core processor system 100 includes a display 107, an I / F (Interface) 108, and a keyboard 109 as input / output devices for a user and other devices. Each unit is connected by a bus 110.

  Here, the CPUs 101 govern the overall control of the multi-core processor system 100. CPUs 101 refers to all CPUs in which single-core processors are connected in parallel. Details of the CPUs 101 will be described later with reference to FIG. A multi-core processor system is a computer system including a processor having a plurality of cores. The present embodiment is premised on the architecture of a TCMP (Title Coupled Multi Processor), that is, regardless of the CPU connection method. In the present embodiment, in order to simplify the explanation, a processor group in which single-core processors are arranged in parallel will be described as an example.

  The ROM 102 stores a program such as a boot program. The RAM 103 is used as a work area for the CPUs 101. The flash ROM 104 stores system software such as an OS (Operating System), application software, and the like. For example, when updating the OS, the multi-core processor system 100 receives the new OS through the I / F 108 and updates the old OS stored in the flash ROM 104 to the received new OS.

  The flash ROM controller 105 controls data read / write with respect to the flash ROM 106 according to the control of the CPUs 101. The flash ROM 106 stores data written under the control of the flash ROM controller 105. Specific examples of the data include image data and video data acquired by the user using the multi-core processor system 100 through the I / F 108. As the flash ROM 106, for example, a memory card, an SD card, or the like can be adopted.

  A display 107 displays data such as a document, an image, and function information as well as a cursor, an icon, or a tool box. As the display 107, for example, a TFT liquid crystal display can be adopted.

  The I / F 108 is connected to a network 111 such as a LAN (Local Area Network), a WAN (Wide Area Network), and the Internet through a communication line, and is connected to other devices via the network 111. The I / F 108 controls an internal interface with the network 111 and controls data input / output from an external device. For example, a modem or a LAN adapter can be employed as the I / F 108.

  The keyboard 109 includes keys for inputting numbers, various instructions, and the like, and inputs data. The keyboard 109 may be a touch panel type input pad or a numeric keypad.

  FIG. 2 is a block diagram showing a part of hardware and software of the multi-core processor system 100. The hardware shown in FIG. 2 is a shared memory 201, a memory controller 202, and CPUs # 1 to # 4 included in the CPUs 101. The memory controller 202 and the CPUs # 1 to # 4 are connected by a bus 110. In addition, among the codes appearing below, the codes to which any of # 1 to # 4 is attached mean codes corresponding to CPU # 1 to CPU # 4, respectively.

  The shared memory 201 is a storage area accessible through the memory controller 202. The storage area is, for example, the ROM 102, the RAM 103, and the flash ROM 104. The shared memory 201 has port # 1 to port # 4 that are accessible lines. CPU # 1 to CPU # 4 can access any of port # 1 to port # 4. In this embodiment, CPU # 1 controls port # 1, CPU # 2 controls port # 2, CPU # 3 controls port # 3, and CPU # 4 controls port # 4. To do.

  The shared memory 201 is divided into shared memory block # 1 to shared memory block # 4 in which the physical address space is divided for each port # 1 to port # 4. In the shared memory block # 1 to the shared memory block # 4, the physical address space may be continuous or separated. Further, the shared memory 201 may exist as one memory bank, or one shared memory block may exist as one memory bank.

  Further, as an initial state, the port # 1 can access the shared memory block # 1. Similarly, port # 2 to port # 4 can also access shared memory block # 2 to shared memory block # 4, respectively. However, one port may be able to access a plurality of shared memory blocks by setting the port. For example, the port # 1 may be accessible to the shared memory block # 1 and the shared memory block # 2 by changing the setting of the port # 1.

  The memory controller 202 has a function of controlling reading and writing of data to the shared memory 201. In the present embodiment, the memory controller 202 controls the access to the shared memory 201 of the CPUs # 1 to # 4 by changing the settings of the ports # 1 to # 4 that access the shared memory 201.

  The port connector 203 exists inside the memory controller 202 and connects or disconnects the ports # 1 to # 4. In the example of FIG. 2, the port connector 203 does not connect the port # 3 on the bus 110 side. The address converter 204 exists inside the memory controller 202 and performs address conversion of the port # 1 to port # 4. An example of the conversion method will be described later with reference to FIG. CPU # 1 to CPU # 4 are equipped with cache memory # 1 to cache memory # 4.

  The software shown in FIG. 2 is scheduler # 1 to scheduler # 4 and software 205-1 to software 205-4. In addition, cache memory blocks 206-1 to 206-4 and shared memory blocks 207-1 to 207-4 exist as storage areas accessed by software.

  The scheduler # 1 to the scheduler # 4 determine which CPU executes the OS or the software requested to be activated by the user from the usage status of the CPU # 1 to CPU # 4. For example, the scheduler # 1 to the scheduler # 4 determine the CPU that is least used among the CPUs # 1 to # 4 as the CPU for which the activation request has been made. Further, the scheduler # 1 to the scheduler # 4 notify the setting to the port connector 203 and the address converter 204 based on the software for which the activation request has been made.

  Software 205-1 is executed by CPU # 1. The CPU # 1 accesses the cache memory block 206-1 by the software 205-1, and also when the necessary data does not exist in the cache memory block 206-1, the shared memory block 207-1 is connected via the port # 1. To access.

  Software 205-2 is executed by CPU # 2 and CPU # 3. The CPU # 2 accesses the cache memory block 206-2-1 by the software 205-2, and when there is no necessary data in the cache memory block 206-2-1, the shared memory block via the port # 2 207-2 is accessed. The CPU # 3 also accesses the cache memory block 206-2-2 by the software 205-2, and when the necessary data does not exist in the cache memory block 206-2-2, the shared memory block via the port # 2 207-2 is accessed.

  Software 205-3 and software 205-4 are executed by CPU # 4. The CPU # 4 accesses the cache memory block 206-3 and the cache memory block 206-4 corresponding to each software by the software 205-3 and the software 205-4. When the necessary data does not exist in the cache memory block, the CPU # 4 accesses the shared memory block 207-3 and the shared memory block 207-4 via the port # 4.

  FIG. 3 is an explanatory diagram showing an example of the division of the physical address space and the combination of the logical address space. As hardware, the physical address spaces of the shared memory block # 1 to the shared memory block # 4 including the shared memory 201 are set as follows. The physical address space of the shared memory block # 1 is 0x0000 to 0x00ff. Similarly, the physical address space of the shared memory block # 2 is 0x1000 to 0x10ff. The physical address space of the shared memory block # 3 is 0x2000 to 0x20ff. The physical address space of the shared memory block # 4 is 0x3000 to 0x30ff.

  Assume that the logical address space accessed by the software 205-1 is 0x0000 to 0x00ff in the above state. In order to access port # 1, CPU # 1 uses port connector 203 to place port # 1 in a connected state. Further, since the logical address space and the physical address space of the shared memory block # 1 are equal, the CPU # 1 sets the address converter 204 to address through. The address through setting is a setting for accessing the shared memory 201 using a logical address as a physical address without conversion.

  Next, it is assumed that the logical address space accessed by the software 205-2 is 0x0000 to 0x01ff. It is assumed that the master thread of software 205-2 executed by CPU # 2 also accesses 0x0000 to 0x01ff as a logical address. In order to access the port # 2, the CPU # 2 sets the port # 2 in the connected state by the port connector 203.

  Further, the CPU # 2 notifies the address converter 204 to convert the logical address space and the physical address spaces of the shared memory block # 2 and the shared memory block # 3. Upon receiving the notification, the port # 2 converts the logical address 0x0000 to 0x00ff into the physical address 0x1000 to 0x10ff, and converts the logical address 0x0100 to 0x01ff into the physical address 0x2000 to 0x20ff. For example, when CPU # 2 accesses a logical address that is 0x0010, the address converter 204 converts it to a physical address that is 0x1010. As a result, the address converter 204 can provide the physical address space that is not continuous to the software as a continuous logical space.

  Similarly, it is assumed that the slave thread of the software 205-2 executed by the CPU # 3 accesses 0x0000 to 0x01ff as a logical address. Since the CPU # 3 accesses the port # 2 and does not access the port # 3, the port connector 203 causes the port # 3 to be disconnected.

  Further, it is assumed that the logical address space accessed by the software 205-3 is 0x0000 to 0x00ff. In order to access port # 4, CPU # 4 uses port connector 203 to place port # 4 in a connected state.

  Further, the CPU # 4 notifies the address converter 204 that the logical address space and the physical address space of the shared memory block # 4 are converted. By receiving the notification, the port # 4 converts the logical address 0x0000 to 0x00ff into the physical address 0x3000 to 0x30ff. In addition, when the logical address 0x0000 to 0x00ff is converted to the physical address 0x3000 to 0x30ff as the initial conversion state, and the CPU # 4 sets address through, the address converter 204 converts the address in the initial conversion state. You may make it do.

(Multi-core processor system 100)
Next, the operation of the multi-core processor system 100 will be described. FIG. 4 is a block diagram for explaining the relationship between the components in the multi-core processor system 100. The multi-core processor system 100 includes, for example, an acquisition unit 402, a determination unit 403, a setting unit 404, an address notification unit 405, a selection unit 406, a release notification unit 407, an aggregation unit 408, a detection unit 409, An execution start notification unit 410. In the acquisition unit 402 to the execution start notification unit 410 serving as the control unit, the CPUs 101 execute the programs stored in the storage device. Examples of the storage device include the ROM 102, the RAM 103, and the flash ROM 104 shown in FIG. Alternatively, another CPU may execute it via the I / F 108.

  The multi-core processor system 100 includes a memory controller 202 having a plurality of cores, a plurality of ports corresponding to the cores, and a shared memory 201 having a physical address space divided for each port. The plurality of cores may be all CPUs belonging to the CPUs 101, or may be a part of the CPUs 101 to which the present embodiment is applied. The plurality of ports corresponding to the core are specific ports accessed by the CPU. For example, port # 1 for CPU # 1, port # 2 for CPU # 2, and so on. The port has been determined. In FIG. 4, since the number of CPUs and the number of ports are the same, the CPUs and ports are in a one-to-one correspondence. However, when the number of ports is smaller than the number of CPUs, the ports corresponding to different CPUs may be the same. .

  Each port is set to be accessible to a physical address space obtained by dividing the physical address space of the shared memory 201. For example, when the physical address space of the shared memory 201 is 0x0000 to 0x01ff, the port # 1 can access the physical address space of 0x0000 to 0x00ff, and the port # 2 can access the physical address space of 0x0100 to 0x01ff To do. As described above, the physical address space may be divided equally for each port as described above, or may be divided unevenly.

  The multi-core processor system 100 can access the parallelism information table 401 as a database that stores the number of cores to which target software is assigned for each software. For example, the software 205-1 is registered as distributed software that assigns one CPU, and the software 205-2 is registered as parallel software that assigns two CPUs. Details of the parallelism information table 401 will be described later with reference to FIG.

  The acquisition unit 402 has a function of acquiring the number of cores to which the execution target software is allocated from the parallelism information table 401. The execution target software is software that has been activated by the user or the OS, or software that is about to be executed by the scheduler again after the CPU is deallocated after execution by the scheduler. For example, when the software 205-2 is the execution target, the acquisition unit 402 acquires from the parallelism information table 401 that the number of CPUs to be allocated is two. The acquired data is stored in a storage area such as the RAM 103 and the flash ROM 104.

  The determination unit 403 has a function of determining the core to which the execution target software is allocated based on the number of cores to which the execution target software acquired by the acquisition unit 402 is allocated and the usage status of the plurality of cores.

  As a specific example of the determination unit 403, for example, a case is assumed where the software 205-2 is the execution target software and the acquisition unit 402 can acquire two CPUs. The determination unit 403 determines the CPUs # 2 and # 3 as low-load CPUs from the CPUs 101 as CPUs to which the software 205-2 is assigned. Note that the determined CPU information is stored in a storage area such as the RAM 103 or the flash ROM 104.

  The setting unit 404 acquires a physical address space that can be accessed by a specific port corresponding to the core determined by the determination unit 403 among the plurality of ports. From the acquired physical address space, the setting unit 404 has a function of setting a physical address space corresponding to the logical address space defined by the execution target software for each determined core. The setting unit 404 may set the physical address space aggregated by the aggregation unit 408 as a physical address space that can be newly accessed by the port selected by the selection unit 406.

  For example, it is assumed that the determined cores are CPU # 2 and CPU # 3, and the ports corresponding to the aforementioned CPU are port # 2 and port # 3. Subsequently, it is assumed that the physical address space in which port # 2 can access the shared memory 201 is 0x1000 to 0x10ff, and the physical address space in which port # 3 can access the shared memory 201 is 0x2000 to 0x20ff.

  At this time, the setting unit 404 sets the physical address space corresponding to the logical address space defined by the execution target software for each determined CPU from the physical address spaces 0x1000 to 0x10ff and 0x2000 to 0x20ff. If the specified logical address space is 0x0000 to 0x01ff, the logical address space 0x0000 to 0x00ff is set in association with the physical address space 0x1000 to 0x10ff when the CPU # 2 accesses the port # 2. Similarly, when the CPU # 3 accesses the port # 3, the logical address space 0x0100 to 0x01ff is set in association with the physical address space 0x2000 to 0x20ff. The set address correspondence information is stored in a storage area such as the RAM 103 and the flash ROM 104.

  The address notification unit 405 has a function of notifying a specific port of the physical address space set by the setting unit 404 and the logical address space corresponding to the set physical address space. The address notification unit 405 may notify the port selected by the selection unit 406 of the newly accessible physical address space set by the setting unit 404.

  For example, it is assumed that when the CPU # 2 accesses the port # 2, the logical address space 0x0000 to 0x00ff is set in association with the physical address space 0x0100 to 0x01ff. At this time, the address notification unit 405 notifies the address correspondence information set by the CPU # 2 to the port # 2 of the address converter 204. Further, it is assumed that the physical address space aggregated by the aggregation unit 408 is 0x0000 to 0x01ff, and the port # 2 is selected by the selection unit 406. At this time, the address notification unit 405 notifies the port # 2 of 0x0000 to 0x01ff as a physical address space that can be newly accessed by the port # 2.

  In addition, when the range is determined to some extent as address correspondence information, a settable pattern may be prepared. For example, when there are four ports and the physical address space of the shared memory 201 is divided into four, the divided physical address space may be associated with the bit string in the register. The logical address space may be associated with the address space starting from 0x0000.

  Thereby, the physical address and the logical address can be associated with each other by setting a specific bit of the register to “1”. As described above, the address notification unit 405 may notify the upper limit value and lower limit value of the physical address space, the upper limit value and lower limit value of the logical address, or prepares a settable pattern, thereby notifying processing. May be simplified.

  Assume that the physical address space of the shared memory 201 described above is divided into four. At this time, the setting unit 404 sets the bit of the register corresponding to the physical address space 0x0200 to 0x02ff to “1”, and sets the physical address space 0x0200 to 0x02ff and the logical address space 0x0000 to 0x00ff in association with each other. The address notification unit 405 may notify the set register value. In addition, when the first and third physical address spaces are aggregated among the four physical address spaces divided by the aggregation unit 408, the address notification unit may notify the corresponding bit “0b1010”. Good. The notified address correspondence information may be stored in a storage area such as the RAM 103 or the flash ROM 104.

  The selection unit 406 has a function of selecting an arbitrary port among the specific ports when there are a plurality of specific ports corresponding to the core determined by the determination unit 403. For example, when CPU # 2 and CPU # 3 are determined by determining unit 403 and there are a plurality of corresponding ports such as port # 2 and port # 3, port # 2 is selected as an arbitrary port.

  The port selection criteria may be set in any way. For example, a port corresponding to the CPU executing the master thread of the execution target software may be selected. Also, if the performance of multiple existing ports is asymmetric and the capabilities of a specific port outperform the capabilities of other ports, you can select a port that performs better than others. . The selected port information is stored in a storage area such as the RAM 103 or the flash ROM 104.

  The cancellation notification unit 407 has a function of notifying the remaining ports of a notification for canceling the connection of the remaining ports excluding the port selected by the selection unit 406 among the specific ports. For example, when the port # 2 and the port # 3 are selected as the specific ports and the port # 2 is selected by the selection unit 406, the port connector 203 notifies the remaining port # 3 of the release of the port connection. To port # 3. The notified connection release information may be stored in a storage area such as the RAM 103 or the flash ROM 104.

  The aggregation unit 408 has a function of aggregating physical address spaces accessible by a plurality of specific ports. For example, it is assumed that the specific ports are port # 2 and port # 3, and the physical address spaces of port # 2 and port # 3 are 0x0000 to 0x00ff and 0x0100 to 0x01ff, respectively. In the above state, the aggregating unit 408 sets the aggregated physical address space to 0x0000 to 0x01ff. The aggregated physical address information is stored in a storage area such as the RAM 103 and the flash ROM 104.

  The detection unit 409 has a function of detecting a start time for simultaneously executing the execution target software among the determined cores when there are a plurality of cores determined by the determination unit 403. Further, the detection unit 409 detects the time when the address notification unit 405 has completed notification to a specific port as the start time. For example, if the determined CPUs are CPU # 2 and CPU # 3 and the specific port is port # 2, CPU # 2 or CPU # 3 has completed execution of address notification unit 405 at port # 2 The time can be detected as the start time of the execution target software. Information indicating that the detection has been performed is stored in a storage area such as the RAM 103 or the flash ROM 104.

  The execution start notification unit 410 has a function of notifying the execution target software of the execution start after notifying a specific port by the address notification unit 405. The execution start notifying unit 410 may notify the execution target software of the execution start after the detection unit 409 detects the start time.

  For example, after the CPU # 2 issues an address notification to the port # 2, the CPU # 2 can notify the execution target software of the execution start. Further, when the determined CPUs are CPU # 2 and CPU # 3, after the start time is detected by the detection unit 409, the CPU # 2 and CPU # 3 notify the execution target software of the execution start. be able to. The execution start notification may be stored in a storage area such as the RAM 103 and the flash ROM 104.

  FIG. 5 is a block diagram of the port connector 203. The port connector 203 is a form of the memory controller 202 and exists between the bus 110 and the address converter 204 and controls connection / disconnection of each port. Connection / disconnection of each port is controlled by a setting register 501 accessed by the CPUs # 1 to # 4. The setting register 501 includes setting registers 501 # 1 to 501 # 4 and controls connection / disconnection of each port.

  For example, the setting register 501 # 1 controls the switch # 1 and sets connection / disconnection of the port # 1. The setting register 501 # 1 connects the port # 1 if the setting value is “1”, and disconnects the port # 1 if the setting value is “0”. Similarly, the setting registers 501 # 2 to 501 # 4 connect and disconnect the ports # 2 to # 4, respectively. The disconnected port is not supplied with power to the connection within the port. As a result, the power saving effect can be obtained by disconnecting the port when the port is unnecessary.

  FIG. 6 is an explanatory diagram showing an example of the address converter 204 and settings. The explanatory diagram denoted by reference numeral 601 shows the address converter 204. The address converter 204 is a form of the memory controller 202 and exists between the port connector 203 and the shared memory 201, and converts the logical address and physical address of each port. The conversion between the logical address and the physical address of each port is controlled by conversion registers 603 # 1 to 603 # 4 accessed by CPU # 1 to CPU # 4.

  As an embodiment, the conversion register 603 # 1 controls a TLB (Translation Lookaside Buffer) # 1. The controlled TLB # 1 converts the logical address space and physical address space of the port # 1. The explanatory diagram denoted by reference numeral 602 is an explanatory diagram illustrating an example of the relationship between the conversion register 603 # 1 and the TLB # 1. The content set in TLB # 1 changes according to the setting of conversion register 603 # 1. For example, when the CPU # 1 sets the conversion register 603 # 1 to “0b0000”, the setting of the TLB # 1 is not set and the address through is set.

  Further, when the CPU # 1 sets the conversion register 603 # 1 to “0b1000”, the setting of the TLB # 1 becomes the TLB # 1 setting 604-1. The TLB # 1 setting 604-1 designates the logical address space 0x0000 to 0x00ff as the physical address space of the shared memory block # 1.

  When the CPU # 1 sets the conversion register 603 # 1 to “0b1100”, the setting of the TLB # 1 becomes the TLB # 1 setting 604-2. The TLB # 1 setting 604-2 designates the logical address space 0x0000 to 0x01ff as the physical address space of the shared memory block # 1 and the shared memory block # 2. Thus, from the state where port # 1 can access shared memory block # 1 and port # 2 can access shared memory block # 2, port # 1 can access physical addresses of port # 1 and port # 2. Space will be aggregated.

  When the CPU # 1 sets the conversion register 603 # 1 to “0b1010”, the setting of the TLB # 1 becomes the TLB # 1 setting 604-3. The TLB # 1 setting 604-3 designates the logical address space 0x0000 to 0x01ff as the physical addresses of the shared memory block # 1 and the shared memory block # 3. Thus, from the state where port # 1 can access shared memory block # 1 and port # 3 can access shared memory block # 3, port # 1 can access physical addresses of port # 1 and port # 3. Space will be aggregated.

  When CPU # 1 sets conversion register 603 # 1 to “0b1110”, the setting of TLB # 1 becomes TLB # 1 setting 604-4. The TLB # 1 setting 604-4 designates the logical address space 0x0000 to 0x02ff as the physical addresses of the shared memory block # 1 to shared memory block # 3. Thus, from the state in which the port # 1 to the port # 3 can access the shared memory block # 1 to the shared memory block # 3, respectively, the physical addresses accessible to the port # 1 to the port # 3 to the port # 1 Space will be aggregated.

  Similarly, for TLB # 2 to TLB # 4, the address conversion method is designated by the conversion registers 603 # 2 to 603 # 4. In this embodiment, the content of the TLB is specified by the conversion register 603. However, the content of the TLB may be directly described by the conversion register 603.

  FIG. 7 is an explanatory diagram showing an example of the stored contents of the parallel degree information table 401. The parallel degree information table 401 includes, for example, three fields: software name, parallel degree information, and parallel number P. The software name field stores the name of the software. For example, a process start address corresponding to software is set, and the CPU can execute processing with reference to the process start address.

  The parallel degree information field stores an identifier indicating whether each CPU is distributed to process software, or a plurality of CPUs operate in parallel to process software. The stored identifiers are “distributed” and “parallel”. The “distributed” identifier indicates that the software stored in the name field is distributed software executed by one CPU. The “parallel” identifier indicates that the software stored in the name field is parallel software executed by two or more CPUs. The parallel number P field indicates the number of CPUs when the software stored in the name field is executed. For example, the UI processing is distributed software and is executed by one CPU. The web browser is parallel software and is executed by three CPUs.

  FIG. 8 is an explanatory diagram showing a state in which distributed software and parallel software are mixedly installed. The multi-core processor system 100 executes parallel software P1, parallel software P2, distributed software S1 to distributed software S6 as software. The CPUs # 1 to # 4 access the shared memory 201 through the memory controller 202.

  Next, the software execution state of each CPU will be described. The CPU # 1 sequentially executes the master thread P1, the distributed software S2, and the distributed software S3 of the parallel software P1 by the OS # 1. The CPU # 2 sequentially executes the slave thread P1-1 of the parallel software P1, the master thread P2 of the parallel software P2, and the distributed software S4 by the OS # 2. The CPU # 3 sequentially executes the slave thread P1-2 of the parallel software P1, the slave thread P2-1 of the parallel software P2, and the distributed software S5 by the OS # 3. The CPU # 4 sequentially executes the distributed software S1, the slave thread P2-2 of the parallel software P2, and the distributed software S6 by the OS # 4.

  FIG. 9 is an explanatory diagram showing a dispatch cycle pattern of the CPU in FIG. CPU # 1 to CPU # 4 periodically notify the settings of the memory controller 202 to the ports # 1 to # 4 through the converter setting process. The converter setting process is a process for setting the setting register 501 of the port connector 203 and setting the conversion register 603 of the address converter 204.

  For example, in port # 1, distributed software can be set by the converter setting process u # 1-1. At the timing when the converter setting process u # 1-1 is executed, the converter setting process u # 2-1 is performed for the port # 2, the converter setting process u # 3-1 is performed for the port # 3, and the port # 4 is processed. The distributed software is set by the converter setting process u # 4-1. As an example of the setting process, there are connection setting and release setting performed for the port connector 203, logical single space setting and logical continuous space setting performed for the address converter 204. By setting the logical continuous space, the physical address space accessible by a plurality of ports is aggregated into the physical address space accessible by one port.

  Further, after a certain period of time, the settings of the ports # 1 to # 4 are updated by the converter setting process u # 1-2 to the converter setting process u # 4-2. As an example, the port # 1 is updated to the setting of the distributed software by the converter setting process u # 1-2. Ports # 2 to # 4 are updated to the settings of the parallel software P2 by the converter setting process u # 2-2 to the converter setting process u # 4-2. In this example, since the parallel software P2 is set at the same time, the CPU that controls the port # 2 to the port # 4 can execute the barrier synchronization code 903-1 to the barrier synchronization code 903-3.

  The barrier synchronization code is a code that waits for the processing of all CPUs that require synchronization to end. For example, in the present embodiment, CPU # 2 controls port # 2, CPU # 3 controls port # 3, and CPU # 4 controls port # 4. Therefore, after the CPU # 2 performs the converter setting process U # 2-2, the CPU # 2 executes the barrier synchronization code 903-1 and stands by.

  Similarly, CPU # 3 and CPU # 4 execute the converter setting process, and then execute the barrier synchronization code and wait. When the CPU # 2 to CPU # 4 execute the barrier synchronization code, the CPU detects the start time for starting execution of the software, and the CPU that has been waiting returns to execute the parallel software P2. Thereby, CPU # 2-CPU # 4 can access parallel software P2 simultaneously.

  The synchronization code 901 with the parallel software P1 is a code for accessing the logical address space where the parallel software P1 is continuous. For example, at the timing t1, the synchronization code 901 sets the parallel software P1 by the converter setting process u # 1-3 to the converter setting process u # 3-3 and the barrier synchronization code 904-1 to the barrier synchronization code 904-3. Do.

  Similarly, the synchronization code 902 with the parallel software P2 is a code for accessing the logical address space where the parallel software P2 is continuous. For example, at the timing t3, the synchronization code 902 sets the parallel software P2 by the converter setting process u # 2-5 to the converter setting process u # 4-5 and the barrier synchronization code 905-1 to the barrier synchronization code 905-3. Do. The execution state of software in the multi-core processor system 100 and the setting state of the memory controller 202 at timing t1 to timing t3 are shown in FIGS.

  FIG. 10 is an explanatory diagram showing a software execution state and a setting state of the memory controller 202 at the timing t1. In the multi-core processor system 100 at the timing t1, the CPU # 1 to CPU # 3 execute the parallel software P1, and the CPU # 4 executes the distributed software S1. As a setting state of the memory controller 202, the port # 1 becomes a master port, and the port # 1 accesses the shared memory 201 by executing the parallel software P1 in the CPUs # 1 to # 3. Port # 2 and port # 3 are not connected. Port # 4 also becomes a master port, and port # 4 accesses shared memory 201 by execution of distributed software S1 in CPU # 4.

  FIG. 11 is an explanatory diagram showing the state of the memory controller 202 at the timing t1. The diagram denoted by reference numeral 1101 shows the state of the port connector 203 and the state of the address converter 204. A table group denoted by reference numeral 1102 indicates a setting state of TLB # 1 and TLB # 4. In port # 1, “1” is set in the setting register 501-1 by the converter setting process u # 1-3. As a result, port # 1 is connected. Subsequently, in the port # 1, the converter setting process u # 1-3 sets the conversion register 603 # 1 to “0b1110”, whereby the TLB # 1 setting 1103 is set to the TLB # 1. As a result, the port # 1 can access the shared memory block # 1 to the shared memory block # 3 and provide the continuous logical address space 0x0000 to 0x02ff to the parallel software P1.

  At port # 2, “0” is set in the setting register 501-2 by the converter setting process u # 2-3. As a result, the port # 2 is disconnected. Similarly, at port # 3, “0” is set in the setting register 501-3 by the converter setting process u # 3-3. As a result, port # 3 is also disconnected. At port # 4, “1” is set in the setting register 501-4 by the converter setting process u # 4-3. As a result, the port # 4 is connected. Subsequently, in the port # 4, the TLB # 4 setting 1104 is set in the TLB # 4 by the converter setting process u # 4-3. As a result, the port # 4 can access the shared memory block # 4 and provide the logical address space converted from the physical address space to the distributed software S1.

  FIG. 12 is an explanatory diagram showing a software execution state and a setting state of the memory controller 202 at the timing t2. The multi-core processor system 100 at the timing t2 executes the distributed software S3 on the CPU # 1. Similarly, in the multi-core processor system 100, the CPU # 2 executes the distributed software S4, the CPU # 3 executes the distributed software S5, and the CPU # 4 executes the distributed software S6. In addition, as a setting state of the memory controller 202, the port # 1 to the port # 4 become master ports and access to the shared memory 201 is performed.

  FIG. 13 is an explanatory diagram showing the state of the memory controller 202 at the timing t2. The diagram denoted by reference numeral 1301 shows the state of the port connector 203 and the state of the address converter 204. A table group denoted by reference numeral 1302 indicates a setting state of TLB # 1 to TLB # 4. At port # 1, “1” is set in the setting register 501-1 by the converter setting processing u # 1-4. As a result, port # 1 is connected. Subsequently, in port # 1, TLB # 1 setting 1303 is set in TLB # 1 by converter setting processing u # 1-4. As a result, the port # 1 can access the shared memory block 201 # 1 and provide the logical address space converted from the physical address space to the distributed software S3.

  The same applies to port # 2 to port # 4. The port # 2 is connected by the converter setting process u # 2-4, accesses the shared memory block 201 # 2, the TLB # 2 setting 1304 is set in the TLB # 2, and the logical address space is set in the distributed software S4. provide. Port # 3 is connected by converter setting processing u # 3-4, accesses shared memory block 201 # 3, TLB # 3 is set to TLB # 3 1305, and logical address space is set to distributed software S5. provide. The port # 4 is connected by the converter setting process u # 4-4, accesses the shared memory block 201 # 4, the TLB # 4 setting 1306 is set in the TLB # 4, and the logical address space is set in the distributed software S6. provide.

  FIG. 14 is an explanatory diagram showing a software execution state and a setting state of the memory controller 202 at the timing t3. The multi-core processor system 100 at the timing t3 executes the distributed software S2 at the CPU # 1, and executes the parallel software P2 at the CPU # 2 to the CPU # 4. As a setting state of the memory controller 202, the port # 1 becomes a master port, and the port # 1 accesses the shared memory 201 by executing the distributed software S2 in the CPU # 1. The port # 2 also becomes a master port, and the port # 2 accesses the shared memory 201 by executing the parallel software P2 in the CPUs # 2 to # 4. Port # 3 and port # 4 are not connected.

  FIG. 15 is an explanatory diagram showing the state of the memory controller 202 at the timing t3. The diagram indicated by reference numeral 1501 shows the state of the port connector 203 and the state of the address converter 204. A table group denoted by reference numeral 1502 indicates a setting state of TLB # 1 and TLB # 2. In the port # 1, “1” is set in the setting register 501-1 by the converter setting process u # 1-5. As a result, port # 1 is connected. Subsequently, in the port # 1, the converter setting process u # 1-5 sets the conversion register 603 # 1 to “0b1000” to set the TLB # 1 to the TLB # 1 setting 1503. Thereby, the port # 1 can access the shared memory block 201 # 1 and provide the logical address space converted from the physical address space to the distributed software S2.

  At port # 2, “1” is set in the setting register 501-2 by the converter setting process u # 2-5. As a result, port # 2 is connected. Subsequently, in the port # 2, the TLB # 2 setting 1504 is set in the TLB # 2 by the converter setting process u # 2-5. Thereby, the port # 2 can access the shared memory block 201 # 2 to the shared memory block 201 # 4, and can provide the continuous logical address space 0x0000 to 0x02ff to the parallel software P2.

  At port # 3, “0” is set in the setting register 501-3 by the converter setting process u # 3-5. As a result, the port # 3 is disconnected. Similarly, at port # 4, “0” is set in the setting register 501-4 by the converter setting process u # 4-5. As a result, port # 4 is also disconnected.

  FIG. 16 is a flowchart showing the scheduling process. The scheduling process is executed by the scheduler # 1 to the scheduler # 4 as a function when the software is activated. Steps S1601 to S1604, S1610, and S1611 are executed by a specific CPU among the CPUs 101, and steps S1605 to S1609 are executed by the CPU detected in step S1603. In the present embodiment, it is assumed that the specific CPU described above is CPU # 1.

  CPU # 1 receives a request to activate the target software (step S1601). The activation request is issued by the user operating the UI, for example. Subsequently, CPU # 1 obtains the parallel degree information and the parallel number P of the target software from the parallel degree information table 401 (step S1602). Subsequently, CPU # 1 detects P CPUs having a low load in parallel (step S1603).

  For example, the CPU # 1 can detect P CPUs from the CPU having a low load according to the usage state of the CPU from the information of the scheduler # 1 to the scheduler # 4. The CPU usage status may be a CPU usage rate or a CPU memory usage rate. For example, if P = 2 and the CPU usage status is highest in the order of CPU4, CPU3, CPU2, and CPU1, CPU # 1 can detect CPU2 and CPU1.

  After the detection, CPU # 1 selects the first CPU from the detected CPU group (step S1604). The selected CPU executes an address space conversion process (step S1605). Details of the address space conversion processing will be described later with reference to FIG. After the processing, the selected CPU determines whether or not the parallel degree information of the target software is “parallel” (step S1606).

  When the degree of parallelism information is “distributed” (step S1606: No), the selected CPU executes a driver task for controlling the port connector 203 and the address converter 204 (step S1608). The operation content of the driver task is a task for performing the setting to the port connector 203 and the address converter 204 set in the processing of step S1605 and the execution of the barrier synchronization code at a constant cycle.

  If the degree of parallelism information is “parallel” (step S1606: Yes), the selected CPU subsequently determines whether the selected CPU is a CPU that operates the main thread of the target software (step S1607). When the selected CPU is a CPU that executes the main thread (step S1607: Yes), the selected CPU proceeds to the process of step S1608. When the selected CPU is a CPU that executes a slave thread (step S1607: No), or after the process of step S1608 is completed, the selected CPU performs dispatch according to the result of the scheduling process (step S1609).

  After step S1609, CPU # 1 determines whether the selected CPU is the last CPU in the detected CPU group (step S1610). If it is not the last CPU (step S1610: No), CPU # 1 selects the next CPU in the detected CPU group (step S1611), and proceeds to the process of step S1605. If it is the last CPU (step S1610: Yes), the CPU # 1 ends the scheduling process.

  FIG. 17 is a flowchart showing the address space conversion process. The address space conversion process is executed by the CPU selected in step S1604 or step S1611. The selected CPU determines whether the parallel number P is 1 (step S1701). When the parallel number P is 1 (step S1701: Yes), the selected CPU executes the port connector 203 connection setting (step S1702) and the address converter 204 logical single space setting (step S1703), and the address The space conversion process ends.

  The port connector 203 connection setting is a process for setting a port corresponding to the selected CPU to a connected state. For example, if the selected CPU is CPU # 1, CPU # 1 can set the setting register 501 # 1 for controlling the connection state of port # 1 to “1”. The address converter 204 logical single space setting is a setting for associating the logical address space of the software with any one physical address space of the shared memory block # 1 to the shared memory block # 4 of the port corresponding to the selected CPU. It is.

  When the parallel number P is not 1 (step S1701: No), the selected CPU determines whether the selected CPU is a CPU that executes the main thread (step S1704). When the selected CPU is a CPU that executes the main thread (step S1704: Yes), the selected CPU sets the port connector 203 connection setting (step S1705) and the address converter 204 logical continuous space setting (step S1706). ). The address converter 204 logical contiguous space setting refers to the physical address of two or more shared memory blocks among the shared memory block # 1 to the shared memory block # 4 of the port corresponding to the selected CPU. It is a setting that aggregates and associates with space. Further, the associated logical addresses are set to be a continuous space.

  When the selected CPU is a CPU that executes a slave thread (step S1704: No), the selected CPU executes the port connector 203 release setting (step S1707). The port connector 203 release setting is a process for disconnecting the port corresponding to the selected CPU. Further, the port connector 203 connection setting, the port connector 203 release setting, the address converter 204 logical single space setting, and the address converter 204 logical continuous space setting are the converter setting processing described above with reference to FIG.

  After the processing in step S1706 or step S1707 is completed, the selected CPU performs simultaneous execution setting in the thread dispatcher (step S1708). For example, the selected CPU registers the target software in the thread dispatcher as software that simultaneously executes the target software. Subsequently, the selected CPU sets the barrier synchronization code and the cycle timing (step S1709), and ends the address space conversion process. By executing the barrier synchronization code before the parallel software is executed, the CPU group executing the parallel software can detect the start time of executing the parallel software simultaneously. The setting of the cycle timing is to set the target software so as to be allocated at the same timing between the CPUs.

  As described above, according to the multi-core processor system, the control method for the multi-core processor system, and the control program for the multi-core processor system, the CPU to which the execution target software is assigned is determined with the physical address space divided for each port. . Subsequently, the logical address defined by the execution target software is designated from the physical address space accessible by the port corresponding to the CPU, and the execution target software is started after notifying the port.

  Thereby, since the physical address space of the port accessed by the CPU executing the execution target software is different from the physical address space of the port accessed by another CPU, it is possible to avoid access contention.

  In addition, when there are a plurality of specific ports corresponding to the CPU to which the execution target software is assigned, the multi-core processor system may select any one port and release the connection of the port that has not been selected. Subsequently, the multi-core processor system may aggregate the physical address space of a specific port and set the aggregated physical address space as the physical address space of the selected port.

  As a result, it is possible to avoid an access conflict between software, and it is possible to obtain a power saving effect by releasing unnecessary ports. Further, in the execution target software using a plurality of CPUs, when the logical address space accessed by the master thread and the slave thread is separated, the physical address space need not be aggregated. As a result, access contention in the software can be avoided.

  Further, when there are a plurality of CPUs to which execution target software is allocated, the multi-core processor system may notify the execution target software of the start of execution after completing the address conversion notification to a specific port.

  As a result, it is possible to avoid an access conflict between software, and it is possible to load software allocated to a plurality of CPUs. As a specific example of the mixed loading, as shown in FIG. 8, the parallel software P1 is assigned to the CPUs # 1 to # 3, and the parallel software P2 is assigned to the CPUs # 2 to # 4. Even when mixed, parallel software should be executed at the same timing in each core. When it becomes an execution target, an address conversion notification is sent to a specific port of the memory controller, and the parallel software is executed after the notification is completed, so that it can operate normally.

  In the multi-core processor system, the number of cores and the number of ports may be equal. As a result, the CPU and the port have a one-to-one correspondence, and access contention between the CPUs can be avoided. Even when the number of ports is smaller than the number of CPUs, access contention among some CPUs can be avoided.

  For example, in a multi-core processor system having four CPUs and three ports, CPU # 1 has port # 1, CPU # 2 has port # 2, and CPU # 3 and CPU # 4 have port # 3. Can be associated. In this case, it is possible to avoid access contention among CPU # 1, CPU # 2, and CPU # 3 or CPU # 4. Further, if the software assigned by CPU # 3 and CPU # 4 is software that frequently accesses each other's memory, the same logical address space may be used for one port.

  In this way, if a plurality of CPUs to which software having a high dependency relationship is determined, ports are prepared for the number of CPUs, and the ports corresponding to the determined CPUs are combined into one to connect the ports. Cost can be reduced.

  Note that the control method of the multi-core processor system described in this embodiment can be realized by executing a prepared program on a computer such as a personal computer or a workstation. The control program of the multi-core processor system is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The control program for the multi-core processor system may be distributed via a network such as the Internet.

100 multi-core processor system # 1 to # 4 CPU, port 110 bus 201 shared memory 202 memory controller 203 port connector 204 address converter 401 parallelism information table 402 acquisition unit 403 determination unit 404 setting unit 405 address notification unit 406 selection unit 407 Cancellation notification unit 408 Aggregation unit 409 Detection unit 410 Execution start notification unit

Claims (3)

With multiple cores,
A memory controller having each port corresponding to each of the plurality of cores and connected to a bus ;
The has a physical address space assigned to each port, a multi-core processor system with a shared memory for storing correspondence information between the number of cores to assign software and the software running on the plurality of cores,
The first core of the plurality of cores, pre SL based on the respective processing loads of correspondence information and the plurality of cores to determine the execution core to assign execution target software of the plurality of cores,
If the decision the execution cores there are multiple, one of the core of the execution core includes a logical address space defined before Symbol executed software, assigned to each port corresponding to the core of the execution core A physical address space obtained by consolidating the physical address space and setting the memory controller,
If the execution core there are multiple residual core except the one of the core of the execution core, the notification for releasing the connection between the bus and the shared memory ports corresponding to the remaining core multi-core processor system that notifies the memory controller. A memory controller having a plurality of cores and ports corresponding to the cores of the plurality of cores and connected to a bus ;
In the having respective port physical address space assigned to preparative method for controlling a multi-core processor system with a shared memory for storing correspondence information between the number of cores to assign the software to run the software on the plurality of cores There,
The first core of the plurality of cores, pre SL based on the respective processing loads of correspondence information and the plurality of cores to determine the execution core to assign execution target software of the plurality of cores, processes Run,
If determined the execution core there are a plurality, one of the core of the execution core, the logical address space defined before Symbol executed software, assigned to each port corresponding to the core of the execution core A physical address space that is a collection of physical address spaces is set in the memory controller, and processing is performed.
When there are a plurality of the execution cores, the remaining cores other than the one of the execution cores notify the connection between the bus and the shared memory of the port corresponding to the remaining cores. A method for controlling a multi-core processor system that executes processing to notify a memory controller. A memory controller having a plurality of cores and ports corresponding to the cores of the plurality of cores and connected to a bus ;
In the having respective port physical address space assigned to preparative, the control program of the multi-core processor system having a shared memory for storing correspondence information between the number of cores to assign the software to run the software on the plurality of cores In the first core of the plurality of cores,
Before SL based on the respective processing loads of correspondence information and the plurality of cores to determine the execution core to assign execution target software of the plurality of cores,
If determined the execution core there are a plurality of the logical address space defined before Symbol executed software, a physical address space that aggregates the physical address space assigned to each port corresponding to the core of the execution core Is set in the memory controller,
When there are a plurality of execution cores, a process of notifying the memory controller of a notification of releasing the connection between the bus and the shared memory of the port corresponding to the remaining core except for any one of the execution cores is performed. A control program for a multi-core processor system to be executed.

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