JP5708450B2 - Multi-core processor system, register utilization method, and register utilization program - Google Patents

Description

  The present invention relates to a multi-core processor system, a register utilization method, and a register utilization program relating to a register utilization method.

  In recent years, an increasing number of devices adopt a form of a multi-core processor system having a plurality of cores in one system. In addition, by using multiple cores, application software (hereinafter referred to as “apps”) is divided into multiple threads and parallelized in units of threads. High-speed processing is possible than when executing. A thread is a unit of program execution.

  Further, by reducing the processing amount of threads and using fine-grain parallelism, the multi-core processor system can improve the performance of parallel processing in units of threads. At this time, the fine-grained thread is executed while sharing a register among the threads. As a processing code for sharing a register, for example, a thread that reads a value from a register waits for synchronization, and a thread that writes a register value sends a synchronization notification to the synchronization waiting thread. As a technique for sharing a register, for example, there is a technique in which a core executes each thread using a method of using an internal register of another core without using its own internal register. Further, a technique is disclosed in which each CPU writes a value to its own register, and the value is written to the register of another processor (see, for example, Patent Documents 1 and 2 below).

JP-A-6-231085 JP 2003-99249 A

  However, in the above-described conventional technology, the number of synchronization notifications and the number of synchronization waits are uneven or equal for each thread, and the processing capability differs depending on the core depending on the technology sharing the register. There is a problem that the processing capacity is reduced.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-core processor system, a register use method, and a register use program capable of improving the processing capability in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, according to one aspect of the present invention, the difference between the number of synchronization notifications and the number of synchronization waits for at least one of the threads assigned to each of the plurality of cores By acquiring information indicating that the value based on the value is greater than a predetermined value, and when the information is acquired, by sharing the register of the core that performs synchronization notification among the plurality of cores with the other cores. Proposes a multi-core processor system for executing each thread, a register use method, and a register use program.

  According to another aspect of the present invention, it is indicated that the value based on the difference between the number of synchronization notifications and the number of synchronization waits is less than or equal to a predetermined value for any of the threads allocated to each of the plurality of cores. Acquire information, and when the information is acquired, each time the value of the register of one of the multiple cores is updated, the thread is executed by multiple cores by copying to the register of the other core A multi-core processor system, a register utilization method, and a register utilization program are proposed.

  Further, according to another aspect of the present invention, is a value based on a difference between the number of synchronization notifications and the number of synchronization waits related to at least one of the threads allocated to each of the plurality of cores greater than a predetermined value? If it is determined that the value is greater than the predetermined value, each thread is executed by a plurality of cores by sharing the register of the core that performs synchronization notification among the plurality of cores with other cores. A multi-core processor system, a register utilization method, and a register utilization program are proposed.

  According to one aspect of the present invention, the processing capacity can be improved.

FIG. 1 is an explanatory diagram illustrating an example of thread allocation in which the number of synchronization notifications and the number of synchronization waits are biased. FIG. 2 is an explanatory diagram showing an example of thread allocation in which the number of synchronization notifications and the number of synchronization waiting are not biased. FIG. 3 is a block diagram illustrating a hardware example of the multi-core processor system. FIG. 4 is an explanatory diagram of an example of the type of synchronization instruction. FIG. 5 is a block diagram illustrating an example of functions of the multi-core processor system. FIG. 6 is an explanatory diagram showing an example of the stored contents of profile information. FIG. 7 is an explanatory diagram illustrating an example of the execution result of a thread having a biased synchronization instruction. FIG. 8 is an explanatory diagram illustrating an example of the execution result of a thread in which there is no bias in synchronization instructions. FIG. 9 is an explanatory diagram illustrating an example of a determination method of the register value sharing method. FIG. 10 is an explanatory diagram illustrating an example of a precondition for the first thread group. FIG. 11 is an explanatory diagram illustrating an example of a result when the first thread group is executed using the sharing method or the copying method. FIG. 12 is an explanatory diagram illustrating an example of a precondition for the second thread group. FIG. 13 is an explanatory diagram illustrating an example of a result when the second thread group is executed using the sharing method or the copying method. FIG. 14 is an explanatory diagram illustrating an example of a precondition for the third thread group. FIG. 15 is an explanatory diagram illustrating an example of a result when the third thread group is executed using the sharing method or the copying method. FIG. 16 is a flowchart illustrating an example of register use processing. FIG. 17 is a flowchart illustrating another example of register use processing. FIG. 18 is an explanatory diagram showing an application example of a system using a computer according to the present embodiment.

  Exemplary embodiments of a disclosed multi-core processor system, a register utilization method, and a register utilization program will be described below in detail with reference to the accompanying drawings.

  FIG. 1 is an explanatory diagram illustrating an example of thread allocation in which the number of synchronization notifications and the number of synchronization waits are biased. A multi-core processor system 100 shown in FIG. 1 includes CPU # 0 to CPU # 2 as a plurality of CPUs, and is connected by a bus 101. CPU # 0 to CPU # 2 have registers R0 to R4, and share the values of the registers of CPU # 0 to CPU # 2 under the control of register I / F 102 # 0 to register I / F 102 # 2. To do.

  First, CPU # 0 obtains information indicating that a value based on the difference between the number of synchronization notifications and the number of waiting for synchronization related to thread A_0 to thread A_2 assigned to CPU # 0 to CPU # 2 is greater than a predetermined value. . Information indicating that the value based on the difference between the number of synchronization notifications and the number of waiting for synchronization is greater than a predetermined value is referred to as information indicating that the synchronization command is biased in the following description. At this time, thread A_0 to thread A_2 are premised on performing fine-grain parallel processing, and are required to share the register values of CPU # 0 to CPU # 2.

  The number of synchronization notifications is the number of times that the synchronization notification of the synchronization command is executed, and the number of synchronization waits is the number of times of waiting for the synchronization of the synchronization command. Details of the synchronization command will be described with reference to FIG. A specific value of the predetermined value will be described later with reference to FIG.

  Regarding the thread A_0, since the number of synchronization notifications of the thread A_0 is 6 and the number of synchronization waits is 0, the difference is 6, and if the predetermined value is 3, the difference becomes larger than the predetermined value. In # 0, information indicating that the synchronization command is biased is acquired. Subsequently, the CPU # 0 uses the register of the CPU # 0 as a sharing source, so that the CPU # 1 and the CPU # 2 access the register of the CPU # 0 through the register I / F 102. / F102 # 2 is notified.

  As described above, the multi-core processor system 100 causes the CPU # 1 and the CPU # 2 to share the register of the CPU # 0 that executes the synchronization notification among the CPU # 0 to the CPU # 2, thereby the CPU # 0 to the CPU # 2. Thread A_0 to thread A_2 are executed. Hereinafter, the register utilization method shown in FIG. 1 is referred to as a sharing method. In the sharing method, the processing of the CPU that becomes the sharing source becomes faster because it accesses its own register, and the other CPUs become slower because they access the CPU that becomes the sharing source via the bus 101.

  In the state of FIG. 1, since the processing of CPU # 0 that performs synchronization notification becomes high speed, the waiting time of CPU # 1 and CPU # 2 that wait for synchronization decreases, and the overall utilization efficiency of CPU # 0 to CPU # 2 Will improve.

  FIG. 2 is an explanatory diagram showing an example of thread allocation in which the number of synchronization notifications and the number of synchronization waiting are not biased. In the multi-core processor system 100 shown in FIG. 2, the CPU # 0 has a value based on the difference between the number of synchronization notifications and the number of synchronization waiting for the thread B_0 to thread B_2 assigned to the CPU # 0 to CPU # 2 equal to or less than a predetermined value Information indicating that is. Information indicating that the value based on the difference between the number of synchronization notifications and the number of synchronization waits is equal to or less than a predetermined value is referred to as information indicating that there is no bias in the synchronization command in the following description. At this time, thread B_0 to thread B_2 are premised on performing fine-grain parallel processing, and are required to share the register values of CPU # 0 to CPU # 2.

  Since the number of synchronization notifications for thread B_0 is 3 and the number of synchronization waits is 3, the difference is 0, and if the predetermined value is 3, the difference is less than or equal to the predetermined value. Information indicating that there is no bias in the synchronization command is acquired. In addition, the CPU # 0 acquires information indicating that there is no bias in the synchronization commands regarding the thread B_1 and the thread B_2. Subsequently, the CPU # 0 notifies the register I / F 102 # 0 to the register I / F 102 # 2 so that each CPU updates the value of its own register so that it is copied to the register of another CPU.

  As described above, the multi-core processor system 100 copies the CPU # 0 to CPU # 2 by copying it to the register of another CPU every time the value of the register of any of the CPUs # 0 to CPU # 2 is updated. In thread 2, thread B_0 to thread B_2 are executed. Hereinafter, the register usage method shown in FIG. 2 is referred to as a copying method. In the copying method, copying does not occur when the register is read, so that processing can be performed at high speed, and copying occurs when writing to the register, and processing is slow. In the copying method, the processing capability of each CPU is the same.

  In the state of FIG. 2, since the processing capability of each CPU is the same in the state where there is no bias in the synchronization command, the synchronization waiting time is reduced, and as a result, the overall utilization efficiency can be improved. As shown in FIGS. 1 and 2, the multi-core processor system 100 uses a sharing method in which the processing capacity of the CPU is biased when the thread has a bias in the synchronous instruction, and the thread has no bias in the synchronous instruction. Use a copying method that does not bias the processing power of the CPU. In this way, the overall processing capability can be improved by matching the bias of the synchronization instruction of each thread with the bias of the processing capability of each CPU. The multi-core processor system 100 that operates as shown in FIGS. 1 and 2 will be described below with reference to FIGS.

(Hardware of the multi-core processor system 100)
FIG. 3 is a block diagram illustrating a hardware example of the multi-core processor system. Multi-core processor system 100 in the present embodiment assumes a mobile terminal such as a mobile phone. In FIG. 3, the multi-core processor system 100 includes CPUs 301, a ROM (Read-Only Memory) 302, and a RAM (Random Access Memory) 303. The multi-core processor system 100 includes a flash ROM 304, a flash ROM controller 305, and a flash ROM 306. The multi-core processor system 100 includes a display 307, an I / F (Interface) 308, and a keyboard 309 as input / output devices for a user and other devices. Each unit is connected by a bus 101.

  Here, the CPUs 301 are responsible for overall control of the multi-core processor system 100. The CPUs 301 includes CPU # 0 to CPU # 2. Further, the number of CPUs included in the multi-core processor system 100 may be two or more. The CPUs 301 may have a dedicated cache memory. The multicore processor system 100 may be a multicore processor system including a plurality of cores. The multi-core processor system is a computer system including a processor having a plurality of cores. If a plurality of cores are mounted, a single processor having a plurality of cores may be used, or a processor group in which single core processors are arranged in parallel may be used. In the present embodiment, an example in which CPUs that are single-core processors are arranged in parallel will be described.

  The ROM 302 stores a program such as a boot program. The RAM 303 is used as a work area for the CPUs 301. The flash ROM 304 is a flash ROM having a high reading speed, and is, for example, a NOR flash memory. For example, the flash ROM 304 stores system software such as an OS (Operating System), applications, and the like. For example, when updating the OS, the multi-core processor system 100 receives the new OS through the I / F 308 and updates the old OS stored in the flash ROM 304 to the received new OS.

  The flash ROM controller 305 controls reading / writing of data with respect to the flash ROM 306 according to the control of the CPUs 301. The flash ROM 306 is a flash ROM mainly intended for data storage and transportation, and is, for example, a NAND flash memory. The flash ROM 306 stores data written under the control of the flash ROM controller 305. Specific examples of the data include image data and video data acquired by the user using the multi-core processor system 100 through the I / F 308, and a program for executing the register using method according to the present embodiment. As the flash ROM 306, for example, a memory card, an SD card, or the like can be adopted.

  The display 307 displays data such as a document, an image, and function information including a cursor, an icon, or a tool box. As the display 307, for example, a TFT (Thin Film Transistor) liquid crystal display can be adopted.

  The I / F 308 is connected to a network 310 such as a LAN, a WAN (Wide Area Network), and the Internet through a communication line, and is connected to another device via the network 310. The I / F 308 controls an internal interface with the network 310 and controls input / output of data from an external device. For example, a modem or a LAN adapter may be employed as the I / F 308.

  The keyboard 309 has keys for inputting numbers, various instructions, and the like, and inputs data. The keyboard 309 may be a touch panel type input pad or a numeric keypad.

  FIG. 4 is an explanatory diagram of an example of the type of synchronization instruction. The diagram denoted by reference numeral 401 shows an example of the execution codes of the threads A_0 and A_1. The diagram denoted by reference numeral 402 shows the execution results of the threads A_0 and A_1. The characteristics of the synchronization command shown from 402 are shown. Both the thread A_0 and the thread A_1 use the register R1, and a synchronization instruction is inserted so that the order of writing to and reading from the register R1 is not changed.

  In the following description, the position of the synchronization instruction in the execution code is defined as a synchronization point. Further, when the position where the synchronization command can be executed is reached, it is called that the synchronization point has been reached. Also, the barrier synchronization of the synchronization commands has a function of proceeding to the next processing when all the threads included in the specific group arrive at the synchronization point. This specific group is defined as a synchronization group. The synchronization command includes synchronization notification, synchronization wait, and barrier synchronization.

  First, the CPU # 0 that executes the thread A_0 writes the sum of the register R2 and the register R3 to the register R1 as a preceding instruction at the time t0, and sends the syncs instruction that is a synchronization notification to the CPU # 1 at the time t2. Execute as a notification destination. The CPU # 1, which executes the thread A_1, executes the preceding instruction at time t0, and notifies the CPU # 0 of the syncr instruction waiting for synchronization at time t1, which is earlier than time t2. Run as. At time t1, since CPU # 0 has not reached the synchronization point, CPU # 1 waits until a synchronization notification is received. At time t3 when the synchronization notification is completed, CPU # 0 executes the subsequent instruction, and at the same time, CPU # 1 also finishes waiting for synchronization and executes the subsequent instruction.

  Next, CPU # 0 executes a synca instruction which is barrier synchronization at time t4. At time t4, since CPU # 1 has not reached the synchronization point, CPU # 0 waits until CPU # 1 reaches the synchronization point. At time t5, CPU # 1 executes a synca instruction.

  As described above, as indicated by reference numerals 401 and 402, as a series of processes including the synchronization notification, the CPU executes the synchronization notification after the preceding instruction ends, and after the synchronization notification ends, Run. Therefore, as shown in Table 403, the CPU executing the synchronization notification does not have to wait for the synchronization waiting side.

  Similarly, as a series of processing including synchronization waiting, the CPU executes synchronization waiting after completion of the preceding instruction, and executes subsequent instructions after receiving the synchronization notification. Therefore, the CPU executing the waiting for synchronization does not have to wait if the synchronization notification has already been received.

  Similarly, as a series of processes including barrier synchronization, the CPU executes the subsequent instruction when all the CPUs belonging to the synchronization group have reached the synchronization point after the preceding instruction is completed. Therefore, the CPU executing the barrier synchronization does not have to wait if other CPUs belonging to the same synchronization group reach the synchronization point at the same time.

(Functions of the multi-core processor system 100)
Next, functions of the multi-core processor system 100 will be described. FIG. 5 is a block diagram illustrating an example of functions of the multi-core processor system. The multi-core processor system 100 includes a scheduler 501, a register use library 502, and a dispatcher 503.

  The multi-core processor system 100 includes a detection unit 511, an update unit 512, an acquisition unit 513, a determination unit 514, a specification unit 515, a notification unit 516, an execution unit 517, and an allocation unit 518. The functions (detecting unit 511 to allocating unit 518) serving as the control unit realize the functions by executing a program stored in the storage device by any one of the CPUs 301. Specifically, the storage device is, for example, the ROM 302, the RAM 303, the flash ROM 304, the flash ROM 306, etc. shown in FIG. Alternatively, the function may be realized by being executed by another CPU via the I / F 308.

  Further, in FIG. 5, each functional unit is illustrated as being a function of CPU # 0, but may be a function of CPU # 1 and CPU # 2. The detection unit 511 to the notification unit 516 are functions of the register use library 502, the execution unit 517 is a function of the register I / F 102, and the allocation unit 518 is a function of the dispatcher 503.

  The multi-core processor system 100 can access the profile information 521. Details of the profile information 521 will be described later with reference to FIG. The profile information 521 exists in the RAM 303, the flash ROM 304, the flash ROM 306, and the like.

  The scheduler 501 has a function of assigning a thread to be executed in the multi-core processor system 100 to each CPU and selecting a thread to be executed next. For example, the scheduler 501 assigns the thread A_0 to the CPU # 0 and assigns the thread A_1 to the CPU # 1.

  Upon receipt of the thread allocation notification from the scheduler 501, the register use library 502 informs the register I / F 102 whether to use either the sharing method or the copying method among the register sharing methods, or not to share the registers. Notice. Further, the register use library 502 notifies the dispatcher 503 of the thread allocation notification received from the scheduler 501 as it is when there is no change in the thread allocation, and notifies the changed thread allocation notification when there is a change.

  The dispatcher 503 has a function of switching the currently operating thread to the next thread determined by the scheduler 501 and the register use library 502. For example, when switching from the thread A_0 executed by the CPU # 0 to the thread B_0, the dispatcher 503 saves register information including a program counter of the thread A_0. After saving, the dispatcher 503 restores the saved register information of the thread B_0. After returning, the dispatcher 503 can continue the processing of the thread B_0 from the time when it was switched last time.

  The detection unit 511 has a function of detecting that a thread is assigned to any one of a plurality of cores. For example, the detection unit 511 detects that the thread A_0 is assigned to the CPU # 0.

  Further, the detection unit 511 may detect that the synchronization wait has been completed in any thread. For example, the detection unit 511 detects that the synchronization waiting has been completed in the thread A_1 being executed. The detection target may include synchronization notification and barrier synchronization. The detection result is stored in a storage area such as the RAM 303, the flash ROM 304, and the flash ROM 306.

  The update unit 512 has a function of updating the number of synchronization notifications and the number of synchronization waits related to a thread when the detection unit 511 detects that synchronization wait has been completed in any thread. For example, the profile information 521 of the thread A_0 is the number of synchronization notifications: 6, the number of synchronization waits: 0, and the profile information 521 of the thread A_1 is the number of synchronization notifications: 0, the number of synchronization waits: 6. In this state, for example, it is assumed that the detection unit 511 detects that the synchronization notification issued from the thread A_0 is completed in the thread A_1. At this time, the update unit 512 updates the profile information 521 of the thread A_0 to the synchronization notification count: 5, the synchronization wait count: 0, and the thread A_1 profile information 521 to the synchronization notification count: 0 and the synchronization wait count: 5. .

  The acquisition unit 513 has a function of acquiring information indicating that a value based on a difference between the number of synchronization notifications and the number of synchronization waits for at least one of the threads allocated to each of the plurality of cores is greater than a predetermined value. Have The information indicating that the value based on the difference between the number of synchronization notifications and the number of waiting for synchronization is larger than a predetermined value is information indicating that the synchronization command is biased and indicates that the synchronization command is biased Information is recorded in profile information 521. The profile information 521 may store an identifier indicating that the synchronization command is biased, or may store values of the number of synchronization notifications and the number of synchronization waits. The identifier indicating that the synchronization instruction is biased may be set by the designer of the multi-core processor system 100.

  Further, information indicating that the synchronization instruction related to the thread is biased is information indicating that the synchronization instruction described in the program in the thread is biased. Therefore, the profile information 521 stores information indicating that the synchronization command is biased for each thread. For example, the acquisition unit 513 acquires information that has a bias in the synchronization command regarding the thread A_0.

  In addition, the acquisition unit 513 acquires information indicating that the value based on the difference between the number of synchronization notifications and the number of synchronization waits is less than or equal to a predetermined value for any of the threads assigned to each of the plurality of cores. Also good. Information indicating that the value based on the difference between the number of synchronization notifications and the number of synchronization waits is equal to or less than a predetermined value is information indicating that there is no bias in the synchronization command, and that there is no bias in the synchronization command. The information shown is recorded in the profile information 521. For example, the profile information 521 stores an identifier indicating that there is no bias in the synchronization command. For example, the acquisition unit 513 acquires information indicating that there is no bias in the synchronization command in all threads as the profile information 521 of the thread A_0 to the thread A_2. The acquired profile information 521 or a pointer to the profile information 521 is stored in a storage area such as the RAM 303, the flash ROM 304, and the flash ROM 306.

  The determination unit 514 has a function of determining whether or not a value based on a difference between the number of synchronization notifications related to at least one of the threads assigned to each of the plurality of cores and the number of synchronization waits is greater than a predetermined value. Have.

  As a specific determination method, for example, the determination unit 514 determines whether or not the absolute value of the difference between the synchronization notification count and the synchronization wait count is greater than a predetermined value. Further, the determination unit 514 may determine whether or not a value obtained by dividing the absolute value of the difference between the number of synchronization notifications and the number of synchronization waits by the total number of synchronization instructions is greater than a predetermined value.

  Further, the determination unit 514 has a value based on the difference larger than a predetermined value when the detection unit 511 detects that a thread is allocated or when the update unit 512 updates information indicating a bias regarding the thread. It may be determined whether or not. The determination result is stored in a storage area such as the RAM 303, the flash ROM 304, and the flash ROM 306.

  The specifying unit 515 has a function of specifying a thread based on the difference between the number of synchronization notifications related to the thread and the number of synchronization waits when the execution unit 517 executes a thread by sharing a register. As a specific specifying method, for example, the specifying unit 515 may specify a thread that maximizes the difference between the synchronization notification count and the synchronization wait count. Alternatively, the specifying unit 515 may specify one of the threads in which the difference between the number of synchronization notifications and the number of synchronization waits is a predetermined value or more. Alternatively, the specifying unit 515 may specify a thread having a maximum value obtained by dividing the difference between the synchronization notification count and the synchronization wait count by the total number of synchronization instructions. Note that the information of the identified thread is stored in a storage area such as the RAM 303, the flash ROM 304, and the flash ROM 306.

  When the information indicating that the value based on the difference is larger than the predetermined value is acquired by the acquisition unit 513, the notification unit 516 is configured to share the register of the core that performs synchronization notification among the plurality of cores with other cores. It has a function of notifying the register I / F 102 that the method is used. Further, the notification unit 516 may notify the use of the sharing method when the determination unit 514 determines that the value based on the difference is larger than a predetermined value. In addition, the notification unit 516 may notify the allocation unit 518 to allocate the thread specified by the specifying unit 515 to a core that is a register sharing source among a plurality of cores.

  In addition, when the acquisition unit 513 acquires profile information 521 that the synchronization command is not biased, the notification unit 516 updates the value of the register of one of the cores every time the value of the register of the other core is updated. It may be notified that a copying method of copying to a register is used. Further, the notification unit 516 may notify the use of the copying method when the determination unit 514 determines that there is no bias in the synchronization command for any thread.

  The execution unit 517 has a function of executing a thread by a plurality of cores in accordance with an instruction whether to use the sharing method notified from the notification unit 516 or the copy method. For example, as a sharing method, the execution unit 517 executes the thread A_0 to the thread A_2 by causing other cores to share a register of a core that performs synchronization notification among a plurality of cores. Further, as a copying method, the execution unit 517 executes the thread B_0 to the thread B_2 by copying to the register of another core every time the value of the register of one of the plurality of cores is updated.

  The allocation unit 518 has a function of allocating the identified thread notified from the notification unit 516 to the core that becomes the register sharing source. For example, the assigning unit 518 assigns the thread A_0 to the CPU # 0 that is the register sharing source.

  FIG. 6 is an explanatory diagram showing an example of the stored contents of profile information. In the profile information 521 shown in FIG. 6, records 521-1 to 521-9 are registered. The profile information 521 includes five fields: thread ID, total number of synchronization instructions, number of synchronization notifications, number of synchronization waits, and number of barrier synchronizations. The thread ID field stores information for uniquely identifying the target thread. The total number of synchronization notifications, synchronization waits, and barrier synchronizations in the target thread is stored in the total number field of synchronization instructions. The synchronization notification number field stores the number of synchronization notifications in the target thread. The synchronization wait number field stores the number of synchronization waits in the target thread. The barrier synchronization number field stores the number of barrier synchronizations in the target thread.

  For example, the record 521-1 indicates that the total number of synchronization instructions is 6, the number of synchronization notifications is 6, and the number of synchronization waits and the number of barrier synchronizations are 0. The profile information 521 may be generated when a developer creates a program, or may be generated by the OS analyzing a binary program of a thread before thread execution.

  FIG. 7 is an explanatory diagram illustrating an example of the execution result of a thread having a biased synchronization instruction. In the diagram indicated by reference numeral 701, the multi-core processor system 100 executing the sharing method assigns a thread A_1 having a lot of synchronization waiting to the CPU # 0 as a register sharing source, and a thread having a lot of synchronization notifications to the CPU # 1. A_0 is assigned. In the diagram indicated by reference numeral 702, the multi-core processor system 100 executing the sharing method assigns the thread A_0 to the CPU # 0 as the register sharing source and assigns the thread A_1 to the CPU # 1.

  First, since the CPU # 0 in the reference numeral 701 is a register sharing source, the processing is completed quickly, and a synchronization notification from the thread A_0 is awaited. For example, after ending the process number {1} of the thread A_1, the CPU # 0 waits for a synchronization notification from the process number 2 of the thread A_0 by the CPU # 1. A similar phenomenon occurs with process number {3} and process number {5}. In this way, if a thread with a high synchronization wait is assigned to a CPU that is a register sharing source, the latency granularity is reduced.

  Next, since the CPU # 0 at the reference numeral 702 is the register sharing source, the processing is completed early, and the CPU # 1 is notified of the synchronization with the processing numbers {2}, {4}, and {6}. , Wait. As described above, if a thread with a large number of synchronization notifications is assigned to a CPU that is a register sharing source, the granularity of the waiting time is increased. As the granularity of the waiting time increases, DVFS (Dynamic Voltage and Frequency Scaling) becomes easier to use, and processing of other applications becomes easier to execute. This is because DVFS has a minimum time that can be applied, and DVFS cannot be applied if the latency granularity is small. Also, regarding the processing of other processes, if the granularity of the waiting time is small, the overhead for switching to the other processes increases.

  FIG. 8 is an explanatory diagram illustrating an example of the execution result of a thread in which there is no bias in synchronization instructions. In the diagram indicated by reference numeral 801, the multi-core processor system 100 executing the sharing method assigns a thread B — 1 with no bias to the synchronization instruction to the CPU # 0 as the register sharing source, and assigns the synchronization instruction to the CPU # 1. An unbiased thread B_0 is assigned. In the diagram indicated by reference numeral 802, the multi-core processor system 100 executing the copying method assigns thread B_1 to CPU # 0 and assigns thread B_0 to CPU # 1.

  First, since the CPU # 0 in the reference numeral 801 is a register sharing source, the processing is completed early and a synchronization notification from the thread B_0 is awaited. For example, after ending the process number {1} of the thread B_0, the CPU # 0 waits for a synchronization notification from the process number {2} of the thread B_0 by the CPU # 1. A similar phenomenon occurs even with process number {5}.

  Next, since CPU # 0 and CPU # 1 in the reference numeral 802 are copying methods, the processing speed is the same, so the time for waiting for synchronization is shorter than the figure indicated by the reference numeral 801. As described above, when there is no bias in the synchronization instruction, the thread is executed by using the copying method, so that the CPU performance difference is eliminated and the synchronization waiting time is reduced. Therefore, the multi-core processor system 100 increases the processor utilization efficiency. It can be improved.

  FIG. 9 is an explanatory diagram illustrating an example of a determination method of the register value sharing method. FIG. 9 illustrates a method for determining which method to use as the register value sharing method, which method to use, the sharing method or the copying method.

  The multi-core processor system 100 uses the sharing method when there is one or more threads that satisfy the following expression (1) in the thread group.

  | (Number of synchronization notifications−Number of synchronization waits) / Total number of synchronization instructions |> α (1)

  Here, | x | means the absolute value of x, and α is a constant. The predetermined value shown in FIGS. 1 and 2 is, for example, α. For example, α = 0.4. The multi-core processor system 100 uses a copying method when the following expression (2) is satisfied.

  Number of barrier synchronizations / total number of synchronization instructions> β (2)

  Here, β is a constant. For example, β = 0.5. Further, when it is determined that the sharing method is used, the multi-core processor system 100 executes an evaluation expression represented by the following expression (3) for each thread, and determines the thread having the largest value as the CPU that becomes the register sharing source. Assign to.

  (Number of synchronization notifications-number of synchronization waits) / total number of synchronization instructions (3)

  Further, the multi-core processor system 100 may use the sharing method when the expression (1) is satisfied, and may use the copying method when the expression (1) is not satisfied. Further, when a certain thread satisfies the expression (1) and another thread satisfies the expression (2), the multi-core processor system 100 uses a sharing method.

  Hereinafter, the determination method of the register value sharing method shown in FIG. 9 is executed, and execution results of the first to third thread groups will be described with reference to FIGS. For example, it is assumed that the thread groups belong to different applications. For example, the first thread group belongs to the app 1, the second thread group belongs to the app 2, and the third thread group belongs to the app 3.

  Further, the first thread group is assumed to be a thread group in which the synchronization instruction is biased, and is, for example, the thread A_0 to the thread A_2 illustrated in FIG. The second thread group is assumed to be a thread group in which there is no bias in the synchronization instruction, and is, for example, the thread B_0 to the thread B_2 illustrated in FIG. The third thread group assumes a case in which a thread having a biased synchronization instruction and a thread having a biased synchronization instruction are mixed, for example, the thread C_0 to the thread C_2 illustrated in FIG.

  FIG. 10 is an explanatory diagram illustrating an example of a precondition for the first thread group. A table 1001 shows the CPU processing capacity in the sharing method and the CPU processing capacity in the copying method. In the precondition 1002, the processing amount of the thread A_0 to the thread A_2 as the first thread group, Details of synchronization notification and waiting for synchronization are shown. A table 1003 shows the calculation results of the expressions (1) to (3) regarding the thread A_0 to the thread A_2. Note that the profile information 521 of the thread A_0 to the thread A_2 in FIG. 10 is the same as the value shown in FIG.

  As shown in Table 1001, for example, the processing capacity of a CPU that accesses its own register by the sharing method is 300 [number of instructions / us], and the processing of the CPU that accesses the register of another CPU by the sharing method Assume that the capability is 100 [number of instructions / us]. Further, it is assumed that the processing capability of the CPU of the copying method is 150 [number of instructions / us].

  Further, in the precondition 1002, for example, the processing number {1} of the thread A_0 has a processing amount of 600 [number of instructions], and a synchronization notification is transmitted to the processing number {5}. Subsequently, the thread A_0 performs processing in the order of processing numbers {4}, {7}, {10}, {13}, and {14}. Further, the processing number {2} of the thread A_1 has a processing amount of 450 [number of instructions], and no synchronous instruction is performed. Subsequently, the thread A_1 performs processing in the order of processing numbers {5}, {8}, and {11}. Further, the processing number {3} of the thread A_2 has a processing amount of 600 [number of instructions], and no synchronous instruction is performed. Subsequently, the thread A_2 performs processing in the order of processing numbers {6}, {9}, and {12}.

  As shown in Table 1003, the multi-core processor system 100 executes Expressions (1) and (2) for the thread A_0 to the thread A_2. For example, the expression (1) for the thread A is executed as follows.

  | (6-0) / 6 | = 1> 0.4

  Thus, the thread A_0 satisfies the expression (1). Similarly, the formula (2) for the thread A_0, the formula (1) and the formula (2) for the thread A_1 and the thread A_2 are calculated. Regarding the calculation result of the expression (1), since all the threads A_0 to A_2 satisfy the expression (1), the multi-core processor system 100 uses a sharing method. Further, the multi-core processor system 100 executes Expression (3) and assigns the thread A_0 to the CPU # 0 because the thread A_0 has the largest value from the calculation result of the expression (3).

  FIG. 11 is an explanatory diagram illustrating an example of a result when the first thread group is executed using the sharing method or the copying method. In the example of FIG. 11, the time chart 1101 shows the result when the thread A_0 is assigned to the CPU # 0 using the sharing method as determined in FIG. For comparison, the time chart 1102 shows the result when the thread A_0 is assigned to the CPU # 2 using the sharing method. Similarly, a time chart 1103 shows the results when the copying method is used. The time required for each process is the result of dividing the processing amount shown in the precondition 1002 by the processing capacity shown in the table 1001.

  In the time chart 1101, the CPU # 0 executing the thread A_0 executes the process numbers {1}, {4}, {7}, {10}, {13}, {14}, and 11.5 [us To finish the process. The CPU # 1 that executes the thread A_1 executes the process numbers {2}, {5}, {8}, and {11}, and ends the process at 19.5 [us]. Similarly, the CPU # 2 executing the thread A_2 executes the process numbers {3}, {6}, {9}, and {12}, and ends the process at 19.5 [us].

  In the time chart 1102, the CPU # 2 executing the thread A_0 ends the process at 34.5 [us], which is not illustrated. Compared with the results of the time chart 1101, in the time chart 1102, the processing of the thread A_0 takes time, and as a result, the processing of the thread A_1 and the thread A_2 waiting for notification also takes time. Further, the CPU # 0 executing the thread A_2 has a waiting time from 2 [us] to 12 [us], for example.

  In the time chart 1103, the CPU # 0 executing the thread A_0 ends the process at 23 [us]. The CPU # 1 executing the thread A_1 ends the process at 22 [us], and the CPU # 2 executing the thread A_2 ends the process at 26 [us]. Compared with the result of the time chart 1101, in the time chart 1103, the processing of the thread A_0 takes time. In addition, the CPU # 1 and the CPU # 2 have generated a short time for waiting for synchronization. For example, in CPU # 1, waiting occurs in a minute time such as 3 [us] to 4 [us] and 8 [us] to 11 [us], and in CPU # 2, 4 [us] to 8 [us] ], 11 [us] to 15 [us], waiting has occurred.

  FIG. 12 is an explanatory diagram illustrating an example of a precondition for the second thread group. A table 1001 shows the CPU processing capacity in the sharing method and the CPU processing capacity in the copying method. In the precondition 1201, the processing amount of the thread B_0 to the thread B_2 as the second thread group, Details of synchronization notification and waiting for synchronization are shown. Table 1202 shows calculation results of Expressions (1) to (3) regarding the thread B_0 to the thread B_2. Note that the profile information 521 of the thread B_0 to thread B_2 in FIG. 12 is the same as the value shown in FIG. The table 1001 is the same as the value described in FIG.

  As indicated by the precondition 1201, for example, the processing number {1} of the thread B_0 has a processing amount of 600 [number of instructions] and transmits a synchronization notification to the processing number {5}. Next, the processing number {4} of the thread B_0 has a processing amount of 450 [number of instructions], waits for synchronization from the processing number {3}, and transmits a synchronization notification to the processing number {8}. Subsequently, the thread B_0 performs processing in the order of processing numbers {7} and {10}. Further, the processing number {2} of the thread B_1 has a processing amount of 450 [number of instructions], and a synchronization notification is transmitted to the processing number {6}. Subsequently, the thread B_1 performs processing in the order of processing numbers {5}, {8}, and {11}. Further, the processing number {3} of the thread B_2 has a processing amount of 600 [number of instructions], and a synchronization notification is transmitted to the processing number {4}. Subsequently, the thread B_2 performs processing in the order of processing numbers {6}, {9}, and {12}.

  As shown in Table 1202, the multi-core processor system 100 executes Expressions (1) and (2) for the thread B_0 to the thread B_2. Regarding the calculation result of the expression (1), since all the threads B_0 to B_2 do not satisfy the expression (1), the multi-core processor system 100 uses a copying method.

  FIG. 13 is an explanatory diagram illustrating an example of a result when the second thread group is executed using the sharing method or the copying method. In the example of FIG. 13, the time chart 1301 shows the result when the copying method is used as determined in FIG. For comparison, a time chart 1302 shows the results when the sharing method is used.

  In the time chart 1301, the CPU # 0 executing the thread B_0 executes the process numbers {1}, {4}, {7}, {10}, and ends the process at 16 [us]. The CPU # 1 that executes the thread B_1 executes the process numbers {2}, {5}, {8}, and {11}, and ends the process at 16 [us]. Similarly, the CPU # 2 executing the thread B_2 executes the process numbers {3}, {6}, {9}, and {12}, and ends the process at 15 [us].

  In the time chart 1302, the CPU # 0 executing the thread B_0 ends the process at 20 [us]. Also, the CPU # 1 executing the thread B_1 ends the process at 21 [us]. Further, the CPU # 2 executing the thread B_2 ends the process at 22.5 [us]. Compared with the result of the time chart 1301, in the time chart 1302, the processing of the thread B_1 and the thread B_2 takes time.

  FIG. 14 is an explanatory diagram illustrating an example of a precondition for the third thread group. A table 1001 shows the CPU processing capacity in the sharing method and the CPU processing capacity in the copying method. The precondition 1401 includes the processing amount of the threads C_0 to C_2 as the third thread group. Details of synchronization notification and waiting for synchronization are shown. A table 1402 shows calculation results of Expressions (1) to (3) regarding the thread C_0 to the thread C_2. Note that the profile information 521 of the thread C_0 to the thread C_2 in FIG. 14 is the same as the value shown in FIG. The table 1001 is the same as the value described in FIG.

  As shown in the diagram shown in the precondition 1401, for example, the processing number {1} of the thread C_0 has a processing amount of 600 [number of instructions], and a synchronization notification is transmitted to the processing number {5}, and the processing number {4 } Has a processing amount of 600 [number of instructions] and transmits a synchronization notification to the processing number {6}. Further, the processing number {2} of the thread C_1 has a processing amount of 450 [number of instructions], and the synchronization processing is not performed. Further, the processing number {3} of the thread B_2 has a processing amount of 600 [number of instructions], and a synchronization notification is transmitted to the processing number {5}.

  As shown in Table 1402, the multi-core processor system 100 executes Expressions (1) and (2) for the threads C_0 to C_2. Regarding the calculation result of the expression (1), since the thread C_0 and the thread C_1 satisfy the expression (1), the multi-core processor system 100 uses a sharing method. Further, the multi-core processor system 100 executes Expression (3) and assigns the thread C_0 to the CPU # 0 because the thread C_0 has the largest value from the calculation result of the expression (3).

  FIG. 15 is an explanatory diagram illustrating an example of a result when the third thread group is executed using the sharing method or the copying method. In the example of FIG. 15, the time chart 1501 shows the result when the thread C_0 is assigned to the CPU # 0 using the sharing method as determined in FIG. For comparison, a time chart 1502 shows a result when the thread C_0 is assigned to the CPU # 2 using the sharing method. Similarly, a time chart 1503 shows the result when the copying method is used.

  In the time chart 1501, the CPU # 0 executing the thread C_0 executes the process numbers {1}, {4}, {7}, {10}, {13}, {14}, and 11.5 [us To finish the process. The CPU # 1 that executes the thread C_1 executes the process numbers {2}, {5}, {8}, and {11}, and ends the process at 21 [us]. Similarly, the CPU # 2 executing the thread A_2 executes the process numbers {3}, {6}, {9}, and {12}, and ends the process at 19.5 [us].

  In the time chart 1502, the CPU # 2 executing the thread C_0 ends the process at 34.5 [us], which is not illustrated. Compared with the result of the time chart 1501, in the time chart 1502, the processing of the thread C_0 takes time, and as a result, the processing of the thread C_1 and the thread C_2 waiting for notification also takes time. Further, the CPU # 0 executing the thread C_2 has a waiting time from 2 [us] to 12 [us], for example.

  In the time chart 1503, the CPU # 0 executing the thread C_0 ends the process at 23 [us]. The CPU # 1 that executes the thread C_1 ends the process at 22 [us], and the CPU # 2 that executes the thread C_2 ends the process at 26 [us]. Compared with the result of the time chart 1501, in the time chart 1503, the processing of the thread C_0 takes time. In addition, the CPU # 1 and the CPU # 2 have generated a short time for waiting for synchronization. For example, in CPU # 1, waiting occurs in a minute time such as 3 [us] to 4 [us] and 8 [us] to 11 [us], and in CPU # 2, 4 [us] to 8 [us] ], 11 [us] to 15 [us], waiting has occurred.

  As shown in FIG. 15, when even one of a plurality of threads has a biased synchronization instruction, the multi-core processor system 100 can process a bottleneck thread at high speed by using the sharing method. The utilization efficiency of CPU # 0 to CPU # 2 can be improved.

  Subsequently, FIGS. 16 and 17 show flowcharts of the register use processing as shown in FIGS. The register use process executed by the multi-core processor system 100 may be either the register use process shown in FIG. 16 or the register use process shown in FIG. Note that the register use processing may be performed by any of the CPUs # 0 to # 2. In the present embodiment, for example, the case where CPU # 0 executes a register use process will be described.

  FIG. 16 is a flowchart illustrating an example of register use processing. The register use process shown in FIG. 16 is executed with a thread allocation notification from the scheduler as a trigger. The CPU # 0 detects that the thread is assigned to any of CPU # 0 to CPU # 2 by the scheduler 501 (step S1601). Hereinafter, in the description of FIG. 16, the assigned thread is referred to as a target thread. CPU # 0 determines whether or not the target thread is a fine-grain parallel processing (step S1602). As a method for determining whether or not the target thread is a fine-grain parallel processing, it is determined whether or not the fine-grain parallel processing is performed based on the presence or absence of a record corresponding to the target thread in the profile information 521.

  In the case of the fine-grain parallel processing (step S1602: Yes), the CPU # 0 acquires profile information corresponding to the allocation target thread (step S1603). Next, CPU # 0 executes formulas (1) and (2) from the profile information (step S1604). In addition, when a plurality of threads are assigned when executing one application, the CPU # 0 executes the expressions (1) and (2) for each of the plurality of threads.

  Based on the results of the expressions (1) and (2), the CPU # 0 determines whether or not the synchronization command is biased (step S1605). When the synchronization command is biased (step S1605: Yes), the CPU # 0 notifies the register I / F 102 that the specific CPU is used as a register sharing source and the sharing method is used (step S1606). Subsequently, CPU # 0 executes Expression (3) from the profile information (step S1607). Based on the result of the expression (3), the CPU # 0 notifies the dispatcher 503 to allocate the thread having the largest value of the expression (3) to a specific CPU (step S1608), and ends the register use process.

  If there is no bias in the synchronization command (step S1605: No), the CPU # 0 notifies the register I / F 102 that the copying method is to be used (step S1609). Next, the CPU # 0 notifies the dispatcher 503 to allocate the target thread as instructed by the scheduler 501 (step S1610), and ends the register use processing.

  If it is not the fine-grain parallel processing (step S1602: No), the CPU # 0 notifies the register I / F that the register value is not shared (step S1611), and the process proceeds to step S1610.

  FIG. 17 is a flowchart illustrating another example of register use processing. The register use process shown in FIG. 17 is executed with the completion of the synchronization instruction in the thread as a trigger. In addition, since processes other than step S1701, step S1704, step S1705, and step S1708 shown in FIG. 17 are the same as those shown in FIG.

  The CPU # 0 detects that the synchronization instruction has been completed in the executing thread (step S1701), and proceeds to the process of step S1702. Hereinafter, in the description of FIG. 17, the thread being executed is referred to as a target thread. Note that the synchronization command to be detected may be only synchronization waiting among synchronization notification, synchronization waiting, and barrier synchronization. The reason is that when the completion of the synchronization notification is detected, the synchronization wait is expected to be performed in the near future, and the frequent use of the register is prevented. Also, the barrier synchronization may not be included in the synchronization command to be detected.

  After executing the processing of step S1703, CPU # 0 decreases the profile information 521 by the number of issued synchronous instructions (step S1704). Next, CPU # 0 executes formulas (1) and (2) from the updated profile information 521 (step S1705), and proceeds to the processing of step S1706.

  Further, after executing the process of step S1707, CPU # 0 executes expression (3) from the updated profile information 521 (step S1708), and proceeds to the process of step S1709.

  FIG. 18 is an explanatory diagram showing an application example of a system using a computer according to the present embodiment. In FIG. 18, a network NW is a network in which a server 1801 and clients 1811 to 1814 can communicate, and includes, for example, a LAN, a WAN, the Internet, a mobile phone network, and the like.

  The client 1811 is a notebook PC (Personal Computer). The client 1812 is a desktop PC, and the client 1813 is a mobile phone. As a mobile phone, the client 1813 may be a smartphone or a PHS (Personal Handyphone System). The client 1814 is a tablet terminal.

  The server 1801 and the clients 1811 to 1814 in FIG. 18 execute the register using method according to the present embodiment as the multi-core processor system described in the embodiment. For example, a plurality of CPUs in the server 1801 execute the register using method according to the present embodiment.

  As described above, according to the multi-core processor system, the register utilization method, and the register utilization program, it is acquired that there is a bias in the synchronization instruction issued by the thread, and the CPU register that performs synchronization notification is shared with other CPUs Use a sharing method. As a result, the CPU that performs the synchronization notification executes faster and the waiting time of the CPU waiting for the notification is shortened, so that the overall processing performance is improved. In addition, if a thread with a lot of synchronization notification is assigned to a CPU that is a register sharing source, the granularity of the waiting time increases, so that the multi-core processor system can easily use DVFS and execute other applications.

  In addition, the multi-core processor system may acquire a fact that there is no bias in the synchronous instruction issued by the thread, and use a copying method that copies the value to the register of another CPU each time the CPU updates the value of its own register. Good. As a result, the multi-core processor system eliminates the performance difference between the CPUs, thereby reducing the synchronization waiting time and improving the CPU processing capability.

  Further, the multi-core processor system determines whether or not a value based on the difference is larger than a predetermined value for at least one thread, and if it is larger, a sharing method may be used. This allows the multi-core processor system to switch the register usage method to the shared method when executing a thread with a bias even if a thread group with a bias in the synchronous instruction and a thread group without a bias are sequentially executed. The processing capacity can be improved.

  In addition, the multi-core processor system determines whether or not a value based on the difference between the number of synchronization notifications and the number of waiting for synchronization is greater than a predetermined value for at least one thread. A method may be used. This allows the multi-core processor system to switch the register usage method to the copy method when executing a non-biased thread group even when sequentially executing a thread group with a biased synchronous instruction and a non-biased thread group. The processing capacity can be improved.

  The multi-core processor system may determine whether a value based on the difference is larger than a predetermined value when a thread is assigned to the CPU. Thereby, the multi-core processor system can switch the usage method at the timing before the thread is executed.

  In addition, when the multi-core processor system detects that the synchronization wait has been completed in the thread, the multi-core processor system updates the synchronization notification count and the synchronization wait count, and based on the difference between the updated synchronization notification count and the synchronization wait count, It may be determined whether there is a bias. As a result, the multi-core processor system can use a more optimal register utilization method even during execution of a thread.

  For example, there is a bias in synchronous instructions when assigning threads, and if the group of threads executed using the sharing method has issued all synchronous instructions in the first half of the process, the second half of the process is copied. The processing power can be improved by using the method. When executing such a group of threads, the multi-core processor system detects the completion of synchronization wait and switches from the sharing method to the copying method, so that the overall processing capacity is more than that when the sharing method is always kept. Can be improved.

  In the case of using the sharing method, the multi-core processor system may specify the CPU to be assigned to the CPU that is the register sharing source based on the difference between the number of synchronization notifications related to threads and the number of synchronization waits. As a result, the multi-core processor system can assign a thread with a high ratio of waiting for other threads to a high-speed CPU, so that the waiting time of other threads can be reduced and the processing capacity can be improved. .

  Note that the register utilization method described in this embodiment can be realized by executing a program prepared in advance on a computer such as a personal computer or a workstation. The register utilization program is recorded on a computer-readable recording medium such as a hard disk, a flexible disk, a CD-ROM, an MO, and a DVD, and is executed by being read from the recording medium by the computer. The register use program may be distributed through a network such as the Internet.

  The following additional notes are disclosed with respect to the embodiment described above.

(Supplementary Note 1) Acquisition means for acquiring information indicating that a value based on a difference between the number of synchronization notifications and the number of synchronization waits for at least one of threads assigned to each of a plurality of cores is greater than a predetermined value When,
When the information is acquired by the acquisition means, execution means for executing the thread by the plurality of cores by sharing a register of a core that performs synchronization notification among the plurality of cores,
A multi-core processor system comprising:

(Additional remark 2) The acquisition means which acquires the information which shows that the value based on the difference of the number of synchronous notifications and the number of waiting for synchronization is below a predetermined value about any thread of the thread allocated to each of a plurality of cores;
When the information is acquired by the acquisition unit, each time the value of the register of one of the plurality of cores is updated, the thread is copied by the plurality of cores to the thread of the other core. Execution means for executing
A multi-core processor system comprising:

(Supplementary Note 3) Judgment means for judging whether or not a value based on a difference between the number of synchronization notifications and the number of synchronization waits for at least one of the threads assigned to each of the plurality of cores is larger than a predetermined value; ,
When the determination unit determines that the value is larger than the predetermined value, by sharing a register of a core that performs synchronization notification among the plurality of cores with other cores, Execution means to execute;
A multi-core processor system comprising:

(Supplementary Note 4) The execution means includes:
When it is determined by the determination means that the value is less than or equal to the predetermined value for any thread, each time the value of the register of one of the plurality of cores is updated, the value is stored in the register of the other core. Executing the thread with the plurality of cores by copying;
The multi-core processor system according to supplementary note 3, wherein

(Additional remark 5) It further has a detecting means for detecting that the thread is assigned to any one of the plurality of cores,
The determination means includes
When it is detected by the detection means that the thread is allocated, a value based on a difference between the synchronization notification count and the synchronization wait count regarding at least one of the threads allocated to each of the plurality of cores is obtained. Determine whether it is greater than a predetermined value,
The multi-core processor system according to appendix 3 or 4, characterized by the above.

(Supplementary Note 6) Detection means for detecting completion of synchronization waiting in any one of the threads,
An update means for updating the number of synchronization notifications and the number of synchronization waits related to the thread when the detection means detects that the waiting for synchronization is completed in any one of the threads;
The determination means includes
When the number of synchronization notifications and the number of synchronization waits related to the thread are updated by the updating means, the number of synchronization notifications and the number of synchronization waits for at least one of the threads assigned to each of the plurality of cores, To determine whether the value based on the difference between is greater than a predetermined value,
The multi-core processor system according to appendix 3 or 4, characterized by the above.

(Supplementary note 7) When the execution unit executes the thread by causing the sharing, the specifying unit that specifies the thread based on the difference between the synchronization notification number and the synchronization waiting number related to the thread among the plurality of threads ,
An allocating unit that allocates the thread identified by the identifying unit to a core that is a register sharing source among the plurality of cores;
The multi-core processor system according to any one of supplementary notes 3, 5, and 6, further comprising:

(Appendix 8) Obtaining information indicating that a value based on a difference between the number of synchronization notifications and the number of waiting for synchronization regarding at least one of the threads assigned to each of the plurality of cores is greater than a predetermined value;
When the information is acquired, the thread is executed by the plurality of cores by causing other cores to share the register of the core that performs synchronization notification among the plurality of cores.
A register utilization method in which a specific core among the plurality of cores executes processing.

(Supplementary Note 9) Acquire information indicating that the value based on the difference between the number of synchronization notifications and the number of synchronization waits for any of the threads assigned to each of the plurality of cores is equal to or less than a predetermined value,
When the information is acquired, each time the value of the register of any of the plurality of cores is updated, the thread is executed by the plurality of cores by copying to the register of another core.
A register utilization method in which a specific core among the plurality of cores executes processing.

(Additional remark 10) It is judged whether the value based on the difference of the synchronous notification number regarding the at least any one thread among the threads allocated to each of a plurality of cores and the synchronous waiting number is larger than a predetermined value,
When it is determined that the value is greater than the predetermined value, the thread is executed by the plurality of cores by causing another core to share a register of a core that performs synchronization notification among the plurality of cores.
A register utilization method in which a specific core among the plurality of cores executes processing.

(Supplementary Note 11) Obtaining information indicating that a value based on a difference between the number of synchronization notifications and the number of waiting for synchronization regarding at least one of the threads allocated to each of the plurality of cores is greater than a predetermined value;
When the information is acquired, by causing another core to share a register of a core that performs synchronization notification among the plurality of cores, the plurality of cores execute the thread.
A register use program that causes a specific core of the plurality of cores to execute processing.

(Supplementary Note 12) For any of the threads assigned to each of the plurality of cores, obtain information indicating that the value based on the difference between the synchronization notification count and the synchronization wait count is equal to or less than a predetermined value,
When the information is acquired, each time the value of the register of one of the plurality of cores is updated, the thread is copied to the register of another core, thereby causing the plurality of cores to execute the thread.
A register use program that causes a specific core of the plurality of cores to execute processing.

(Additional remark 13) It is judged whether the value based on the difference of the synchronous notification number regarding the at least any one thread among the threads allocated to each of a plurality of cores and the synchronous waiting number is larger than a predetermined value,
When it is determined that the value is larger than the predetermined value, by causing another core to share a register of a core that performs synchronization notification among the plurality of cores, the plurality of cores execute the thread.
A register use program that causes a specific core of the plurality of cores to execute processing.

# 0 to # 2 CPU
A_1 to A_2 Thread 101 Bus 501 Scheduler 502 Register use library 503 Dispatcher 511 Detection unit 512 Update unit 513 Acquisition unit 514 Judgment unit 515 Identification unit 516 Notification unit 517 Execution unit 518 Allocation unit 521 Profile information

Claims (9)

An acquisition unit configured to acquire information indicating that a value based on a difference between the number of synchronization notifications and the number of synchronization waits regarding at least one of the threads allocated to each of the plurality of cores is greater than a predetermined value;
When the information is acquired by the acquisition means, execution means for executing the thread by the plurality of cores by sharing a register of a core that performs synchronization notification among the plurality of cores,
A multi-core processor system comprising: An acquisition means for acquiring information indicating that a value based on a difference between the number of synchronization notifications and the number of waiting for synchronization is less than or equal to a predetermined value for any of the threads assigned to each of the plurality of cores;
When the information is acquired by the acquisition unit, each time the value of the register of one of the plurality of cores is updated, the thread is copied by the plurality of cores to the thread of the other core. Execution means for executing
A multi-core processor system comprising: A determination unit that determines whether or not a value based on a difference between the number of synchronization notifications and the number of synchronization waits for at least one of the threads allocated to each of the plurality of cores is greater than a predetermined value;
When the determination unit determines that the value is larger than the predetermined value, by sharing a register of a core that performs synchronization notification among the plurality of cores with other cores, Execution means to execute;
A multi-core processor system comprising: The execution means includes
When it is determined by the determination means that the value is less than or equal to the predetermined value for any thread, each time the value of the register of one of the plurality of cores is updated, the value is stored in the register of the other core. Executing the thread with the plurality of cores by copying;
The multi-core processor system according to claim 3. Detecting means for detecting that the thread is assigned to any one of the plurality of cores;
The determination means includes
When it is detected by the detection means that the thread is allocated, a value based on a difference between the synchronization notification count and the synchronization wait count regarding at least one of the threads allocated to each of the plurality of cores is obtained. Determine whether it is greater than a predetermined value,
The multi-core processor system according to claim 3 or 4, wherein Detecting means for detecting completion of synchronization waiting in any one of the threads;
An update means for updating the number of synchronization notifications and the number of synchronization waits related to the thread when the detection means detects that the waiting for synchronization is completed in any one of the threads;
The determination means includes
When the number of synchronization notifications and the number of synchronization waits related to the thread are updated by the updating means, the number of synchronization notifications and the number of synchronization waits for at least one of the threads assigned to each of the plurality of cores, To determine whether the value based on the difference between is greater than a predetermined value,
The multi-core processor system according to claim 3 or 4, wherein When the execution means executes the thread by causing the sharing, the specifying means for specifying the thread based on the difference between the number of synchronization notifications and the number of synchronization waits for the thread among the plurality of threads,
An allocating unit that allocates the thread identified by the identifying unit to a core that is a register sharing source among the plurality of cores;
The multi-core processor system according to claim 3, further comprising: Obtaining information indicating that a value based on a difference between the number of synchronization notifications and the number of synchronization waits regarding at least one of the threads allocated to each of the plurality of cores is greater than a predetermined value;
When the information is acquired, the thread is executed by the plurality of cores by causing other cores to share the register of the core that performs synchronization notification among the plurality of cores.
A register utilization method in which a specific core among the plurality of cores executes processing. Obtaining information indicating that a value based on a difference between the number of synchronization notifications and the number of synchronization waits regarding at least one of the threads allocated to each of the plurality of cores is greater than a predetermined value;
When the information is acquired, by causing another core to share a register of a core that performs synchronization notification among the plurality of cores, the plurality of cores execute the thread.
A register use program that causes a specific core of the plurality of cores to execute processing.

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