JP5811853B2 - Sensor signal processing circuit and vehicle safe driving apparatus using the same - Google Patents

Description

  The present invention relates to a sensor signal processing circuit and a vehicle safe driving apparatus using the same.

  Conventionally, a ring delay pulse generation circuit comprising a plurality of delay elements connected in a ring shape is provided, and after the ring delay pulse generation circuit starts to circulate the pulse PA, the pulse PB is input to the ring delay pulse generation circuit. Thus, there is a pulse phase difference encoding circuit that encodes the phase difference between the pulse PA and the pulse PB at the input timing of the pulse PB (see, for example, Patent Document 1).

  According to this, in the ring delay pulse generation circuit, the time from when the pulse PA starts to circulate until the pulse PB is input thereafter can be measured as the phase difference.

JP-A-6-28384

  The present inventor pays attention to reducing the measurement error included in the phase difference, and uses the pulse phase difference encoding circuit of Patent Document 1 to emit laser light from the laser diode and then reflect it by the photodiode. The time until the laser beam was received was measured, and it was studied to obtain normalized data obtained by normalizing the measured time (hereinafter referred to as measurement time) with a reference value.

  For example, the control circuit emits laser light from the laser diode, and the ring delay pulse generation circuit starts the circulation of the pulse PA. Thereafter, the reflected laser light is received by the photodiode and output from the photodiode. Is output to the pulse phase difference encoding circuit as a pulse PB, the phase difference between the pulse PA and the pulse PB can be obtained as the measurement time.

  Here, external noise may be superimposed on the light reception pulse output from the photodiode. For this reason, it is necessary to provide a waveform shaping circuit for shaping the waveform of the received light pulse between the pulse phase difference encoding circuit and the photodiode. However, there is a delay time from when the received light pulse is received by the waveform shaping circuit to when the received light pulse is output from the waveform shaping circuit. For this reason, the measurement time includes a measurement error due to the delay time. Therefore, simply by normalizing the measurement time with the reference value, the normalized data includes a measurement error. In addition to this, the delay time generated in the waveform shaping circuit changes due to a temperature change of the waveform shaping circuit. For this reason, the measurement error included in the normalized data changes due to the temperature change of the waveform shaping circuit.

  In view of the above, the present invention reduces a measurement error included in normalized data in a sensor signal processing circuit that obtains normalized data obtained by normalizing the time required to receive reflected light after emitting light. The first object is to provide a vehicle safe driving device that uses the normalized data to allow the vehicle to travel safely.

In order to achieve the above object, according to the first aspect of the present invention, the control circuit (36) outputs a trigger signal to the light emitting element and transmits a control pulse through the first selection gate (42) at the first timing. Output to the phase difference detection circuit, the second selection gate (41) causes the second pulse based on the received light pulse to be output to the phase difference detection circuit to detect the phase difference corresponding to the received light pulse,
The control circuit outputs a control pulse to the phase difference detection circuit through the first selection gate (42) at a second timing different from the first timing, and outputs the first substitute pulse to the output switching means (35) and the first switching pulse. The second selection gate (41) outputs the second pulse to the phase difference detection circuit to detect the phase difference corresponding to the first substitute pulse; and After a certain period (Ts) after the output of the control pulse, a second substitute pulse is applied to the second selection gate (41), and the second pulse is output from the second selection gate (41) to the phase difference detection circuit. The phase difference corresponding to the second substitute pulse is detected,
The phase difference corresponding to the received light pulse is Da, the phase difference corresponding to the first substitute pulse is Db, the phase difference corresponding to the second substitute pulse is De, and normalized data (Da−Db) / De The data operation circuit (34) which calculates | requires is provided.

  According to the first aspect of the present invention, the phase difference De indicates a phase difference generated between the first pulse and the second pulse during the certain period. Then, the control circuit gives the second substitute pulse to the first selection gate (42) bypassing the first waveform shaper. For this reason, the phase difference De does not include the measurement error of the first waveform shaper.

  The phase difference Db indicates a delay time (that is, measurement error) from when the received light pulse is received by the first waveform shaper to when the received light pulse is output from the first waveform shaper. Therefore, by subtracting the phase difference Db from the phase difference Da, the measurement error due to the delay time of the first waveform shaper can be removed from the phase difference Da.

  Here, the phase differences Da, Db, and De obtained by the phase difference detection circuit include measurement errors caused by disturbances such as temperature changes.

  Therefore, by dividing (Da−Db) by De, the measurement error of the phase difference detection circuit can be canceled in the normalized data. Therefore, the measurement error of the first waveform shaper and the measurement error of the phase difference detection circuit can be removed from the normalized data. For this reason, the measurement error contained in the normalized data can be reduced.

  Furthermore, in the invention according to claim 1, the control circuit bypasses the first waveform shaper and outputs the second substitute pulse to the phase difference detection circuit to output the second selection gate (41). Used. For this reason, the delay time until the second pulse is output from the second selection gate (41) after the second selection gate (41) receives one of the received light pulse and the first substitute pulse. Although it occurs, the first selection gate (42) is also arranged between the control circuit and the phase difference detection circuit. For this reason, there is a delay time from when the first selection gate receives the control pulse until the control pulse is output from the first selection gate (42). Here, the first and second selection gates have the same circuit configuration. For this reason, the delay time generated in the first selection gate and the delay time generated in the second selection gate are the same time. Therefore, in the phase difference required for the phase difference detection circuit, the delay time generated in the second selection gate is offset by the delay time generated in the first selection gate. Therefore, no error occurs in the phase difference obtained by the phase difference detection circuit due to the delay time generated in the second selection gate. As a result, it is possible to avoid the measurement error caused by the delay time generated in the first and second selection gates from being included in the normalized data.

In the invention according to claim 4, the peak hold circuit (50) for sampling the peak voltage of the received light pulse and holding the output voltage at the sampled voltage;
A bottom hold circuit (51) for sampling the bottom voltage of the received light pulse and holding the output voltage at the sampled voltage;
When the first substitute pulse output from the control circuit (36) is received, the first substitute pulse whose peak voltage is the same as the output voltage of the peak hold circuit and whose bottom voltage is the same as the output voltage of the bottom hold circuit. And a second waveform shaping circuit (52 to 55) for outputting to the output switching means (35).

According to the fourth aspect of the present invention, the peak voltage of the first substitute pulse output from the output switching means to the first waveform shaper is the same as the peak voltage of the received light pulse, and the bottom of the first substitute pulse. The voltage is the same as the bottom voltage of the received light pulse. For this reason,
The delay time that occurs after the first substitute pulse is output from the first waveform shaper after the first substitute pulse is input to the first waveform shaper, and the received light pulse is supplied to the first waveform shaper. It is possible to approach the delay time that occurs when the received light pulse is output from the first waveform shaper after being input. For this reason, the accuracy of the phase difference (Db) corresponding to the first substitute pulse can be increased.

In the invention according to claim 5, a first averaging processing circuit (56) for outputting an average voltage value indicating an average value of the output voltage output for each sampling from the peak hold circuit;
A second averaging processing circuit (57) for outputting an average voltage value indicating an average value of output voltages output for each sampling from the bottom hold circuit;
Upon receiving the first substitute pulse output from the control circuit (36), the peak voltage is the same as the output voltage of the first averaging processing circuit (56), and the bottom voltage is the second averaging processing circuit ( And a third waveform shaping circuit (52 to 55) for outputting a first substitute pulse having the same output voltage as the output voltage to the output switching means (35).

  According to the fifth aspect of the invention, the peak voltage of the first substitute pulse is the same as the output voltage of the first averaging processing circuit (56), and the bottom voltage of the first substitute pulse is the second voltage. It becomes the same as the output voltage of the averaging processing circuit (57). For this reason, the delay time of the first substitute pulse generated in the first waveform shaper can be made closer to the light reception pulse delay time generated in the first waveform shaper. Thereby, the accuracy of the phase difference (Db) corresponding to the first substitute pulse can be further increased.

  In the invention according to claim 6, when the distance (theoretical value) through which light propagates during a certain period is L, L × {(Da−Db) / De} / 2 is set between the sensor and the obstacle. It is characterized by comprising distance calculation means (34) for calculating as a distance between them.

  According to the invention described in claim 6, since the distance between the sensor and the obstacle is obtained using {(Da-Db) / De} obtained in the invention described in claim 1, the accuracy is high. The distance can be determined.

In the seventh aspect of the invention, the control pulse is output to the phase difference detection circuit at the first timing , the first circuit is started to circulate in the ring circuit, and the trigger signal is output to the light emitting element. The first pulse shaper outputs a second pulse based on the received light pulse to the phase difference detection circuit, the phase difference detection circuit detects the phase difference corresponding to the received light pulse, and the control circuit is different from the first timing. The control pulse is output to the phase difference detection circuit at two timings, and the first substitute pulse (PC1) replacing the received light pulse is output to the phase difference detection circuit through the output switching means (35) and the first waveform shaper (31). The output is detected by detecting the phase difference corresponding to the first substitute pulse, and the second substitute pulse (PC2) is output after a certain period (Ts) has elapsed after the start of the circulation of the first pulse. And by detecting the phase difference corresponding to the second substitute pulse is output to the phase difference detection circuit through a first waveform shaper,
The phase difference corresponding to the received light pulse after waveform shaping is Da, the phase difference corresponding to the first substitute pulse is Db, the phase difference corresponding to the second substitute pulse is Dc, and normalized data is (Da A data operation circuit (34) for obtaining -Db) / (Dc-Db) is provided.

  According to the seventh aspect of the invention, the phase difference Db indicates a delay time from when the received light pulse is received by the first waveform shaper to when the received light pulse is output from the first waveform shaper. Yes. Therefore, by subtracting the phase difference Db from the phase difference Da, the measurement error due to the delay time can be removed from the phase difference Da. By subtracting the phase difference Db from the phase difference Dc, the measurement error due to the delay time can be removed from the phase difference Dc.

  Here, the phase difference Da indicates a light propagation time required for the light receiving element to receive light after the light emitting element emits light. The phase difference Dc indicates a phase difference generated between the first pulse and the second pulse during the certain period.

  The phase difference obtained by the phase difference detection circuit may include a measurement error due to a disturbance such as a temperature change.

  Therefore, by dividing (Da−Db) by (Dc−Db), the measurement error of the phase difference detection circuit can be canceled in the normalized data. Therefore, the measurement error of the first waveform shaper and the measurement error of the phase difference detection circuit can be removed from the normalized data obtained by normalizing the light propagation time. For this reason, the measurement error contained in the normalized data can be reduced.

  In the invention according to claim 8, when the distance that light propagates during a certain period is L, L × {(Da−Db) / (Dc−Db)} / 2 is set between the sensor and the obstacle. It is characterized by comprising distance calculation means (34) for calculating as a distance between them.

  According to the invention described in claim 8, the distance between the sensor and the obstacle is obtained using {(Da-Db) / (Dc-Db)} obtained in the invention described in claim 7. Therefore, the distance can be obtained with high accuracy.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

It is a figure which shows the circuit structure of the signal processing circuit for sensors in 1st Embodiment of this invention. It is a figure which shows the circuit structure of the pulse phase difference encoding circuit in FIG. It is a timing chart for demonstrating the action | operation of the signal processing circuit for sensors of FIG. It is a figure which shows the circuit structure of the signal processing circuit for sensors in 2nd Embodiment of this invention. FIG. 5 is a diagram showing a circuit configuration of a peak hold circuit in FIG. 4. FIG. 5 is a diagram illustrating a circuit configuration of a bottom hold circuit in FIG. 4. 5 is a timing chart for explaining the operation of the sensor signal processing circuit of FIG. 4. It is a timing chart for demonstrating the action | operation of the said bottom hold circuit. It is a timing chart for demonstrating the action | operation of the said peak hold circuit. It is a figure which shows the circuit structure of the signal processing circuit for sensors in 3rd Embodiment of this invention. It is a figure which shows the circuit structure of the averaging process circuit of FIG. It is a timing chart for demonstrating the action | operation of the averaging process circuit of FIG. It is a timing chart for demonstrating the action | operation of the averaging process circuit of FIG. It is a figure which shows the circuit structure of the signal processing circuit for sensors in 4th Embodiment of this invention. It is a timing chart for demonstrating the action | operation of the signal processing circuit for sensors of FIG. It is a figure which shows the whole vehicle-mounted system structure in 5th Embodiment of this invention. It is a figure which shows the control processing in VSC_ECU of FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.

(First embodiment)
FIG. 1 is a diagram showing a circuit configuration of an automotive ranging system_ECU 100 to which a sensor signal processing circuit according to a first embodiment of the present invention is applied.

  The distance measuring system_ECU 100 is for measuring a distance between an obstacle (for example, a forward vehicle) in front of the host vehicle and a distance sensor (host vehicle). The own vehicle is an automobile on which the ranging system_ECU 100 is mounted. A forward vehicle is an automobile located in front of the traveling direction with respect to the host vehicle.

  Specifically, the ranging system_ECU 100 includes a diode 10, a photodiode 11, an operational amplifier 13, an nMOS transistor 14, a resistance element R1, and a sensor signal processing circuit 20.

  The diode 10 constitutes a light emitting element, and is connected between the power supply Vdd and the ground, and is disposed, for example, with the light emitting part facing the front of the vehicle. The diode 10 is a laser diode that emits laser light. The nMOS transistor 14 is disposed between the diode 10 and the ground, and connects or opens the diode 10 and the ground.

  The photodiode 11 constitutes a light receiving element and detects reflected laser light emitted from the diode 10 and reflected by an obstacle, and is arranged between the power supply Vdd and the ground. The resistance element R1 is disposed between the light receiving diode 11 and the ground.

  The diode 10 and the photodiode 11 of this embodiment constitute a distance sensor.

  The operational amplifier 13 constitutes a circuit for impedance conversion by connecting its inverting input terminal (−) to the output terminal, and outputs the voltage between both terminals of the resistance element R1 to the light receiving terminal 60 of the sensor signal processing circuit 20. To do. A non-inverting input terminal (+) of the operational amplifier 13 is connected to a common connection terminal 15 between the photodiode 11 and the resistance element R1.

  The sensor signal processing circuit 20 includes a D / A converter 30, a comparator 31, a pulse phase difference encoding circuit 32, an arithmetic processing circuit 34, a switch 35, a control circuit 36, and OR gates 41 and 42.

  The D / A converter 30 converts predetermined digital data into an analog signal and supplies the analog signal to the inverting input terminal (−) of the comparator 31. As will be described later, the output voltage of the D / A converter 30 is used as a threshold value for comparing the magnitude of the input voltage applied to the non-inverting input terminal (+) in the comparator 31. As will be described later, the comparator 31 constitutes a waveform shaper that shapes the signal output from the switch 35.

  The pulse phase difference encoding circuit 32 has a phase difference from the rising timing of the control signal supplied from the OR gate 42 to the input terminal PA to the rising timing of the signal supplied from the OR gate 41 to the input terminal PB ( This is a phase difference detection circuit that encodes (time) into a binary digital signal. That is, the pulse phase difference encoding circuit 32 calculates the phase difference from when the control pulse is supplied from the OR gate 42 to the input terminal PA until the pulse PB is supplied from the OR gate 41 to the input terminal PB. Will be detected.

  Specifically, the pulse phase difference encoding circuit 32 includes the ring delay pulse generation circuit 1, the counter 2, the data latch circuits 3 and 4, the delay circuit 5, the pulse selector 6, the encoder 7, and the like that constitute the above-mentioned Patent Document 1. In addition, a circuit configuration for initializing the counter 2 and the data latch circuits 3 and 4 by a reset signal RST is added to the pulse phase difference encoding circuit (see FIG. 2) having the multiplexer 8.

  Here, it is a well-known technique to reset the counter 2 and the data latch circuits 3 and 4 by supplying a reset signal RST to the counter 2 and the data latch circuits 3 and 4. For this reason, it is considered that the pulse phase difference encoding circuit 32 of the present embodiment and the pulse phase difference encoding circuit of Patent Document 1 described above are substantially the same. Therefore, a specific description of the pulse phase difference encoding circuit 32 of the present embodiment is omitted.

  Here, the ring delay pulse generation circuit 1 includes a plurality of signal delay elements connected in a ring shape, and constitutes a ring circuit that circulates an input pulse PA as described later. The counter 2 counts the number of times the pulse PA has circulated in the ring delay pulse generation circuit 1 after the pulse PA is input to the ring delay pulse generation circuit 1. The data latch circuits 3 and 4 specify the number of circulations of the pulse PA at the input timing of the pulse PB input after the input of the pulse PA in the ring delay pulse generation circuit 1. The multiplexer 8 outputs one of the output signals D1 and D2 of the data latch circuits 3 and 4 as HB. The pulse selector 6 specifies the rotation position of the pulse PA at the input timing of the pulse PB in the ring delay pulse generation circuit 1 and outputs a signal indicating the specified rotation position to the encoder 7. The encoder 7 encodes the output signal of the pulse selector 6 into a binary digital signal and outputs it as LB. LB constitutes the lower bits of the phase difference data D1 output from the pulse phase difference encoding circuit 32, and HB constitutes the upper bits of the phase difference data D1.

  Further, the arithmetic processing circuit 34 in FIG. 1 uses the phase difference obtained by the pulse phase difference encoding circuit 32, and the light required for the photodiode 11 to receive the reflected laser after the diode 10 emits the laser light. The propagation time normalized data is calculated, and the distance between the distance sensor and the obstacle is calculated based on the normalized data.

  The switch 35 constitutes an output switching means. The switch 35 opens between one of the operational amplifier 13 and the control circuit 36 and the non-inverting input terminal (+) of the comparator 31, and other than one of the operational amplifier 13 and the control circuit 36. Is connected to the non-inverting input terminal (+) of the comparator 31.

  The control circuit 34 controls the pulse phase difference encoding circuit 32, the arithmetic processing circuit 34, and the switch 35.

  The OR gate 41 includes first and second input terminals. The output terminal of the comparator 31 is connected to the first input terminal of the OR gate 41. The output terminal PC2 of the control circuit 36 is connected to the second input terminal of the OR gate 41. The OR gate 42 includes first and second input terminals. The output terminal of the control circuit 36 is connected to the first input terminal of the OR gate 42. By connecting the ground to the second input terminal of the OR gate 42, the signal level input to the second input terminal of the OR gate 42 is set to a low level.

  Next, the operation of the distance measuring system_ECU 100 of the present embodiment will be described with reference to FIG. 3A to 3L show timing charts, where FIG. 3A is a light emission trigger, FIG. 3B is a voltage change at the input terminal PA of the pulse phase difference encoding circuit, FIG. 3C is a received light signal, and FIG. Is a voltage change of the input terminal PC of the switch 35, (e) is a voltage change of the output terminal PC2 of the control circuit 36, (f) is a voltage change of the input terminal PB of the pulse phase difference encoding circuit, and (g) is a selection signal. SEL, (h) is phase difference data output from the pulse phase difference encoding circuit (denoted as D in the figure), (i) is a reset signal (RST), (j) is a reset signal (RST1), (k) Indicates a data load signal (LOAD), and (L) indicates an operation permission signal (ENA).

  First, the control circuit 36 outputs a pulse signal (see FIG. 3 (i)) as the reset signal RST to the pulse phase difference encoding circuit 32. For this reason, the pulse phase difference encoding circuit 32 is initialized. In addition to this, the control circuit 36 outputs a pulse signal (see FIG. 3J) as the reset signal RST1 to the arithmetic processing circuit 34. Thereby, the arithmetic processing circuit 34 is initialized.

  Next, the control circuit 36 outputs a low level selection signal SEL (see FIG. 3G) to the switch 35. Therefore, the switch 35 connects between the output terminal of the operational amplifier 13 and the non-inverting input terminal (+) of the comparator 31, and between the output terminal of the control circuit 36 and the non-inverting input terminal (+) of the comparator 31. Is released.

  Next, the control circuit 36 outputs a pulse as a light emission trigger (see FIG. 3A) to the gate terminal of the nMOS transistor 14 through the light emission trigger terminal 61 at timing t1. For this reason, the nMOS transistor 14 is turned on for a predetermined period based on the light emission trigger. Therefore, a current flows from the power supply Vdd to the ground through the diode 10 and the nMOS transistor 14. Therefore, the diode 10 emits laser light.

  In addition, the control circuit 36 changes the control signal level output to the first input terminal of the OR gate 42 from the low level (Lo) to the high level (Hi) at the timing t1. That is, the control circuit 36 outputs a control pulse to the first input terminal of the OR gate 42 at the timing t1. At this time, the second input terminal of the OR gate 42 is connected to the ground, and the signal level input to the second input terminal is set to the low level. Therefore, when receiving a control pulse from the control circuit 36, the OR gate 42 changes the control signal level output to the input terminal PA of the pulse phase difference encoding circuit 32 from the low level to the high level (FIG. 3B). reference). That is, the OR gate 42 outputs a control pulse to the input terminal PA of the pulse phase difference encoding circuit 32. For this reason, in the ring delay pulse generation circuit 1 of the pulse phase difference encoding circuit 32, the pulse PA starts to circulate.

  On the other hand, when the laser beam emitted from the diode 10 is reflected by an obstacle and the reflected laser beam is received by the photodiode 11, a pulse current is supplied from the power source Vdd to the ground through the photodiode 11 and the resistor element R1. Flowing. For this reason, the voltage between the common connection terminal 15 between the photodiode 11 and the resistance element R1 and the ground increases. That is, a light reception pulse is output from the photodiode 11 to the resistance element R1.

  Along with this, the signal level of the light receiving signal applied from the operational amplifier 13 to the non-inverting input terminal (+) of the comparator 31 through the light receiving terminal 60 and the switch 35 becomes a high level (see FIG. 3C). That is, the operational amplifier 13 outputs the received light pulse to the non-inverting input terminal (+) of the comparator 31 through the light receiving terminal 60 and the switch 35.

  Due to the light receiving pulse output in this way, the input voltage of the non-inverting input terminal (+) of the comparator 31 becomes higher than the input voltage of the inverting input terminal (−) only for a predetermined period.

  For this reason, the signal level given from the comparator 31 to the first input terminal of the OR gate 41 becomes a high level only for a predetermined period. That is, the comparator 31 shapes the light reception pulse output from the operational amplifier 13 and outputs the waveform-shaped pulse to the first input terminal of the OR gate 41. At this time, the signal level applied from the output terminal PC2 of the control circuit 36 to the second input terminal of the OR gate 41 is low.

  Accordingly, the OR gate 41 changes the level of the output signal for the input terminal PB of the pulse phase difference encoding circuit 32 from the low level to the high level in accordance with the high level signal output from the comparator 31 (FIG. 3). (Refer to (f)). That is, the OR gate 41 outputs the pulse PB to the input terminal PB of the pulse phase difference encoding circuit 32. Along with this, the pulse phase difference encoding circuit 32 specifies the circulation position of the pulse PA and the number of circulations of the pulse PA at the input timing of the pulse PB to the ring delay pulse generation circuit 1, respectively, and the identified circulation position. The phase difference Da between the pulse PA and the pulse PB is detected based on the rotation number and the number of laps, and the detected phase difference Da is output to the arithmetic processing circuit 34.

  Next, the control circuit 36 outputs the data load signal LOAD to the arithmetic processing circuit 34. Therefore, the arithmetic processing circuit 34 reads the phase difference Da output from the pulse phase difference encoding circuit 32.

  Here, the phase difference Da indicates the light propagation time required from when the diode 10 emits the laser light to when the photodiode 11 receives the laser light reflected by the obstacle. However, the phase difference Da includes a delay time that occurs when the comparator 31 shapes the received light pulse (that is, a delay time from when the received light pulse is input to the comparator 31 to when the received light pulse is output from the comparator 31). included. Therefore, the delay time including the phase difference Da is obtained as follows.

  First, the control circuit 36 outputs a high level signal (see FIG. 3I) to the pulse phase difference encoding circuit 32 as the reset signal RST. For this reason, the pulse phase difference encoding circuit 32 is initialized again. In addition to this, the control circuit 36 changes the signal level of the selection signal SEL from the low level to the high level (see FIG. 3G). Therefore, the switch 35 opens between the output terminal of the operational amplifier 13 and the non-inverting input terminal (+) of the comparator 31 according to the change in the signal level of the selection signal SEL, and the output terminal of the control circuit 36 and the comparator. The non-inverting input terminal (+) 31 is connected.

  Next, the control circuit 36 again changes the control signal level output to the first input terminal of the OR gate 42 from the low level (Lo) to the high level (Hi) at the timing t2. That is, the control circuit 36 outputs a control pulse to the first input terminal of the OR gate 42 at the timing t2. Therefore, when receiving a control pulse from the control circuit 36, the OR gate 42 changes the control signal level output to the input terminal PA of the pulse phase difference encoding circuit 32 from the low level to the high level (FIG. 3B). reference). That is, the OR gate 42 outputs a control pulse to the input terminal PA of the pulse phase difference encoding circuit 32. For this reason, in the ring delay pulse generation circuit 1 of the pulse phase difference encoding circuit 32, the pulse PA starts to circulate.

  In addition, the control circuit 36 outputs a substitute pulse PC1 (see FIG. 3D) instead of the received light pulse to the non-inverting input terminal (+) of the comparator 31 via the switch 35 at the timing t2.

  By the substitute pulse PC1 output in this way, the input voltage of the non-inverting input terminal (+) of the comparator 31 becomes higher than the input voltage of the inverting input terminal (−) only for a predetermined period. As a result, the substitute pulse PC1 is waveform-shaped by the comparator 31, and the waveform-shaped substitute pulse PC1 is output to the first input terminal of the OR gate 41. At this time, the signal level applied from the output terminal PC2 of the control circuit 36 to the second input terminal of the OR gate 41 is low.

  Thereby, the OR gate 41 changes the level of the output signal for the input terminal PB of the pulse phase difference encoding circuit 32 from the low level to the high level in accordance with the substitute pulse PC1 output from the comparator 31 (FIG. 3 ( f)). That is, the OR gate 41 outputs the pulse PB to the input terminal PB of the pulse phase difference encoding circuit 32.

  Along with this, the pulse phase difference encoding circuit 32 specifies the circulation position of the pulse PA and the number of circulations of the pulse PA at the input timing of the pulse PB to the ring delay pulse generation circuit 1, respectively, and the identified circulation position. The phase difference Db between the pulse PA and the pulse PB is detected based on the number of laps and the number of laps, and the detected phase difference Db is output to the arithmetic processing circuit 34.

  Next, the control circuit 36 outputs the data load signal LOAD to the arithmetic processing circuit 34. Therefore, the arithmetic processing circuit 34 reads the phase difference Db output from the pulse phase difference encoding circuit 32. As described above, the phase difference Db indicates a delay time (that is, an offset time) that occurs when the comparator 31 shapes the received light pulse.

  Thereafter, the control circuit 36 receives the substitute pulse PC2 (see FIG. 3E) instead of the received light pulse at the second input of the OR gate 41 at the timing t3 when a certain period Ts (for example, 2 μsec) has elapsed from the timing t2 described above. Output to the terminal. At this time, the signal level output from the comparator 31 to the first input terminal of the OR gate 41 is low. Therefore, when receiving the substitute pulse PC2 from the control circuit 36, the OR gate 41 changes the signal level output to the input terminal PB of the pulse phase difference encoding circuit 32 from the low level to the high level. That is, when the OR gate 41 receives the substitute pulse PC 2 from the control circuit 36, the OR gate 41 outputs the pulse PB to the input terminal PB of the pulse phase difference encoding circuit 32.

  Along with this, the pulse phase difference encoding circuit 32 specifies the circulation position of the pulse PA and the number of circulations of the pulse PA at the input timing of the pulse PB to the ring delay pulse generation circuit 1, respectively, and the identified circulation position. The phase difference De between the pulse PA and the pulse PB is detected based on the number of rotations and the number of laps, and the detected phase difference De is output to the arithmetic processing circuit 34.

  Thereafter, the control circuit 36 outputs a high level calculation enable signal ENA to the calculation processing circuit 34. Accordingly, the arithmetic processing circuit 34 reads the phase difference De output from the pulse phase difference encoding circuit 32. Accordingly, the arithmetic processing circuit 34 calculates the normalized data Ds by substituting the phase differences Da, Db, and De into the following Equation 1.

Ds = (Da−Db) / De (Equation 1)
Next, the arithmetic processing circuit 34 uses L and Ds as the distance calculation means, where L is the distance that the light propagates during a certain period Ts (= the period from timing t2 to timing t3). Substituting into Equation 2, the distance Z between the distance sensor and the obstacle is calculated.

Z = L × Ds ÷ 2 (Equation 2)
In the present embodiment, for example, if the fixed period Ts is 2 μsec, the distance L is 600 meters.

  In the present embodiment described above, the pulse phase difference encoding circuit 32 obtains the phase difference Da corresponding to the received light pulse, the phase difference Db corresponding to the substitute pulse PC1, and the phase difference De corresponding to the substitute pulse PC2.

  The phase difference Da indicates the time required from when the laser beam is emitted from the diode 10 to when the reflected laser beam is received by the photodiode 11. The phase difference Db indicates a delay time required from when the received light pulse is input to the comparator 31 to when the received light pulse is output from the comparator 31. The phase difference De indicates a phase difference generated between the pulse PA and the pulse PB in a certain period Ts (for example, 2 μsec).

  The phase difference Da includes a delay time that occurs when the received light pulse passes through the comparator 31. Therefore, by subtracting the phase difference Db from the phase difference Da, the delay time due to the comparator 31 can be removed from the phase difference Da.

Here, a measurement error may occur in the pulse phase difference encoding circuit 32 due to a disturbance such as a temperature change of the pulse phase difference encoding circuit 32. For this reason, the phase differences Da, Db, and De obtained by the pulse phase difference encoding circuit 32 may change due to a temperature change or the like of the pulse phase difference encoding circuit 32.
Therefore, by dividing (Da−Db) by De, the measurement error of the pulse phase difference encoding circuit 32 can be canceled in the normalized data Ds. Thereby, the normalized data obtained by removing the measurement error of the comparator 31 and the measurement error of the pulse phase difference encoding circuit 32 can be obtained. Therefore, measurement errors included in the normalized data can be reduced.

  In the present embodiment, since the normalized data {(Da−Db) / De} is used when calculating the distance L between the sensor and the obstacle, the distance L can be obtained with high accuracy.

  In this embodiment, in order to output the substitute pulse PC2 from the control circuit 36 to the input terminal PB of the pulse phase difference encoding circuit 32, bypassing the comparator 31, the output terminal PC2 of the control circuit 36 and the pulse phase difference encoding are output. An OR gate 41 is arranged between the input terminal PB of the circuit 32. Therefore, a delay time occurs when a pulse output from one of the output terminal PC2 of the control circuit 36 and the output terminal of the comparator 31 is input to the OR gate 41 and the pulse PB is output from the OR gate 41. However, an OR gate 42 is provided between the control circuit 36 and the input terminal PA of the pulse phase difference encoding circuit 32. Therefore, there is a delay time from when the control pulse from the control circuit 36 is input to the OR gate 42 until when the control pulse is output from the OR gate 42.

  Here, the OR gates 41 and 42 have the same circuit configuration. For this reason, the delay time generated in the OR gate 41 and the delay time generated in the OR gate 42 can be set to the same time. Therefore, the delay time generated in the OR gate 42 can be canceled in the phase differences Da, Db, and De. Therefore, the measurement error in the normalized data is not increased by the delay time of the OR gates 41 and 42.

(Second Embodiment)
In the second embodiment, an example in which the bottom voltage and the peak voltage of the substitute pulse PC1 are set using the bottom voltage and the peak voltage of the received light pulse output from the operational amplifier 13 in the first embodiment described above will be described.

  FIG. 4 is a diagram showing a circuit configuration of the automotive ranging system_ECU 100 according to the present embodiment of the present invention.

  The distance measuring system_ECU 100 of this embodiment is configured by adding a configuration for setting the bottom voltage and the peak voltage of the substitute pulse PC1 based on the output signal of the operational amplifier 13 to the distance measuring system_ECU 100 of FIG. .

  Therefore, hereinafter, the description of the common configuration between the present embodiment and the above-described first embodiment will be omitted, and different configurations will be described.

  In the distance measuring system_ECU 100 of the present embodiment, a peak hold circuit 50, a bottom hold circuit 51, switches 52 and 53, and NOT gates 54 and 55 are added to the distance measuring system_ECU 100 of FIG.

  The peak hold circuit 50 is a circuit for sampling the peak voltage of the received light pulse output from the operational amplifier 13. The bottom hold circuit 51 is a circuit for sampling the bottom voltage of the light reception pulse output from the operational amplifier 13. Details of the circuit configuration of the peak hold circuit 50 and the bottom hold circuit 51 will be described later. Hereinafter, for convenience, the peak hold circuit 50 and the bottom hold circuit 51 are simplified and referred to as hold circuits 50 and 51.

  The switches 52 and 53 are connected in series between the output terminal POUT of the peak hold circuit 50 and the output terminal BOUT of the bottom hold circuit 51. A common connection terminal 58 between the switches 52 and 53 is connected to the input terminal PC_A of the switch 35.

  The NOT gates 54 and 55 are connected in series between the light receiving terminal 60 and the control input terminal of the switch 52. The output terminal of the NOT gate 54 is connected to the control input terminal of the switch 53.

  The NOT gate 54 outputs an output signal corresponding to the substitute pulse PC 1 output from the output terminal PC of the control circuit 36 to the control input terminal of the switch 53. The NOT gate 55 outputs an output signal corresponding to the output signal of the NOT gate 54 to the control input terminal of the switch 52.

  Note that the switches 52 and 53 and the NOT gates 54 and 55 of the present embodiment constitute the second waveform shaper described in the claims.

  Next, the circuit configuration of the peak hold circuit 50 will be described. FIG. 5 is a diagram showing details of the circuit configuration of the peak hold circuit 50.

  The peak hold circuit 50 includes an analog switch 70, a reference voltage generation circuit 72, an nMOS transistor 73, a capacitor 74, a constant current generation circuit 75, a differential amplifier circuit 76, and an output circuit 77.

  The analog switch 70 includes an nMOS transistor 70a, a pMOS transistor 70b, and a NOT gate 71, and is a switch circuit that opens and closes between the input terminal IN and the positive terminal of the capacitor 74. The nMOS transistor 70a is turned on / off according to a hold signal output from the output terminal HOLD_H of the control circuit 36. The NOT gate 71 turns on and off the pMOS transistor 70b according to the hold signal output from the output terminal HOLD_H of the control circuit 36.

  The reference voltage generation circuit 72 outputs a constant reference voltage Ref1. The nMOS transistor 73 connects or opens the output terminal of the reference voltage generation circuit 72 and the positive electrode of the capacitor 74 in accordance with an initialization signal given from the control circuit 36 through the input terminal INIT. The capacitor 74 is disposed between the analog switch 70 and the ground.

  The constant current generation circuit 75 includes a resistance element 75a and an nMOS transistor 75b connected in series between the power supply Vdd and the ground. The gate terminal and drain terminal of the nMOS transistor 75b are connected. The common connection terminal 78 between the gate terminal and the drain terminal of the nMOS transistor 75b outputs a constant voltage to the gate terminals of the nMOS transistors 76e and 77e.

  The differential amplifier circuit 76 includes pMOS transistors 76a and 76b and nMOS transistors 76c, 76d and 76e. The gate terminals of the pMOS transistors 76a and 76b are connected to the drain terminal of the pMOS transistor 76a to form a current mirror circuit. The nMOS transistor 76c is disposed between the pMOS transistor 76a and the ground. The nMOS transistor 76d is disposed between the pMOS transistor 76b and the ground. The nMOS transistor 76e is disposed between the source terminals of the nMOS transistors 76c and 76d and the ground.

  The output circuit 77 includes a capacitor 77a and nMOS transistors 77b, 77c, 77d, and 77e. The capacitor 77a is disposed between the common connection terminal 76g between the pMOS transistor 76b and the nMOS transistor 76d and the ground. The nMOS transistors 77b and 77c are arranged in parallel between the positive terminal of the capacitor 77a and the common connection terminal 76g. The nMOS transistor 77b has its gate terminal and drain terminal connected to the common connection terminal 76g side, and prevents current from flowing from the positive electrode side of the capacitor 77a to the common connection terminal 76g side. The nMOS transistor 77c connects or opens the capacitor 77a and the common connection terminal 76g according to the initialization signal supplied from the control circuit 36. The nMOS transistors 77d and 77e are connected in series between the power supply Vdd and the ground. The nMOS transistor 77e causes a current to flow from the power supply Vdd to the ground through the nMOS transistor 77e in accordance with a constant voltage output from the common connection terminal 78.

  FIG. 6 is a diagram showing details of the circuit configuration of the bottom hold circuit 51. The bottom hold circuit 51 includes an analog switch 70, a reference voltage generation circuit 72a, a pMOS transistor 73a, a NOT gate 73b, a capacitor 74, a constant current generation circuit 75, a differential amplifier circuit 76, and an output circuit 77A. In the bottom hold circuit 51 of FIG. 6, the same reference numerals as those of the peak hold circuit 50 of FIG. Hereinafter, the description of the configuration common to the peak hold circuit 50 in the bottom hold circuit 51 will be simplified, and the configuration that is mainly different will be described.

  The gate terminal of the nMOS transistor 70a of the analog switch 70 is turned on and off according to the hold signal output from the output terminal HOLD_L, not the output terminal HOLD_H of the control circuit 36. The NOT gate 71 turns on and off the pMOS transistor 70b according to the hold signal output from the output terminal HOLD_L. The reference voltage generation circuit 72a corresponds to the reference voltage generation circuit 72 and outputs a constant reference voltage Ref2. The reference voltage Ref2 is higher than the reference voltage Ref1. The pMOS transistor 73a is disposed between the positive electrode of the capacitor 74 and the reference voltage generation circuit 72a. The NOT gate 73b turns on and off the pMOS transistor 73a according to the initialization signal supplied from the control circuit 36. The capacitor 77a of the output circuit 77A is disposed not between the common connection terminal 76g and the ground but between the power supply Vdd and the common connection terminal 76g. The nMOS transistors 77b and 77c are arranged in parallel between the negative electrode of the capacitor 77a and the common connection terminal 76g.

  Next, the operation of the bottom hold circuit 51 will be described.

  FIG. 7 is a timing chart of each output signal corresponding to FIG.

  8A is a timing chart of an initialization signal given from the control circuit 36 to the input terminal INIT of the bottom hold circuit 51. FIG. 8B is a hold chart given from the output terminal HOLD_L of the control circuit 36 to the bottom hold circuit 51. FIG. 8C is a timing chart showing the voltage change at the input terminal IN of the bottom hold circuit 51, and FIG. 8D is a timing chart showing the voltage change at the output terminal BOUT of the bottom hold circuit 51. .

  First, the initialization signal level applied from the control circuit 36 to the gate terminal of the nMOS transistor 77c and the NOT gate 73b through the input terminal INIT is for a certain period (timing t0-t1 in FIGS. 7 and 8A). When set to the high level, the output signal of the NOT gate 73b becomes the low level for a certain period. Accordingly, the pMOS transistor 73a is turned on for a certain period. Therefore, a current flows from the reference voltage generation circuit 72a to the capacitor 74 through the pMOS transistor 73a. As a result, the voltage between the positive electrode and the negative electrode of the capacitor 74 (hereinafter referred to as the voltage between both electrodes) gradually increases with time and approaches the voltage Ref2. The on-resistance value of the nMOS transistor 76c is reduced by the voltage between both electrodes that rises in this way. Along with this, the potential Va of the common connection terminal 76f decreases. Accordingly, the current that the pMOS transistor 76b flows from the power source Vdd to the ground through the nMOS transistors 76d and 76e is increased. Along with this, the potential Vb of the common connection terminal 76g increases.

  Here, the nMOS transistor 77c is turned on by a high level initialization signal supplied from the control circuit 36 for the predetermined period. Therefore, a current flows from the common connection terminal 76g to the negative electrode side of the capacitor 77a through the nMOS transistor 77c. For this reason, the voltage output from the negative electrode of the capacitor 77a to the gate terminal of the nMOS transistor 77d increases. Therefore, the nMOS transistor 77d increases the current flowing from the power source Vdd to the ground through the nMOS transistor 77e. For this reason, the output voltage output from the output terminal POUT between the nMOS transistors 77d and 77e rises and approaches the voltage Ref2. The on-resistance of the nMOS transistor 76d is reduced by the output voltage thus rising. Along with this, an increase in current flowing from the power source Vdd to the ground through the pMOS transistor 76b and the nMOS transistors 76d and 76e is suppressed. And the rise in the potential Vb of the common connection terminal 76g is suppressed. By such an operation, the output voltage of the output terminal BOUT maintains the voltage Ref2 that is the voltage between both electrodes of the capacitor 74.

  Next, the control circuit 36 changes the level of the initialization signal supplied to the input terminal of the NOT gate 73b and the gate terminal of the nMOS transistor 77c from the high level to the low level. Therefore, the nMOS transistor 77c is turned off, and the NOT gate 73b turns off the pMOS transistor 73a.

  Next, the level of the hold signal that the control circuit 36 gives from the output terminal HOLD_B to the analog switch 70 is set to the high level for a certain period (timing t2-t3 in FIGS. 7 and 8B). Therefore, the analog switch 70 connects the input terminal IN and the positive electrode of the capacitor 74 for a certain period. The certain period is a period before the light reception pulse from the operational amplifier 13 is received. Therefore, a current flows from the positive electrode of the capacitor 74 to the output terminal side of the operational amplifier 13 through the analog switch 70. As a result, the voltage between the input terminal IN and the ground decreases (see FIG. 8C). That is, the voltage applied from the capacitor 74 to the gate terminal of the nMOS transistor 76c decreases. Then, the potential Va of the common connection terminal 77f increases, and the current that the pMOS transistor 76b flows from the power supply Vdd to the ground through the nMOS transistors 76d and 76e is reduced. Along with this, the potential Vb of the common connection terminal 76g decreases.

  Therefore, a current flows from the negative electrode of the capacitor 77a to the common connection terminal 76g side through the nMOS transistor 77b. Therefore, the voltage output from the capacitor 77a to the gate terminal of the nMOS transistor 77d decreases. For this reason, the current flowing from the power supply Vdd to the ground through the nMOS transistors 77d and 77e decreases. Therefore, the output voltage output from the output terminal POUT between the nMOS transistors 77d and 77e decreases. The on-resistance of the nMOS transistor 76d increases due to the output voltage that decreases in this way. Along with this, a decrease in the potential Vb of the common connection terminal 76g is suppressed.

  By such an operation, the output voltage of the output terminal BOUT decreases and approaches the voltage between both electrodes of the capacitor 74. Thereafter, even if the potential of the negative electrode of the capacitor 77a becomes lower than the potential Vb of the common connection terminal 76g, the nMOS transistor 77b is prevented from flowing current from the common connection terminal 76g side to the negative electrode side of the capacitor 77a. Thereby, when the output voltage of the output terminal BOUT reaches the bottom voltage (that is, the lowest voltage of the output voltage of the operational amplifier 13), the bottom voltage is maintained (see FIG. 8D). As a result, the bottom voltage of the received light pulse is sampled, and the output voltage of the output terminal BOUT is held at the sampled voltage.

  Next, the peak hold circuit 50 will be described. 9A is a timing chart of the initialization signal, FIG. 9B is a timing chart of the hold signal output from the output terminal HOLD_H of the control circuit 36, and FIG. 9C is an input terminal IN of the peak hold circuit 50. FIG. 9D is a timing chart showing the voltage change of the peak hold circuit 50 output terminal POUT.

  First, the initialization signal level given from the control circuit 36 through the input terminal INIT to the gate terminals of the nMOS transistors 73 and 77c of the peak hold circuit 50 is set for a certain period (between timing t0 and t1 in FIGS. 7 and 9A). ) When the level is high, the nMOS transistors 73 and 77c are turned on for a certain period. For this reason, the voltage between both electrodes of the capacitor 74 gradually decreases with time and approaches the voltage Ref1.

  When the voltage between both electrodes that decreases in this way is applied to the gate terminal of the nMOS transistor 76c, the on-resistance value of the nMOS transistor 76c increases. For this reason, the current flowing from the power source Vdd to the ground through the pMOS transistor 76a and the nMOS transistors 76c and 76e is reduced. Along with this, the potential Va of the common connection terminal 76f increases. Then, the current that the pMOS transistor 76b passes from the power source Vdd to the ground through the nMOS transistors 76d and 76e is reduced. Along with this, the potential Vb of the common connection terminal 76g decreases.

  Here, when the nMOS transistor 77c is turned on, a current flows from the capacitor 77a to the common connection terminal 76g through the nMOS transistor 77c. Therefore, the voltage output from the capacitor 77a to the gate terminal of the nMOS transistor 77d decreases. For this reason, the current flowing from the power supply Vdd to the ground through the nMOS transistors 77d and 77e decreases. For this reason, the output voltage output from the output terminal POUT between the nMOS transistors 77d and 77e decreases and approaches the voltage Ref1. The on-resistance of the nMOS transistor 76d increases due to the output voltage that decreases in this way. Along with this, a decrease in the potential Vb of the common connection terminal 76g is suppressed. By such an operation, the output voltage of the output terminal POUT maintains the voltage Ref1 that is the voltage between both electrodes of the capacitor 74.

  Next, the control circuit 36 sets the output signal level applied to the gate terminals of the nMOS transistors 73 and 77c through the input terminal INIT to a low level. Therefore, the nMOS transistors 73 and 77c are turned off.

  Next, the hold signal level that is supplied from the output terminal HOLD_H to the analog switch 70 by the control circuit 36 is set to the high level for a certain period (timing t4-t5 in FIGS. 7 and 9B). Therefore, the analog switch 70 connects the input terminal IN and the positive electrode of the capacitor 74 for a certain period. The certain period is a period during which a light reception pulse from the operational amplifier 13 is received. Therefore, a current corresponding to the received light pulse flows from the output terminal of the operational amplifier 13 to the positive electrode side of the capacitor 74 through the analog switch 70. As a result, the voltage between the input terminal IN and the ground increases (see FIG. 9C). That is, the voltage applied from the capacitor 74 to the gate terminal of the nMOS transistor 76c increases. As a result, the on-resistance of the nMOS transistor 76c decreases. As a result, the current flowing from the power source Vdd to the ground through the pMOS transistor 76a and the nMOS transistors 76c and 76e increases. For this reason, the potential Va of the common connection terminal 76f decreases. Accordingly, the current that the pMOS transistor 76b flows from the power source Vdd to the ground through the nMOS transistors 76d and 76e is increased. Along with this, the potential Vb of the common connection terminal 76g increases.

  Therefore, a current flows from the common connection terminal 76g side to the capacitor 77a through the nMOS transistor 77b. Therefore, the voltage output from the capacitor 77a to the gate terminal of the nMOS transistor 77d increases. For this reason, the current flowing from the power supply Vdd to the ground through the nMOS transistors 77d and 77e increases. For this reason, the output voltage output from the output terminal POUT between the nMOS transistors 77d and 77e increases. The on-resistance of the nMOS transistor 76d is lowered by the output voltage that rises in this way. Along with this, an increase in the potential Vb of the common connection terminal 76g is suppressed. By such an operation, the output voltage of the output terminal POUT rises and approaches the voltage between both electrodes of the capacitor 74.

  Thereafter, even if the potential of the positive electrode of the capacitor 77a becomes higher than the potential Vb of the common connection terminal 76g, the nMOS transistor 77b is prevented from flowing current from the positive electrode side of the capacitor 77a to the common connection terminal 76g. Thus, when the output voltage of the output terminal POUT rises and reaches the peak voltage (that is, the maximum voltage of the output voltage of the operational amplifier 13), the peak voltage is held (see FIG. 9D). As a result, the peak voltage of the received light pulse is sampled, and the output voltage of the output terminal POUT is held at the sampled voltage.

  Next, the overall operation of the distance measuring system_ECU 100 according to the present embodiment will be described.

  First, as in the first embodiment, the control circuit 36 initializes the pulse phase difference encoding circuit 32 and the arithmetic processing circuit 34 with a reset signal (RST, RST1: see FIG. 7) and selects a low level. The switch 35 is controlled by the signal SEL to connect the output terminal of the operational amplifier 13 and the non-inverting input terminal (+) of the comparator 31, and the common connection terminal 58 between the switches 52 and 53 and the non-inverting terminal of the comparator 31. Open to the inverting input terminal (+).

  Thereafter, the control circuit 36 sets the output signal level applied to the input terminals INIT of the hold circuits 50 and 51 to a high level for a certain period (timing t0-t1 in FIG. 7). As a result, the hold circuits 50 and 51 are initialized respectively.

  In addition, the control circuit 36 outputs a low level signal from its output terminal PC to the NOT gate 54. Therefore, the NOT gate 54 outputs a high level signal to the switch 53. Accordingly, the switch 53 connects between the output terminal BOUT of the bottom hold circuit 51 and the input terminal PC_A of the switch 35. The high level signal output from the NOT gate 54 is also applied to the NOT gate 55. Therefore, the NOT gate 55 outputs a low level signal to the switch 52. Along with this, the switch 52 opens between the output terminal POUT of the peak hold circuit 50 and the input terminal PC_A of the switch 35.

  Next, the control circuit 36 sets the hold signal applied from the output terminal HOLD_B to the bottom hold circuit 51 to a high level for a certain period (timing t2-t3 in FIG. 7). During this fixed period, the bottom hold circuit 51 samples the bottom voltage VOL (minimum voltage) out of the signal level of the received light signal supplied from the operational amplifier 13 to the input terminal IN, and outputs the sampled voltage to the sampled voltage. Hold the voltage. Thereafter, the bottom voltage VOL is continuously output as the output voltage from the output terminal BOUT of the bottom hold circuit 51 (see FIG. 7 (i)).

  Next, the control circuit 36 sets the hold signal output from the output terminal HOLD_H to the peak hold circuit 50 to a high level for a certain period (timing t4-t5 in FIG. 7 (h)). In addition, the control circuit 36 changes the control signal level output to the first input terminal of the OR gate 42 from the low level (Lo) to the high level (Hi), as in the first embodiment. Accordingly, the signal level output from the OR gate 42 to the input terminal PA of the pulse phase difference encoding circuit 32 changes from the low level (Lo) to the high level (Hi) (see FIG. 7B). That is, the control circuit 36 outputs the control pulse to the input terminal PA of the pulse phase difference encoding circuit 32 through the OR gate 42. Further, the control circuit 36 turns on the nMOS transistor 14 by a light emission trigger, thereby emitting laser light from the diode 10. Thereafter, when the reflected laser beam reflected by the obstacle is received by the photodiode 11, a light reception pulse is applied from the operational amplifier 13 to the OR gate 41 through the switch 35 and the comparator 31. Accordingly, the OR gate 41 applies the pulse PB to the input terminal PB of the pulse phase difference encoding circuit 32. Then, the pulse phase difference encoding circuit 32 outputs the phase difference Da between the pulse PA and the pulse PB to the arithmetic processing circuit 34.

  Further, as described above, when the reflected laser beam reflected by the obstacle is received by the photodiode 11, the light reception pulse from the operational amplifier 13 is also applied to the input terminal IN of the peak hold 50. That is, when the reflected laser light is received by the photodiode 11, the level of the received light signal applied from the operational amplifier 13 to the input terminal IN of the peak hold 50 is high for a certain period (timing t6-t7 in FIG. 7). become. At this time, the peak hold 50 samples the peak voltage VOH (maximum voltage) in the level of the received light signal, and holds the output voltage at the sampled peak voltage VOH. Thereafter, the peak voltage VOH is continuously output as the output voltage from the output terminal POUT of the peak hold 50 (see FIG. 7J).

  Next, the control circuit 36 changes the signal level applied to the input terminal PA of the pulse phase difference encoding circuit 32 from the high level to the low level (see timing t8 in FIG. 7).

  Next, the control circuit 36 changes the level of the selection signal SEL supplied to the switch 35 from the low level to the high level. As a result, the switch 35 opens between the output terminal of the operational amplifier 13 and the non-inverting input terminal (+) of the comparator 31, and the common connection terminal 58 between the switches 52 and 53 and the non-inverting input terminal (+ of the comparator 31). ).

  Here, as described above, the switch 53 connects the output terminal BOUT of the bottom hold circuit 51 and the input terminal PC_A of the switch 35. The bottom hold circuit 51 is in a state where the output voltage is the bottom voltage VOL. Therefore, the bottom hold circuit 51 outputs the bottom voltage VOL to the non-inverting input terminal (+) of the comparator 31 through the switches 53 and 35.

  Here, the bottom voltage VOL is lower than the output voltage of the D / A converter 30. For this reason, the output signal level given from the comparator 31 to the first input terminal of the OR gate 41 becomes a low level. At this time, the output signal level applied from the output terminal PC of the control circuit 36 to the second input terminal of the OR gate 41 is low. Therefore, the signal level applied from the OR gate 41 to the input terminal PB of the pulse phase difference encoding circuit 32 becomes a low level.

  Next, the control circuit 36 changes the control output signal level for the first input terminal of the OR gate 42 from the low level to the high level at timing t9. Accordingly, the control signal level applied from the OR gate 42 to the input terminal PA of the pulse phase difference encoding circuit 32 changes from the low level to the high level. That is, the control circuit 36 outputs the control pulse to the input terminal PA of the pulse phase difference encoding circuit 32 through the OR gate 42. Thereby, in the ring delay pulse generation circuit 1 of the pulse phase difference encoding circuit 32, the pulse PA starts to circulate.

  Further, at timing t9, the control circuit 36 outputs the substitute pulse PC1 from the output terminal PC to the NOT gate 54. Therefore, the NOT gate 54 keeps the level of the output signal at a low level for a certain period. Accordingly, the switch 53 opens between the output terminal BOUT of the bottom hold circuit 51 and the input terminal PC_A of the switch 35 for a certain period. The low level output signal output from the NOT gate 54 is also applied to the NOT gate 55. Therefore, the NOT gate 55 sets the output signal level applied to the switch 52 to a high level for a certain period.

  Accordingly, the switch 52 connects the output terminal POUT of the peak hold circuit 50 and the input terminal PC_A of the switch 35 for a certain period. At this time, as described above, the output voltage of the peak hold 50 is the same as the peak voltage VOH. For this reason, the peak voltage VOH output from the peak hold 50 is applied to the non-inverting input terminal (+) of the comparator 31 through the switches 52 and 35. As a result, the substitute pulse PC1 having the same bottom voltage as the bottom voltage VOL and the same peak voltage as the peak voltage VOH is applied to the non-inverting input terminal (+) of the comparator 31 through the switch 35.

  Here, the peak voltage VOH is higher than the output voltage of the D / A converter 30. For this reason, the output signal level applied from the comparator 31 to the first input terminal of the OR gate 41 becomes a high level. Therefore, the signal level applied from the OR gate 41 to the input terminal PB of the pulse phase difference encoding circuit 32 becomes a high level. That is, the pulse PB is supplied from the OR gate 41 to the input terminal PB of the pulse phase difference encoding circuit 32.

  Accordingly, the pulse phase difference encoding circuit 32 determines the interval between the pulse PA and the pulse PB based on the circulation position of the pulse PA and the number of circulations of the pulse PA at the input timing of the pulse PB to the ring delay pulse generation circuit 1. The phase difference Db is detected, and this phase difference Db is output to the arithmetic processing circuit 34. Thereafter, the control circuit 36 outputs a data load signal LOAD to the arithmetic processing circuit 34. Therefore, the arithmetic processing circuit 34 reads the phase difference Db output from the pulse phase difference encoding circuit 32.

  Thereafter, the control circuit 36, the OR gate 41, the pulse phase difference encoding circuit 32, and the arithmetic processing circuit 34 operate in the same manner as in the second embodiment, and the arithmetic processing circuit 34 is operated by the pulse phase difference encoding circuit 32. Normalized data Ds (= (Da−Db) / De) is calculated on the basis of the phase differences Da, Db, and De output from.

  In the present embodiment described above, the arithmetic processing circuit 34 calculates the normalized data {(Da−Db) / De} using the phase differences Da, Db, and De, as in the second embodiment. As a result, as in the first and second embodiments described above, normalized data obtained by removing the measurement error of the comparator 31 and the measurement error of the pulse phase difference encoding circuit 32 can be obtained.

  The phase difference Db in the present embodiment indicates a delay time (that is, measurement error) that occurs between the time when the light reception pulse is input to the comparator 31 and the time when the light reception pulse is output from the comparator 31.

  Therefore, the control circuit 36 passes the substitute pulse PC1 whose bottom voltage is the same as the bottom voltage VOL of the received light pulse and whose peak voltage is the same as the peak voltage VOH of the received light pulse through the switch 35 to the non-inverting input terminal (+ ). As a result, the peak voltage (or bottom voltage) of the substitute pulse PC1 applied to the non-inverting input terminal (+) of the comparator 31 can be brought close to the peak voltage (or bottom voltage) of the received light pulse. Therefore, the delay time caused by the substitute pulse PC1 in the comparator 31 can be brought close to the delay time caused by the received light pulse. For this reason, the pulse phase difference encoding circuit 32 can obtain the phase difference Db with high accuracy corresponding to the substitute pulse PC1. Accordingly, the normalized data Ds can be calculated with high accuracy.

(Third embodiment)
In the third embodiment, an example in which the average value of the peak voltages of a plurality of received light pulses is used as the peak voltage of the substitute pulse PC1, and the average value of the bottom voltages of the received light pulses is used as the bottom voltage of the substitute pulse PC1. To do.

  FIG. 10 is a diagram illustrating a circuit configuration of the ranging system_ECU 100 of the present embodiment.

  The ranging system_ECU 100 of FIG. 10 is obtained by adding averaging processing circuits 56 and 57 to the ranging system_ECU 100 of FIG. The averaging processing circuit 56 outputs an average voltage obtained by averaging the peak voltages of a plurality of received light pulses (for example, four received light pulses) based on the output voltage of the peak hold circuit 50. The averaging processing circuit 57 outputs an average voltage obtained by averaging the bottom voltages of a plurality of light reception pulses (for example, four light reception pulses) based on the output voltage of the bottom hold circuit 51. Note that the output voltages of the averaging processing circuits 56 and 57 are used to set the bottom voltage and the peak voltage of the substitute pulse PC1 applied to the comparator 31 through the switch 35, as will be described later.

  The averaging processing circuits 56 and 57 have the same circuit configuration except that the output voltages of the target circuits for obtaining the average voltage are different from each other. Therefore, a circuit configuration of the averaging processing circuit 56 as a representative example of the averaging processing circuits 56 and 57 will be described with reference to FIG. FIG. 11 is a diagram showing a circuit configuration of the averaging processing circuit 56.

  The averaging processing circuit 56 includes sample and hold circuits 80a, 80b, 80c, and 80d, an adding circuit 80e, and an inverting circuit 80f.

  The sample hold circuit 80a includes a capacitor C1, a switch SW1, and an operational amplifier 80. The capacitor C1 is disposed between the output terminal POUT of the peak hold circuit 50 and the ground, and stabilizes the output voltage of the output terminal POUT. The switch SW1 connects or opens between the output terminal POUT of the peak hold circuit 50 and the non-inverting input terminal (+) of the operational amplifier 80. The operational amplifier 80 has a voltage follower circuit in which the positive electrode of the capacitor C1 is connected to the non-inverting input terminal (+) and the inverting input terminal (−) is connected to the output terminal. As a result, the output voltage of the output terminal POUT of the peak hold circuit 50 is sampled and the sampled voltage is output as the operational amplifier 80 output voltage V1.

  Similar to the sample hold circuit 80a, the sample hold circuit 80b includes a capacitor C2, a switch SW2, and an operational amplifier 81. The capacitor C2 corresponds to the capacitor C1, the switch SW2 corresponds to the switch SW1, and the operational amplifier 81 corresponds to the operational amplifier 80. As a result, the sample hold circuit 80b samples the output voltage of the output terminal POUT of the peak hold circuit 50 and outputs the sampled voltage as the operational amplifier 81 output voltage V2.

  Similar to the sample and hold circuit 80a, the sample and hold circuit 80c includes a capacitor C3, a switch SW3, and an operational amplifier 82. The sample and hold circuit 80c samples the output voltage of the output terminal POUT of the peak hold circuit 50, and uses the sampled voltage of the operational amplifier 82. Output as output voltage V3.

  Similar to the sample hold circuit 80a, the sample hold circuit 80d includes a capacitor C4, a switch SW4, and an operational amplifier 83. The sample hold circuit 80d samples the output voltage of the output terminal POUT of the peak hold circuit 50, and uses the sampled voltage of the operational amplifier 83. Output as output voltage V4.

  The adder circuit 80e adds the output voltages V1, V2, V3, and V4 of the sample and hold circuits 80a, 80b, 80c, and 80d. The resistor elements 90, 91, 92, 93, and 100, the operational amplifier 101, and the reference voltage generator The circuit 102 is configured.

  The resistance element 90 is disposed between the output terminal of the operational amplifier 80 and the inverting input terminal (−) of the operational amplifier 101. The resistance element 91 is disposed between the output terminal of the operational amplifier 81 and the inverting input terminal (−) of the operational amplifier 101. The resistance element 92 is disposed between the output terminal of the operational amplifier 82 and the inverting input terminal (−) of the operational amplifier 101. The resistance element 93 is disposed between the output terminal of the operational amplifier 83 and the inverting input terminal (−) of the operational amplifier 101. The resistance element 100 is disposed between the output terminal of the operational amplifier 101 and the inverting input terminal (−). The reference voltage generation circuit 102 outputs a constant reference voltage to the non-inverting input terminal (+) of the operational amplifier 101.

  The inverting circuit 80f includes an operational amplifier 113 and resistance elements 111 and 112. The resistance element 111 is disposed between the output terminal of the operational amplifier 113 and the inverting input terminal (−). The resistance element 112 is disposed between the output terminal of the operational amplifier 101 and the inverting input terminal (−) of the operational amplifier 113. The output voltage of the reference voltage generation circuit 102 is applied to the non-inverting input terminal (+) of the operational amplifier 113.

  Next, as the operation of the distance measuring system_ECU 100 of the present embodiment, (1) operation of the averaging processing circuit 56, (2) operation of the averaging processing circuit 57, and (3) common connection between the switches 52 and 53 The operation for outputting the substitute pulse PC1 from the terminal 58 to the switch 35 will be described separately.

  (1) The operation of the averaging processing circuit 56 will be described. 12A is a timing chart of a light emission trigger output from the control circuit 36, FIG. 12B is a timing chart of an initialization signal that the control circuit 36 gives to the input terminal INIT of the peak hold circuit 50, and FIG. , (D), (e), and (f) are timing charts showing the ON timing of the switches SW1, SW2, SW3, and SW4.

  First, the signal level of the initialization signal given to the peak hold circuit 50 by the control circuit 36 is set to a high level for a certain period. For this reason, the peak hold circuit 50 is initialized. Next, the control circuit 36 turns on the switch SW <b> 1 for a certain period and outputs the first light emission trigger to the gate terminal of the nMOS transistor 14. For this reason, the diode 10 emits laser light. Thereafter, the reflected laser beam is received by the photodiode 11, the peak voltage of the first received light pulse output from the operational amplifier 13 is sampled by the peak hold circuit 50, and this sampled voltage is input to the non-inverting input of the operational amplifier 80 through the switch SW1. Output to terminal (+). Therefore, the operational amplifier 80 outputs the peak voltage of the first received light pulse as the output voltage V1.

  Next, the signal level of the initialization signal given to the peak hold circuit 50 by the control circuit 36 is set to a high level for a certain period. For this reason, the peak hold circuit 50 is initialized. Thereafter, the control circuit 36 turns on the switch SW2 for a certain period and outputs a second light emission trigger to the nMOS transistor 14 to emit laser light from the diode 10. Next, the reflected laser beam is received by the photodiode 11, the peak voltage of the second received light pulse output from the operational amplifier 13 is sampled by the peak hold circuit 50, and the sampled voltage is output from the operational amplifier 81 through the switch SW2. Output to the inverting input terminal (+). Accordingly, the operational amplifier 81 outputs the peak voltage of the second received light pulse as the output voltage V2.

  Next, the signal level of the initialization signal given to the peak hold circuit 50 by the control circuit 36 is set to a high level for a certain period. For this reason, the peak hold circuit 50 is initialized. Thereafter, the control circuit 36 turns on the switch SW3 for a certain period and outputs a third light emission trigger to the nMOS transistor 14 to emit laser light from the diode 10. Next, the reflected laser beam is received by the photodiode 11, the peak voltage of the third received light pulse output from the operational amplifier 13 is sampled by the peak hold circuit 50, and this sampled voltage is supplied to the operational amplifier 82 through the switch SW3. Output to the non-inverting input terminal (+). Accordingly, the operational amplifier 82 outputs the peak voltage of the third received light pulse as the output voltage V3.

  Next, the signal level of the initialization signal given to the peak hold circuit 50 by the control circuit 36 is set to a high level for a certain period. For this reason, the peak hold circuit 50 is initialized. Thereafter, the control circuit 36 turns on the switch SW4 for a certain period and outputs a fourth light emission trigger to the nMOS transistor 14 to emit laser light from the diode 10. Thereafter, the reflected laser beam is received by the photodiode 11, the peak voltage of the fourth received light pulse output from the operational amplifier 13 is sampled by the peak hold circuit 50, and the sampled voltage is supplied to the operational amplifier 82 through the switch SW4. Output to the non-inverting input terminal (+). Accordingly, the operational amplifier 83 outputs the peak voltage of the fourth received light pulse as the output voltage V4.

  Here, the current flowing from the output terminal of the operational amplifier 80 to the inverting input terminal (−) side of the operational amplifier 101 through the resistance element 90 is I1, and from the output terminal of the operational amplifier 81 to the inverting input terminal (−) side of the operational amplifier 101 through the resistance element 91. Current flowing from the output terminal of the operational amplifier 82 through the resistance element 92 to the inverting input terminal (−) side of the operational amplifier 101 is I3, and the current flowing from the output terminal of the operational amplifier 83 through the resistance element 93 to the inverting input terminal of the operational amplifier 101. When the current flowing in the (−) side is I4, the output voltage of the reference voltage generation circuit 102 is Vref, and the resistance values of the resistance elements 90, 91, 93, 94 are R, the following formulas 3, 4, 5 , 6 is established.

I1 = (V1−Vref) / R (Equation 3)
I2 = (V2−Vref) / R (Equation 4)
I3 = (V3-Vref) / R (5)
I4 = (V4−Vref) / R (Equation 6)
Next, the current flowing from the common connection terminal 94 side between the resistance elements 90, 91, 92, 93 and the inverting input terminal (−) of the operational amplifier 101 to the output terminal side of the operational amplifier 101 through the resistance element 100 is defined as Iref. When the resistance value of the element 100 is Rf, the following formulas 7 and 8 are established.

Iref = (Verf−Vo1) / Rf (Formula 7)
Iref = I1 + I2 + I3 + I4 (Equation 8)
Next, substituting I1 of Formula 3, I2 of Formula 4, I3 of Formula 5, I4 of Formula 6, and Iref of Formula 7 into Formula 8, the following Formula 9 is obtained.

(Verf−Vo1) / Rf =
1 / R (V1 + V2 + V3 + V4-4 × Vref) (Equation 9)
When Expression 9 is transformed, the following Expression 10 is obtained.
(Verf1-Vo1) =
(Rf / R) × (V1 + V2 + V3 + V4-4 × Vref) (Equation 10)
Next, when R = 4 × Rf, the following formula 11 is obtained.

Vo1 = 2 × Verf− (V1 + V2 + V3 + V4) / 4 (Expression 11)
Here, the current flowing from the output terminal side of the operational amplifier 113 to the common connection terminal 114 side through the resistance element 111 is equal to the current flowing from the common connection terminal 114 side to the output terminal side of the operational amplifier 101 through the resistance element 112. The common connection terminal 114 is a common connection terminal between the resistance elements 111 and 112. Then, assuming that the resistance values of the resistance elements 111 and 112 are the same value and the output voltage of the operational amplifier 101 is Vo2, the following formula 12 is established.

Vo2-Verf = Verf-Vo1 (Equation 12)
When Expression 12 is transformed, the following Expression 13 is obtained.

Vo2 = 2 × Vref−Vo1 (Expression 13)
Next, when Vo1 of Expression 11 is substituted into Expression 13, the following Expression 14 is established.

Vo2 = (V1 + V2 + V3 + V4) / 4 (Equation 14)
From the above, it can be seen that the output voltage Vo2 of the averaging processing circuit 56 is equal to the voltage obtained by averaging the peak voltages of the four received light pulses.

  (2) Next, the operation of the averaging processing circuit 57 will be described.

  13A is a timing chart of a light emission trigger output from the control circuit 36, FIG. 13B is a timing chart of an initialization signal that the control circuit 36 gives to the input terminal INIT of the bottom hold circuit 51, and FIG. , (D), (e), and (f) are timing charts showing the ON timing of the switches SW1, SW2, SW3, and SW4.

  First, the control circuit 36 turns on the switch SW1 for a certain period after setting the signal level of the initialization signal supplied to the bottom hold circuit 51 to a high level for a certain period. Thereafter, the first light emission trigger is output to the nMOS transistor 14. As a result, the sample hold circuit 80a outputs the bottom voltage V1 of the received light signal before receiving the first received light pulse.

  Next, the control circuit 36 sets the signal level of the initialization signal to high for a certain period, and then turns on the switch SW2 for a certain period. Thereafter, the second light emission trigger is output to the nMOS transistor 14. As a result, the sample hold circuit 80b outputs the bottom voltage V2 of the received light signal before receiving the second received light pulse.

  Next, the control circuit 36 sets the signal level of the initialization signal to high for a certain period, and then turns on the switch SW3 for a certain period. Thereafter, a third light emission trigger is output to the nMOS transistor 14. As a result, the sample hold circuit 80c outputs the bottom voltage V3 of the received light signal before receiving the third received light pulse.

  Thereafter, the control circuit 36 turns on the switch SW4 for a certain period after setting the signal level of the initialization signal to a high level for a certain period. Thereafter, the fourth light emission trigger is output to the nMOS transistor 14. As a result, the sample hold circuit 80d outputs the bottom voltage V4 of the received light signal before receiving the fourth received light pulse.

As described above, the sample hold circuits 80a to 80d output the bottom voltages V1, V2, V3, and V4 of the reception pulse for each reception pulse. Therefore, the averaging processing circuit 57 outputs the average value (= (V1 + V2 + V3 + V4) / 4) of the bottom voltages V1, V2, V3, V4 for each reception pulse as the output voltage Vo2.
(3) Next, an operation for outputting the substitute pulse PC1 from the common connection terminal 58 to the switch 35 will be described.

  First, the control circuit 36 controls the switch 35 with the high-level selection signal SEL to open the gap between the output terminal of the operational amplifier 13 and the non-inverting input terminal (+) of the comparator 31, and the control circuit 36. The output terminal and the non-inverting input terminal (+) of the comparator 31 are connected.

  Next, the control circuit 36 outputs a low level signal from its output terminal PC to the NOT gate 54. Therefore, the NOT gate 54 outputs a high level signal to the switch 53. Accordingly, the switch 53 connects between the output terminal of the averaging processing circuit 57 and the input terminal PC_A of the switch 35. The high level signal output from the NOT gate 54 is also applied to the NOT gate 55. Therefore, the NOT gate 55 outputs a low level signal to the switch 52. Along with this, the switch 52 opens between the output terminal of the averaging processing circuit 56 and the input terminal PC_A of the switch 35. As a result, the output voltage of the averaging processing circuit 57 is output from the common connection terminal 58 to the non-inverting input terminal (+) of the comparator 31 through the switch 35.

  Thereafter, the control circuit 36 changes the signal level output from the output terminal PC to the NOT gate 54 from the low level to the high level. That is, when the control circuit 36 outputs the substitute pulse PC1 to the NOT gate 54, the level of the output signal of the NOT gate 54 changes from the high level to the low level. Along with this, the switch 53 opens between the output terminal of the averaging processing circuit 57 and the input terminal PC_A of the switch 35. Then, the signal level output from the NOT gate 55 to the switch 52 is changed from the low level to the high level. Along with this, the switch 52 connects between the output terminal of the averaging processing circuit 56 and the input terminal PC_A of the switch 35. As a result, the output voltage of the averaging processing circuit 56 is output from the common connection terminal 58 to the non-inverting input terminal (+) of the comparator 31 through the switch 35.

  As described above, when the control circuit 36 outputs a substitute pulse from the output terminal PC to the NOT gate 54, the peak voltage is the same as the output voltage of the averaging processing circuit 56 and the bottom voltage is equal to the output voltage of the averaging processing circuit 57. The same substitute pulse PC1 is output from the common connection terminal 58 to the non-inverting input terminal (+) of the comparator 31 through the switch 35. That is, the switches 52 and 53 and the NOT gates 54 and 55 function as a waveform shaper that shapes the waveform by adjusting the peak voltage / bottom voltage of the substitute pulse output from the control circuit 36.

  According to the present embodiment described above, averaging processing circuits 56 and 57 are added to the distance measuring system_ECU 100 of the second embodiment, and a substitute pulse is output from the control circuit 36 to the NOT gate 54. Then, a substitute pulse PC1 having a peak voltage that is the same as the output voltage of the averaging processing circuit 56 and a bottom voltage that is the same as the output voltage of the averaging processing circuit 57 passes through the switch 35 from the common connection terminal 58 and the non-output of the comparator 31 Output to the inverting input terminal (+). For this reason, the bottom voltage of the substitute pulse PC1 can be brought close to the bottom voltage of the received light pulse, and the peak voltage of the substitute pulse PC1 can be brought closer to the peak voltage of the received light pulse. For this reason, the delay time of the received light pulse generated in the comparator 31 can be made closer to the delay time of the substitute pulse PC1 generated in the comparator 31. For this reason, the accuracy of the phase difference Db obtained by the pulse phase difference encoding circuit 32 corresponding to the substitute pulse PC1 can be further improved.

(Fourth embodiment)
In the first embodiment, the example in which the substitute pulse PC2 from the control circuit 36 is bypassed the comparator 31 and output to the pulse phase difference encoding circuit 32 has been described. Instead, in the fourth embodiment, An example in which the substitute pulse PC2 from the control circuit 36 is output to the pulse phase difference encoding circuit 32 through the comparator 31 will be described.

  FIG. 15 is a diagram illustrating a circuit configuration in the ranging system_ECU 100 of the present embodiment.

  In the ranging system_ECU 100 of this embodiment, the OR gates 41 and 42 are removed from the sensor signal processing circuit 20 of FIG. 1, and the substitute pulse PC2 output from the control circuit 36 is passed through the switch 35 to the non-inverting input of the comparator 31. The configuration is given to the terminal (+).

  In addition, in the sensor signal processing circuit 20 of the present embodiment, the control pulse from the control circuit 36 is directly applied to the input terminal PA of the pulse phase difference encoding circuit 32, and the output signal of the comparator 31 is directly This is applied to the input terminal PB of the pulse phase difference encoding circuit 32.

  Next, the operation of the distance measuring system_ECU 100 of the present embodiment will be described.

  FIG. 15 is a timing chart of each output signal and terminal voltage with respect to FIG.

  First, the control circuit 36 initializes the pulse phase difference encoding circuit 32 and the arithmetic processing circuit 34 with a reset signal (RST, RST1: see FIG. 15 (h), (i)), and selects the selection signal SEL (FIG. 15). (See (f)), the switch 35 is controlled to connect between the output terminal of the operational amplifier 13 and the non-inverting input terminal (+) of the comparator 31, and the output terminal of the control circuit 36 and the non-inverting input of the comparator 31. Open the terminal (+).

  Next, the control circuit 36 emits laser light from the diode 10 by turning on the nMOS transistor 14 by the light emission trigger (see FIG. 15A) at the timing t1, as in the first embodiment. In addition, the control circuit 36 changes the control signal level output to the input terminal PA of the pulse phase difference encoding circuit 32 from the low level to the high level at the timing t1. That is, the control circuit 36 outputs a control pulse to the input terminal PA of the pulse phase difference encoding circuit 32 at timing t1. Thereby, in the pulse phase difference encoding circuit 32, the circulation of the pulse PA is started.

  On the other hand, when the laser beam reflected by the obstacle is received by the photodiode 11, a pulse current flows from the power source Vdd to the photodiode 11, and the operational amplifier 13 compares the received pulse with the comparator as in the first embodiment. It outputs to the non-inverting input terminal (+) of 31 (refer FIG.15 (c)). Along with this, the comparator 31 shapes the received light pulse, and outputs the shaped pulse as a pulse PB to the input terminal PB of the pulse phase difference encoding circuit 32 (see FIG. 15E). Then, the pulse phase difference encoding circuit 32 detects the phase difference Da between the pulse PA and the pulse PB, and outputs the detected phase difference Da to the arithmetic processing circuit 34. Thereafter, the control circuit 36 outputs the data load signal LOAD to the arithmetic processing circuit 34 and causes the arithmetic processing circuit 34 to read the phase difference Da.

  Next, the control circuit 36 initializes the pulse phase difference encoding circuit 32 with a high level reset signal RST (see FIG. 15H). In addition to this, the control circuit 36 controls the switch 35 by a selection signal SEL (see FIG. 15 (f)), and opens between the output terminal of the operational amplifier 13 and the non-inverting input terminal (+) of the comparator 31. In addition, the output terminal of the control circuit 36 and the non-inverting input terminal (+) of the comparator 31 are connected.

  Next, at the timing t2, the control circuit 36 again changes the control signal level output to the input terminal PA of the pulse phase difference encoding circuit 32 from the low level (Lo) to the high level (Hi) (FIG. 15 ( b)). That is, the control circuit 36 again outputs a control pulse to the input terminal PA of the pulse phase difference encoding circuit 32 at the timing t2. For this reason, in the ring delay pulse generation circuit 1 of the pulse phase difference encoding circuit 32, the pulse PA starts to circulate.

  In addition to this, the control circuit 36 outputs a substitute pulse PC1 (see FIG. 15D) instead of the received light pulse to the non-inverting input terminal (+) of the comparator 31 via the switch 35 at the timing t2.

  By the substitute pulse PC1 output in this way, the input voltage of the non-inverting input terminal (+) of the comparator 31 becomes higher than the input voltage of the inverting input terminal (−) only for a predetermined period.

  Therefore, the comparator 31 outputs the pulse PB to the pulse phase difference encoding circuit 32. At this time, the comparator 31 shapes the substitute pulse PC1 and outputs the shaped pulse to the input terminal PB of the pulse phase difference encoding circuit 32 as a pulse PB. Along with this, the pulse phase difference encoding circuit 32 specifies the circulation position of the pulse PA and the number of circulations of the pulse PA at the input timing of the pulse PB to the ring delay pulse generation circuit 1, respectively, and the identified circulation position. The phase difference Db between the pulse PA and the pulse PB is detected based on the number of laps and the number of laps, and the detected phase difference Db is output to the arithmetic processing circuit 34.

  Next, the control circuit 36 outputs the data load signal LOAD to the arithmetic processing circuit 34. Therefore, the arithmetic processing circuit 34 reads the phase difference Db output from the pulse phase difference encoding circuit 32.

  Thereafter, the control circuit 36 outputs a substitute pulse PC2 instead of the received light pulse to the non-inverting input terminal (+) of the comparator 31 via the switch 35 at a timing t3 when a certain period Ts has elapsed from the timing t2. By the substitute pulse PC2 output in this way, the input voltage of the non-inverting input terminal (+) of the comparator 31 becomes higher than the input voltage of the inverting input terminal (−) only for a predetermined period. For this reason, the comparator 31 shapes the substitute pulse PC2 and outputs the shaped pulse to the input terminal PB of the pulse phase difference encoding circuit 32 as a pulse PB. Along with this, the pulse phase difference encoding circuit 32 specifies the circulation position of the pulse PA and the number of circulations of the pulse PA at the input timing of the pulse PB to the ring delay pulse generation circuit 1, respectively, and the identified circulation position. The phase difference Dc between the pulse PA and the pulse PB is detected based on the number of rotations and the number of laps, and the detected phase difference Dc is output to the arithmetic processing circuit 34.

  Thereafter, the control circuit 36 outputs the calculation permission signal ENA to the calculation processing circuit 34 as a high level signal. Accordingly, the arithmetic processing circuit 34 reads the phase difference Dc output from the pulse phase difference encoding circuit 32. Accordingly, the arithmetic processing circuit 34 substitutes the phase differences Da, Db, and Dc into the following formula 15 to calculate normalized data Dy.

Dy = (Da−Db) / (Dc−Db) (Equation 15)
Next, the arithmetic processing circuit 34 uses L and Dy as the distance calculation means, where L is the distance that the light propagates during a certain period Ts (= the period from timing t2 to timing t3). Substituting into Equation 16, the distance Z between the distance sensor and the obstacle is obtained.

Z = (L × Ds) / 2 (Equation 16)
In the present embodiment described above, the pulse phase difference encoding circuit 32 obtains the phase difference Da corresponding to the received light pulse, the phase difference Db corresponding to the substitute pulse PC1, and the phase difference Dc corresponding to the substitute pulse PC2.

  The phase difference Da indicates the time required from when the laser beam is emitted from the diode 10 to when the reflected laser beam is received by the photodiode 11. The phase difference Db indicates a delay time required from when the received light pulse is input to the comparator 31 to when the received light pulse is output from the comparator 31. The phase difference Dc indicates a phase difference generated between the pulse PA and the pulse PB in a certain period Ts (for example, 2 μsec).

  The phase differences Da and Dc include a delay time that occurs when the light reception pulse passes through the comparator 31. Therefore, by subtracting the phase difference Db from the phase difference Da, the delay time due to the comparator 31 can be removed from the phase difference Da. By subtracting the phase difference Db from the phase difference Dc, the delay time due to the comparator 31 can be removed from the phase difference Dc.

Here, a measurement error may occur in the pulse phase difference encoding circuit 32 due to a disturbance such as a temperature change of the pulse phase difference encoding circuit 32. For this reason, the phase differences Da, Db, and Dc obtained by the pulse phase difference encoding circuit 32 may change due to a temperature change of the pulse phase difference encoding circuit 32 or the like.
Therefore, by dividing (Da−Db) by (Dc−Db), the measurement error of the pulse phase difference encoding circuit 32 can be canceled in the normalized data Dy. As a result, the normalized data obtained by removing the measurement error of the comparator 31 and the measurement error of the pulse phase difference encoding circuit 32 can be obtained as in the first, second, and third embodiments. Therefore, as in the first, second, and third embodiments, measurement errors included in the normalized data can be reduced.

  In this embodiment, since the normalized data {(Da−Db) / (Dc−Db)} is used when calculating the distance L between the sensor and the obstacle, the distance between the sensor and the obstacle is determined. Can be obtained with high accuracy.

(Fifth embodiment)
In the present embodiment, an in-vehicle system that achieves safe traveling of the vehicle using the distance Z obtained by the ranging system_ECU 100 of the first embodiment described above will be described.

  FIG. 16 is a diagram illustrating an overall configuration of the in-vehicle system 200 according to the present embodiment. The in-vehicle system 200 includes a ranging system_ECU 100, a meter_ECU 101, and a VSC_ECU 102.

  The ranging system_ECU 100 is configured in addition to the configuration (10, 11, 13, 14, R1, 20) for measuring the distance between the distance sensor and surrounding obstacles as in the first embodiment. A configuration for outputting a distance signal indicating the measured distance is provided.

  The meter_ECU 101 includes a speed sensor that detects the speed of the host vehicle and outputs a vehicle speed signal indicating the vehicle speed. The VSC_ECU 102 constitutes a vehicle safe driving device, and is a well-known electronic control device composed of a microcomputer, a memory, and the like. The VSC_ECU 102 is an alarm device according to the distance between the host vehicle and surrounding obstacles. The control process which controls control and the braking device of the own vehicle is performed.

  The distance measurement system_ECU 100, meter_ECU 101, and VSC_ECU 102 of the present embodiment are connected by an in-vehicle LAN 103. As the in-vehicle LAN 103, for example, CAN (Controller Area Network) is used.

  Next, the control processing of the VSC_ECU 102 of the present embodiment will be described using FIG. FIG. 17 is a flowchart showing a control process of the VSC_ECU 102.

  First, in step S100, a vehicle speed signal is received from the speed sensor of the meter_ECU 101 via the in-vehicle LAN 103, and based on the received vehicle speed signal, it is determined whether or not the vehicle speed is equal to or less than a threshold A (km / h). Determine (speed determination means).

  At this time, when the vehicle speed is greater than the threshold value A, it is determined as NO, and the determination in step S100 is performed again. For this reason, as long as the vehicle speed is maintained higher than the threshold value A, the NO determination in step S100 is repeated.

  Thereafter, when the vehicle speed becomes equal to or less than the threshold value A, YES is determined in step S100, and the process proceeds to step S110. At this time, a distance signal is received from the ranging system_ECU 100 via the in-vehicle LAN 103, and based on the received distance signal, the distance between the preceding vehicle and the distance sensor is equal to or less than a threshold value B (km). (First determination means). For this reason, when the distance is larger than the threshold value B, NO is determined in step S110, and the determination in step S110 is performed again. Therefore, thereafter, as long as the distance remains larger than the threshold value B, the NO determination in step S110 is repeated.

  Thereafter, when the distance becomes equal to or less than the threshold value B, YES is determined in step S110, and in step S120, the warning device is controlled to warn the driver that the distance between the preceding vehicle and the distance sensor is too short. Then, an alarm is issued (warning control means).

  As the warning device, a device that warns the driver by voice or a device that warns the driver by display on the display panel is used.

  In the next step S130, a distance signal is received from the ranging system_ECU 100 via the in-vehicle LAN 103, and the distance between the preceding vehicle and the distance sensor is equal to or less than a threshold C (km) based on the received distance signal. Is determined (second determination means). The threshold C is set to a distance shorter than the threshold B.

  Here, when the distance is larger than the threshold value C, NO is determined in step S130, and the determination in step S130 is performed again. For this reason, thereafter, as long as the distance remains larger than the threshold value C, the NO determination in step S130 is repeated. Thereafter, when the distance becomes equal to or smaller than the threshold value C, YES is determined in step S130, and the process proceeds to step S140. At this time, as a braking control means, a brake device (braking device) of the host vehicle is controlled to stop the host vehicle. Thereby, the own vehicle can be stopped.

  According to the present embodiment described above, when it is determined that the vehicle speed is equal to or less than the threshold A (step S100: YES), and the distance between the preceding vehicle and the distance sensor is determined to be equal to or less than the threshold B (step S110: NO), in order to warn the driver that the distance between the vehicle ahead and the distance sensor is too short, the warning device is controlled to issue an alarm (step S120). Thereby, it is possible to prompt the driver to drive the vehicle safely.

  In this embodiment, when it is determined that the vehicle speed is equal to or less than the threshold A (step S100: YES), and the distance between the preceding vehicle and the distance sensor is equal to or less than the threshold C, the brake device is controlled to control the own vehicle. stop. For this reason, the collision with respect to the front vehicle in the own vehicle can be avoided beforehand.

Here, in steps S110 and S130, the distance comparison determination is performed using the distance Z obtained in the first embodiment. For this reason, distance comparison determination can be performed with high accuracy. Therefore, safe traveling of the vehicle can be achieved by using the distance Z obtained in the first embodiment.
(Other embodiments)
In the first to fourth embodiments described above, L × {(Da−Db) where L is the distance between the distance sensor and the obstacle and the light propagation distance during the predetermined period (Ts). Although an example has been described in which the calculation processing circuit (distance calculation means) 34 calculates / (Dc−Db)} / 2 as the distance between the sensor and the obstacle, the calculation processing circuit is used instead. The distance between the distance sensor and the obstacle may be calculated by a circuit device other than 34.

  In the above-described third embodiment, the example in which the four light receiving pulses are used when the averaging processing circuits 56 and 57 obtain the average voltage of the peak voltage and the bottom voltage has been described. , The averaging processing circuits 56 and 57 may obtain the average voltage of the peak voltage and the bottom voltage using a number of received light pulses other than four.

  In the first, second, and third embodiments described above, OR gates 41 and 42 (see FIGS. 1, 4, and 10) are used as the first and second selection gates having the same circuit configuration. Although the example has been described, the first and second input terminals are provided, one of the first and second input terminals is connected to the output terminal, and the other input terminal is connected to the output terminal. A switch circuit that opens the switch may be used. In the switch circuit, whether one of the first and second input terminals is connected to the output terminal is switched according to a switching signal output from the control circuit 36.

  For example, when a switch circuit is used instead of the OR gate 41, the output terminal of the comparator 31 is connected to the first input terminal and the output terminal of the control circuit 36 is connected to the second input terminal in the switch circuit. . When a switch circuit is used instead of the OR gate 42, the output terminal of the control circuit 36 is connected to the first input terminal and the second input terminal is connected to the ground in the switch circuit.

  In the above-described fifth embodiment, the example in which the control process of FIG. 17 is performed using the distance obtained by the distance measuring system_ECU 100 of the above-described first embodiment has been described. The control process of FIG. 17 may be performed using the distance obtained by any one of the distance measurement system_ECU 100 in the third and fourth embodiments.

  In the above-described fifth embodiment, the example in which the warning is issued and the vehicle is braked using the distance obtained by the distance measuring system_ECU 100 has been described. The distance obtained by the distance measuring system_ECU 100 may be used for control of auto-cruising that travels while maintaining the distance. Alternatively, the distance between the host vehicle and an obstacle around the host vehicle may be measured, and the measured distance may be used for control for parking assistance of the host vehicle.

  In the first to fifth embodiments described above, the example in which the sensor signal processing circuit 20 of the present invention is applied to an automobile has been described. Instead, the sensor signal processing circuit 20 of the present invention is replaced with a train other than an automobile, etc. The present invention may be applied to various vehicles. When the sensor signal processing circuit 20 is applied to a train, the distance between the train on which the sensor signal processing circuit 20 is mounted and the forward train located in front of the train can be measured.

DESCRIPTION OF SYMBOLS 10 Diode 11 Photodiode 13 Operational amplifier 14 nMOS transistor 20 Signal processing circuit 31 for sensors 31 Comparator (1st waveform shaper)
32 Pulse phase difference encoding circuit (phase difference detection circuit)
34 Arithmetic processing circuit (data arithmetic circuit, distance calculation means)
35 switch (output switching means)
36 control circuit 41 OR gate (second selection gate)
42 OR gate (first selection gate)
50 Peak hold circuit 51 Bottom hold circuit 52 Switch 53 Switch 54 NOT gate 55 NOT gate 56 Averaging circuit 57 Averaging circuit 80a Sample hold circuit 80b Sample hold circuit 80c Sample hold circuit 80d Sample hold circuit 80e Adder circuit 80f Inverting circuit 100 Ranging system_ECU
101 Meter_ECU
102 VSC_ECU
200 In-vehicle system

Claims (9)

Based on an output signal of a sensor including a light emitting element (10) that emits light and a light receiving element (11) that receives reflected light reflected by an obstacle and outputs a light reception pulse, the light emitting element emits light. A sensor signal processing circuit that calculates normalized data obtained by normalizing a time required for the light receiving element to receive light after being emitted,
In a ring circuit having a plurality of delay elements connected in a ring shape, the circulating position of the first pulse at the input timing of the second pulse (PB) input after starting the circulation of the first pulse (PA) And the number of laps of the first pulse, and a phase difference detection circuit (32) for detecting a phase difference between the first pulse and the second pulse based on the specified lap position and number of laps. )When,
A trigger signal for emitting light to the light emitting element, a control pulse for starting the circulation of the first pulse in the ring circuit, and first and second substitute pulses in place of the light receiving pulse are output, respectively. A control circuit (36) for
A first input terminal to which the control pulse is input; and a second input terminal in which an input signal level is set to a low level, and the control pulse is output to the phase difference detection circuit to output the first A first selection gate (42) for starting the circulation of one pulse;
An output switching means (35) for outputting any one of the received light pulse from the light receiving element and the first substitute pulse (PC1) from the control circuit;
A first waveform shaper (31) that shapes the pulse output from the output switching means;
A first input terminal having a circuit configuration identical to that of the first selection gate, to which a pulse output from the first waveform shaper is applied, and the second substitute pulse (PC2) from the control circuit And a second input terminal that outputs the second pulse to the phase difference detection circuit when a pulse is applied to one of the first and second input terminals. (41)
The control circuit (36) outputs the trigger signal to the light emitting element, and outputs the control pulse to the phase difference detection circuit through the first selection gate (42) at a first timing, The selection gate (41) outputs the second pulse based on the received light pulse to the phase difference detection circuit to detect the phase difference corresponding to the received light pulse,
The control circuit outputs the control pulse to the phase difference detection circuit through the first selection gate (42) at a second timing different from the first timing, and outputs the first substitute pulse to the output switching means. (35) and the first waveform shaper to the second selection gate to output the second pulse from the second selection gate (41) to the phase difference detection circuit. The second substitute pulse is supplied to the second selection gate (41) after the phase difference corresponding to the pulse is detected and after a lapse of a certain period (Ts) after the output of the control pulse. The second pulse is output from the selection gate (41) to the phase difference detection circuit to detect the phase difference corresponding to the second substitute pulse,
The phase difference corresponding to the received light pulse is Da, the phase difference corresponding to the first substitute pulse is Db, the phase difference corresponding to the second substitute pulse is De, and the normalized data is (Da A signal processing circuit for sensors, comprising a data operation circuit (34) for obtaining -Db) / De.   The sensor signal processing circuit according to claim 1, wherein the first and second selection gates (41, 42) are OR gates. The output switching means (35) connects between one of the light receiving element (11) and the control circuit (36) and the first waveform shaper (31), and the other and the first It is a switch that opens between the waveform shaper (31) of
The control circuit controls the switch to connect between the light receiving element (11) and the first waveform shaper (31), and between the control circuit and the first waveform shaper (31). When the gap is opened, the light receiving pulse output from the light receiving element is output to the first waveform shaper through the switch,
The control circuit controls the switch to open the space between the light receiving element (11) and the first waveform shaper (31), and between the control circuit and the first waveform shaper (31). The first substitute pulse (PC1) output from the control circuit is connected to the first waveform shaper through the switch when connected to each other. Alternatively, the sensor signal processing circuit according to 2. A peak hold circuit (50) for sampling a peak voltage of the received light pulse and holding an output voltage at the sampled voltage;
A bottom hold circuit (51) for sampling a bottom voltage of the received light pulse and holding an output voltage at the sampled voltage;
Upon receiving the first substitute pulse output from the control circuit (36), the peak voltage is the same as the output voltage of the peak hold circuit, and the bottom voltage is the same as the output voltage of the bottom hold circuit. The sensor according to any one of claims 1 to 3, further comprising a second waveform shaping circuit (52 to 55) for outputting a first substitute pulse to the output switching means (35). Signal processing circuit. The control circuit (36) outputs the trigger signal to the light emitting element a plurality of times so that light is emitted from the light emitting element a plurality of times, and the light receiving element receives the reflected light a plurality of times. The light reception pulse is output to the peak hold circuit and the bottom hold circuit for each light reception,
The peak hold circuit is configured to sample the peak voltage of the received light pulse for each received light pulse,
The bottom hold circuit is configured to sample the bottom voltage of the light reception pulse for each light reception pulse,
A first averaging processing circuit (56) for outputting an average voltage value indicating an average value of output voltages output from the peak hold circuit for each sampling;
A second averaging processing circuit (57) for outputting an average voltage value indicating an average value of the output voltages output for each sampling from the bottom hold circuit;
Upon receiving the first substitute pulse output from the control circuit (36), the peak voltage is the same as the output voltage of the first averaging processing circuit (56), and the bottom voltage is the second average. And a third waveform shaping circuit (52 to 55) for outputting the first substitute pulse, which is the same as the output voltage of the conversion processing circuit (57), to the output switching means (35). The sensor signal processing circuit according to claim 1.   A distance calculation means for calculating L × {(Da−Db) / De} / 2 as a distance between the sensor and the obstacle, where L is a distance through which light propagates during the predetermined period. 34) The signal processing circuit for a sensor according to any one of claims 1 to 5, further comprising: 34). Based on an output signal of a sensor including a light emitting element (10) that emits light and a light receiving element (11) that receives reflected light reflected by an obstacle and outputs a light reception pulse, the light emitting element emits light. A sensor signal processing circuit that calculates normalized data obtained by normalizing a time required for the light receiving element to receive light after being emitted,
In a ring circuit having a plurality of delay elements connected in a ring shape, the circulating position of the first pulse at the input timing of the second pulse (PB) input after starting the circulation of the first pulse (PA) A phase difference detection circuit that detects a phase difference between the first pulse and the second pulse based on the specified circulation position and the number of circulations. 32)
A trigger signal for emitting light to the light emitting element, a control pulse for starting the circulation of the first pulse in the ring circuit, and first and second substitute pulses in place of the light receiving pulse are output, respectively. A control circuit (36) for
An output switching means (35) for outputting any one of the received light pulse from the light receiving element and the first and second substitute pulses (PC1, PC2) from the control circuit;
A first waveform shaper (31) that shapes the pulse output from the output switching means and outputs the waveform-shaped pulse as the second pulse to the phase difference detection circuit;
The control circuit outputs the control pulse to the phase difference detection circuit at a first timing, causes the ring circuit to start circulating the first pulse, and outputs the trigger signal to the light emitting element. The first waveform shaper outputs the second pulse based on the received light pulse to the phase difference detection circuit, the phase difference detection circuit detects the phase difference corresponding to the received light pulse, and The control circuit outputs the control pulse to the phase difference detection circuit at a second timing different from the first timing, and outputs the first substitute pulse (PC1) instead of the received light pulse to the output switching means (35). And outputting to the phase difference detection circuit through the first waveform shaper (31) to detect the phase difference corresponding to the first substitute pulse, and The second substitute pulse (PC2) is output to the phase difference detection circuit through the output switching means and the first waveform shaper after a lapse of a certain period (Ts) after the start of the first pulse. Detecting the phase difference corresponding to two substitute pulses,
The phase difference corresponding to the received light pulse after the waveform shaping is Da, the phase difference corresponding to the first substitute pulse is Db, the phase difference corresponding to the second substitute pulse is Dc, A sensor signal processing circuit comprising a data operation circuit (34) for obtaining (Da-Db) / (Dc-Db) as normalized data.   L × {(Da−Db) / (Dc−Db)} / 2 is calculated as the distance between the sensor and the obstacle, where L is the distance that the light propagates during the certain period. 8. The sensor signal processing circuit according to claim 7, further comprising a distance calculating means (34).   The first waveform shaper (31) has an output signal at a high level when a signal output from the light receiving element is equal to or greater than a predetermined value, and a signal output from the light receiving element is less than a predetermined value. 9. The sensor signal processing circuit according to claim 1, wherein the output signal is sometimes at a low level.

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