JP5810882B2 - Demodulator and demodulation method - Google Patents

Description

  The present invention relates to a demodulator that performs demodulation and a demodulation method.

  A software defined radio capable of supporting various wireless systems by replacing software is known (for example, see Patent Document 1 below). The software defined radio is used not only in a standardized system such as a cellular system but also in a monitoring system for monitoring an illegal radio system and various business radios. For example, radio wave monitoring systems are required to be able to set flexible specifications in order to receive and demodulate unknown specifications (for example, symbol rate and carrier frequency).

  Conventional demodulator of software defined radio includes a baseband signal sampling method (direct conversion method) and an IF sampling method, for example, when classified according to a signal stage that performs A / D (Analog / Digital) conversion.

  In the baseband signal sampling method, from reception of an RF (Radio Frequency) signal to quadrature detection (orthogonal demodulation) is performed by analog processing, and baseband demodulation after quadrature detection is performed by digital processing. Therefore, since the complex local signal used for quadrature detection is generated by analog processing, the orthogonality of the I component and the Q component of the complex local signal is not perfect. For this reason, the orthogonality of the I component and the Q component of the baseband signal after quadrature detection is not perfect, and the demodulation characteristics deteriorate.

  On the other hand, in the IF sampling method, the RF signal is converted into an IF (Intermediate Frequency) signal by frequency conversion. Then, the converted IF signal is converted into a digital signal, and quadrature detection and baseband signal demodulation are performed by digital processing.

  By the way, in order to remove noise in a spread spectrum receiver, a technique is known in which a signal is converted into an analog signal at a subsequent stage of the spread spectrum demodulator and converted into a digital signal after passing through a filter (for example, Patent Document 2 below). reference.).

JP 2000-91936 A Japanese Patent Laid-Open No. 10-303764

  However, in the above-described conventional IF sampling method, the sampling frequency at the time of A / D conversion depends on the frequency of the IF signal in consideration of aliasing at the time of sampling, so it is difficult to set the sampling frequency suitable for baseband demodulation. It is. For this reason, there is a problem that the demodulation performance is lowered depending on the frequency of the IF signal.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a demodulator and a demodulation method that can improve demodulation performance in order to solve the above-described problems caused by the prior art.

  In order to solve the above-described problems and achieve the object, according to one aspect of the present invention, the frequency of the first sampling clock is adjusted, and the first analog clock to be demodulated is adjusted in frequency. To convert the first digital signal into a first digital signal, perform quadrature detection of the converted first digital signal, convert the second digital signal obtained by the detection result into a second analog signal, and The frequency of the second sampling clock different from the above is adjusted, the converted second analog signal is sampled by the second sampling clock adjusted in frequency, converted into a third digital signal, and the converted third digital signal A demodulator and a demodulation method are proposed for baseband demodulation.

  According to one aspect of the present invention, it is possible to improve the demodulation performance.

FIG. 1 is a diagram illustrating an example of a configuration of a demodulator according to the first embodiment. FIG. 2-1 is a graph illustrating a first example of folding by sampling. FIG. 2-2 is a graph showing a second example of aliasing by sampling as a reference. FIG. 3A is a diagram (part 1) illustrating an example of a relationship between an IF frequency and a sampling frequency. FIG. 3-2 is a diagram (part 2) illustrating an example of a relationship between the IF frequency and the sampling frequency. FIG. 3C is a diagram (part 3) illustrating an example of the relationship between the IF frequency and the sampling frequency. FIG. 4 is a diagram illustrating an example of a configuration of a receiving device to which a demodulator is applied. FIG. 5A is a diagram illustrating an example of the configuration of the digital orthogonal demodulation unit. FIG. 5B is a diagram illustrating an example of the configuration of the sampling rate conversion unit. FIG. 5C is a diagram illustrating an example of the configuration of the baseband demodulation unit. FIG. 6 is a diagram illustrating an example of the configuration of the wireless unit. FIG. 7 is a diagram illustrating another example of the configuration of the orthogonal demodulation unit. FIG. 8 is a diagram illustrating another example of the sampling rate conversion unit. FIG. 9 is a diagram illustrating an example of the configuration of the demodulation processing unit. FIG. 10 is a diagram illustrating an example of the configuration of each clock generation unit. FIG. 11 is a diagram illustrating an example of the configuration of the quadrature detection unit. FIG. 12A is a graph (part 1) illustrating an example of a local signal generated by the complex LO generation unit. FIG. 12-2 is a graph (part 2) illustrating an example of a local signal generated by the complex LO generation unit. FIG. 13 is a diagram illustrating an example of the configuration of the IQ mismatch correction unit. FIG. 14 is a graph illustrating an example of a training signal generated by the training signal generation unit. FIG. 15 is a graph showing an example of IQ mismatch occurring in the training signal. FIG. 16 is a sequence diagram illustrating a specific example of IQ mismatch correction processing. FIG. 17 is a sequence diagram illustrating a specific example of the initial setting process. FIG. 18 is a flowchart illustrating an example of an operation during continuous reception in the reception device. FIG. 19 is a flowchart illustrating an example of an operation at the time of TDD reception in the reception device. FIG. 20 is a diagram of an example of a configuration of the receiving apparatus according to the second embodiment. FIG. 21 is a flowchart of an example of AFC processing in the receiving apparatus according to the second embodiment. FIG. 22 is a sequence diagram illustrating a specific example of the AFC process in the receiving apparatus according to the second embodiment. FIG. 23 is a diagram of an example of a configuration of the receiving apparatus according to the third embodiment. FIG. 24 is a flowchart of an example of timing synchronization processing in the receiving apparatus according to the third embodiment. FIG. 25 is a sequence diagram of a specific example of timing synchronization processing in the receiving apparatus according to the third embodiment.

  Exemplary embodiments of a demodulator and a demodulation method according to the present invention will be explained below in detail with reference to the accompanying drawings.

(Embodiment 1)
(Configuration of Demodulator According to First Embodiment)
FIG. 1 is a diagram illustrating an example of a configuration of a demodulator according to the first embodiment. As illustrated in FIG. 1, the demodulator 100 according to the first exemplary embodiment includes a first adjustment unit 110, a first digital conversion unit 120, a quadrature detection unit 130, an analog conversion unit 140, and a second adjustment unit 150. And a second digital converter 160 and a baseband demodulator 170.

  The first adjustment unit 110 adjusts the frequency of the first sampling clock input to the first digital conversion unit 120. For example, the first adjustment unit 110 adjusts the frequency of the first sampling clock by controlling a first clock generation unit that generates a first sampling clock having a variable frequency input to the first digital conversion unit 120. The first adjustment unit 110 may automatically adjust the frequency of the first sampling clock, for example, by a control circuit, or may adjust the frequency of the first sampling clock according to a user operation.

  An analog signal to be demodulated by the demodulator 100 is input to the first digital conversion unit 120. The analog signal to be demodulated by the demodulator 100 is, for example, an analog signal that is received by an antenna at the front stage of the demodulator 100 and converted from an RF signal to an IF signal. However, the analog signal to be demodulated by the demodulator 100 is not limited to such an analog signal.

  The first digital conversion unit 120 converts an input analog signal into a digital signal by sampling and quantizing the input analog signal using a first sampling clock whose frequency is adjusted by the first adjustment unit 110. The first digital conversion unit 120 outputs the converted digital signal to the quadrature detection unit 130.

  The quadrature detection unit 130 performs quadrature detection of the digital signal output from the first digital conversion unit 120. The quadrature detection unit 130 outputs a baseband (baseband) digital signal obtained from the detection result to the analog conversion unit 140. The analog conversion unit 140 converts the digital signal output from the quadrature detection unit 130 into an analog signal. The analog conversion unit 140 outputs the converted analog signal to the second digital conversion unit 160.

  The second adjustment unit 150 adjusts the frequency of the second sampling clock input to the second digital conversion unit 160. For example, the second adjustment unit 150 adjusts the frequency of the second sampling clock by controlling a second clock generation unit that generates a second sampling clock having a variable frequency input to the second digital conversion unit 160. For example, the second adjustment unit 150 may automatically adjust the frequency of the second sampling clock by a control circuit, or may adjust the frequency of the second sampling clock in accordance with a user operation.

  The second digital converter 160 converts the analog signal output from the analog converter 140 into a digital signal by sampling and quantizing with the second sampling clock whose frequency is adjusted by the second adjuster 150. . Second digital converter 160 outputs the converted digital signal to baseband demodulator 170. The baseband demodulator 170 performs baseband demodulation on the digital signal output from the second digital converter 160. The baseband demodulator 170 outputs a demodulation result by baseband demodulation.

  As described above, the demodulator 100 is configured to resample at an arbitrary rate between the quadrature detection unit 130 and the baseband demodulation unit 170 by the analog conversion unit 140, the second adjustment unit 150, and the second digital conversion unit 160. It is. Thereby, digital quadrature detection by the quadrature detection unit 130 and baseband demodulation by the baseband demodulation unit 170 can be performed at independent rates.

(Return by sampling)
FIG. 2-1 is a graph illustrating a first example of folding by sampling. The vertical axis in FIG. 2A represents the level of the IF signal converted from the received RF signal. The horizontal axis of FIG. 2A represents the frequency of the IF signal converted from the received RF signal. The frequency Fs on the horizontal axis indicates the sampling frequency when the IF signal is converted into a digital signal by the first digital conversion unit 120. Therefore, the frequency Fs / 2 on the horizontal axis is a Nyquist frequency when the IF signal is converted into a digital signal by the first digital conversion unit 120.

  Here, frequency 0 to frequency Fs / 2 is referred to as a first Nyquist zone, frequency Fs / 2 to frequency Fs is referred to as a second Nyquist zone, and frequency Fs to frequency 3 * Fs / 2 is referred to as a third Nyquist zone.

  An IF signal 211 indicates an IF signal converted from the received RF signal. In the example illustrated in FIG. 2A, the frequency of the IF signal 211 is the center frequency of the third Nyquist zone. When the IF signal 211 is converted into a digital signal, a folding phenomenon occurs in which the IF signal 211 is copied to another Nyquist zone.

  The aliasing component 212 is a component obtained by copying the IF signal 211 to the second Nyquist zone. The folding component 213 is a component obtained by copying the folding component 212 to the first Nyquist zone. In the example illustrated in FIG. 2A, the aliasing components 212 and 213 are generated in the second Nyquist zone and the first Nyquist zone, respectively, and do not overlap the IF signal 211. Therefore, for example, the IF signal 211 can be demodulated (reference numeral 214) by quadrature detection based on the aliasing component 213 and baseband demodulation.

  FIG. 2-2 is a graph showing a second example of aliasing by sampling as a reference. 2-2, the same parts as those shown in FIG. 2-1 are denoted by the same reference numerals and description thereof is omitted. In the example shown in FIG. 2B, the frequency of the IF signal 211 is a frequency Fs / 2 that is a boundary between the first Nyquist zone and the second Nyquist zone. For this reason, the band of the IF signal 211 straddles the first Nyquist zone and the second Nyquist zone.

  The aliasing component 221 (shaded portion) is a component obtained by copying the IF signal 211 due to the aliasing phenomenon. In the example shown in FIG. 2-2, the band of the IF signal 211 straddles the first Nyquist zone and the second Nyquist zone.

  For this reason, the aliasing component 221 overlaps with the IF signal 211, and it is difficult to demodulate the IF signal 211 even if quadrature detection and baseband demodulation are performed. As described above, the sampling frequency Fs depends on the frequency of the IF signal in consideration of aliasing during sampling. On the other hand, in baseband demodulation, it is desirable that the sampling frequency Fs be an integral multiple (for example, four times) of the symbol rate (oversampling).

  On the other hand, the demodulator 100 is configured to resample at an arbitrary rate between the quadrature detection unit 130 and the baseband demodulation unit 170. For this reason, in A / D conversion before quadrature detection, a sampling frequency in which the IF signal does not straddle a plurality of Nyquist zones is set, and in A / D conversion in the previous stage of baseband demodulation, an integer multiple of the symbol rate is set. Thus, the sampling frequency can be set.

  Therefore, since it is possible to perform baseband demodulation by oversampling an integer multiple of the symbol rate while avoiding overlapping of the aliasing component with the IF signal in sampling, it is possible to improve demodulation performance. In the A / D conversion preceding the baseband demodulation, in the A / D conversion preceding the baseband demodulation, the signal to be A / D converted is a baseband signal by quadrature detection, and the symbol Since oversampling is performed at an integral multiple of the rate, no aliasing component occurs.

  Further, as a configuration for re-sampling, a configuration is used in which the digital signal obtained by the quadrature detection unit 130 is converted into an analog signal, and the converted analog signal is converted again into a digital signal using a second sampling clock. Thereby, for example, a more flexible sampling rate conversion ratio including a rational number ratio can be realized as compared with a configuration in which the sampling rate is converted by digital processing. For this reason, for example, a signal whose symbol rate is unknown can be demodulated by changing the sampling rate flexibly.

  FIG. 3A is a diagram (part 1) illustrating an example of a relationship between an IF frequency and a sampling frequency. 3A, the same parts as those shown in FIG. 2A are denoted by the same reference numerals and description thereof is omitted. In the IF sampling method, when the relationship between the frequency (IF) of the IF signal 211 and the sampling frequency (Fs) satisfies the following expression (1), the frequency of the IF signal 211 matches the center wavelength of the Nyquist zone. Thereby, it is possible to avoid the folded component of the IF signal 211 from overlapping the IF signal 211.

  IF = (1/4) * Fs + ((n−1) / 2) * Fs (1)

  In the above formula (1), n is a natural number (1, 2, 3,...). When n = 1, the frequency IF of the IF signal 211 matches the center wavelength (1/4) * Fs of the first Nyquist zone shown in FIG. When n = 2, the frequency IF of the IF signal 211 matches the center wavelength (3/4) * Fs of the second Nyquist zone shown in FIG. When n = 3, the frequency IF of the IF signal 211 matches the center wavelength (5/4) * Fs of the third Nyquist zone shown in FIG. Thus, when n = k, the frequency IF of the IF signal 211 matches the center frequency of the kth Nyquist zone.

  FIG. 3-2 is a diagram (part 2) illustrating an example of a relationship between the IF frequency and the sampling frequency. In FIG. 3B, the same parts as those shown in FIG. As illustrated in FIG. 3B, for example, it is assumed that the frequency IF of the IF signal 211 is between the center wavelength (3/4) * Fs of the second Nyquist zone and the sampling frequency Fs.

  In this case, since the IF signal 211 is not in the center of the Nyquist zone, it is difficult to realize a filter having a filter characteristic 321 that transmits the IF signal 211 and attenuates frequency components different from the IF signal 211.

  FIG. 3C is a diagram (part 3) illustrating an example of the relationship between the IF frequency and the sampling frequency. 3C, the same parts as those shown in FIG. 3B are denoted by the same reference numerals and description thereof is omitted. In the example illustrated in FIG. 3C, the frequency IF of the IF signal 211 matches the center wavelength (3/4) * Fs of the second Nyquist zone.

  In this case, since the IF signal 211 is at the center of the Nyquist zone, a filter having a filter characteristic 321 that transmits the IF signal 211 and attenuates frequency components different from the IF signal 211 can be easily realized. As a result, it becomes easy to prevent folding from another Nyquist zone. As described above, in order to improve the anti-aliasing effect in sampling, it is desirable that the frequency IF of the IF signal 211 matches the center wavelength of the Nyquist zone.

(Configuration of receiving device to which demodulator is applied)
FIG. 4 is a diagram illustrating an example of a configuration of a receiving device to which a demodulator is applied. A receiving apparatus 400 illustrated in FIG. 4 is a receiving apparatus to which the demodulator 100 illustrated in FIG. 1 is applied. The receiving apparatus 400 includes a receiving antenna 410, a radio unit 420, a demodulator 430, and a control unit 440. FIG. 4 illustrates a configuration of receiving apparatus 400 that receives a signal of an OFDM (Orthogonal Frequency Division Multiple) modulation system. For example, receiving apparatus 400 is a software defined radio that can change the demodulation specifications in demodulator 430 by rewriting software.

  The reception antenna 410 receives an RF signal wirelessly transmitted from the transmission side. The RF signal received by the receiving antenna 410 is an OFDM signal including an I signal (first signal) and a Q signal (second signal) whose phases are orthogonal to each other. The receiving antenna 410 outputs the received RF signal to the radio unit 420.

  The radio unit 420 is a frequency conversion unit that converts an analog signal received by the receiving antenna 410 into a frequency (IF) between the frequency (RF) of the radio signal and the baseband frequency. Specifically, the radio unit 420 performs processing such as amplification, filtering, and frequency conversion to IF on the RF signal output from the receiving antenna 410 under the control of the control unit 440 (see, for example, FIG. 6). ). Radio section 420 outputs the processed IF signal to demodulator 430.

  Demodulator 430 has a configuration corresponding to demodulator 100 shown in FIG. The demodulator 430 demodulates the IF signal output from the radio unit 420 under the control of the control unit 440 and outputs the demodulation result. Specifically, the demodulator 430 includes an orthogonal demodulation clock generation unit 431, a baseband demodulation clock generation unit 432, a digital orthogonal demodulation unit 433, a sampling rate conversion unit 434, a baseband demodulation unit 435, It has.

  The orthogonal demodulation clock generation unit 431 and the control unit 440 have a configuration corresponding to the first adjustment unit 110 illustrated in FIG. The orthogonal demodulation clock generation unit 431 generates a clock signal used by the digital orthogonal demodulation unit 433 (see, for example, FIG. 10). Further, the orthogonal demodulation clock generation unit 431 changes the frequency of the generated clock signal under the control of the control unit 440. The orthogonal demodulation clock generation unit 431 outputs the generated clock signal to the digital orthogonal demodulation unit 433 and the sampling rate conversion unit 434.

  The baseband demodulation clock generation unit 432 and the control unit 440 have a configuration corresponding to the second adjustment unit 150 illustrated in FIG. The baseband demodulation clock generation unit 432 generates a clock signal used by the baseband demodulation unit 435 (see, for example, FIG. 10). The baseband demodulation clock generation unit 432 changes the frequency of the generated clock signal under the control of the control unit 440. Baseband demodulation clock generation section 432 outputs the generated clock signal to sampling rate conversion section 434 and baseband demodulation section 435.

  The digital quadrature demodulation unit 433 has a configuration corresponding to the first digital conversion unit 120 and the quadrature detection unit 130 illustrated in FIG. The digital orthogonal demodulator 433 converts the IF signal output from the radio unit 420 into a digital signal by sampling and quantizing the clock signal output from the orthogonal demodulation clock generator 431 as a sampling clock. Then, the digital orthogonal demodulator 433 performs orthogonal demodulation on the converted digital signal (see, for example, FIGS. 5-1 and 7). The digital orthogonal demodulator 433 outputs the digital baseband signal obtained by the orthogonal demodulation to the sampling rate converter 434.

  The sampling rate conversion unit 434 has a configuration corresponding to the analog conversion unit 140, the second adjustment unit 150, and the second digital conversion unit 160 illustrated in FIG. The sampling rate conversion unit 434 converts the sampling rate of the baseband signal output from the digital orthogonal demodulation unit 433 based on the clock signals output from the orthogonal demodulation clock generation unit 431 and the baseband demodulation clock generation unit 432. Convert.

  Specifically, the sampling rate conversion unit 434 converts the baseband signal output from the digital orthogonal demodulation unit 433 from the sampling rate used by the digital orthogonal demodulation unit 433 to the sampling rate used by the baseband demodulation unit 435. Conversion is performed (see, for example, FIGS. 5-2 and 8). The sampling rate conversion unit 434 outputs the baseband signal obtained by converting the sampling rate to the baseband demodulation unit 435.

  Baseband demodulation section 435 has a configuration corresponding to baseband demodulation section 170 shown in FIG. The baseband demodulator 435 performs baseband demodulation of a digital modulation scheme on the baseband signal output from the sampling rate converter 434. Baseband demodulation section 435 outputs the result of baseband demodulation as the demodulation result.

  The control unit 440 controls the radio unit 420 and the demodulator 430. For example, the control unit 440 performs each control in accordance with an instruction input from the user through the user interface of the receiving device 400. The contents of control by the control unit 440 will be described later.

  Thus, according to the receiving apparatus 400, the I signal and the Q signal can be accurately orthogonalized by performing quadrature demodulation (orthogonal detection) by digital processing. Furthermore, according to the receiving apparatus 400, by performing sampling again between the quadrature detection and the baseband demodulation and converting the sampling rate, it is possible to perform the quadrature detection and the baseband demodulation with an operation clock suitable for each. Become.

  The wireless unit 420 shown in FIG. 4 can be realized by an analog circuit, for example. The orthogonal demodulation clock generation unit 431 and the baseband demodulation clock generation unit 432 can be realized by, for example, an FPGA (Field Programmable Gate Array) or a VCO (Voltage Controlled Oscillator).

  The digital quadrature demodulator 433 can be realized by, for example, an ADC or an FPGA. The sampling rate conversion unit 434 can be realized by, for example, a DAC or an ADC. The baseband demodulator 435 and the controller 440 can be realized by, for example, an FPGA or a DSP (Digital Signal Processor).

(Configuration of digital quadrature demodulation unit)
FIG. 5A is a diagram illustrating an example of the configuration of the digital orthogonal demodulation unit. The digital quadrature demodulation unit 433 illustrated in FIG. 4 includes an ADC 511, a quadrature detection unit 512, a training signal generation unit 513, and a signal switching unit 514, for example, as illustrated in FIG. The ADC 511, the quadrature detection unit 512, the training signal generation unit 513, and the signal switching unit 514 operate at the timing of the clock signal output from the quadrature demodulation clock generation unit 431.

  The ADC 511 (Analog / Digital Converter) corresponds to the first digital conversion unit 120 illustrated in FIG. 1. The ADC 511 converts the IF signal output from the radio unit 420 into a digital signal using the clock signal from the orthogonal demodulation clock generation unit 431 as a sampling clock. The ADC 511 outputs the converted digital signal to the quadrature detection unit 512.

  The quadrature detection unit 512 performs quadrature detection of the digital signal output from the ADC 511 (see, for example, FIG. 11). The quadrature detection unit 512 outputs baseband I and Q signals orthogonal to each other obtained by the quadrature detection to the signal switching unit 514.

  The training signal generation unit 513 is a generation unit that generates the same signal (for example, see FIG. 14) as the I signal and the Q signal as the training signal. The training signal generation unit 513 outputs the I signal and the Q signal generated as the training signal to the signal switching unit 514.

  The signal switching unit 514 switches and outputs either the I signal and the Q signal separated by the quadrature detection unit 512 or each training signal generated by the training signal generation unit 513. Specifically, the signal switching unit 514 is one of the I signal and Q signal from the training signal generation unit 513 and the I signal and Q signal from the training signal generation unit 513 under the control of the control unit 440. The signal to be output is switched by selecting.

(Configuration of sampling rate converter)
FIG. 5B is a diagram illustrating an example of the configuration of the sampling rate conversion unit. The sampling rate conversion unit 434 illustrated in FIG. 4 includes DACs 521 and 522 and ADCs 523 and 524, for example, as illustrated in FIG. The DACs 521 and 522 correspond to the analog conversion unit 140 shown in FIG. The ADCs 523 and 524 have a configuration corresponding to the second digital conversion unit 160 illustrated in FIG.

  The DAC 521 (Digital / Analog Converter) converts the I signal output from the digital quadrature demodulation unit 433 into an analog signal based on the clock signal output from the quadrature demodulation clock generation unit 431. The DAC 521 outputs the I signal converted into the analog signal to the ADC 523. The DAC 522 converts the Q signal output from the digital quadrature demodulation unit 433 into an analog signal based on the clock signal output from the quadrature demodulation clock generation unit 431. The DAC 522 outputs the Q signal converted into the analog signal to the ADC 524.

  The ADC 523 converts the analog I signal output from the DAC 521 into a digital signal using the clock signal from the baseband demodulation clock generation unit 432 as a sampling clock. The ADC 523 outputs the I signal converted into the digital signal to the baseband demodulation unit 435. The ADC 524 converts the analog Q signal output from the DAC 522 into a digital signal using the clock signal from the baseband demodulation clock generation unit 432 as a sampling clock. The ADC 524 outputs the Q signal converted into the digital signal to the baseband demodulation unit 435.

(Configuration of baseband demodulator)
FIG. 5C is a diagram illustrating an example of the configuration of the baseband demodulation unit. The baseband demodulation unit 435 illustrated in FIG. 4 includes an IQ mismatch correction unit 531 and a demodulation processing unit 532, for example, as illustrated in FIG. 5-3. The IQ mismatch correction unit 531 and the demodulation processing unit 532 operate at the timing of the clock signal output from the baseband demodulation clock generation unit 432.

  The IQ mismatch correction unit 531 is a compensation unit that compensates for a deviation in characteristics between the I signal and the Q signal separated by the quadrature detection unit 512 and passed through the sampling rate conversion unit 434 by digital processing. Specifically, the IQ mismatch correction unit 531 corrects mismatch between the I signal and the Q signal output from the sampling rate conversion unit 434 under the control of the control unit 440. Correction of mismatch between the I signal and the Q signal by the IQ mismatch correction unit 531 will be described later (see, for example, FIG. 16). The IQ mismatch correction unit 531 outputs the I signal and Q signal whose mismatch has been corrected to the demodulation processing unit 532.

  The demodulation processing unit 532 demodulates the I signal and the Q signal output from the IQ mismatch correction unit 531. In the example shown in FIG. 9, since the I signal and the Q signal are baseband signals of the OFDM modulation scheme, the demodulation processing unit 532 demodulates using a scheme corresponding to the OFDM modulation scheme. The demodulation processing unit 532 outputs a demodulation result.

(Configuration of radio unit)
FIG. 6 is a diagram illustrating an example of the configuration of the wireless unit. 4 includes, for example, a first BPF 601, an LNA 602, an LO 603, a MIX 604, a second BPF 605, and a VGA 606, as shown in FIG.

  The first BPF 601 (Band Pass Filter: band pass filter) is a filter that transmits a frequency component in a specific RF band of the RF signal output from the receiving antenna 410 and attenuates a frequency component other than the specific RF band. . The center frequency and bandwidth of the specific band that passes through the first BPF 601 can be set from the control unit 440. The RF signal that has passed through the first BPF 601 is output to the LNA 602.

  An LNA 602 (Low Noise Amplifier) amplifies the RF signal output from the first BPF 601 with low noise. The LNA 602 outputs the amplified RF signal to the MIX 604. The LO 603 (Local Oscillator) generates a local signal (local oscillation number) and outputs it to the MIX 604. The frequency of the local signal generated by the LO 603 (local frequency) can be set from the control unit 440.

  The MIX 604 (Mixer) mixes (multiplies) the RF signal output from the LNA 602 and the local signal output from the LO 603. Thereby, the RF signal output from the LNA 602 can be converted into an IF signal. The MIX 604 outputs the multiplication result signal to the second BPF 605.

  The second BPF 605 is a filter that transmits a frequency component in a specific IF band of the signal output from the MIX 604 and attenuates a frequency component other than the specific IF band. The center frequency and bandwidth of the specific band that passes through the second BPF 605 can be set from the control unit 440. The IF signal that has passed through the second BPF 605 is output to the VGA 606.

  A VGA 606 (Variable Gain Amplifier) adjusts the amplitude of the IF signal output from the second BPF 605 to a predetermined level suitable for demodulation. The VGA 606 outputs the IF signal whose amplitude is adjusted to the demodulator 430. The amplitude adjusted by the second BPF 605 can be set from the control unit 440.

  Note that the configuration of the wireless unit 420 illustrated in FIG. 6 is an example. For example, in the wireless unit 420 shown in FIG. 6, the RF signal is converted into an IF signal by one time mixing by the MIX 604, but the RF signal is converted into an IF signal by multiple times mixing by the plurality of MIX 604. Also good.

(Another example of the configuration of the orthogonal demodulation unit)
FIG. 7 is a diagram illustrating another example of the configuration of the orthogonal demodulation unit. In FIG. 7, the same parts as those shown in FIG. As illustrated in FIG. 7, the digital orthogonal demodulation unit 433 may include a signal extraction unit 701 and a power normalization unit 702 in addition to the configuration illustrated in FIG.

  The signal extraction unit 701 extracts only the component to be demodulated from the baseband I signal and Q signal output from the quadrature detection unit 512. The signal extraction unit 701 outputs the extracted I signal and Q signal components to the power normalization unit 702. The component extracted by the signal extraction unit 701 can be set from the control unit 440.

  The power normalization unit 702 normalizes the I signal and the Q signal output from the signal extraction unit 701 by adjusting each power to be a predetermined power. The power normalization unit 702 outputs the I signal and Q signal whose power has been normalized to the signal switching unit 514. The predetermined power adjusted by the power normalization unit 702 can be set from the control unit 440.

(Another example of sampling rate converter)
FIG. 8 is a diagram illustrating another example of the sampling rate conversion unit. In FIG. 8, the same parts as those shown in FIG. As illustrated in FIG. 8, the sampling rate conversion unit 434 may include LPFs 801 and 802 in addition to the configuration illustrated in FIG. 5B.

  An LPF 801 (Low Pass Filter) removes a harmonic component generated in the DAC 521 from the analog I signal output from the DAC 521. The LPF 801 outputs the I signal from which the harmonic component has been removed to the ADC 523. The LPF 802 removes harmonic components generated in the DAC 522 from the analog Q signal output from the DAC 522. The LPF 802 outputs a Q signal from which harmonic components have been removed to the ADC 524.

  The cutoff frequency of the LPFs 801 and 802 can be set from the control unit 440. Further, the cutoff frequency of the LPFs 801 and 802 may be a preset fixed cutoff frequency.

(Configuration of demodulation processor)
FIG. 9 is a diagram illustrating an example of the configuration of the demodulation processing unit. In FIG. 9, the same parts as those shown in FIG. The baseband demodulation unit 435 illustrated in FIG. 4 includes, for example, a timing synchronization unit 901, a GI removal unit 902, an equalization unit 903, a determination unit 904, and a frequency deviation detection unit 905, as illustrated in FIG. It is equipped with.

  The timing synchronization unit 901 detects the reception timing of the radio frame based on the I signal and the Q signal output from the IQ mismatch correction unit 531 and synchronizes the demodulation timing with the reception timing. Timing synchronization section 901 outputs the synchronized I signal and Q signal to GI removal section 902 and frequency deviation detection section 905.

  The GI removal unit 902 removes a GI (Guard Interval) included in the I signal and the Q signal output from the timing synchronization unit 901. The GI removal unit 902 outputs the I signal and Q signal from which the GI has been removed to the equalization unit 903. The equalization unit 903 performs equalization processing on the I signal and the Q signal output from the GI removal unit 902. The equalization unit 903 outputs the I signal and Q signal subjected to the equalization process to the determination unit 904. The determination unit 904 determines a value by comparing each of the I signal and the Q signal output from the equalization unit 903 with a threshold value. The determination unit 904 outputs the determination result as a demodulation result.

  Based on the I signal and the Q signal output from the timing synchronization unit 901, the frequency deviation detection unit 905 generates a frequency deviation between the carrier signal received by the receiving apparatus 400 and the local signal in the digital orthogonal demodulation unit 433 ( ) Is detected. The frequency deviation detection unit 905 outputs the detection result of the frequency deviation to the control unit 440.

(Configuration of each clock generator)
FIG. 10 is a diagram illustrating an example of the configuration of each clock generation unit. In FIG. 10, the same parts as those shown in FIG. Each of the orthogonal demodulation clock generation unit 431 and the baseband demodulation clock generation unit 432 illustrated in FIG. 4 can be realized by, for example, the clock generation unit 1000 illustrated in FIG.

  The clock generation unit 1000 includes a frequency setting unit 1001, a frequency correction unit 1002, and an oscillation unit 1003. The frequency setting unit 1001 sets the frequency of the clock signal oscillated by the oscillation unit 1003 under the control of the control unit 440. The frequency correction unit 1002 corrects (finely adjusts) the frequency of the clock signal oscillated by the oscillation unit 1003 set by the frequency setting unit 1001 under the control of the control unit 440.

  The oscillating unit 1003 oscillates a clock signal having a frequency obtained by correcting the frequency set by the frequency correcting unit 1002 using the correction value set by the frequency correcting unit 1002. The oscillation unit 1003 outputs an oscillated clock signal. Note that the frequency setting unit 1001 and the frequency correction unit 1002 may be configured by one setting unit.

(Configuration of quadrature detector)
FIG. 11 is a diagram illustrating an example of the configuration of the quadrature detection unit. In FIG. 11, the same parts as those shown in FIG. The orthogonal detection unit 512 illustrated in FIG. 5A includes, for example, a complex LO generation unit 1101, a table storage unit 1101a, multiplication units 1102 and 1103, and LPFs 1104 and 1105, as illustrated in FIG. Yes. In the table storage unit 1101a, for example, “+1”, “0”, and “−1” are stored as table values.

  The complex LO generation unit 1101 generates local signals supplied to the multiplication units 1102 and 1103. Each local signal generated by the complex LO generation unit 1101 is, for example, a digital complex sine wave (two sine waves shifted by 90 [°]). The complex LO generation unit 1101 generates each local signal by sequentially reading the table values from the table storage unit 1101a at a cycle four times the sampling cycle of the quadrature detection unit 512.

  Thereby, two sine waves orthogonal to each other with high accuracy can be generated with a simple configuration (see, for example, FIGS. 12-1 and 12-2). Note that the sampling period of the complex LO generation unit 1101 is set by the sampling clock from the orthogonal demodulation clock generation unit 431. Complex LO generation section 1101 outputs the generated local signals to multiplication sections 1102 and 1103, respectively. The complex LO generator 1101 can be realized by, for example, an NCO (Numerically Controlled Oscillator).

  Digital IF signals output from the ADC 511 are input to the multipliers 1102 and 1103. For example, the IF signal input to the multipliers 1102 and 1103 can be a folded component that is folded back to the first Nyquist zone in the ADC 511 (for example, the folded component 213 in FIG. 2A).

  Multiplier 1102 multiplies the input IF signal by the local signal output from complex LO generator 1101, and outputs the multiplication result signal to LPF 1104. Multiplier 1103 multiplies the input IF signal by the local signal output from complex LO generator 1101, and outputs the multiplication result signal to LPF 1105.

  The signal output to the LPF 1104 includes a frequency component that is the sum of the frequencies of the IF signal multiplied by the multiplier 1102 and the local signal, and a frequency component that is the difference between the frequencies. The LPF 1104 attenuates the frequency component of the sum of the frequencies in the signal output from the multiplier 1102 and transmits the frequency component of the difference between the frequencies as an I signal. As a result, a baseband I signal can be output.

  The signal output to the LPF 1105 includes a frequency component that is the sum of the frequencies of the IF signal multiplied by the multiplier 1103 and the local signal, and a frequency component that is the difference between the frequencies. The LPF 1105 attenuates the frequency component of the sum of the frequencies in the signal output from the multiplier 1103 and transmits the frequency component of the difference between the frequencies as a Q signal. As a result, a baseband Q signal can be output.

(Local signal generated by the complex LO generator)
FIG. 12A is a graph (part 1) illustrating an example of a local signal generated by the complex LO generation unit. FIG. 12-2 is a graph (part 2) illustrating an example of a local signal generated by the complex LO generation unit. In FIGS. 12-1 and 12-2, the horizontal axis indicates time. The horizontal axes 0, T, 2T, 3T,... Are sampling periods of the complex LO generator 1101. The vertical axis indicates the amplitude of the local signal.

  The table storage unit 1101a illustrated in FIG. 11 stores three values “+1”, “0”, and “−1” as table values. The complex LO generation unit 1101 reads out the table values in the table storage unit 1101a in the order of “+1”, “0”, “−1”, “0”,... And outputs them to the multiplication unit 1102 at each sampling period. A local signal 1210 is generated. The local signal 1210 can be indicated by COS (2πfT).

  Further, the complex LO generation unit 1101 reads the table values in the table storage unit 1101a in the order of “0”, “−1”, “0”, “+1”,... A local signal 1220 to be output is generated. The local signal 1220 can be indicated by -SIN (2πfT). Further, the local signal 1220 has a phase shift of π / 2 with respect to the local signal 1210 (orthogonal).

(Configuration of IQ mismatch correction unit)
FIG. 13 is a diagram illustrating an example of the configuration of the IQ mismatch correction unit. The IQ mismatch correction unit 531 illustrated in FIG. 5C includes an amplitude correction unit 1310, a DC offset correction unit 1320, and a phase correction unit 1330, for example, as illustrated in FIG.

<Amplitude correction unit>
The amplitude correction unit 1310 corrects an amplitude mismatch between the I signal and the Q signal output from the sampling rate conversion unit 434. Specifically, the amplitude correction unit 1310 includes a power detection unit 1311, an amplification unit 1312, a power detection unit 1313, and an amplification unit 1314. The I signal input to the amplitude correction unit 1310 is input to the power detection unit 1311 and the amplification unit 1312. The Q signal input to the amplitude correction unit 1310 is input to the power detection unit 1313 and the amplification unit 1314.

  The power detection unit 1311 detects the power of the input I signal by integrating the I signal. The power detection unit 1311 outputs a gain coefficient indicating the difference between the detected power and the target power W to the amplification unit 1312. The amplifying unit 1312 adjusts the power of the I signal to the target power W by amplifying the input I signal based on the gain coefficient from the power detecting unit 1311. The amplification unit 1312 outputs the amplified I signal to the DC offset correction unit 1320.

  The power detection unit 1313 detects the power of the input Q signal by integrating the Q signal. The power detection unit 1313 outputs a gain coefficient indicating the difference between the detected power and the target power W to the amplification unit 1314. The amplifying unit 1314 adjusts the power of the Q signal to the target power W by amplifying the input Q signal based on the gain coefficient from the power detecting unit 1313. The amplifying unit 1314 outputs the amplified Q signal to the DC offset correcting unit 1320. Thereby, both the amplitudes of the I signal and the Q signal can be set to the target power W.

<DC offset correction unit>
The DC offset correction unit 1320 corrects the mismatch of the DC offset (DC offset) of the I signal and the Q signal output from the amplitude correction unit 1310. Specifically, the DC offset correction unit 1320 includes a DC offset detection unit 1321, a subtraction unit 1322, a DC offset detection unit 1323, and a subtraction unit 1324.

  The I signal input to the DC offset correction unit 1320 is input to the DC offset detection unit 1321 and the subtraction unit 1322. The DC offset detector 1321 detects the DC offset of the input I signal by averaging the I signal. The DC offset detection unit 1321 outputs to the subtraction unit 1322 a DC offset amount at which the integrated value of the detected DC offset becomes zero. The subtractor 1322 adjusts the DC offset of the I signal to zero by subtracting the DC offset amount from the DC offset detector 1321 from the input I signal. Subtraction unit 1322 outputs the subtracted I signal to phase correction unit 1330.

  The Q signal input to the DC offset correction unit 1320 is input to the DC offset detection unit 1323 and the subtraction unit 1324. The DC offset detector 1323 detects the DC offset of the input Q signal by averaging the Q signal. The DC offset detection unit 1323 outputs a DC offset amount at which the detected integrated value of the DC offset becomes zero to the subtraction unit 1324. The subtraction unit 1324 adjusts the DC offset of the Q signal to zero by subtracting the DC offset amount from the DC offset detection unit 1323 from the input Q signal. The subtraction unit 1324 outputs the subtracted Q signal to the phase correction unit 1330. Thereby, both the DC offset of the I signal and the Q signal can be made zero.

<Phase correction unit>
The phase correction unit 1330 corrects a mismatch in phase (timing) of the I signal and the Q signal output from the DC offset correction unit 1320. Specifically, the phase correction unit 1330 includes a switch 1331, an FIR filter 1332, a switch 1333, a subtraction unit 1334, and a coefficient control unit 1335. The I signal output from the DC offset correction unit 1320 is input to the switch 1331. The Q signal output from the DC offset correction unit 1320 is input to the FIR filter 1332 and the coefficient control unit 1335.

  The switch 1331 is connected to the first path R11 connected to the subsequent stage of the IQ mismatch correction unit 531 and the subtraction unit 1334 with the I signal output from the DC offset correction unit 1320 under the control of the control unit 440. Output to one of the second routes R12.

  The FIR filter 1332 is a FIR (Finite Impulse Response) filter that delays the Q signal output from the DC offset correction unit 1320 in accordance with a set filter coefficient. The filter coefficient of the FIR filter 1332 is controlled by the coefficient control unit 1335. The FIR filter 1332 outputs the delayed Q signal to the switch 1333.

  The switch 1333 controls the Q signal output from the FIR filter 1332 by the control from the control unit 440, the third path R 21 connected to the subsequent stage of the IQ mismatch correction unit 531, and the fourth signal connected to the subtraction unit 1334. To one of the routes R22.

  The subtracting unit 1334 subtracts the Q signal output from the switch 1333 from the I signal output from the switch 1331. The subtraction unit 1334 outputs a signal of the subtraction result to the coefficient control unit 1335. Coefficient control unit 1335 controls the filter coefficient of FIR filter 1332 based on the signal output from subtraction unit 1334.

  For example, the coefficient control unit 1335 corrects the phase mismatch of the I signal and the Q signal by correcting the phase of the Q signal using an LMS (Least Mean Square) algorithm with the I signal as a reference. For example, the Q signal output from the DC offset correction unit 1320 at time m is assumed to be X (m).

  Further, the filter coefficient of the FIR filter 1332 controlled by the coefficient control unit 1335 at time m is assumed to be W (m). Further, a signal output from the switch 1333 to the subtracting unit 1334 at time m is Y (m). Y (m) can be represented by, for example, Y (m) = Σ {W (k) * X (m−k)}.

  Further, the I signal output from the switch 1331 to the subtracting unit 1334 at time m is R (m). Further, a signal output from the subtraction unit 1334 to the coefficient control unit 1335 at time m is assumed to be E (m). E (m) is R (m) −Y (m), and is a signal indicating the difference between the I signal and the Q signal at time m.

  For example, the coefficient control unit 1335 sets the filter coefficient W (m + 1) to be set in the FIR filter 1332 at time (m + 1), for example, W (m + 1) = W (m) + μ * E (m) * conj (X (m) ). μ is a step coefficient. Thereby, the phase mismatch of the I signal and the Q signal can be corrected.

  First, the control unit 440 controls the signal switching unit 514 (see, for example, FIGS. 5-1 and 11) of the digital quadrature demodulation unit 433 so as to output a training signal. In the training signal, the control unit 440 performs amplitude correction, DC offset correction, and so on. Perform phase correction. When the amplitude correction, the DC offset correction, and the phase correction in the training signal are completed, the control unit 440 controls each gain coefficient of the amplitude correction unit 1310, each DC offset amount of the DC offset correction unit 1320, and filter coefficient W of the phase correction unit 1330. Fix (m).

  Then, the control unit 440 controls the signal switching unit 514 of the digital orthogonal demodulation unit 433 so as to output the I signal and the Q signal included in the received signal. Thereby, the mismatch of the I signal and the Q signal to be demodulated can be corrected using each parameter of each gain coefficient, each DC offset amount, and filter coefficient W (m) set by the training signal.

(Training signal)
FIG. 14 is a graph illustrating an example of a training signal generated by the training signal generation unit. In FIG. 14, the horizontal axis represents time. The vertical axis represents the amplitude of the training signal. The training signal 1400 is a training signal generated by the training signal generation unit 513. Like the training signal 1400, the training signal generator 513 generates, for example, a sinusoidal training signal.

  The training signal 1400 has an amplitude between +1 and -1. The phase of the training signal 1400 is 0 [°] at time zero. The DC component (center of amplitude) of the training signal 1400 is zero.

  FIG. 15 is a graph showing an example of IQ mismatch occurring in the training signal. In FIG. 15, the horizontal axis represents time. The vertical axis represents the amplitude of the training signal. The training signal 1500 is a training signal that passes through the sampling rate conversion unit 434 and is input to the IQ mismatch correction unit 531.

  When the training signal 1400 (FIG. 14) generated by the training signal generation unit 513 passes through the analog circuit of the sampling rate conversion unit 434, the amplitude and phase fluctuate or a DC offset occurs. Therefore, the training signal input to the IQ mismatch correction unit 531 is, for example, a training signal 1500.

  Specifically, the amplitude of the training signal 1500 shown in FIG. 15 is an amplitude between + α and −β, and is smaller than the training signal 1400 that is an amplitude between +1 and −1. Further, a positive DC offset occurs in the training signal 1500. Further, the phase of the training signal 1500 is a phase that is slower than the phase that is 0 [°] at time zero.

  On the other hand, the IQ mismatch correction unit 531 performs amplitude correction by the amplitude correction unit 1310, DC offset correction by the DC offset correction unit 1320, and phase correction by the phase correction unit 1330, so that the I signal and the Q signal are Inconsistencies between them are corrected.

(IQ mismatch correction processing)
FIG. 16 is a sequence diagram illustrating a specific example of IQ mismatch correction processing. The receiving apparatus 400 executes, for example, the following steps as the IQ mismatch correction process. First, the control unit 440 instructs the signal switching unit 514 to start training signal output (step S1601). Further, the control unit 440 switches the switch 1331 to the second path R12 and switches the switch 1333 to the fourth path R22 (step S1602). As a result, the I signal and the Q signal are output to the subtraction unit 1334.

  Next, the signal switching unit 514 outputs the training signal from the training signal generation unit 513 to the IQ mismatch correction unit 531 according to the instruction in step S1601 (step S1603). Next, the control unit 440 instructs the IQ mismatch correction unit 531 to correct the amplitude of the I signal and the Q signal (step S1604).

  Next, the amplitude correction unit 1310 of the IQ mismatch correction unit 531 performs gain correction of the I signal and the Q signal according to the instruction in step S1604 (step S1605). As a result, the amplitude mismatch between the I signal and the Q signal is corrected. The amplitude correction unit 1310 fixes the gain coefficients of the I signal and the Q signal after correcting the amplitude mismatch between the I signal and the Q signal. Next, the IQ mismatch correction unit 531 notifies the control unit 440 of the completion of gain correction in step S1605 (step S1606).

  Next, the control unit 440 instructs the IQ mismatch correction unit 531 to perform DC offset correction of the I signal and the Q signal (step S1607). Next, the DC offset correction unit 1320 of the IQ mismatch correction unit 531 performs DC offset correction of the I signal and the Q signal according to the instruction in step S1607 (step S1608). Thereby, the mismatch of the DC offset correction between the I signal and the Q signal is corrected. The DC offset correction unit 1320 corrects the DC offset mismatch between the I signal and the Q signal, and then fixes each DC offset amount of the I signal and the Q signal. Next, the IQ mismatch correction unit 531 notifies the control unit 440 of the completion of the DC offset correction in step S1608 (step S1609).

  Next, the control unit 440 instructs the IQ mismatch correction unit 531 to perform timing correction (step S1610). Next, the phase correction unit 1330 of the IQ mismatch correction unit 531 corrects the timing of the Q signal in accordance with the instruction in step S1610 (step S1611). Thereby, the phase mismatch between the I signal and the Q signal is corrected. The phase correction unit 1330 fixes the filter coefficient W after correcting the DC phase mismatch between the I signal and the Q signal. Next, the IQ mismatch correction unit 531 notifies the control unit 440 of completion of the timing correction in step S1611 (step S1612).

  Next, the control unit 440 instructs the signal switching unit 514 to end the training signal output (step S1613). As a result, the signal switching unit 514 ends the output of the training signal from the training signal generation unit 513 and starts outputting the I signal and the Q signal to be demodulated. Next, the control unit 440 switches the switch 1331 to the first path R11 and switches the switch 1333 to the third path R21 (step S1614). As a result, the I signal and the Q signal to be demodulated are output to the demodulation processing unit 532 with the amplitude correction, the DC offset correction, and the timing correction performed.

  As described above, the control unit 440 first controls the signal switching unit 514 so as to output each training signal, and sets the IQ mismatch correction unit 531 (compensation unit) as a parameter for compensating for the deviation in characteristics between the training signals. ). The parameters include, for example, a gain coefficient, a DC offset, and a filter coefficient. Thereafter, the control unit 440 controls the signal switching unit 514 to output the I signal and the Q signal to be demodulated while maintaining the parameters in the IQ mismatch correction unit 531. As a result, it is possible to derive a parameter for compensating the characteristic deviation caused by the analog circuit of the sampling rate conversion unit 434, and to accurately compensate the characteristic deviation between the I signal and the Q signal to be demodulated.

  In addition, when the control unit 440 causes the IQ mismatch correction unit 531 to set parameters, first, parameters (gain coefficient and DC offset) for compensating for deviations in amplitude and DC offset characteristics between training signals are set to IQ. The mismatch correction unit 531 is set. Thereafter, the control unit 440 causes the IQ mismatch correction unit 531 to set a parameter (filter coefficient) that compensates for a phase shift between the training signals.

  Further, the control unit 440 sets, for example, the filter coefficient of the FIR filter 1332 that allows the Q signal to pass so as to match the phase of the Q signal with the phase of the I signal. As a result, the IQ mismatch correction unit 531 can set a filter coefficient that compensates for a phase shift between the training signals. This further corrects the amplitude and DC offset of the Q signal with reference to the I signal.

(Initial setting process)
FIG. 17 is a sequence diagram illustrating a specific example of the initial setting process. The receiving apparatus 400 executes, for example, the following steps as the initial setting process. In the example shown below, it is assumed that the carrier frequency of the RF signal received by the receiving apparatus 400 is 3 [GHz]. The modulation method of the RF signal is QPSK (Quadrature Phase Shift Keying), and the roll-off rate is 0.3.

  First, the control unit 440 sets the center frequency and bandwidth of the first BPF 601 in the radio unit 420 (step S1701). In step S1701, for example, the center frequency of the first BPF 601 is set to 3 [GHz], and the bandwidth of the first BPF 601 is set to 20 [MHz].

  Next, the control unit 440 sets the frequency of the local signal generated by the LO 603 in the wireless unit 420 (step S1702). In step S1702, for example, the frequency of the local signal is set to 2710 [MHz]. In this case, the frequency of the IF signal output from the MIX 604 is 90 [MHz].

  Next, the control unit 440 sets the bandwidth of the second BPF 605 in the radio unit 420 (step S1703). In step S1703, for example, the bandwidth of the second BPF 605 is set to 20 [MHz]. Next, the control unit 440 sets an initial value (predetermined level) of the VGA 606 in the wireless unit 420 (step S1704). In step S1704, for example, the initial value of VGA 606 is set to full gain.

  Next, the control unit 440 sets the frequency of the orthogonal demodulation clock generated by the orthogonal demodulation clock generation unit 431 (step S1705). In step S1705, for example, the frequency of the orthogonal demodulation clock is set to 120 [MHz]. Thereby, when the frequency of the IF signal is 90 [MHz] and the sampling frequency is 120 [MHz], the frequency of the IF signal becomes the center of the Nyquist zone (n = 2).

  Next, the quadrature demodulation clock generation unit 431 starts supplying the clock signal to the digital quadrature demodulation unit 433 and the sampling rate conversion unit 434 (step S1706). Next, the control unit 440 sets the frequency of the baseband demodulation clock generated by the baseband demodulation clock generation unit 432 (step S1707). In step S1707, for example, the frequency of the baseband demodulation clock is set to 64 [MHz]. Next, the baseband demodulation clock generation unit 432 starts supplying the clock signal to the sampling rate conversion unit 434 and the baseband demodulation unit 435 (step S1708).

  Next, the control unit 440 sets a bandwidth to be extracted in the signal extraction unit 701 of the digital orthogonal demodulation unit 433 (step S1709). In step S1709, for example, the bandwidth is set to 20 [MHz]. Next, the control unit 440 sets demodulation parameters in the baseband demodulation unit 435 (step S1710). In step S1710, for example, QPSK is set as the modulation scheme, the roll-off rate is set to 0.3, and the symbol rate (modulation speed) is set to 16 [MHz]. In step S1710, the oversampling sampling rate is set to four times the symbol rate (64 [MHz]).

(Operation during continuous reception in the receiver)
FIG. 18 is a flowchart illustrating an example of an operation during continuous reception in the reception device. The reception device 400 executes the following steps by the control unit 440, for example, when performing continuous reception that is continuously performed during operation. First, the receiving apparatus 400 executes the initial setting process shown in FIG. 17 (step S1801). Next, the receiving apparatus 400 executes the IQ mismatch correction process shown in FIG. 16 (step S1802).

  Next, the receiving apparatus 400 determines whether or not there is an external reception instruction (step S1803). The reception instruction is input to the reception device 400 by, for example, a user of the reception device 400 or a management device that manages the reception device 400. If there is no reception instruction (step S1803: No), the receiving apparatus 400 returns to step S1802 and executes IQ mismatch correction processing. If there is a reception instruction (step S1803: Yes), the receiving apparatus 400 performs a reception process (step S1804). The reception process is, for example, a demodulation process in which the demodulation signal is demodulated by the demodulation processing unit 532.

  Next, the receiving apparatus 400 determines whether or not there is an external reception instruction (step S1805). If there is still a reception instruction (step S1805: Yes), the reception apparatus 400 returns to step S1804 and performs reception processing. If there is no reception instruction (step S1805: No), the receiving apparatus 400 determines whether or not the demodulation specifications of the demodulator 430 have been changed (step S1806).

  If the demodulation specifications have not been changed in step S1806 (step S1806: No), the receiving apparatus 400 returns to step S1802 and executes IQ mismatch correction processing. If the demodulation specifications have been changed (step S1806: YES), the receiving apparatus 400 returns to step S1801 and starts over from the initial setting process.

  As illustrated in FIG. 18, the receiving apparatus 400 performs IQ mismatch correction processing after the initial setting by the control unit 440 until a reception instruction is issued, and prepares for reception processing. Then, when there is a reception instruction, the reception apparatus 400 ends the IQ mismatch correction process and starts the reception process. When there is no reception instruction, receiving apparatus 400 restarts from the initial setting process when there is a change in the demodulation specifications, and restarts from the IQ mismatch correction process when there is no change in the demodulation specifications.

(Operation when receiving TDD in receiving apparatus)
FIG. 19 is a flowchart illustrating an example of an operation at the time of TDD reception in the reception device. For example, the control unit 440 performs the following steps when the reception device 400 performs TDD (Time Division Duplex) reception that alternately performs transmission and reception. Steps S1901 to S1903 shown in FIG. 19 are the same as steps S1801 to S1803 shown in FIG.

  In step S1903, when there is a reception instruction (step S1903: Yes), the receiving apparatus 400 determines whether or not the current time is the reception timing (step S1904). If it is the reception timing (step S1904: Yes), the reception apparatus 400 performs reception processing (step S1905), and proceeds to step S1907.

  In step S1904, when the current time is not the reception timing but the transmission timing (step S1904: No), the receiving apparatus 400 executes the IQ mismatch correction process shown in FIG. 16 (step S1906), and step S1907. Migrate to Steps S1907 and S1908 are the same as steps S1805 and S1806 shown in FIG.

  As shown in FIG. 19, when TDD reception is performed, the receiving apparatus 400 performs reception processing at the reception timing after receiving the reception instruction, and performs IQ mismatch correction processing at the transmission timing.

  As described above, according to the demodulator 100 according to the first embodiment, the digital quadrature detection and the baseband demodulation are performed by re-sampling at an arbitrary rate between the digital quadrature detection and the baseband demodulation. It becomes possible to carry out at an appropriate rate.

  Specifically, in digital quadrature detection, the sampling rate is set so that the IF signal band does not cross the Nyquist zone, so that the aliasing component of the IF signal does not overlap the IF signal. Demodulation performance can be improved.

  In baseband demodulation, for example, the demodulation performance in baseband demodulation can be improved by setting the sampling rate (oversampling) so as to be an integral multiple of the symbol rate of the IF signal.

  That is, since the sampling clock used for the baseband demodulation process can be determined by the demodulation parameters (for example, symbol rate) without considering the relationship with the frequency of the IF signal, any symbol rate is supported. It becomes possible.

  Further, by performing quadrature detection by digital processing, it is possible to suppress the occurrence of mismatch between the I signal and the Q signal in quadrature detection. Further, the IQ mismatch correction unit 531 can compensate for mismatch between the I signal and the Q signal generated in the analog circuit of the sampling rate conversion unit 434 by digital processing. Therefore, for example, the mismatch between the I signal and the Q signal can be compensated more accurately than the baseband signal sampling method that compensates for the mismatch between the I signal and the Q signal by analog processing.

(Embodiment 2)
(Configuration of receiving apparatus according to the second embodiment)
FIG. 20 is a diagram of an example of a configuration of the receiving apparatus according to the second embodiment. 20, parts that are the same as the parts shown in FIG. 4 are given the same reference numerals, and descriptions thereof will be omitted. As illustrated in FIG. 20, the control unit 440 acquires the detection result of the frequency deviation between the carrier signal and the local signal from the frequency deviation detection unit 905 of the baseband demodulation unit 435. The detection result of the frequency deviation is information indicating whether the local frequency in the receiving apparatus 400 is higher, lower, or equal to the carrier frequency of the received signal, for example.

  The control unit 440 adjusts the frequency of the clock signal generated by the orthogonal demodulation clock generation unit 431 in accordance with the acquired frequency deviation detection result. As a result, the sampling rate (operating frequency) in the digital orthogonal demodulator 433 changes, and the frequency of the local signal generated by the complex LO generator 1101 changes. For this reason, AFC (Automatic Frequency Control: automatic frequency control) is realizable.

(AFC processing in the receiving apparatus according to the second embodiment)
FIG. 21 is a flowchart of an example of AFC processing in the receiving apparatus according to the second embodiment. The control unit 440 according to the second embodiment executes, for example, the following steps as the AFC process. First, the control unit 440 obtains a frequency deviation detection result from the frequency deviation detection unit 905 (step S2101).

  Next, the control unit 440 determines whether or not the local frequency is higher than the carrier frequency based on the detection result acquired in step S2101 (step S2102). When the local frequency is higher than the carrier frequency (step S2102: Yes), the control unit 440 decreases the clock frequency of the orthogonal demodulation clock generation unit 431 (step S2103) and returns to step S2101. As a result, the frequency (local frequency) of the local signal generated by the complex LO generation unit 1101 decreases.

  In step S2102, when the local frequency is not higher than the carrier frequency (step S2102: No), the control unit 440 determines whether the local frequency is lower than the carrier frequency (step S2104). When the local frequency is lower than the carrier frequency (step S2104: Yes), the control unit 440 increases the clock frequency of the orthogonal demodulation clock generation unit 431 (step S2105) and returns to step S2101. As a result, the frequency (local frequency) of the local signal generated by the complex LO generation unit 1101 increases.

  In step S2104, when the local frequency is not lower than the carrier frequency (step S2104: No), the control unit 440 returns to step S2101. Thereby, when the local frequency and the carrier frequency match, the local frequency can be maintained.

  As described above, the reception device 400 changes the local signal generated by the complex LO generation unit 1101 by controlling the clock frequency of the orthogonal demodulation clock generation unit 431 based on the detection result of the frequency deviation, thereby changing the AFC. Can be realized.

  FIG. 22 is a sequence diagram illustrating a specific example of the AFC process in the receiving apparatus according to the second embodiment. The receiving apparatus 400 according to the second embodiment repeatedly executes, for example, the following steps as the AFC process. First, the baseband demodulator 435 detects the frequency deviation between the carrier signal and the local signal by the frequency deviation detector 905 (step S2201). Next, the baseband demodulation unit 435 notifies the control unit 440 of the detection result of the frequency deviation in step S2201 (step S2202).

  Next, the control unit 440 instructs the orthogonal demodulation clock generation unit 431 to finely adjust the clock frequency based on the detection result of the frequency deviation notified in step S2202 (step S2203). Next, the quadrature demodulation clock generation unit 431 finely adjusts the clock frequency output to the digital quadrature demodulation unit 433 and the sampling rate conversion unit 434 in accordance with the instruction in step S2203 (step S2204), and the series of AFC processing ends. To do.

  In this manner, the quadrature detection unit 512 performs quadrature detection using a local signal having a frequency that is an integer multiple of the frequency of the first sampling clock generated based on the first sampling clock output from the quadrature demodulation clock generation unit 431. Do. Then, according to the demodulator 100 and the receiving apparatus 400 according to the second embodiment, the control unit 440 performs the first sampling based on the detection result of the deviation between the carrier frequency of the analog signal to be demodulated and the frequency of the local signal. Adjust the clock frequency.

  Specifically, the control unit 440 adjusts the frequency of the first sampling clock so that the deviation between the carrier frequency of the analog signal to be demodulated and the frequency of the local signal becomes small. By adjusting the frequency of the first sampling clock, the frequency of the local signal can be automatically adjusted without using an NCO having a large circuit scale. For this reason, the AFC function can be realized while suppressing an increase in circuit scale.

  In demodulator 100 and receiving apparatus 400, the first sampling clock and the second sampling clock can be adjusted independently. Therefore, even if the frequency of the first sampling clock is adjusted for the AFC function, it does not affect the baseband demodulation using the second sampling clock, so the AFC function is realized while avoiding deterioration of the performance of the baseband demodulation. can do.

(Embodiment 3)
FIG. 23 is a diagram of an example of a configuration of the receiving apparatus according to the third embodiment. In FIG. 23, the same parts as those shown in FIG. The timing synchronization unit 901 (see, for example, FIG. 9) of the baseband demodulation unit 435 performs a timing shift of the operation of the baseband demodulation unit 435 with respect to the carrier signal based on the I signal and the Q signal output from the IQ mismatch correction unit 531. Is detected and the detection result is output.

  As illustrated in FIG. 23, the control unit 440 acquires the detection result of the timing shift of the operation of the baseband demodulation unit 435 with respect to the carrier signal from the timing synchronization unit 901 of the baseband demodulation unit 435. Then, the control unit 440 adjusts the frequency of the clock signal generated by the baseband demodulation clock generation unit 432 according to the acquired timing shift detection result. As a result, the sampling clock in the baseband demodulator 435 changes. For this reason, the function of timing synchronization (frequency synchronization) can be realized.

  In the case of the conventional IF sampling method, if the clock frequency is finely adjusted for timing synchronization processing, the carrier frequency (NCO oscillation frequency) for AFC is also changed, so the clock frequency cannot be finely adjusted. It was. On the other hand, in the timing synchronization processing of the demodulator 100 and the receiving apparatus 400, the clocks of the quadrature detection unit 512 and the baseband demodulation unit 435 are separate systems, and can be controlled individually. For this reason, timing synchronization processing by fine adjustment of the clock frequency is possible.

(Timing synchronization processing in the receiving apparatus according to the third embodiment)
FIG. 24 is a flowchart of an example of timing synchronization processing in the receiving apparatus according to the third embodiment. The control unit 440 according to the second embodiment executes, for example, the following steps as the timing synchronization process. First, the control unit 440 acquires a timing shift detection result from the timing synchronization unit 901 (step S2401).

  Next, the control unit 440 determines whether or not the operation timing of the baseband demodulation unit 435 is earlier than the received signal based on the detection result acquired in step S2401 (step S2402). When the operation timing is earlier than the received signal (step S2402: Yes), the control unit 440 decreases the clock frequency of the baseband demodulation clock generation unit 432 (step S2403), and the process returns to step S2401. Thereby, the sampling rate (operating frequency) of the baseband demodulator 435 decreases.

  In step S2402, when the operation timing is not earlier than the received signal (step S2402: No), the control unit 440 determines whether the operation timing is later than the received signal (the phase is delayed) (step S2402). S2404). If the operation timing is later than the received signal (step S2404: YES), the control unit 440 increases the clock frequency of the baseband demodulation clock generation unit 432 (step S2405), and the process returns to step S2401. Thereby, the sampling rate (operating frequency) of the baseband demodulator 435 increases.

  In step S2404, when the operation timing is not later than the received signal (step S2404: No), the control unit 440 returns to step S2401. As a result, when the operation timing of the baseband demodulation unit 435 matches the received signal, the operation timing of the baseband demodulation unit 435 can be maintained.

  As described above, the reception device 400 controls the clock frequency of the baseband demodulation clock generation unit 432 based on the detection result of the operation timing deviation, thereby changing the operation timing in the baseband demodulation and performing the timing synchronization processing. Can be realized.

  FIG. 25 is a sequence diagram of a specific example of timing synchronization processing in the receiving apparatus according to the third embodiment. The receiving apparatus 400 according to the third embodiment repeatedly executes, for example, the following steps as the AFC process. First, the baseband demodulator 435 detects a timing shift of the operation of the baseband demodulator 435 with respect to the carrier signal by the timing synchronizer 901 (step S2501). Next, the baseband demodulating unit 435 notifies the control unit 440 of the timing shift detection result in step S2501 (step S2502).

  Next, the control unit 440 instructs the baseband demodulation clock generation unit 432 to finely adjust the clock frequency based on the timing shift detection result notified in step S2502 (step S2503). Next, the baseband demodulation clock generation unit 432 finely adjusts the clock frequency of the sampling rate conversion unit 434 and the baseband demodulation unit 435 according to the instruction in step S2503 (step S2504), and ends a series of timing synchronization processing. To do.

  As described above, the baseband demodulation unit 435 performs baseband demodulation at the frequency of the second sampling clock output from the baseband demodulation clock generation unit 432. Then, according to the demodulator 100 and the receiving device 400 according to the third embodiment, the control unit 440 performs the second operation based on the detection result of the deviation between the carrier frequency of the analog signal to be demodulated and the frequency of the baseband demodulation. Adjust the sampling clock frequency.

  Specifically, the control unit 440 adjusts the frequency of the second sampling clock so that the difference between the carrier frequency of the analog signal to be demodulated and the frequency of the baseband demodulation becomes small. By adjusting the frequency of the second sampling clock, the baseband demodulation frequency of the baseband demodulation unit 435 can be automatically adjusted without performing complicated processing. Therefore, the timing synchronization function can be realized while suppressing an increase in circuit scale.

  In demodulator 100 and receiving apparatus 400, the first sampling clock and the second sampling clock can be adjusted independently. Therefore, even if the frequency of the second sampling clock is adjusted for the timing synchronization function, it does not affect the quadrature detection using the first sampling clock. Therefore, the timing synchronization function is realized while suppressing the deterioration of the demodulation performance due to the quadrature detection. can do.

  As described above, according to the demodulator and the demodulation method, the demodulation performance can be improved.

  In each of the above-described embodiments, the configuration of receiving apparatus 400 that receives an OFDM modulation scheme signal has been described. However, the modulation scheme supported by receiving apparatus 400 is not limited to the OFDM modulation scheme. For example, the receiving apparatus 400 may be configured to receive a single carrier modulation signal. In this case, for example, the IQ mismatch correction unit 531, the GI removal unit 902, the equalization unit 903, and the like in the baseband demodulation unit 435 may be omitted.

  The following additional notes are disclosed with respect to the above-described embodiments.

(Supplementary note 1) a first adjustment unit for adjusting the frequency of the first sampling clock;
A first digital conversion unit that samples an analog signal to be demodulated by a first sampling clock whose frequency is adjusted by the first adjustment unit and converts the sampled signal into a digital signal;
A quadrature detection unit that performs quadrature detection of the digital signal converted by the first digital conversion unit;
An analog conversion unit that converts a digital signal obtained by the quadrature detection of the quadrature detection unit into an analog signal;
A second adjustment unit for adjusting a frequency of a second sampling clock different from the first sampling clock;
A second digital conversion unit that samples the analog signal converted by the analog conversion unit with a second sampling clock whose frequency is adjusted by the second adjustment unit and converts the sampled signal into a digital signal;
A baseband demodulator for baseband demodulating the digital signal converted by the second digital converter;
A demodulator.

(Supplementary Note 2) The quadrature detection unit separates signals orthogonal to each other included in the digital signal converted by the first digital conversion unit by the quadrature detection,
The baseband demodulator includes a compensation unit that is separated by the quadrature detection unit and compensates for deviation of characteristics generated between the signals that have passed through the analog conversion unit and the second digital conversion unit by digital processing, 2. The demodulator according to appendix 1, wherein each signal whose compensation for the characteristic is compensated by the compensation unit is baseband demodulated.

(Supplementary Note 3) a generation unit that generates a sine wave as a training signal;
A signal switching unit that switches between each signal separated by the quadrature detection unit and each training signal generated by the generation unit and outputs the signal to the analog conversion unit;
The signal switching unit is controlled so as to output each training signal, and after the parameter for compensating the characteristic deviation between the training signals is set in the compensation unit, the parameter is maintained in the compensation unit. A control unit for controlling the signal switching unit to output each signal,
The demodulator according to appendix 2, characterized by comprising:

(Appendix 4) The characteristic deviation includes a deviation in at least one of an amplitude and a direct current offset, and a phase deviation.
The control unit compensates for a phase shift between the training signals after causing the compensation unit to set a parameter that compensates for a shift in at least one of amplitude and DC offset between the training signals. 4. The demodulator according to appendix 3, wherein a parameter is set in the compensation unit.

(Supplementary Note 5) The compensator passes the other training signal so that the phase of one of the training signals matches the phase of the other training signal of the training signals. The demodulator according to appendix 4, wherein coefficients of an FIR (Finite Impulse Response) filter are set.

(Supplementary Note 6) The quadrature detection unit performs the quadrature detection using a local signal having a frequency that is 1 / integer of the frequency of the first sampling clock whose frequency is adjusted by the first adjustment unit,
The first adjustment unit adjusts the frequency of the first sampling clock based on a detection result of a deviation between a carrier frequency of the analog signal to be demodulated and a frequency of the local signal. The demodulator according to any one of 5.

(Supplementary note 7) The baseband demodulation unit performs the baseband demodulation at a frequency of a second sampling clock whose frequency is adjusted by the second adjustment unit,
The second adjustment unit adjusts the frequency of the second sampling clock based on a detection result of a deviation between a carrier frequency of the analog signal to be demodulated and a frequency of the baseband demodulation. The demodulator according to any one of -6.

(Appendix 8) Adjust the frequency of the first sampling clock,
The first analog signal to be demodulated is sampled by the first sampling clock whose frequency is adjusted and converted into a first digital signal,
Performing quadrature detection of the converted first digital signal;
Converting the second digital signal obtained by the quadrature detection into a second analog signal;
Adjusting a frequency of a second sampling clock different from the first sampling clock;
The converted second analog signal is sampled by the second sampling clock whose frequency is adjusted and converted into a third digital signal,
A demodulating method comprising baseband demodulating the converted third digital signal.

(Supplementary note 9) an antenna for receiving a radio signal;
A frequency converter that converts an analog signal received by the antenna into a frequency between a frequency of the radio signal and a baseband frequency;
A first adjustment unit for adjusting the frequency of the first sampling clock;
A first digital converter that samples the analog signal whose frequency has been converted by the frequency converter by a first sampling clock whose frequency has been adjusted by the first adjuster and converts the analog signal into a digital signal;
A quadrature detection unit that performs quadrature detection of the digital signal converted by the first digital conversion unit;
An analog conversion unit that converts a digital signal obtained by the quadrature detection of the quadrature detection unit into an analog signal;
A second adjustment unit for adjusting a frequency of a second sampling clock different from the first sampling clock;
A second digital conversion unit that samples the analog signal converted by the analog conversion unit with a second sampling clock whose frequency is adjusted by the second adjustment unit and converts the sampled signal into a digital signal;
A baseband demodulator for baseband demodulating the digital signal converted by the second digital converter;
A receiving apparatus comprising:

211 IF signal 212, 213, 221 Folding component 321 Filter characteristic 410 Receiving antenna 1210, 1220 Local signal 1331, 1333 Switch R11 1st route R12 2nd route R21 3rd route R22 4th route 1400, 1500 Training signal

Claims (6)

The analog signal demodulation target, a first digital converter which converts the digital signal sampled by the first sampling clock,
A quadrature detection unit that performs quadrature detection of the digital signal converted by the first digital conversion unit;
An analog conversion unit that converts a digital signal obtained by the quadrature detection of the quadrature detection unit into an analog signal ;
The analog signal converted by the front SL-analog converter, a second digital converter which converts the digital signal is sampled by a different second sampling clock and the first sampling clock,
A baseband demodulator for baseband demodulating the digital signal converted by the second digital converter;
A demodulator. The orthogonal detection unit separates signals orthogonal to each other included in the digital signal converted by the first digital conversion unit by the orthogonal detection,
The baseband demodulator includes a compensation unit that is separated by the quadrature detection unit and compensates for deviation of characteristics generated between the signals that have passed through the analog conversion unit and the second digital conversion unit by digital processing, 2. The demodulator according to claim 1, wherein each signal whose deviation in characteristics is compensated by the compensation unit is baseband demodulated. A generator for generating a sine wave as a training signal;
A signal switching unit that switches between each signal separated by the quadrature detection unit and each training signal generated by the generation unit and outputs the signal to the analog conversion unit;
The signal switching unit is controlled so as to output each training signal, and after the parameter for compensating the characteristic deviation between the training signals is set in the compensation unit, the parameter is maintained in the compensation unit. A control unit for controlling the signal switching unit to output each signal,
The demodulator according to claim 2, comprising: A first adjustment unit for adjusting a frequency of the first sampling clock;
A second adjustment unit for adjusting the frequency of the second sampling clock;
With
The first digital conversion unit samples the analog signal to be demodulated by the first sampling clock whose frequency is adjusted by the first adjustment unit and converts it into a digital signal,
The second digital conversion unit samples the analog signal converted by the analog conversion unit using the second sampling clock whose frequency is adjusted by the second adjustment unit, and converts the sampled signal into a digital signal.
The quadrature detection unit performs the quadrature detection using a local signal having a frequency that is 1 / integer of the frequency of the first sampling clock whose frequency is adjusted by the first adjustment unit,
The first adjustment unit adjusts the frequency of the first sampling clock based on a detection result of a deviation between a carrier frequency of the analog signal to be demodulated and a frequency of the local signal. The demodulator according to any one of? The baseband demodulation unit performs the baseband demodulation at a frequency of a second sampling clock whose frequency is adjusted by the second adjustment unit;
The second adjustment unit, claims on the basis of the deviation of the detection result of the frequency of the carrier frequency the baseband demodulation of demodulated analog signal, and adjusts the frequency of the second sampling clock 5. The demodulator according to 4 . A first analog signal demodulation target, into a first digital signal sampled by a first sampling clock,
Performing quadrature detection of the converted first digital signal;
Converting the second digital signal obtained by the quadrature detection into a second analog signal;
The converted second analog signal is sampled by a second sampling clock different from the first sampling clock and converted into a third digital signal,
A demodulating method comprising baseband demodulating the converted third digital signal.

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