JP5791326B2 - Multilayer integrated circuit device - Google Patents

Description

  The present invention relates to a stacked integrated circuit device, for example, a layout of coils for stacking integrated circuit devices such as semiconductor chips or electronic circuit boards in multiple layers and performing wireless data communication between the integrated circuit devices by inductive coupling. Is.

  In recent years, a large-capacity stacked semiconductor memory device that can be controlled from the outside in the same manner as one semiconductor memory by stacking a plurality of semiconductor memories has been developed. For example, in Solid State Drive (SSD) using a nonvolatile memory instead of a magnetic hard disk, the storage capacity can be increased by stacking a plurality of the same flash memory chips.

  In such a stacked semiconductor device, connection between chips and power supply are performed using wire wiring. However, such wire wiring becomes difficult as the density of semiconductor devices increases.

  In view of this, the present inventor is formed by wiring of a semiconductor integrated circuit chip or an electronic circuit board as a technique for wirelessly connecting between multiple stacked chips or stacked printed wiring boards in such a stacked device. It has been proposed to perform communication by inductive coupling between chips and substrates stacked and mounted via a coil (see, for example, Patent Document 1 to Patent Document 12, Non-Patent Document 1 to Non-Patent Document 4).

  For example, according to Patent Document 1, wireless data communication can be performed using inductive coupling of a coil pair between stacked chips (substrates). The coil is formed by wiring on the chip, and is a rectangular coil having a size about twice the communication distance. Further, according to Patent Document 3, a plurality of communication channels can be configured in parallel to perform high-speed communication by arranging coils in a matrix in a direction along a wiring layer on an orthogonal chip (substrate).

  According to Patent Document 5, the same chip (substrate) is stacked and mounted, wireless communication is performed between the chips (substrate), and power supply and the like can be performed by wire bonding. Further, according to Patent Document 8, a rectangular coil composed of coil elements along the wiring layer on an orthogonal chip (substrate) can be used for inductively coupled data communication.

  According to Patent Document 9, in an electronic circuit in which chips (substrates) are stacked and mounted, data can be transferred at high speed to a chip farther than the coil dimensions by inductive coupling communication. Further, according to Patent Document 12, the wiring of the logic circuit can traverse a rectangular coil formed by coil elements along the wiring layer on an orthogonal chip (substrate), and inductive coupling data communication can be performed without bit errors. can do.

  Further, according to Non-Patent Document 1, inductive coupling data communication can be performed without bit errors if the coils are arranged at a pitch of twice (or three times) or more of one side of the coil. If the technique shown in Non-Patent Document 2 is used, a NAND flash memory can be stacked and mounted in a package, and data can be read from and written to the memory by inter-chip wireless data communication.

  Further, according to Non-Patent Document 3, a processor and an SRAM chip are stacked and mounted in a package, and the processor can read and write data to and from the SRAM by inter-chip wireless data communication. Furthermore, according to Non-Patent Document 4, high-speed data transfer can be performed in a non-contact manner between a personal computer and a memory card inserted into the slot.

JP 2005-228981 A JP 2005-348264 A JP 2006-066644 A JP 2006-173986 A WO2009 / 069532 JP 2009-188468 A JP 2009-266109 A JP 2009-277842 A JP 2009-295699 A JP 2010-015654 A JP 2010-045166 A JP 2010-199280 A

N. Miura, D.M. Mizoguchi, T .; Sakurai and T.K. Kuroda, “Cross Talk Countermeasures in Inductive Inter-Chip Wireless Superconnect”, in Proc. IEEE Custom Integrated Circuits Conference, CICC '04. 99-102, Oct. 2004 Y. Sugimori, Y .; Kohama, M .; Saito, Y .; Yoshida, N .; Miura, H. et al. Ishikuro, T .; Sakurai and T. Kuroda, “A 2 Gb / s 15pJ / b / chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking”, IEEE International Solid-State Circuits CCC. Tech. Papers, pp. 244-245, Feb. 2009 K. Niitsu, Y. Shimazaki, Y. Shugimori, Y. Kohama, K. Kasuga, I. Nonmura, M. Saen, S. Komatsu, K. Osada, N. Irie, T. Hattori, A. Kuroda, “An Inductive-Coupling Link for 3D Integration of a 90 nm CMOS Processor and a 65 nm CMOS SRAM”, IEEE International Solid-State CI 80C4. 2009 S. Kawai, H .; Ishikuro and T. Kuroda, “A 2.5 Gb / s / Inductive-Coupling Transformer for Non-Contact Memory Card”, IEEE International Solid-State Circuits Conf. 10 (ISCC Tech. Papers, pp. 264-265, Feb. 2010

  In such conventional inventions and techniques, as in Non-Patent Document 1, a rectangular coil having a size about twice the communication distance formed by the wiring on the chip has a size of the coil along the wiring direction of the chip. It was arranged on an orthogonal lattice installed at a pitch of 2 to 3 times or more. As the pitch increases, the crosstalk between the coils decreases, but the mounting density of the coils decreases, and the data transfer rate that can be realized in a certain substrate area decreases. Double or triple is a matter of choice of how much design margin to include.

  It is generally difficult to place a coil in the memory area because of a shortage of wiring resources or concerns about the effect on memory operation. The coil is placed in the peripheral area where the input / output circuits are placed. Often. Therefore, even if the chip size is, for example, 10 mm square, the area where the coil can be arranged is limited, for example, about 10 mm × 1 mm.

  The data communication speed increases in proportion to the number of coils arranged. Therefore, in order to meet the demand for higher communication speeds year by year, it is necessary to increase the coil mounting density. However, as pointed out in Non-Patent Document 1, when the mounting density of the coil is increased, there is a problem that the crosstalk between channels increases and the reliability of communication is impaired.

  Therefore, Patent Document 9 proposes to prepare three communication paths by inductive coupling of coils and transfer data to a chip farther than the dimensions of the coils. In other words, the coil size can be made smaller than before with the same communication distance. Further, if the number of necessary coils can be reduced from three to two, the layout area can be reduced and more repeat transmission lines can be provided, which contributes to cost reduction and speed improvement.

  However, when the number of coils is two, a problem of signal interference occurs during a large number of repeat transmissions. In order to solve this problem, Patent Document 9 proposes to provide a shielding layer made of metal wiring to shield crosstalk. For this purpose, the chips had to be stacked while rotating 180 degrees.

  Therefore, an object of the present invention is to increase the mounting density of the coil by about twice without increasing the crosstalk between channels.

(1) In order to solve the above-described problem, the present invention is configured in a stacked integrated circuit device by a rectangular coil that transmits a signal by inductive coupling formed by wiring on a substrate and a transmission circuit connected thereto. A rectangular coil formed by a first substrate having a plurality of transmission channels, wiring on the substrate stacked on the first substrate, and formed at a position corresponding to the coil provided on the first substrate, and connected thereto. At least a second substrate having a plurality of receiving channels each including a receiving circuit, and each of the quadrangular coils is arranged such that the coils adjacent to each other are arranged in a diagonal direction of the coil in the diagonal direction of the square coil. disposed on the grid provided with 2/2 ^1/2 to 3/2 ^1/2 of the length of a single side, and the coil is a matrix array along a direction perpendicular to the wire It is characterized in that is.

As described above, the rectangular coils provided on each substrate are arranged such that the adjacent coils are 2/2 ^1/2 times to 3/2 ^1/2 of one side of the coil in the diagonal direction of the square coil. By disposing on a grid provided at double intervals , the mounting density can be made about twice that of the conventional coil arrangement.

(2) Further, according to the present invention, in the stacked integrated circuit device, an nth substrate (provided that an integer of 1 ≦ n ≦ N) including a transmitter that transmits a signal by inductive coupling, and a signal transmitted from the transmitter Is received by inductive coupling, relayed and transmitted by inductive coupling, and an n + x substrate (where 1 ≦ x ≦ N−n−1) and a signal relayed from the repeater are guided An n + y substrate having a plurality of receivers to be received by coupling (provided that x <y ≦ N−n), and the transmitter, the receiver, and the repeater are wired on the substrate. is connected to a coil of a square formed by, and wireless communication by inductive coupling coil pair stacking position corresponding coil of the rectangle diagonals center of the coil between which the highest adjacent the coil of the coil of the quadrangle Forward in direction The coils are arranged on a grid provided at an interval of 2/2 ^1/2 times to 3/2 ^1/2 times one side of the coil, and the coils are arranged in a matrix along the direction perpendicular to the wiring, The repeater is characterized in that one of the adjacent coil pairs among the coils arranged in a matrix is received using a receiving coil, and the other is transmitted using a transmitting coil.

  By adopting such a coil arrangement, it is possible to achieve a mounting density about twice that of the conventional coil arrangement, and this coil is paired to constitute a transmitter, a receiver and a repeater. Therefore, it becomes possible to transmit the signal repeatedly.

(3) Further, in the above (2), the present invention is characterized in that an interval along one side in the chip side direction of the lattice of each substrate is shorter than one side of the coil. With such a coil arrangement, it is possible to further improve the coil mounting density while keeping the crosstalk constant.

(4) Further, the present invention is, in any of the above (1) to (3), said top adjacent coils each other, characterized in that the vertically aligned or horizontally along the tip side direction.
(5) Further, the present invention is, in any of the above (1) to (3), said top adjacent coils each other, characterized in that arranged along the diagonal direction of the chip-side direction.

Thus, when configuring the coil pairs, coil each other and nearest neighbor is also be arranged vertically or horizontally along the tip-side direction, or, as arranged along the diagonal direction of the chip-side direction In the case where they are arranged along the diagonal direction of the chip side direction, the connection wiring length is shortened, so that higher speed communication is possible.

(6) Further, according to the present invention, in any one of the above (1) to (5), the rectangular coil is formed by alternately connecting wirings orthogonal to each other at different layer levels on the substrate. It is a three-dimensional coil. Thus, by making a coil into a three-dimensional coil, a coil and a transmitter or a receiver can be connected without vias.

  According to the disclosed laminated integrated circuit device, the mounting density of the coil can be increased by a factor of two without increasing crosstalk between channels as compared with the conventional one. Regardless of the stacking method, data can be transmitted repeatedly with two coils, which greatly contributes to cost reduction and transfer rate improvement.

It is explanatory drawing of the semiconductor integrated circuit device of embodiment of this invention. It is explanatory drawing of the magnetic field intensity which a square coil produces. It is arrangement | positioning drawing of a coil. It is explanatory drawing of the transmitter / receiver which performs repeat transmission. It is a lamination | stacking sectional view in case repeat transmission is performed once. It is explanatory drawing of the semiconductor integrated circuit device of Example 1 of this invention. It is an arrangement view of a transmission coil and a reception coil in each chip. 1 is a partial equivalent circuit diagram of a semiconductor integrated circuit device according to a first embodiment of the present invention. It is a circuit block diagram of a transmission / reception apparatus. It is explanatory drawing of the semiconductor integrated circuit device of Example 2 of this invention. It is explanatory drawing of the semiconductor integrated circuit device of Example 3 of this invention. It is explanatory drawing of the data write-in operation | movement in Example 3 of this invention. It is explanatory drawing of the data read-out operation | movement in Example 3 of this invention. It is explanatory drawing of the semiconductor integrated circuit device of Example 4 of this invention. It is explanatory drawing of the pair relationship of the transmission coil T and the receiving coil R by Example 4 of this invention. It is explanatory drawing of the other pair relation of the transmission coil T and the receiving coil R by Example 4 of this invention. It is explanatory drawing of the role sharing of the coil between each chip | tip in Example 4 of this invention. It is explanatory drawing of the pair relationship of the transmission coil T and the receiving coil R by Example 5 of this invention. It is explanatory drawing of the other pair relation of the transmission coil T and the receiving coil R by Example 5 of this invention. It is explanatory drawing of the pair relationship of the transmission coil T and the receiving coil R by Example 6 of this invention. It is explanatory drawing of the pair relationship of the transmission coil T and the receiving coil R by Example 7 of this invention. It is explanatory drawing of the semiconductor integrated circuit device of Example 8 of this invention. It is explanatory drawing of the semiconductor integrated circuit device of Example 9 of this invention. It is a lamination | stacking sectional view of the semiconductor integrated circuit device of Example 10 of this invention. It is explanatory drawing of the connection state of the coil group in each chip | tip. It is explanatory drawing of the connection state of the coil group in each chip | tip in Example 11 of invention. It is a lamination | stacking sectional drawing of the semiconductor integrated circuit device of Example 12 of this invention.

Here, the semiconductor integrated circuit device according to the embodiment of the present invention will be described with reference to FIGS. FIG. 1 is an explanatory diagram of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 1 (a) is an explanatory diagram of an arrangement of coils, and FIG. 1 (b) is a conceptual structural diagram of the coils. It is. As shown in FIG. 1B, the coil 1 is formed by alternately connecting X-direction wirings (solid lines) 2 and Y-direction wirings (broken lines) 3 formed in different layers with via conductors 4. It is a three-dimensional square coil. As shown in FIG. 1A, the coil 1 is arranged on a lattice inclined at 45 ° with respect to the XY direction. In this case, two adjacent coils form a pair, one being the reception coil R _x and the other being the transmission coil T _x . The coil may be a planar spiral coil.

The lattice interval P in the oblique direction is 2/2 ^1/2 (≈1.41) times or more of one side D of the coil 1. In this example, the coil 1 is shown as a square, but may be another rectangle such as a rectangle or a parallelogram. Further, one side D of the coil 1 is generally set to about twice the communication distance. For example, when the thickness of chips to be stacked is 100 μm, one side of the coil 1 is typically 200 μm.

  FIG. 2 is an explanatory diagram of the magnetic field intensity generated by the square coil. First, as shown in FIG. 2A, the magnitude of the magnetic field strength generated at the X and Y points by the current I flowing through the short line segment is considered. As shown in FIG. 2B, when the line segment is divided into two at the point B, the distances from the line segment BC to the X point and the Y point are equal. The strength of the magnetic field generated at the point is equal. Similarly, the strength of the magnetic field generated at the point X at the line segment AB is weaker than the strength of the magnetic field generated at the point Y.

  Since the magnetic field generated by the line current I can be obtained by superimposing the magnetic fields generated by the line segment AB and the line segment BC, it can be seen that the magnetic field at the point X is weaker than the magnetic field at the point Y. When this concept is extended and contour lines of magnetic field strength are drawn, the result is as shown in FIG. That is, the magnetic field at the center of the line segment is strong, and the magnetic field is weakened from the center toward both ends.

  Furthermore, when this magnetic field strength distribution is applied to a rectangular coil, as shown in FIG. 2 (d), the magnetic field is strong in the central part of the side of the square, but the magnetic field is weak in the diagonal part. FIG. 2 (e) is a diagram showing the magnetic field strength distribution actually calculated by the electromagnetic field simulator as contour lines approximately.

Approximating this result, the contour line of the magnetic field intensity resulting from the signal flowing through the rectangular coil becomes the shape of the broken line shown in FIG. That is, the magnetic field reaching the point separated from the center of the coil by M in the XY direction and the point separated by M / ^{21/2 in} a direction inclined by 45 ° with respect to the XY direction is the same. Conversely, a magnetic field of the same strength generated by another coil that has reached this boundary line has the same strength of crosstalk when it reaches the center of the coil.

  FIG. 3A is a conventional coil arrangement diagram, in which square coils are arranged in a matrix in the XY directions so as to be in contact with adjacent square coils across a boundary line. At this time, it is known that if the distance P between the centers of the coils is about twice or more the one side D of the coil, the influence of noise from other coils is sufficiently small and highly reliable communication without bit errors can be performed. (For example, refer nonpatent literature 1).

FIG. 3B is a coil arrangement diagram according to the embodiment of the present invention, and the magnetic field strength in the diagonal direction of the square coil is 1/2 ^1/2 (≈0.7) times smaller than that in the side direction. It is arranged using At this time, it is geometrically understood that the coil arrangement pitch P ′ in the XY directions is equal to P in FIG. In other words, using the same region as in FIG. 3A, twice as many coils can be arranged in FIG. 3B.

  FIG. 1 is obtained by repeatedly arranging squares obtained by connecting the center points of the four coils around FIG. 3B in the XY directions. Therefore, in the embodiment of the present invention, the mounting density of the coil can be increased about twice as compared with the conventional coil arrangement. Note that it is not necessary to strictly double the pitch P ′, and the pitch P ′ may be larger than the pitch P so as to have a density of about 1.5 times, so that crosstalk can be prevented more reliably.

  Note that the coil arrangement is not limited to a square lattice, but may be a rectangular lattice. This is because the effect of the magnetic field from the coil provided in the same layer level is greater than the effect of the magnetic field from the coil provided in the other layer level, so that the transmission / reception coil is formed of a pair of the receiving coil and the transmitting coil. This is because the distance between adjacent transmitting and receiving coils can be further narrowed.

Next, a signal transmission method in the semiconductor integrated circuit device having the coil arrangement according to the embodiment of the present invention will be described with reference to FIGS. FIG. 4 is an explanatory diagram of a transceiver that performs repeat transmission, FIG. 4A is a block diagram of the transceiver, and FIG. 4B is a circuit diagram of the transceiver. FIG. 4C is a diagram in which the coils are doubled to enable transmission / reception. A transmitter 13 is connected to the transmission coil (T _x ) 11, a receiver 14 is connected to the reception coil (R _x ) 12, and is controlled by the control circuit 15.

  FIG. 5 is a cross-sectional view illustrating a case where repeat transmission is performed once. FIG. 5A is a cross-sectional view in the case where repeat transmission is performed once between adjacent chips, and FIG. 5B is a case in which five chips are stacked and data transfer is performed every two chips. FIG. In this case, data communication is performed by inductive coupling of a coil pair, and power is supplied by wire wiring or a through silicon via (TSV).

  As shown in FIG. 5A, when three chips are stacked and data is transferred for each chip, the number of repeats is one. Therefore, a conventional shielding layer is not required. Further, as shown in FIG. 5B, when data transfer is performed every two chips in which five chips are stacked, the number of repeats is one.

  As described above, in the embodiment of the present invention, the coil is arranged on the grid in the direction inclined by 45 ° with respect to the XY direction. Therefore, compared with the case where the coil is arranged on the grid in the conventional XY direction, A mounting density of about twice can be realized. In addition, in the case of skipping one layer in a three-layer chip stack or a five-layer chip stack, repeat transmission is possible without providing a shielding layer, and there is no need to rotate 180 ° when stacking chips. . In this embodiment, the stacked semiconductor integrated circuit device is described. However, the present invention is not limited to the stacked semiconductor integrated circuit device, but can be applied to other integrated circuit devices such as an electronic circuit board. is there.

Next, a semiconductor integrated circuit device according to the first embodiment of the present invention will be described with reference to FIGS. 6A and 6B are explanatory diagrams of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 6A is a stacked sectional view, and FIG. 6B is a coil layout diagram. Here, two adjacent coils is a pair, one other one of the receiving coils R _x is transmitting coil T _x becomes performs data communication with the inductive coupling of the coil pair, the power supply wire line or through silicon via Supply.

  As shown in FIG. 6 (b), a three-dimensional square coil formed by alternately connecting wirings in the X direction (solid lines) and wirings in the Y direction (broken lines) formed in different layers is formed in the XY direction. Are arranged on a grid inclined at an angle of 45 °.

The lattice spacing P in the oblique direction is 2/2 ^1/2 (≈1.41) times or more of one side D of the coil. In this example, the coil is shown as a square, but one side D of the coil is generally set to about twice the communication distance. For example, when the thickness of the stacked chip is 100 μm, one side of the coil is 200 μm.

  FIG. 7 is an arrangement diagram of the transmission coil and the reception coil in each chip. In the chip 2, the reception coil R is arranged at a position corresponding to the transmission coil T of the chip 1, and the position where the reception coil R is paired is shown. The coil is referred to as a transmission coil T. In the chip 3, the receiving coil R is arranged at a position corresponding to the transmitting coil T of the chip 2. When transmitting a signal from the chip 1, the coil at the position of the receiving coil in the chip 1 is a dormant coil, and the coil at the position of the transmitting coil in the chip 3 is a dormant coil.

  8A and 8B are partial equivalent circuit diagrams of the semiconductor integrated circuit device according to the first embodiment of the present invention. FIG. 8A shows a memory write operation, and FIG. 8B shows a memory read operation. As shown in the figure, a coil used in the control circuit is selected to perform predetermined transmission and reception. In addition, since the receiving coil located on the opposite side to the signal transmission direction with respect to the transmitting coil becomes a sleep coil during signal transmission, crosstalk does not occur.

  9 is a circuit configuration diagram of the transmission / reception device, FIG. 9A is a reception circuit diagram, FIG. 9B is a transmission circuit diagram, and FIG. 9C is a control circuit diagram.

  As described above, in the first embodiment of the present invention, the coil is disposed on the lattice in the direction inclined by 45 ° with respect to the XY direction. Therefore, compared with the case where the coil is disposed on the lattice in the conventional XY direction, A mounting density of about twice can be realized. Further, it is possible to perform one-time repeat transmission without providing a shielding layer, and there is no need to rotate 180 ° when stacking chips.

  Next, a semiconductor integrated circuit device according to a second embodiment of the present invention will be described with reference to FIG. 10. Since the stacked structure and the signal transmission method are the same as those in the first embodiment, only the coil arrangement will be described. To do. FIG. 10 is an explanatory diagram of a semiconductor integrated circuit device according to a second embodiment of the present invention, FIG. 10 (a) is a coil layout diagram, and FIG. 10 (b) is a configuration diagram of a coil.

As shown in FIG. 10B, the coil is formed of a planar spiral coil. Further, as shown in FIG. 10A, as in the prior art, the coils are arranged in the XY directions on the grid, but the coils are arranged in a state inclined by 45 °. However, since the lattice interval P ′ is 2 ^1/2 (≈1.41) times or more of one side D of the coil, the mounting density of the coil is about twice as high as that of the conventional coil arrangement.

  As described above, in the second embodiment of the present invention, by arranging the coil by being inclined by 45 ° with respect to the XY direction, it is possible to realize a mounting density that is about twice that of the conventional case. Further, it is possible to perform one-time repeat transmission without providing a shielding layer, and there is no need to rotate 180 ° when stacking chips. The coil may be a three-dimensional square coil as in the first embodiment.

Next, a semiconductor integrated circuit device according to Embodiment 3 of the present invention will be described with reference to FIGS. FIG. 11 is an explanatory diagram of the semiconductor integrated circuit device according to the third embodiment of the present invention, which is the same as the first embodiment except that the number of stacked layers is five. FIG. 11A is a cross-sectional view of a laminated structure, and FIG. 11B is a coil arrangement diagram. Again, the two adjacent coils is a pair, one other one of the receiving coils R _x is transmitting coil T _x becomes performs data communication with the inductive coupling of the coil pair, the power supply wire line or through silicon via Supply.

  12 and 13 are partial equivalent circuit diagrams of the semiconductor integrated circuit device according to the third embodiment of the present invention. FIG. 12 shows the data write operation to the uppermost chip 4 and FIG. The data read operation from the chip 3 is shown. As shown in the figure, a coil used in the control circuit is selected to perform predetermined transmission and reception. In addition, since the receiving coil located on the opposite side to the signal transmission direction with respect to the transmitting coil becomes a dormant coil at the time of signal transmission, crosstalk does not occur.

  Thus, also in Example 3 of the present invention, since the coils are arranged on the grid in the direction inclined by 45 ° with respect to the XY direction, compared with the case where the coils are arranged on the grid in the conventional XY direction, A mounting density of about twice can be realized. Further, it is possible to perform one-time repeat transmission without providing a shielding layer, and there is no need to rotate 180 ° when stacking chips. Also in the third embodiment, as in the second embodiment, coils having a shape inclined by 45 ° with respect to the XY direction may be arranged on the lattice in the XY direction.

Next, a semiconductor integrated circuit device according to a fourth embodiment of the present invention will be described with reference to FIGS. 14A and 14B are explanatory diagrams of a semiconductor integrated circuit device according to a fourth embodiment of the present invention. FIG. 14A is a cross-sectional view of stacked layers, and FIG. 14B is a diagram of coil arrangement. Again, the two adjacent coils is a pair, one other one of the receiving coils R _x is transmitting coil T _x becomes performs data communication with the inductive coupling of the coil pair, the power supply wire line or through silicon via Supply.

In the fourth embodiment, as shown in FIG. 14B, the pitch P _X ″ in the X direction of the coil is smaller than the pitch P _X ′ in the X direction of the coil of the first embodiment. P _Y ″ is larger than the pitch P _Y ′ in the Y direction of the coil of the first embodiment. At this time, by making (P _X ′ −P _X ″) larger than (P _Y ″ −P _Y ′), the mounting density of the coil can be increased as compared with the first embodiment.

When the pitch P _X ″ in the X direction of the coil is made smaller than in the first embodiment, the crosstalk from the adjacent coils of the chip 1 and the chip 3 is increased, and the pitch P _Y ″ in the Y direction of the coil is increased as compared with the first embodiment. If it is increased, crosstalk from adjacent coils in the chip 2 is reduced. In this case, crosstalk from adjacent transmission coils in the same chip is more dominant, and crosstalk from adjacent transmission coils in the upper or lower chip is smaller than that. Compared to 1, there is no increase or decrease in crosstalk. Therefore, in the fourth embodiment of the present invention, it is possible to further increase the coil mounting density while keeping the crosstalk constant.

  FIG. 15 is an explanatory diagram of a pair relationship between the transmission coil T and the reception coil R according to the fourth embodiment of the present invention, and is positioned adjacent to the upper and lower sides of the adjacent coils with respect to the coil illustrated in FIG. Four examples in which coils are used in pairs are shown in FIGS. 15 (b) to 15 (e). Here, an arrangement is shown in which the vertical relationship between the transmitting coil T and the receiving coil R in the adjacent coil pairs is reversed.

  FIG. 16 is also an explanatory diagram of a pair relationship between the transmission coil T and the reception coil R according to the fourth embodiment of the present invention, and is positioned adjacent to the upper and lower sides of the adjacent coils with respect to the coil shown in FIG. Four examples in which coils are used in pairs are shown in FIGS. 16 (b) to 16 (e). Here, an arrangement is shown in which the vertical relationship between the transmitting coil T and the receiving coil R in the adjacent coil pair is the same.

  FIG. 17 is an explanatory diagram of the role sharing of the coils between the chips in the fourth embodiment of the present invention. Here, an example of the signal transmission state shown in FIG. 14A is shown. Further, the combination of chip pairs is the case of the combination of FIG. The operation of each coil in each chip is exactly the same as in FIG.

  Next, a semiconductor integrated circuit device according to a fifth embodiment of the present invention will be described with reference to FIGS. 18 and 19. The basic configuration is the same as that of the fourth embodiment described above, and the overall arrangement of the coils is vertically long. It has been changed to landscape. That is, in the semiconductor integrated circuit device, the vacant space in the chip varies depending on the type, and this corresponds to the case where there is an vacant space in the horizontal direction of the chip.

  FIG. 18 is an explanatory diagram of a pair relationship between the transmission coil T and the reception coil R according to the fifth embodiment of the present invention, and is located adjacent to the left and right of the adjacent coils with respect to the coil illustrated in FIG. Four examples in which coils are used in pairs are shown in FIGS. 18B to 18E. Here, an arrangement is shown in which the left-right relationship between the transmission coil T and the reception coil R in the adjacent coil pairs is reversed.

  FIG. 19 is also an explanatory diagram of a pair relationship between the transmission coil T and the reception coil R according to the fifth embodiment of the present invention, and is positioned adjacent to the upper and lower sides of the adjacent coils with respect to the coil illustrated in FIG. Four examples when coils are used in pairs are shown in FIGS. 19B to 19E. Here, an arrangement is shown in which the left-right relationship between the transmitting coil T and the receiving coil R in the adjacent coil pair is the same.

  Next, a semiconductor integrated circuit device according to a sixth embodiment of the present invention will be described with reference to FIG. 20. The basic configuration is the same as that of the fourth embodiment, and a transmission coil T and a reception coil that form a coil pair. The only difference is the R pair.

  FIG. 20 is an explanatory diagram of a pair relationship between the transmission coil T and the reception coil R according to the sixth embodiment of the present invention. Of the coils shown in FIG. FIG. 20B to FIG. 20E show four examples in the case where the coil located at is used as a pair. Here, the vertical relationship between the transmission coil T and the reception coil R in adjacent coil pairs is reversed.

  In the sixth embodiment, among the adjacent coils, a pair of coils located on a diagonal line is used, so that the distance between the coils, that is, the connection wiring length is shorter than in the case of the third or fourth embodiment. Therefore, the repeat delay is short, and higher-speed data transfer becomes possible. Since the coil arrangement is the same as in the third or fourth embodiment, the crosstalk is also the same.

  Next, a semiconductor integrated circuit device according to a seventh embodiment of the present invention will be described with reference to FIG. 21. The basic configuration is the same as that of the seventh embodiment, and the overall arrangement of the coil is changed from a vertically long shape to a horizontally long shape. It is a thing.

  FIG. 21 is an explanatory diagram of a pair relationship between the transmission coil T and the reception coil R according to the seventh embodiment of the present invention. Of the coils adjacent to the coil illustrated in FIG. FIG. 21B to FIG. 21E show four examples in the case where the coils located at are used in pairs. Here, the left-right relationship between the transmission coil T and the reception coil R in adjacent coil pairs is opposite to each other.

  Next, a semiconductor integrated circuit device according to an eighth embodiment of the present invention will be described with reference to FIG. 22. The basic configuration is the same as that of the third embodiment, and the chip stack structure is sequentially shifted by one coil pitch. The power is supplied by wire bonding.

  FIG. 22 is an explanatory diagram of a semiconductor integrated circuit device according to an eighth embodiment of the present invention, FIG. 22 (a) is a cross-sectional view of a stacked layer, and FIG. 22 (b) is an explanatory diagram of role sharing in a coil pair in each chip. It is. As shown in the figure, since there is no coil at a position opposite to the signal transmission direction with respect to the transmission coil, a laminated structure can be formed with an arbitrary number of layers, and repeat transmission can be performed twice or more.

  Next, the semiconductor integrated circuit device according to the ninth embodiment of the present invention will be described with reference to FIG. 23. The basic configuration is the same as that of the third embodiment, and the chip stacking structure is divided by 1/2 coil pitch. The power is supplied by wire bonding.

  FIG. 23 is an explanatory diagram of a semiconductor integrated circuit device according to a ninth embodiment of the present invention, FIG. 23 (a) is a cross-sectional view of a stacked layer, and FIG. 23 (b) is an explanatory diagram of role sharing in a coil pair in each chip. Also in this case, since the coil does not exist at the position opposite to the signal transmission direction with respect to the transmission coil, the laminated structure can be configured with an arbitrary number of laminations, and repeat transmission can be performed twice or more.

  Next, a semiconductor integrated circuit device according to a tenth embodiment of the present invention will be described with reference to FIGS. 24 and 25. The coil arrangement itself is the same as in the third embodiment, but here three coils are used. This constitutes a coil group. FIG. 24 is a laminated cross-sectional view, and the role sharing of the coils in each chip is divided into transmission, reception, and sleep and constitutes one coil group.

  In this case, since the coils on the opposite side of the signal transmission direction with respect to the transmitting coil are divided in roles so as to become a sleep coil in the chips adjacent vertically, crosstalk does not occur, and therefore, two or more times. Repeat transmission becomes possible.

  FIG. 25 is an explanatory diagram of the connection state of the coil groups in each chip. Here, the connection state of the coil groups in the three adjacent chips is shown, and as shown in the figure, the three coils adjacent in the vertical direction are shown. The coil group is configured by.

  In the tenth embodiment, the coil group is constituted by three coils, and the coil at the position opposite to the signal transmission direction with respect to the transmission coil is a dormant coil. Repeat transmission more than once becomes possible.

  Next, the semiconductor integrated circuit device according to the eleventh embodiment of the present invention will be described with reference to FIG. 26. The basic structure itself is the same as that of the tenth embodiment, but here, it is composed of three coils. The connection state of the coil group to be changed is changed.

  FIG. 26 is an explanatory diagram of the connection state of the coil groups in each chip. Here, the connection state of the coil groups in the three adjacent chips is shown, and as shown in the figure, adjacent ones constituting the smallest triangle are shown. A coil group is composed of three coils.

  In the eleventh embodiment, the connection wiring length between the transmitting coil and the receiving coil in two of the three adjacent chips is shorter than that in the tenth embodiment, so that the repeat delay is short and the speed is higher. Data transfer is possible.

  Next, with reference to FIG. 27, a semiconductor integrated circuit device according to Embodiment 12 of the present invention will be described. FIG. 27 is a cross-sectional view of the stacked semiconductor integrated circuit device according to the twelfth embodiment of the present invention. The basic structure itself is the same as that of the eleventh embodiment. In addition, the stacking direction is reversed with a spacer in the middle. It should be noted that the role sharing of each coil is set every other layer as compared with FIG. 25 or FIG. That is, if the role assignment of each coil in a certain chip is as shown in FIG. 25A, the role assignment of each coil in the next chip is as shown in FIG.

DESCRIPTION OF SYMBOLS 1 Coil 2 Wiring 3 Wiring 4 Via conductor 11 Transmission coil 12 Reception coil 13 Transmitter 14 Receiver 15 Control circuit

Claims (6)

A first substrate comprising a plurality of transmission channels each composed of a rectangular coil for transmitting a signal by inductive coupling formed by wiring on the substrate and a transmission circuit connected thereto;
A reception channel comprising a rectangular coil formed by wiring on a substrate stacked on the first substrate and formed at a position corresponding to the coil provided on the first substrate, and a receiving circuit connected thereto. A plurality of second substrates, and
Coil of each square, provided at the top adjacent 2/2 ^1/2 to 3/2 ^1/2 of the spacing between coils is the center of the coil side of the coil in the diagonal direction of the coils of the quadrangle are arranged on a grid, and, laminated integrated circuit device, characterized in that the coil along a direction orthogonal to the wiring is matrix array. An nth substrate having a transmitter for transmitting a signal by inductive coupling (where 1 ≦ n ≦ N),
An n + xth substrate (wherein an integer of 1 ≦ x ≦ N−n−1) having a plurality of repeaters that receive, relay, and transmit signals transmitted from the transmitter by inductive coupling;
A stack of an n + y substrate (provided that x <y ≦ N−n) having a plurality of receivers for receiving signals relayed from the repeater by inductive coupling;
The transmitter, the receiver, and the repeater are connected to a rectangular coil formed by wiring on a substrate, and wirelessly communicate by inductive coupling of a coil pair corresponding to the stacking position;
Coil of each square, provided at the top adjacent 2/2 ^1/2 to 3/2 ^1/2 of the spacing between coils is the center of the coil side of the coil in the diagonal direction of the coils of the quadrangle Arranged in a grid , and the coils are arranged in a matrix along the orthogonal direction of the wiring,
The repeater is configured to receive one of adjacent coil pairs among the coils arranged in a matrix using a receiving coil and transmit the other using a transmitting coil.   3. The stacked integrated circuit device according to claim 2, wherein an interval along one side of a chip side of the lattice of each substrate is shorter than one side of the coil. The outermost adjacent coils each other, the laminated integrated circuit device according to any one of claims 1 to 3, characterized in that arranged vertically or horizontally along the tip side direction. The outermost adjacent coils each other, the laminated integrated circuit device according to any one of claims 1 to 3, characterized in that arranged along the diagonal direction of the chip-side direction.   6. The rectangular coil according to claim 1, wherein the rectangular coil is a three-dimensional coil formed by alternately connecting wirings orthogonal to each other in different layer levels on the substrate. 2. A laminated integrated circuit device according to 1.

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