JP2015149340A - semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a coupling noise between signal paths.SOLUTION: A signal transfer through electrode T1 of a first semiconductor chip is arranged adjacently to respective potential supply through electrodes S1 and S2 of the first semiconductor chip. A second signal transfer through electrode T2 of the first semiconductor chip is arranged adjacently to respective potential supply through electrodes S1 and S3 of the first semiconductor chip. A signal transfer through electrode T1 of a second semiconductor chip is arranged adjacently to respective potential supply through electrodes S1 and S2 of the second semiconductor chip. A signal transfer through electrode T2 of the second semiconductor chip is arranged adjacently to the respective potential supply through electrodes S1 and S3 of the second semiconductor chip. The signal transfer through electrode T1 of the first semiconductor chip and the signal transfer through electrode T2 of the second semiconductor chip are electrically connected with each other.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a structure in which a plurality of semiconductor chips are stacked.

  In recent years, a memory in which semiconductor chips are stacked has been developed as means for realizing an ultra-wideband memory, and in particular, a through electrode called TSV (Through Substrate Via) is used for connection between the semiconductor chips. Patent Document 1 discloses an example of a through electrode.

  Each semiconductor chip is configured to have two channels. Therefore, the semiconductor device as a whole has twice as many channels as the number of semiconductor chips. The HBM stipulates that these channels operate independently of each other. For this reason, a signal path between the controller and each semiconductor chip is provided independently for each channel. Such a signal path for each channel is conventionally realized by a signal path having a multiple spiral structure.

JP 2010-287859 A

  However, the above-described multiple spiral structure has a problem that the coupling noise between signal paths is large due to the structure, and improvement is required.

  A semiconductor device according to an aspect of the present invention includes a semiconductor substrate, first and second signal transmission through electrodes that pass through the semiconductor substrate and receive signals, respectively, and a fixed potential is supplied through the semiconductor substrate. The first semiconductor chip includes first and second semiconductor chips each having first to third potential supply through electrodes and a multilayer wiring structure provided on the semiconductor substrate, and stacked on each other. The first signal transmission through-electrode is disposed adjacent to each of the first and second potential supply through-electrodes of the first semiconductor chip, and the first semiconductor chip of the first semiconductor chip Two signal transmission through electrodes are disposed adjacent to the first and third potential supply through electrodes of the first semiconductor chip, and the first signal of the second semiconductor chip. Transmission A through electrode is disposed adjacent to each of the first and second potential supply through electrodes of the second semiconductor chip, and the second signal transmission through electrode of the second semiconductor chip is , Arranged adjacent to each of the first and third potential supply through electrodes of the second semiconductor chip, and the multilayer wiring structure of the first semiconductor chip and the second semiconductor chip of the second semiconductor chip. Either one of the multilayer wiring structures electrically connects the first signal transmission through electrode of the first semiconductor chip and the second signal transmission through electrode of the second semiconductor chip. It is comprised by this.

  A semiconductor device according to another aspect of the present invention includes a semiconductor substrate, an internal circuit, a plurality of signal transmission through electrodes that respectively penetrate the semiconductor substrate, and a fixed potential that is supplied through the semiconductor substrate. First and second semiconductor chips each having one potential supply through electrode, one of the plurality of signal transmission through electrodes of the first semiconductor chip, and the plurality of second semiconductor chips. A first signal path formed in a spiral shape including one of the signal transmission through electrodes and connected to an internal circuit of the first semiconductor chip in the first semiconductor chip, and the first Including another one of the plurality of signal transmission through electrodes of the semiconductor chip and the other one of the plurality of signal transmission through electrodes of the second semiconductor chip. A second signal path formed in a spiral shape that forms a multiple spiral with the first signal path and connected to an internal circuit of the second semiconductor chip in the second semiconductor chip; and the first semiconductor chip Including one of the at least one potential supply through electrode and one of the at least one potential supply through electrode of the second semiconductor chip, and is configured by the first and second signal paths. And a potential supply path arranged so as to penetrate the center of the multiple spiral structure.

  According to still another aspect of the present invention, a semiconductor device includes a semiconductor substrate, an internal circuit, first to fourth signal transmission through electrodes penetrating the semiconductor substrate, and a fixed potential penetrating the semiconductor substrate. First to third semiconductor chips each having a supplied potential supply through electrode, a fourth semiconductor chip having a semiconductor substrate and an internal circuit, and the first signal transmission of the first semiconductor chip A through-electrode, a second signal-transmitting through-electrode of the second semiconductor chip, and a third signal-transmitting through-electrode of the first semiconductor chip, and formed in a spiral shape, A first signal path connected to an internal circuit of the first semiconductor chip in the semiconductor chip; the fourth signal transmission through electrode of the first semiconductor chip; and the first signal path of the second semiconductor chip. The signal transmission through electrode and the second signal transmission through electrode of the first semiconductor chip are formed in a spiral shape, and the internal circuit of the second semiconductor chip is formed in the second semiconductor chip. A second signal path connected to the first semiconductor chip, the third signal transmission through electrode of the first semiconductor chip, the fourth signal transmission through electrode of the second semiconductor chip, and the first signal transmission circuit. A third signal path formed in a spiral shape including the first signal transmission through electrode of the semiconductor chip and connected to an internal circuit of the third semiconductor chip in the third semiconductor chip; The second signal transmission through electrode of the first semiconductor chip, the third signal transmission through electrode of the second semiconductor chip, and the fourth signal transmission through electrode of the first semiconductor chip Including spiral And a fourth signal path connected to the internal circuit of the fourth semiconductor chip in the fourth semiconductor chip, and the first signal of each of the first to third semiconductor chips. The transmission through electrodes are arranged so as to overlap each other when viewed from the stacking direction of the first to fourth semiconductor chips, and the second signal transmission through electrodes of the first to third semiconductor chips are The third signal transmitting through electrodes of each of the first to third semiconductor chips are arranged so as to overlap each other when viewed from the stacking direction, and are arranged so as to overlap when viewed from the stacking direction. The fourth signal transmission through electrodes of each of the three semiconductor chips are arranged so as to overlap each other when viewed from the stacking direction, and the potential supply through electrodes of the first to third semiconductor chips are stacked in the stacked layers. Direction The first to fourth signal paths form a multi-spiral structure and include the potential supply through electrode of each of the first to third semiconductor chips, and the first to fourth signal paths include the through electrodes for potential supply of the first to third semiconductor chips, It is further characterized by further comprising a potential supply path arranged so as to penetrate through the central part of the multiple spiral structure constituted by the first to fourth signal paths.

  According to the present invention, the coupling between signal paths is weakened by the fixed potential supplied to the potential supply through electrode (potential supply path). Therefore, it is possible to reduce coupling noise between signal paths.

1 is a schematic front view of a semiconductor device 10a according to a preferred first embodiment of the present invention. It is a figure which shows the planar structure of the semiconductor chip Cn (n is an integer of 1-4) shown in FIG. FIG. 2 is a diagram showing an arrangement of a plurality of through silicon vias TSV in a part of an IO TSV region IOA ₀₀ -1 included in the semiconductor chip C1 shown in FIG. Is a diagram showing the arrangement of the plurality of through electrodes TSV in some IO for TSV region _IOA 00 -2 included in the semiconductor chip C2 illustrated in FIG. It is typical sectional drawing of the semiconductor chip C1 in the AA line shown in FIG. 3, and its related part. It is typical sectional drawing of the semiconductor chip C1 in the BB line shown in FIG. 3, and its related part. It is typical sectional drawing of the semiconductor chip C2 in the CC line | wire shown in FIG. 4, and its relevant part. FIG. 5 is a diagram schematically illustrating a three-dimensional structure of signal paths DQ2-1 to DQ2-4 illustrated in FIGS. 3 and 4. FIG. 2 is a diagram showing an arrangement of a plurality of through silicon vias TSV in a part of a CMD / ADD TSV region CAA ₀ -1 included in the semiconductor chip C1 shown in FIG. FIG. 7 is a diagram showing an arrangement of a plurality of through silicon vias TSV in another part of the CMD / ADD TSV area CAA ₀ -1 included in the semiconductor chip C1 shown in FIG. It is typical sectional drawing of the semiconductor chip C1 in the DD line | wire shown in FIG. 9, and its relevant part. It is typical sectional drawing of the semiconductor chip C1 in the EE line | wire shown in FIG. 10, and its relevant part. FIG. 4 is a diagram illustrating a modification of the arrangement of the plurality of through silicon vias TSV illustrated in FIG. 3. FIG. 12 is a diagram showing a modification of the arrangement of the plurality of through silicon vias TSV shown in FIGS. 10 and 11. It is a typical front view of the semiconductor device 10b by preferable 2nd Embodiment of this invention. FIG. 16 is a diagram showing an arrangement of a plurality of through silicon vias TSV in a part of an IO TSV region IOA ₀₀ -1 provided in the semiconductor device 10b included in the semiconductor chip C1 shown in FIG. It is a figure which shows the modification of arrangement | positioning of several penetration electrode TSV shown in FIG.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  A semiconductor device 10a according to the first embodiment of the present invention is a semiconductor device compliant with, for example, HBM (High Bandwidth Memory), and as shown in FIG. 1, a substrate 14, an interposer 11, a controller 12, and a buffer The die 13 includes four semiconductor chips C1 to C4 (first to fourth semiconductor chips). Each semiconductor chip, which will be described in detail later, is configured to have two channels. Therefore, the semiconductor device as a whole has twice as many channels as the number of semiconductor chips. The HBM stipulates that these channels operate independently of each other. For this reason, a signal path between the controller and each semiconductor chip is provided independently for each channel. Such a signal path for each channel is realized by a so-called multiple spiral structure signal path. Note that the present embodiment is not limited to the HBM, and includes one having all or part of the above-described configurations.

  The controller 12 is a control circuit for the semiconductor chips C1 to C4, has a function of supplying various signals such as a command signal CMD and an address signal ADD to the semiconductor chips C1 to C4, and a data signal between the semiconductor chips C1 to C4. It has a function of inputting and outputting DQ. The controller 12 is mounted on the upper surface of the interposer 11 by a plurality of solder balls 20 formed on the lower surface, and the interposer 11 is mounted on the substrate 14.

  The buffer die 13 is a chip that performs pitch conversion between a plurality of back surface bumps 21 formed on the upper surface and a plurality of solder balls 20 formed on the lower surface, and includes a semiconductor substrate. The connection between the back bump 21 and the solder ball 20 is realized by a through electrode TSV (not shown) penetrating the semiconductor substrate. The buffer die 13 is also mounted on the upper surface of the interposer 11 by a plurality of solder balls 20 formed on the lower surface.

  On the upper surface of the buffer die 13, semiconductor chips C1 to C4 are stacked in this order. Each of the semiconductor chips C1 to C4 includes a semiconductor substrate, a through-hole electrode TSV penetrating the semiconductor substrate, and a multilayer wiring structure formed on the main surface of the semiconductor substrate. In a state where the main surface is facing down, it is placed on the buffer die 13 or another semiconductor chip adjacent to the lower side.

  Of the semiconductor chips C1 to C4, the semiconductor chips C1 to C3 are formed with the same mask and have the same structure. The semiconductor chip C4 located in the uppermost layer also has the same structure as the semiconductor chips C1 to C3 except that the through silicon via TSV and the back surface bump 21 described later are not formed. The reason why the through silicon via TSV and the rear surface bump 21 are not provided in the semiconductor chip C4 is that it is located in the uppermost layer, so that it is not necessary to extend a potential supply path and a signal path described later to the upper semiconductor chip. When the through electrode TSV is formed, it is necessary to make the semiconductor substrate thin so as to have a thickness suitable for the formation, but in the semiconductor chip C4 in which the through electrode TSV is not formed, the thickness can be relatively increased. Therefore, it is possible to reduce the warpage of the stacked body of the semiconductor chips C1 to C4. However, even if the through electrode TSV and the back surface bump 21 are not provided on the semiconductor chip C4, other configurations such as internal wiring are formed in the same manner as in the case where the through electrode TSV and the back surface bump 21 are provided. Therefore, hereinafter, for convenience of explanation, the description may be made assuming that the through-hole electrode TSV and the back surface bump 21 are provided in the semiconductor chip C4.

  As shown in FIG. 1, a plurality of surface bumps 22 are formed on the main surface (surface on the buffer die 13 side) of each of the semiconductor chips C1 to C4. A plurality of back surface bumps 21 are formed on the back surfaces of the semiconductor chips C1 to C3 excluding the semiconductor chip C4. The plurality of front surface bumps 22 of the semiconductor chip C1 located in the lowermost layer are provided on a one-to-one basis with respect to the plurality of back surface bumps 21 formed on the upper surface of the buffer die 13, and are connected to the corresponding back surface bumps 21. Yes. Similarly, the plurality of front surface bumps 22 of the semiconductor chips C2 to C4 are provided one-to-one with respect to the plurality of back surface bumps 21 formed on the back surfaces of the semiconductor chips C1 to C3 adjacent to the lower side, respectively. The back surface bump 21 is connected. In the semiconductor device 10a, the back surface bump 21 of the chip (including the buffer die 13) positioned relatively below is connected to the surface bump 22 of the chip positioned relatively above, and the semiconductor chips C1 to C1 are further connected. By connecting the front surface bump 22 and the rear surface bump 21 via the through-electrode TSV inside each C3, a plurality of potential supply paths and a plurality of signals from the buffer die 13 to the semiconductor chip C4 through the semiconductor chips C1 to C3, respectively. A path is constructed.

  Here, the potential supply path is a wiring for supplying various fixed potentials such as the power supply potential VDD, VSS, VDDQ, VSSQ to each circuit in the buffer die 13 and the semiconductor chips C1 to C4. The signal path transmits and receives various signals such as a command signal CMD, an address signal ADD, a write data strobe signal WDQS, a read data strobe signal RDQS, and a data signal DQ between the controller 12 and each of the semiconductor chips C1 to C4. Wiring.

Each of the semiconductor chips C1 to C4 is internally divided into two channels Ch ₀ and Ch ₁ as shown in FIG. Accordingly, eight channels are provided in the semiconductor device 10a. The semiconductor device 10a is configured such that these eight channels operate as independent DRAMs.

  In order to realize the operation of each channel, it is necessary to provide the above-described plurality of signal paths independently for each channel. In the semiconductor device 10a, such a signal path for each channel is realized by making the structure of each signal path into a multiple spiral structure. The details of the multi-spiral structure will be described later. By adopting the multi-spiral structure, it is possible to simultaneously provide a signal path for each channel and to form the semiconductor chips C1 to C4 with the same mask. become.

  Among a plurality of signal paths, a signal path for inputting / outputting the data signal DQ (hereinafter referred to as “data signal transmission / reception signal path” may be distinguished from other signal paths) is one channel. 128 are provided. That is, each channel of the semiconductor device 10a is configured to be able to input / output a 128-bit data signal DQ in parallel. Therefore, the entire semiconductor device 10a is provided with 128 × 8 = 1024 signal paths for transmitting and receiving data signals. Hereinafter, 256 data signal transmission / reception signal paths corresponding to the semiconductor chip Cn (n is an integer of 1 to 4) may be represented as a signal path DQm-n (m is an integer of 0 to 255).

FIG. 2 also shows the internal configurations of the channels Ch ₀ and Ch ₁ . As shown in the figure, the channel Ch _k (k is 0 or 1) of the semiconductor chip Cn (n is an integer of 1 to 4) includes memory cell array areas MA _k0 -n, MA _k1 -n, and an IO TSV area IOA. _{k0 -n,} configured with a _IOA k1 -n, and CMD / ADD for TSV region _CAA k -n. The memory cell array regions MA _k0 -n and MA _k1 -n are regions in which the memory cell array and its peripheral circuits are arranged. The peripheral circuit includes a command decoder, an address latch circuit, a row system control circuit, a column system control circuit, a sense amplifier, a data amplifier, and the like. In the IO TSV areas IOA _k0 -n and IOA _k1 -n, the data signal transmission / reception signal path and the potential supply path described above are arranged. Further, other signal paths and potential supply paths are arranged in the CMD / ADD TSV area CAA _k -n.

Hereinafter, with reference to FIGS. 3 to 7, the structure and arrangement of the through silicon vias TSV for configuring the data signal transmission / reception signal path will be described in detail. Incidentally, FIG. 3 and IO for TSV region _IOA 00 -1 in Fig. _4, shows only _IOA 00 -2, other IO for TSV region _IOA k0 _-n, the same configuration _IOA k1 -n Yes doing. Moreover, although only the structure regarding only a part of penetration electrode TSV is shown in FIGS. 5-7, other penetration electrode TSV also has the same structure.

  Each of the rounded rectangles shown in FIGS. 3 and 4 represents one through electrode TSV. The characters in the rounded rectangle represent the type of potential supplied to the through electrode TSV or the type of signal path that includes the through electrode TSV. For example, the power supply potential VSS is supplied via the substrate 14 to the through silicon via TSV indicated as “VSS”, and the power supply potential VDDQ is supplied via the substrate 14 to the through silicon via TSV indicated as “VDDQ”. Further, the through silicon via TSV described as “DQm-n” constitutes a part of the data signal transmission / reception signal path DQm-n described above. Further, symbols (such as “T1” and “S1”) attached to the right shoulder of the rounded rectangle are identification codes of the through silicon via TSV attached for the convenience of explanation.

As illustrated in FIGS. 3 and 4, in each of the IO TSV areas IOA _k0 -n and IOA _k1 -n, a plurality of through silicon vias TSV are arranged in a matrix. Further, as illustrated in FIGS. 5 to 7, each of the semiconductor chips Cn includes a semiconductor substrate SS and insulating layers I1a to I1d and I2 stacked on the main surface (lower surface in the drawing) of the semiconductor substrate SS. It is comprised.

  As shown in FIGS. 5 to 7, wirings 25, 27, 29, and 31 are formed on the surfaces of the insulating layers I1a to I1d, respectively. In addition, via conductors 24, 26, 28, and 30 are formed in the insulating layers I1a to I1d, respectively. These wirings and via conductors constitute a multilayer wiring structure embedded in the semiconductor chip Cn. The through electrode TSV is formed so as to penetrate the semiconductor substrate SS and the insulating layer I1a, and is connected to the corresponding back bump 21 at one end and the wiring 25 at the other end. The side surface of the through electrode TSV is covered with an insulating film 23, thereby ensuring insulation between the through electrode TSV and the semiconductor substrate SS. The surface bump 22 is formed so that one end is connected to the wiring 31 and the other end protrudes from the surface of the insulating layer I2.

  With respect to the potential supply path, the multilayer wiring structure of the semiconductor chip Cn is configured to connect the through electrodes TSV and the surface bumps 22 that overlap each other when viewed from the stacking direction, as shown in FIGS. . In other words, the potential supply path is configured by connecting the through silicon vias TSV of the respective semiconductor chips Cn that are overlapped when viewed from the stacking direction. Therefore, the potential supply path is a wiring extending linearly from the buffer die 13 to the semiconductor chip C4 along the stacking direction.

  Further, as shown in FIG. 5, the semiconductor chip Cn has a gate electrode 42 covering the main surface of the semiconductor substrate SS with a gate insulating film 41 interposed therebetween, and a main surface of the semiconductor substrate SS so as to sandwich the gate electrode 42. A transistor Tr including two buried impurity diffusion layers 40 is formed. The multilayer wiring structure of the semiconductor chip Cn is configured to connect the potential supply path to one of the two impurity diffusion layers 40. Thereby, the fixed potential supplied to the potential supply path functions as the source potential of the transistor Tr, for example.

  On the other hand, with respect to the signal path for data signal transmission / reception, the multilayer wiring structure of the semiconductor chip Cn connects the through electrodes TSV and the surface bumps 22 that are not overlapped when viewed from the stacking direction, as shown in FIGS. Configured to do. As a result, with respect to the data signal transmission / reception signal path, at least two semiconductor chips Cn that are vertically adjacent to each other are connected to the through silicon vias TSV that are not overlapped when viewed from the stacking direction. As will be described in detail later, the above-described multiple spiral structure is realized by adopting such a connection for connection of a plurality of through silicon vias TSV constituting a signal path for data signal transmission / reception.

  Further, as shown in FIG. 6, the semiconductor chip Cn corresponds to two gate electrodes 42 covering the main surface of the semiconductor substrate SS via the gate insulating film 41, and between and both sides of these gate electrodes 42. Two transistors each including three impurity diffusion layers 40 embedded in the main surface of the semiconductor substrate SS are formed. These two transistors constitute an input / output circuit IOC (internal circuit, see FIGS. 3 and 4) connected to a data signal transmission / reception signal path. The input / output circuit IOC outputs a data signal DQ (read data) read from the memory cell array to a corresponding data signal transmission / reception signal path during a read operation, and transmits a corresponding data signal transmission / reception from the controller 12 during a write operation. A data signal DQ (write data) supplied to the signal path is configured to be supplied to the memory cell array. The multi-layer wiring structure of the semiconductor chip Cn connects the data signal transmission / reception signal path to one gate electrode of the two transistors and one impurity diffusion layer 40 of the other transistor (which is not shared with one transistor). It is configured to be connected to the impurity diffusion layer 40). As a result, the two illustrated transistors can function as the input / output circuit IOC having the above functions.

  Hereinafter, the description will be continued focusing on the data signal transmission / reception signal path DQ2-n, but the same applies to other data signal transmission / reception signal paths.

As shown in FIGS. 3 and 4, each of the data signal transmission / reception signal paths DQ2-1 to DQ2-4 (first to fourth signal paths) is provided in the IO TSV area IOA _k0 -n of the semiconductor chip Cn. The through electrodes T1 to T4 (first to fourth signal transmission through electrodes) are arranged in relation to the above. These penetration electrodes T1-T4 are arrange | positioned so that a rhombus may be comprised. In addition, the four through electrodes T1 provided in each of the semiconductor chips C1 to C4 are arranged at positions overlapping when viewed from the stacking direction (arranged side by side in the stacking direction). The same applies to the through electrodes T2 to T4.

In the IO TSV region IOA _k0 −1 of the semiconductor chip C1, as shown in FIG. 3, the through electrodes T1 to T4 are respectively connected to data signal transmission / reception signal paths DQ2-1, 2-4, 2-3, 2-. Part of 2. On the other hand, in the IO TSV area IOA _k0 -2 of the semiconductor chip C2, as shown in FIG. 4, the through electrodes T1 to T4 are respectively connected to data signal transmission / reception signal paths DQ2-2, 2-1, 2- 4, 2-3. As described above, such a configuration is realized by connecting the through silicon vias TSV and the surface bumps 22 that are not overlapped when viewed from the stacking direction by the multilayer wiring structure of the semiconductor chip C2.

  The structure of data signal transmission / reception signal paths DQ2-1 to DQ2-4 will be described in more detail with reference to FIG. As shown in FIG. 8, the data signal transmission / reception signal path DQ2-1 includes the through electrode T4 of the buffer die 13, the through electrode T1 of the semiconductor chip C1, the through electrode T2 of the semiconductor chip C2, and the through electrode T3 of the semiconductor chip C3. It is configured in a spiral shape. If the through-hole electrode TSV is provided in the semiconductor chip C4, the data signal transmission / reception signal path DQ2-1 is formed in a spiral shape including the through-hole electrode T4 of the semiconductor chip C4.

  Similarly, the data signal transmission / reception signal path DQ2-2 is provided through the through electrode T3 of the buffer die 13, the through electrode T4 of the semiconductor chip C1, the through electrode T1 of the semiconductor chip C2, and the through electrode T2 of the semiconductor chip C3. Then, it is configured in a spiral shape including the through electrode T3 of the semiconductor chip C4. The data signal transmission / reception signal path DQ2-3 includes the through electrode T2 of the buffer die 13, the through electrode T3 of the semiconductor chip C1, the through electrode T4 of the semiconductor chip C2, the through electrode T1 of the semiconductor chip C3, and a semiconductor if provided. It is configured in a spiral shape including the through electrode T2 of the chip C4. The data signal transmission / reception signal path DQ2-4 includes the through electrode T1 of the buffer die 13, the through electrode T2 of the semiconductor chip C1, the through electrode T3 of the semiconductor chip C2, the through electrode T4 of the semiconductor chip C3, and a semiconductor if provided. It is configured in a spiral shape including the through electrode T1 of the chip C4.

  The data signal transmission / reception signal paths DQ2-1 to DQ2-4 configured as described above form a multiple spiral structure, as can be understood from FIG. A through electrode T1 of a certain semiconductor chip Cn always constitutes a part of a data signal transmission / reception signal path DQ2-n to be connected to the input / output circuit IOC in the semiconductor chip Cn. Therefore, in any semiconductor chip Cn, the connection destination of the input / output circuit IOC may be the through electrode T1, and in the semiconductor device 10a, the semiconductor chips C1 to C4 are formed by the same mask.

  As shown in FIG. 8, each of the data signal transmission / reception signal paths DQ2-1 to DQ2-4 is connected to one end of the input / output circuit IOC in the corresponding semiconductor chip Cn, and also in the buffer die 13. Connected to one end of the output circuit. Although not shown, the other end of the input / output circuit is connected to the wiring in the interposer 11 shown in FIG. 1 via the solder ball 20 shown in FIG.

  Returning to FIG. 3 and FIG. 4, in the vicinity of the through electrodes T1 to T4, through electrodes S1 to S9 (first to ninth potential supply through electrodes) constituting a part of the potential supply path are arranged. The four through electrodes S1 provided in each of the semiconductor chips C1 to C4 are arranged at positions overlapping with each other when viewed from the stacking direction (in the stacking direction), like the four through electrodes T1 provided in each of the semiconductor chips C1 to C4. Placed side by side). The same applies to the through electrodes S2 to S9. The power supply potential VSS is supplied to the through electrodes S1 to S5, and the power supply potential VDDQ is supplied to the through electrodes S6 to S9. However, the fixed potential supplied to the through electrodes S1 to S9 is not limited to these, and other fixed potentials may be used.

  The through electrode S1 is disposed at a position corresponding to the center of the rhombus formed by the through electrodes T1 to T4. As a result, the potential supply path including the through electrode S1 penetrates through the central portion of the multiple spiral structure including the data signal transmission / reception signal paths DQ2-1 to DQ2-4 as shown in FIG. Will be arranged as follows.

  In the through electrodes S2 to S5, the through electrode T1 is adjacent to each of the through electrodes S1 and S2, the through electrode T2 is adjacent to each of the through electrodes S1 and S3, and the through electrode T3 is adjacent to each of the through electrodes S1 and S4. The through electrode T4 is disposed adjacent to the through electrodes S1 and S5. More specifically, the through electrodes S2, T1, S1, T3, and S4 are arranged in a straight line in this order and at equal intervals, and the through electrodes S3, T2, S1, T4, and S5 are penetrated in this order at equal intervals. The electrodes S2, T1, S1, T3, and S4 are arranged in a straight line in a direction orthogonal to the straight line formed by the electrodes.

  The through electrodes S6 to S9 are arranged between the through electrodes T1 to T4. Specifically, the penetration electrode T1 is sandwiched between the penetration electrodes S6 and S9, the penetration electrode T2 is sandwiched between the penetration electrodes S6 and S7, the penetration electrode T3 is sandwiched between the penetration electrodes S7 and S8, and the penetration electrode T4 is the penetration electrode. It arrange | positions so that it may be pinched | interposed into S8 and S9. The VDD supply through electrode and the VSS supply through electrode are arranged adjacent to the data signal transmission / reception through electrode. Ensure power supply for data signal transmission / reception input / output circuit.

  As described above, in the semiconductor device 10a, the through electrodes S1 to S9 (potential supply paths) are arranged in the vicinity of the through electrodes T1 to T4 (data signal transmission / reception signal paths DQ2-1 to DQ2-4). Thereby, in the semiconductor device 10a, the coupling between the data signal transmission / reception signal paths DQ2-1, DQ2-2, DQ2-3, and DQ2-4 is weakened. Therefore, the coupling noise between the data signal transmission / reception signal paths DQ2-1, DQ2-2, DQ2-3, and DQ2-4 is reduced. The coupling between the data signal transmission / reception signal paths DQ2-1 and DQ1-4 is also weakened by the through electrodes S2 and S9 supplied with the power supply potentials VSS and VDDQ, respectively. Therefore, the coupling noise between the data signal transmission / reception signal paths DQ2-1 and DQ1-4 is also reduced. That is, both the coupling noise within the same DQ group forming the multiple spiral structure and the coupling noise between different DQ groups are reduced.

  However, such an effect of the semiconductor device 10a is not obtained unless all of the through electrodes S1 to S9 are provided in the vicinity of the through electrodes T1 to T4. At least a part of the through electrodes S1 to S9 is provided. Can be obtained. Actually, as can be understood from FIG. 3, for example, with respect to the data signal transmission / reception signal path DQ0-n, the through electrodes TSV corresponding to the through electrodes S2 and S3 are not arranged. For example, a through electrode TSV to which a power supply potential corresponding to the through electrode S2 is not provided is provided in the lower part of the data signal transmission / reception signal path DQ0-1 in the drawing, but a wiring or a through electrode TSV that generates noise is provided. If it is not provided or is provided, but the arrangement location is remote, the arrangement is not necessarily required. This is because there is no cause of coupling noise in the first place.

  Note that the potential supply path (potential supply path configured by the through electrode S1) that penetrates the central portion of the multiple spiral structure has a particularly great effect from the viewpoint of reducing coupling noise. Therefore, it is preferable not to omit this potential supply path as much as possible.

Next, with reference to FIGS. 9 to 12, the structure and arrangement of the through silicon vias TSV for configuring a signal path other than the data signal transmission / reception signal path will be described in detail. Hereinafter, signal paths for transmitting and receiving the command signal CMD and the read data strobe signal RDQS (hereinafter referred to as “command signal transmission / reception signal path” and “read data strobe signal transmission / reception signal path”, However, the same applies to signal paths for transmitting and receiving other signals. 9 and 10 show only the CMD / ADD TSV area CAA ₀ -1, other CMD / ADD TSV areas CAA _k -n have the same configuration. Further, FIG. 11 and FIG. 12 show only the configuration related to a small part of the through silicon vias TSV, but the other through silicon vias TSV have the same configuration.

  Here, the command signal CMD is a signal representing a command for controlling the operation of the semiconductor chip Cn, such as a read command or a write command, and is supplied from the controller 12 to each semiconductor chip Cn. The command signal CMD is information of a plurality of bits, and these are supplied to each semiconductor chip Cn in parallel. Therefore, the semiconductor device 10a includes a plurality of command signal transmission / reception signal paths for each semiconductor chip Cn. Hereinafter, a plurality of command signal transmission / reception signal paths corresponding to the semiconductor chip Cn may be represented as a signal path CMDm-n (m is an integer of 0 or more). The read data strobe signal RDQS is a signal indicating the timing at which read data is output from the semiconductor chip Cn, and is supplied from each semiconductor chip Cn to the controller 12 in synchronization with the output of the read data. The controller 12 takes in the read data using the read data strobe signal RDQS. The semiconductor device 10a is configured to have one read data strobe signal transmission / reception signal path for each semiconductor chip Cn. Hereinafter, the read data strobe signal transmission / reception signal path corresponding to the semiconductor chip Cn may be represented as a signal path RDQS-n.

  Each of the rounded rectangles shown in FIGS. 9 and 10 represents one through electrode TSV, as in FIGS. 3 and 4. The meanings of the characters in the rounded rectangle and the symbol attached to the right shoulder of the rounded rectangle are the same as those in FIGS. 3 and 4. However, the through silicon via TSV indicated as “CMDm-n” in FIG. 9 constitutes a part of the above-described command signal transmission / reception signal path CMDm-n. Further, the through silicon via TSV indicated as “RDQS-n” in FIG. 10 constitutes a part of the read data strobe signal transmission / reception signal path RDQS-n described above.

As understood from a comparison between FIG. 9 and FIG. 3, the arrangement of the through silicon vias TSV for the command signal transmission / reception signal path CMDm-n is the same as the arrangement of the through silicon vias TSV for the data signal transmission / reception signal path DQm-n. . In more detail the command signal transmitting and receiving signal paths CMD2-1~CMD2-4 As an example, the first CMD / ADD for TSV region _CAA 0 -1, a command signal for transmission and reception signal paths CMD2-1~CMD2-4 Correspondingly, through electrodes T1 to T4 and through electrodes S1 to S9 are arranged as shown in FIG. Specific roles and arrangements of the through electrodes T1 to T4 and the through electrodes S1 to S9 are the same as those described for the data signal transmission / reception signal path DQ2-n. Further, the through electrodes T1 to T4 and the through electrodes S1 to S9 are similarly provided in the CMD / ADD TSV areas CAA ₀ -2 and CAA ₀ -3. The through electrodes T1 to T4 and S1 to S9 are connected to each other between the semiconductor chips in the same connection manner as the data signal transmission / reception signal path DQ2-n, and are also connected to the surface bumps 22 of the semiconductor chip C4. Is done. Therefore, the command signal transmission / reception signal path CMDm-n also has the same multi-spiral structure as the data signal transmission / reception signal path DQm-n, and a potential supply path to which the power supply potential VSS is supplied is arranged at the center thereof. Will be.

As understood from comparison between FIG. 10 and FIG. 3, the arrangement of the through electrodes TSV related to the read data strobe signal transmission / reception signal path RDQS-n is also the same as the arrangement of the through electrodes TSV related to the data signal transmission / reception signal path DQm-n. It is the same. More specifically, first, in the CMD / ADD TSV area CAA ₀ -1, corresponding to the read data strobe signal transmission / reception signal paths RDQS-1 to RDQS-4, as shown in FIG. T4 and through electrodes S1 to S9 are arranged. Specific roles and arrangements of the through electrodes T1 to T4 and the through electrodes S1 to S9 are the same as those described for the data signal transmission / reception signal path DQ2-n. Further, the through electrodes T1 to T4 and the through electrodes S1 to S9 are similarly provided in the CMD / ADD TSV areas CAA ₀ -2 and CAA ₀ -3. These through electrodes T1 to T4 and S1 to S9 are connected to each other between the semiconductor chips in the same connection manner as the data signal transmission / reception signal path DQ2-n, and are also connected to the surface bump 22 of the semiconductor chip C4. Connected. Therefore, the read data strobe signal transmission / reception signal path RDQS-n also has the same multi-spiral structure as the data signal transmission / reception signal path DQm-n, and a potential supply path to which the power supply potential VSS is supplied at the center. Will be placed.

  As described above, in the semiconductor device 10a, four signal paths other than the data signal transmission / reception signal paths are also provided for each semiconductor chip Cn corresponding to four similar signal paths corresponding to the semiconductor chips C1 to C4, respectively. The through electrodes T1 to T4 are provided, and the through electrodes S1 to S9 constituting the potential supply path are disposed in the vicinity thereof. Therefore, the coupling noise between these four signal paths is reduced as compared with the background art that does not have the through electrodes S1 to S9.

  The data signal transmission / reception signal path is connected to the input / output circuit IOC as shown in FIG. 3 and the like, while the command signal transmission / reception signal path and the read data strobe signal transmission / reception signal path are shown in FIGS. As shown in FIG. 10, the input circuit IC and the output circuit OC are connected to each other. Hereinafter, this point will be described in detail.

  As illustrated in FIGS. 11 and 12, the semiconductor chip Cn includes a gate electrode 42 that covers the main surface of the semiconductor substrate SS with the gate insulating film 41 interposed therebetween, and a main surface of the semiconductor substrate SS that sandwiches the gate electrode 42. And a plurality of transistors each including two impurity diffusion layers 40 embedded in the structure. Each of the input circuit IC and the output circuit OC is constituted by one of the plurality of transistors.

  The multilayer wiring structure of the semiconductor chip Cn connects a command signal transmission / reception signal path to the gate electrode 42 of the transistor constituting the input circuit IC, and leads to one of the two impurity diffusion layers 40 of the transistor constituting the input circuit IC. A data strobe signal transmission / reception signal path is configured to be connected. As a result, the former transistor can function as an input circuit IC for a command signal transmission / reception signal path, and the latter transistor can function as an output circuit OC for a read data strobe signal transmission / reception signal path.

  Although the semiconductor device 10a according to the first embodiment has been described above, various modifications can be made to the semiconductor device 10a according to the first embodiment without departing from the gist of the present invention. Hereinafter, two modifications will be described.

As shown in FIG. 13, the semiconductor device 10 a according to the first modification includes all the through electrodes S <b> 1 to S <b> 9 in the vicinity of the through electrodes T <b> 1 to T <b> 4 for all the data signal transmission / reception signal paths. By doing so, although the areas of the IO TSV areas IOA _k0 -n and IOA _k1 -n are expanded, it is possible to obtain a higher coupling noise reduction effect for all the data signal transmission / reception signal paths. Become.

  As shown in FIG. 14, the semiconductor device 10 a according to the second modification has a through electrode in the vicinity of the through electrodes T <b> 1 to T <b> 4 related to signal paths other than the data signal transmission / reception signal path instead of the above-described through electrodes S <b> 1 to S <b> 9. S10 to S17 are arranged. In this modification, the rows of through electrodes S16, S12, T2, T1, S10, and S14 and the rows of through electrodes S17, S13, T3, T4, S11, and S15 are arranged adjacent to each other. The The power supply potential VSS is supplied to the through electrodes S10, S11, S16, and S17. On the other hand, the power supply potential VDD is supplied to the through electrodes S12, S13, S14, and S15.

  In this modification, since the potential supply path is not arranged in the central portion of the multi-spiral structure constituted by four signal paths, the coupling noise reduction effect can be obtained as compared with the semiconductor device 10a according to the first embodiment. Get smaller. However, since the through electrodes S10 to S17 are arranged, it is possible to obtain a certain degree of coupling noise reduction effect. In this modification, signal paths other than the data signal transmission / reception signal paths are illustrated, but the same arrangement of the through silicon vias TSV can be applied to the data signal transmission / reception signal paths.

  Next, a semiconductor device 10b according to a second embodiment of the present invention will be described with reference to FIGS.

  As understood from comparison between FIG. 15 and FIG. 1, the semiconductor device 10 b is different from the semiconductor device 10 a in that eight semiconductor chips C <b> 1 to C <b> 8 are stacked on the upper surface of the buffer die 13. Hereinafter, the same components as those of the semiconductor device 10a will be denoted by the same reference numerals, and description thereof will be omitted. Description will be made focusing on differences from the semiconductor device 10a.

  In the semiconductor device 10b, since eight semiconductor chips C1 to C8 are stacked, one multiple spiral structure is configured by eight signal paths. Hereinafter, the description will be continued focusing on the data signal transmission / reception signal path DQ5-n (n is an integer of 1 to 8), but the same applies to other signal paths.

As illustrated in FIG. 16, the TSV area IOA _k0 -n for IO of the semiconductor chip Cn according to the present embodiment includes through electrodes in association with the data signal transmission / reception signal paths DQ5-1 to DQ5-8. T1 to T8 are arranged. These through electrodes T1 to T8 are arranged so as to form a rectangular shape clockwise. The through electrodes T2, T4, T6, and T8 are located at the vertices of the rectangle. As in the first embodiment, the eight through electrodes T1 provided in each of the semiconductor chips C1 to C8 are disposed at overlapping positions as viewed from the stacking direction (arranged in the stacking direction). The same applies to the through electrodes T2 to T8. The through electrodes T1 to T8 of the semiconductor chips C1 to C8 are connected to each other by the multilayer wiring structure in each of the semiconductor chips C1 to C8 so that the data signal transmission / reception signal paths DQ5-1 to DQ5-8 form a multiple spiral structure. Connected.

  In the vicinity of the through electrodes T1 to T8, through electrodes S1 to S12 that constitute a part of the potential supply path are arranged. The power supply potential VSS is supplied to the through electrodes S1, S2, S4, S6, S9, and S11, and the power supply potential VDDQ is supplied to the through electrodes S3, S5, S7, S8, S10, and S12. However, the fixed potential supplied to the through electrodes S1 to S12 is not limited to these, and other fixed potentials may be used.

  The through electrode S1 is disposed at a position corresponding to the center of a rectangle formed by the through electrodes T1 to T8. Thus, the potential supply path including the through electrode S1 is disposed so as to penetrate the central portion of the multiple spiral structure configured by the data signal transmission / reception signal paths DQ5-1 to DQ5-8. .

  The through electrodes S2 to S12 are arranged so as to surround the periphery of the rectangle formed by the through electrodes T1 to T8. More specifically, in the through electrodes S2 to S12, the through electrode T1 is positioned adjacent to and between the through electrodes S1 and S2, and the through electrode T2 is adjacent to and between the through electrodes S1 and S4. The through electrode T3 is located adjacent to and between the through electrodes S1 and S6, the through electrode T7 is located adjacent to and between the through electrodes S1 and S9, and the through electrode T8 is disposed between the through electrodes. S1 and S11 are adjacent to each other, and the through electrodes S4 to S7 and S8 to S11 are arranged in a straight line along the same direction in this order and at equal intervals. S3, S2, S12, and S11 are arranged so as to be arranged in a straight line in a direction orthogonal to the straight line formed by the through electrodes S4 to S7 in this order and at equal intervals. The VDD supply through electrode and the VSS supply through electrode are arranged adjacent to the data signal transmission / reception through electrode. Ensure power supply for data signal transmission / reception input / output circuit.

  As described above, in the semiconductor device 10b, the through electrodes S1 to S12 (potential supply path) are arranged in the vicinity of the through electrodes T1 to T8 (data signal transmission / reception signal paths DQ5-1 to 5-8). Accordingly, the coupling between the data signal transmission / reception signal paths DQ5-1 to DQ5-8 is weakened as compared with the background art that does not include the through electrodes S1 to S12. Therefore, the coupling noise between the data signal transmission / reception signal paths DQ5-1 to DQ5-8 is reduced as compared with the background art. The coupling between the data signal transmission / reception signal paths DQ5-1 to DQ1-5 is also weakened by the through electrode S2 to which the power supply potential VSS is supplied. Therefore, the coupling noise between the data signal transmission / reception signal paths DQ5-1 and DQ1-5 is also reduced. That is, both the coupling noise within the same DQ group forming the multiple spiral structure and the coupling noise between different DQ groups are reduced.

  In the second embodiment, as understood from FIG. 16, the through electrode constituting the potential supply path does not completely surround the rectangle formed by the through electrodes T1 to T8. . For example, the through electrode constituting the potential supply path does not exist in the upper region of the through electrodes T4 to T6 shown in FIG. Even with such an arrangement, it is possible to reduce the coupling noise between the data signal transmission / reception signal paths DQ2-1 to DQ2-8 as described above, but the rectangular shape constituted by the through electrodes T1 to T8. It is possible to further enhance the effect of reducing the coupling noise by completely surrounding the periphery of the substrate by a through electrode to which a power supply potential is supplied.

  FIG. 17 shows the arrangement of the through silicon vias TSV according to an example in which the effect of reducing the coupling noise is thus increased. As shown in the figure, in this example, through electrodes S1 to S17 to which a power supply potential is supplied are arranged in the vicinity of the through electrodes T1 to T8. The potential supplied to each of the through electrodes T1 to T8 and the through electrodes S1 to S12 and their arrangement are the same as those shown in FIG. The power supply potential VSS is supplied to the through electrodes S13, S15, and S17, and the power supply potential VDDQ is supplied to the through electrodes S14 and S16. In the through electrodes S13 to S17, the through electrode T4 is located between and adjacent to the through electrodes S1 and S13, and the through electrode T5 is located between and adjacent to the through electrodes S1 and S15. The electrode T6 is positioned adjacent to and between the through electrodes S1, S17, and the through electrodes S13, S14, S15, S16, S17 are orthogonal to the straight line formed by the through electrodes S4 to S7 in this order and at equal intervals. It arrange | positions so that it may arrange in a line with a direction.

  By thus arranging the through electrodes S1 to S17 in the vicinity of the through electrodes T1 to T8, the coupling noise between the data signal transmission / reception signal paths DQ5-1 to DQ5-8 can be more effectively reduced. Is possible.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

  For example, in each of the above embodiments, the semiconductor chips Cn are stacked face-down on the upper surface of the buffer die 13, but may be stacked face-up. In this case, the uppermost semiconductor chip Cn (in the case of stacking four semiconductor chips C1 to C4 as shown in FIG. 1), the semiconductor chip C4, and in the case of stacking eight semiconductor chips C1 to C8 as shown in FIG. In addition, it is necessary to form the through silicon via TSV also in the semiconductor chip C8). Further, the through electrode TSV of the relatively lower semiconductor chip Cn and the through electrode TSV of the relatively upper semiconductor chip Cn are multilayer wirings in the relatively lower semiconductor chip Cn. Depending on the structure, they will be connected to each other.

  Further, although cases have been described with the above embodiments where the number of stacked semiconductor chips Cn is 4 or 8, the present invention can be suitably applied to a semiconductor device in which a plurality of semiconductor chips Cn are stacked.

C1 to C8 Semiconductor chips CAA ₀ -n, CAA ₀ -n CMD / ADD TSV area Ch ₀ , Ch ₁ channel CMDm-n Command signal transmission / reception signal path DQ Data signal DQm-n Data signal transmission / reception signal path I 1 a -I 1 d , I2 insulating layer IC input circuit _{IOA 00 -n, IOA 01 -n,} IOA 10 -n, IOA 11 -n IO for TSV region IOC input-output circuit _{MA 00, MA 01, MA 10} , MA 11 memory cell array region OC output Circuit RDQS-n Read data strobe signal transmission / reception signal path S1 to S17 Potential supply through electrode SS Semiconductor substrate T1 to T8 Signal transmission through electrode TSV Through electrode Tr Transistors 10a and 10b Semiconductor device 11 Interposer 12 Controller 13 Buffer die 14 Substrate 20 Solder Bo Le 21 backside bumps 22 surface bumps 23 insulating film 24, 26, 28, 30 via conductors 25, 27, 29 and 31 lines 40 impurity diffused layer 41 gate insulating film 42 gate electrode

Claims (9)

A semiconductor substrate, first and second signal transmission through electrodes that pass through the semiconductor substrate and receive signals, and first to third potential supply throughs that pass through the semiconductor substrate and are supplied with a fixed potential, respectively. Each having an electrode and a multilayer wiring structure provided on the semiconductor substrate, each including a first and a second semiconductor chip stacked on each other;
The first signal transmission through electrode of the first semiconductor chip is disposed adjacent to each of the first and second potential supply through electrodes of the first semiconductor chip;
The second signal transmission through electrode of the first semiconductor chip is disposed adjacent to each of the first and third potential supply through electrodes of the first semiconductor chip;
The first signal transmission through electrode of the second semiconductor chip is disposed adjacent to each of the first and second potential supply through electrodes of the second semiconductor chip;
The second signal transmission through electrode of the second semiconductor chip is disposed adjacent to each of the first and third potential supply through electrodes of the second semiconductor chip;
One of the multilayer wiring structure of the first semiconductor chip and the multilayer wiring structure of the second semiconductor chip includes the first signal transmission through electrode of the first semiconductor chip and the second semiconductor chip. A semiconductor device configured to electrically connect the second signal transmission through electrode of a semiconductor chip. The first signal transmission through electrode of the first semiconductor chip and the first signal transmission through electrode of the second semiconductor chip are aligned in the stacking direction of the first and second semiconductor chips. Placed in
The second signal transmission through electrode of the first semiconductor chip and the second signal transmission through electrode of the second semiconductor chip are arranged side by side in the stacking direction. The semiconductor device according to claim 1. The first potential supply through electrode of the first semiconductor chip and the first potential supply through electrode of the second semiconductor chip are arranged side by side in the stacking direction,
The second potential supply through electrode of the first semiconductor chip and the second potential supply through electrode of the second semiconductor chip are arranged side by side in the stacking direction,
The third potential supply through electrode of the first semiconductor chip and the third potential supply through electrode of the second semiconductor chip are arranged side by side in the stacking direction. The semiconductor device according to claim 2. The one of the multilayer wiring structure of the first semiconductor chip and the multilayer wiring structure of the second semiconductor chip is:
Electrically connecting the first potential supply through electrode of the first semiconductor chip and the first potential supply through electrode of the second semiconductor chip;
Electrically connecting the second potential supply through electrode of the first semiconductor chip and the second potential supply through electrode of the second semiconductor chip;
The third potential supply through electrode of the first semiconductor chip and the third potential supply through electrode of the second semiconductor chip are electrically connected to each other. The semiconductor device according to claim 1. Each of the first and second semiconductor chips includes third and fourth signal transmission through electrodes that pass through the semiconductor substrate and receive signals, respectively, and a fixed potential is supplied through the semiconductor substrate. 4 and a fifth potential supply through electrode,
The semiconductor device includes:
A semiconductor substrate, first to fourth signal transmission through electrodes that pass through the semiconductor substrate and receive signals, and first to fifth potential supply throughs that pass through the semiconductor substrate and are supplied with a fixed potential, respectively. A third semiconductor chip having an electrode and a multilayer wiring structure provided on the semiconductor substrate;
A fourth semiconductor chip having a semiconductor substrate and a multilayer wiring structure provided on the semiconductor substrate;
Each of the first to fourth semiconductor chips has an internal circuit,
The third signal transmission through electrode of the first semiconductor chip is disposed adjacent to each of the first and fourth potential supply through electrodes of the first semiconductor chip;
The fourth signal transmission through electrode of the first semiconductor chip is disposed adjacent to each of the first and fifth potential supply through electrodes of the first semiconductor chip;
The third signal transmission through electrode of the second semiconductor chip is disposed adjacent to each of the first and fourth potential supply through electrodes of the second semiconductor chip;
The fourth signal transmission through electrode of the second semiconductor chip is disposed adjacent to each of the first and fifth potential supply through electrodes of the second semiconductor chip;
The first signal transmission through electrode of the third semiconductor chip is disposed adjacent to each of the first and second potential supply through electrodes of the third semiconductor chip;
The second signal transmission through electrode of the third semiconductor chip is disposed adjacent to each of the first and third potential supply through electrodes of the third semiconductor chip;
The third signal transmission through electrode of the third semiconductor chip is disposed adjacent to each of the first and fourth potential supply through electrodes of the third semiconductor chip;
The fourth signal transmission through electrode of the third semiconductor chip is disposed adjacent to the first and fifth potential supply through electrodes of the third semiconductor chip;
The multilayer wiring structure of the second semiconductor chip electrically connects the first signal transmission through electrode of the first semiconductor chip and the second signal transmission through electrode of the second semiconductor chip. And electrically connecting the second signal transmission through-electrode of the first semiconductor chip and the third signal transmission through-electrode of the second semiconductor chip, and the first semiconductor The third signal transmission through electrode of the chip is electrically connected to the fourth signal transmission through electrode of the second semiconductor chip, and the fourth signal transmission of the first semiconductor chip is performed. A through electrode is electrically connected to the first signal transmission through electrode of the second semiconductor chip, and the first signal transmission through electrode of the second semiconductor chip is connected to the second signal. Configured to connect to the internal circuit of the semiconductor chip ,
The multilayer wiring structure of the third semiconductor chip electrically connects the first signal transmission through electrode of the second semiconductor chip and the second signal transmission through electrode of the third semiconductor chip. And electrically connecting the second signal transmission through-electrode of the second semiconductor chip and the third signal transmission through-electrode of the third semiconductor chip, and the second semiconductor The third signal transmission through electrode of the chip and the fourth signal transmission through electrode of the third semiconductor chip are electrically connected, and the fourth signal transmission of the second semiconductor chip is performed. A through electrode is electrically connected to the first signal transmitting through electrode of the third semiconductor chip, and the first signal transmitting through electrode of the third semiconductor chip is connected to the third signal. Configured to connect to the internal circuit of the semiconductor chip ,
The multilayer wiring structure of the fourth semiconductor chip is configured to connect the fourth signal transmission through electrode of the third semiconductor chip to the internal circuit of the fourth semiconductor chip. The semiconductor device according to claim 1, wherein the semiconductor device is characterized in that: A semiconductor substrate; an internal circuit; a plurality of signal transmission through electrodes that respectively penetrate the semiconductor substrate; and at least one potential supply through electrode that passes through the semiconductor substrate and is supplied with a fixed potential. First and second semiconductor chips;
The first semiconductor chip is formed in a spiral shape including one of the plurality of signal transmission through electrodes and one of the plurality of signal transmission through electrodes of the second semiconductor chip, and A first signal path connected to an internal circuit of the first semiconductor chip in one semiconductor chip;
Including the other one of the plurality of signal transmission through-electrodes of the first semiconductor chip and the other one of the plurality of signal transmission through-electrodes of the second semiconductor chip. A second signal path formed in a spiral shape that forms a multiple spiral with the signal path and connected to an internal circuit of the second semiconductor chip in the second semiconductor chip;
Including one of the at least one potential supply through electrode of the first semiconductor chip and one of the at least one potential supply through electrode of the second semiconductor chip, the first and second And a potential supply path arranged so as to penetrate through the central portion of the multiple spiral structure constituted by the signal paths. The plurality of signal transmission through electrodes of the first semiconductor chip include a first signal transmission through electrode that constitutes a part of the first signal path,
The plurality of signal transmission through electrodes of the second semiconductor chip form a first signal transmission through electrode that forms part of the second signal path and a part of the first signal path. A second signal transmission through electrode that
Each of the first signal transmission through electrode of the first semiconductor chip and the first signal transmission through electrode of the second semiconductor chip is a stack of the first and second semiconductor chips. The semiconductor device according to claim 6, further comprising: arranged so as to overlap when viewed from a direction. A semiconductor substrate; an internal circuit; first to fourth signal transmission through electrodes that respectively penetrate the semiconductor substrate; and a potential supply through electrode that passes through the semiconductor substrate and is supplied with a fixed potential. First to third semiconductor chips;
A fourth semiconductor chip having a semiconductor substrate and an internal circuit;
The first signal transmission through electrode of the first semiconductor chip, the second signal transmission through electrode of the second semiconductor chip, and the third signal transmission through of the first semiconductor chip. A first signal path formed in a spiral shape including an electrode and connected to an internal circuit of the first semiconductor chip in the first semiconductor chip;
The fourth signal transmission through electrode of the first semiconductor chip, the first signal transmission through electrode of the second semiconductor chip, and the second signal transmission through of the first semiconductor chip. A second signal path formed in a spiral shape including an electrode and connected to an internal circuit of the second semiconductor chip in the second semiconductor chip;
The third signal transmission through electrode of the first semiconductor chip, the fourth signal transmission through electrode of the second semiconductor chip, and the first signal transmission through of the first semiconductor chip A third signal path formed in a spiral shape including an electrode and connected to an internal circuit of the third semiconductor chip in the third semiconductor chip;
The second signal transmission through electrode of the first semiconductor chip, the third signal transmission through electrode of the second semiconductor chip, and the fourth signal transmission through of the first semiconductor chip. A fourth signal path formed in a spiral shape including an electrode and connected to an internal circuit of the fourth semiconductor chip in the fourth semiconductor chip;
The first signal transmission through electrodes of the first to third semiconductor chips are arranged so as to overlap each other when viewed from the stacking direction of the first to fourth semiconductor chips,
The second signal transmission through electrodes of each of the first to third semiconductor chips are arranged to overlap each other when viewed from the stacking direction,
The third signal transmission through electrodes of each of the first to third semiconductor chips are arranged to overlap each other when viewed from the stacking direction,
The fourth signal transmission through electrodes of each of the first to third semiconductor chips are arranged to overlap each other when viewed from the stacking direction,
The potential supply through electrodes of each of the first to third semiconductor chips are arranged to overlap each other when viewed from the stacking direction,
The first to fourth signal paths constitute a multiple spiral structure,
A potential supply path including the potential supply through electrode of each of the first to third semiconductor chips and disposed so as to penetrate a central portion of a multi-spiral structure constituted by the first to fourth signal paths. A semiconductor device, further comprising: Each of the first to fourth semiconductor chips has a memory cell array,
The internal circuit of the first semiconductor chip supplies read data read from the memory cell array of the first semiconductor chip to the first signal path and arrives at the first signal path. Configured to supply write data to the memory cell array of the first semiconductor chip;
The internal circuit of the second semiconductor chip supplies read data read from the memory cell array of the second semiconductor chip to the second signal path and arrives at the second signal path. Configured to supply write data to the memory cell array of the first semiconductor chip;
The internal circuit of the third semiconductor chip supplies read data read from the memory cell array of the third semiconductor chip to the third signal path and arrives at the third signal path. Configured to supply write data to the memory cell array of the third semiconductor chip;
The internal circuit of the fourth semiconductor chip supplies read data read from the memory cell array of the fourth semiconductor chip to the fourth signal path and arrives at the fourth signal path. The semiconductor device according to claim 8, wherein write data is supplied to the memory cell array of the fourth semiconductor chip.

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