JP2015018899A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of attaining both prevention of reduction in signal quality and prevention of increase in signal skew.SOLUTION: The semiconductor device includes a semiconductor chip including first and second chip pads, and a wiring substrate. The wiring substrate includes: a first area in which a plurality of connection pads including first and second connection pads connected corresponding to the first and second chip pads are formed in juxtaposition to one another in a first direction; a second area on which the semiconductor chip is mounted; a third area located between the first area and the second area; a fourth area located on the opposite side of the third area with respect to the first area; first and second power-supply patterns formed corresponding to the third and fourth areas, respectively; and a third power-supply pattern crossing the first area and mutually connecting the first and second power-supply patterns. The third power-supply pattern is disposed between the first and second connection pads without being connected to any of the plurality of connection pads.

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a wiring board provided with a wiring pattern.

  With the recent high performance of digital devices, improvement in operation speed is also required for various semiconductor devices mounted on these digital devices. For this reason, in a DRAM (Dynamic Random Memory) which is one of semiconductor devices, it is more important than ever to suppress skew (temporal shift) between a command signal, an address signal, and a clock signal. In some DRAMs, power supply pads are arranged as much as possible between pads (signal pads) which are input terminals of these signals in order to reduce the skew between the command signal, address signal and clock signal inside the semiconductor chip. There are things that I try not to do.

  However, reducing the number of power supply pads disposed between signal pads is not desirable from the viewpoint of signal quality (signal integrity) outside the semiconductor chip, for example, a wiring board on which the semiconductor chip is mounted. . More specifically, when the number of power supply pads is reduced, the signal pads are adjacent to each other. When wirings connected to adjacent signal pads are arranged in parallel with each other, interference occurs between signals transmitted through these wirings. As a result, the quality of the signal associated with each signal pad is degraded.

  As a related semiconductor device capable of avoiding such a decrease in signal quality, there is one described in Patent Document 1. In the semiconductor device described in Patent Document 1, wirings connected to signal pads adjacent to each other are drawn out in opposite directions.

JP 2006-114595 A

  As described in the cited document 1, the method of drawing out wirings connected to adjacent signal pads in opposite directions is to a semiconductor device in which a plurality of signal pads are arranged along the edge of a semiconductor chip. Is practically impossible to apply.

  The present invention provides a semiconductor device including a semiconductor chip in which a plurality of chip pads are arrayed along an edge thereof, and can reduce the electrode pads of the semiconductor chip and prevent deterioration of signal quality. .

  A semiconductor device according to an embodiment of the present invention includes a semiconductor chip including first and second chip pads, and a first and second chip connected to the first and second chip pads, respectively. A first area in which a plurality of connection pads including connection pads are formed side by side in a first direction; a second area on which the semiconductor chip is mounted; the first area and the second area; A third area located between the first area, a fourth area located on the opposite side of the third area with respect to the first area, and the third area and the fourth area, respectively. A wiring board including first and second power supply patterns and a third power supply pattern that interconnects the first and second power supply patterns across the first area; Of the plurality of connection patterns. Without being with any connection de, characterized in that it is disposed between the first and second connection pads.

  A semiconductor device according to another embodiment of the present invention includes a semiconductor including a first area where a plurality of connection pads are formed, and a plurality of chip pads connected to the plurality of connection pads by bonding wires, respectively. A second power supply pattern is formed which is located between the second area for mounting the chip, and between the first area and the second area, and overlaps a part of each of the bonding wires in plan view. A third area formed, a wiring pattern adjacent to the first area and connected to the plurality of connection pads, and at least one second power supply pattern disposed therebetween are formed. And a fourth area, wherein a plurality of the plurality of the first power supply pattern and the second power supply pattern are formed so as to cross the first area. It is connected by electrically independent third power supply pattern from the connection pads, characterized in that.

  A third interconnecting the first and second power supply patterns formed in the third and fourth areas, respectively, without being connected to these connection pads between the first and second connection pads. By arranging this power supply pattern, it is possible to achieve both reduction of the number of electrode pads of the semiconductor chip and prevention of deterioration of signal quality.

1 is a longitudinal sectional view of a semiconductor device having a package-on-package structure to which the present invention is applied. FIG. 2 is a plan view of an upper package 100 included in the semiconductor device of FIG. 1. FIG. 3 is a cross-sectional view taken along line A-A ′ of FIG. 2. FIG. 3 is a plan view showing a main part of the semiconductor device according to the first embodiment of the present invention, and shows a portion corresponding to a wavy line frame B in FIG. 2. It is a top view which shows an example of the wiring pattern which concerns on 1st Example of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device having a package on package (POP) structure to which the present invention can be applied.

  The illustrated semiconductor device 1000 includes an upper package 100 and a lower package 200. Specifically, the semiconductor device 1000 is a semiconductor memory device, the upper package 100 is a memory package, and the lower package is a controller package.

  The lower package 200 includes a wiring board 201 and a controller chip 202 flip-chip mounted thereon. On one surface of the wiring board 201, a land 203 for connection with the upper package 100 is disposed around the controller chip 202. Solder balls 204 are provided on the other surface of the wiring board 201. The upper package 100 is stacked and mounted on one surface side of the lower package 200.

  The upper package 100 includes a wiring board 101 and first and second semiconductor chips 102 and 103 mounted on one surface thereof. A plurality of solder balls 104 are arranged on the other surface of the wiring board 101 as external terminals. These solder balls 104 are arranged in two rows along the outer periphery of the wiring board 101 so as to avoid the controller chip 202 of the lower package 200.

  Next, the configuration of the upper package (memory package) 100 will be further described with reference to FIGS. 2 is a plan view showing the configuration of the upper package 100, and FIG. 3 is a cross-sectional view taken along the line A-A 'showing the configuration of the upper package 100. As shown in FIG. Hereinafter, the upper package 100 is referred to as a semiconductor device.

  As shown in FIGS. 2 and 3, a first semiconductor chip (first memory chip) 102 is mounted on an approximately central portion of one surface of the wiring substrate 101 with an adhesive member 105 with the circuit formation surface facing upward. Has been.

  The first semiconductor chip 102 has, for example, a substantially rectangular plate shape, and a plurality of chip pads 106 are arranged on the short side (see FIG. 2). For example, a command signal, an address signal, and a clock signal chip pad (CA pad) 106 are arranged on one short side, and a data signal chip pad (DQ pad) 106 is arranged on the other short side. can do.

  Above the first semiconductor chip 102, a second semiconductor chip (second memory chip) 103 is stacked and mounted via an adhesive member 107 with the circuit formation surface facing upward. The second semiconductor chip 103 is configured similarly to the first semiconductor chip 102. Specifically, the second semiconductor chip 103 has, for example, a substantially rectangular plate shape, and a plurality of chip pads 108 are arranged on the short side (see FIG. 2). The second semiconductor chip 103 is stacked so as to expose the chip pads 106 of the first semiconductor chip 102 while being rotated by 90 ° with respect to the first semiconductor chip 102.

  The wiring board 101 is, for example, a glass epoxy wiring board. More specifically, the wiring board 101 includes an insulating base material 109 and an insulating film (solder resist) 110 covering both surfaces thereof. A plurality of connection pads 111 corresponding to the chip pads 106 of the first semiconductor chip 102 and the chip pads 108 of the second semiconductor chip 103 are arranged on one surface of the wiring substrate 101. The plurality of connection pads 111 are exposed to the outside through openings formed in the insulating film 110. A plurality of lands 112 on which a plurality of solder balls 104 are mounted are formed on the other surface of the wiring board 101. The plurality of lands 112 are also exposed to the outside through openings formed in the insulating film 110. The plurality of lands 112 correspond to the plurality of connection pads 111, respectively, and are electrically connected to each other through through vias 113 that penetrate the insulating base material 109.

  The chip pads 106 of the first semiconductor chip 102 and the chip pads 108 of the second semiconductor chip 103 and the corresponding connection pads 111 are electrically connected by a conductive wire 114 made of Au or the like. ing.

  A sealing body (sealing resin) 115 is further formed on one surface of the wiring substrate 101 so as to cover the first semiconductor chip 102, the second semiconductor chip 103, and the wires 114.

  Next, with reference to FIG. 4, a semiconductor device according to the first embodiment of the present invention will be described. The overall structure of the semiconductor device according to the present embodiment is as described with reference to FIGS.

  FIG. 4 is a diagram showing a region corresponding to the region surrounded by the broken line frame B in FIG. 2 of the semiconductor device according to the present embodiment. That is, FIG. 4 is a diagram showing the conductive pattern included in the peripheral region of the connection pad 111. Here, the conductive pattern includes a wiring pattern, a solid pattern for power supply, a solid pattern for grounding, and the like. These conductive patterns differ in size and shape depending on their intended use, but their structures are common.

  The chip pad 106 of the first semiconductor chip 102 includes a signal chip pad 106a including first and second chip pads arranged adjacent to each other, a power supply chip pad 106b, and a grounding chip pad 106c. In order to avoid skew between signals in the first semiconductor chip 102 and / or to realize shrinking (reduction) of the first semiconductor chip 102, a power supply chip pad is provided between the signal chip pads 106a. Alternatively, no grounding chip pad is provided.

  The wiring substrate 101 is positioned between the first area 401 where the connection pads 111 are formed, the second area 402 where the first semiconductor chip 102 is mounted, and the first area 401 and the second area 402. It includes a third area 403 and a fourth area 404 that is located on the opposite side of the third area 403 with respect to the first area 401 and is adjacent to the first area 401. These areas are arranged side by side in a direction (second direction) orthogonal to the direction in which the chip pads 106 and connection pads 111 are arranged (first direction).

  In the first area 401, a plurality of connection pads 111 are arranged in the left-right direction (first direction) in the figure. The plurality of connection pads 111 include a signal connection pad 111a, a power connection pad 111b, and a ground connection pad 111c. These connection pads 111 correspond to the signal chip pads 106a, the power supply chip pads 106b, and the ground connection pads 106c formed on the first semiconductor chip 102, respectively.

  The signal connection pad 111a is used to transmit a command signal, an address signal, and a clock signal. Alternatively, the signal connection pad 111a is used for data signal transmission. The power connection pad 111b is used to supply the power supply voltage VDD, and the ground connection pad 111c is used to supply the ground voltage VSS.

  One end of a corresponding wiring pattern is connected to each connection pad 111. The other end of the signal wiring pattern 411a connected to the signal connection pad 111a is connected to the corresponding land 112 through the through via 113 (see FIG. 3).

  The other end of the power supply wiring pattern 411 b connected to the power supply connection pad 111 b is connected to the power supply solid pattern 412. The other end of the ground wiring pattern 411c connected to the ground connection pad 111c is connected to the ground solid pattern 413.

  A first power pattern 414 is formed in the third area 403. The first power supply pattern 414 is connected to the grounding solid pattern 413 through the grounding connection pad 111c and the wiring pattern. The first power supply pattern 414 may be a conductive pattern formed continuously on the ground solid pattern 413.

  The first power supply pattern 414 is formed so as to overlap at least a part of each of the wires 114 that connect the chip pad 106 and the connection pad 111 in a plan view. In other words, the first power supply pattern 414 is formed with a length extending from one end of the row to the other end along the row of the connection pads 111. Note that when the width of the first power supply pattern 414 (the length in the second direction) is larger, the routing direction of the wires 114 approaches parallel, and the length difference between the wires 114 (cause of skew) is reduced. However, this increases the size of the semiconductor device. Therefore, it is desirable to increase the arrangement interval of the chip pads 106 as much as possible and to reduce the width (second direction length) of the first power supply pattern 414 as much as possible.

  A plurality of second power supply patterns 415 are formed in the fourth area 404. The width (area per unit length) of the second power supply pattern 415 is sufficiently larger than the wiring pattern. Each of the second power supply patterns 415 is disposed between two adjacent signal wiring patterns 411a. In other words, each of the second power supply patterns 415 is arranged along one of the signal wiring patterns 411a and spaced from the signal wiring pattern 411. In the example shown in the drawing, a plurality of second power supply patterns 415 are arranged alternately between a plurality of signal wiring patterns 411a. However, the number of the second power supply patterns 415 may be larger than this, for example, all of the plurality of signal wiring patterns 411a. In any case, the second power supply pattern 415 is provided so that the three signal wiring patterns 411a are not lined up continuously. That is, the second power supply pattern 415 is arranged such that any one of the power supply solid pattern 412, the grounding solid pattern 413, and the second power supply pattern 415 is arranged on at least one of both sides of each signal wiring pattern 411a. Is done. The second power supply pattern 415 may be a conductive pattern formed continuously on the ground solid pattern 413.

  Each of the second power supply patterns 415 is connected to the first power supply pattern 414 via a third power supply pattern 416 formed so that the tip end portion thereof crosses the first area 401. The reason why the third power supply pattern 416 is indicated by a broken line is to distinguish it from the wiring pattern connected to the connection pad 111. Each of the third power supply patterns 416 is not connected to any of the connection pads 111, and is adjacent to two signal connection pads (first and second chip pads corresponding to the first and second chip pads, respectively). (Connection pad) 111a. The third power supply pattern 416 may be formed with the same width as the wiring pattern, or may be configured wider than that. However, if the width of the third power supply pattern 416 is too large, the advantage of not being connected to the connection pad 111 is lost, so the width of the second power supply pattern 415 is made smaller.

  As described above, at least one second power supply pattern 415 (or ground solid pattern 413) is disposed in proximity to each of the signal wiring patterns 411a. Then, the second power supply pattern 415 is electrically connected to the first power supply pattern 414 via the third power supply pattern 416 at the tip portion. According to this configuration, interference between the signal wiring patterns 411a is suppressed, and deterioration of signal quality can be prevented. Further, since the third power supply pattern 416 is arranged between the signal connection pads 111a without providing a ground pad, it is possible to avoid an increase in signal path and to suppress an increase in skew of various signals. it can.

  FIG. 5 is a diagram showing a wiring pattern around the connection pad 111 of the semiconductor device according to the first example of the present invention. In FIG. 5, the chip pad 106 and the wire 114 are omitted. Hereinafter, differences from FIG. 4 will be described.

  In the semiconductor device of the present embodiment, as shown in the drawing, the first and second power connection pads 111b1 corresponding to the first and second power supply voltages (VDD1, VDD2) different from each other as the power connection pads 111b. , 111b2 are provided.

  First and second power supply voltages for supplying first and second power supply voltages (VDD1 and VDD2) as a power supply solid pattern 412 so as to correspond to the first and second power supply connection pads 111b1 and 111b2. Solid patterns 412a and 412b are provided.

  The first power connection pad 111b1 is connected to the first power solid pattern 412a via the power wiring pattern 411b1. The second power connection pad 111b2 is connected to the second power solid pattern 412b or the through via 417 via the power wiring pattern 411b2.

  FIG. 5 shows two first solid patterns 412a for power supply, but these patterns are electrically connected to each other in a region not shown, for example, on the other surface side of the wiring board 101. ing. The same applies to the second power solid pattern 412b. In addition, the second power supply solid pattern 412 b is also electrically connected to the plurality of through vias 417. The first power supply pattern 414 and the second power supply pattern 415 (and the third power supply pattern 416) are formed as conductive patterns that are continuous with the grounding solid pattern 413.

  In an actual wiring pattern, each signal wiring pattern 411a is bent and disposed substantially obliquely with respect to the first direction in which the connection pads 111 are arranged. In accordance with the arrangement of the signal wiring pattern 411a, the second power supply pattern 415 is also arranged substantially obliquely. However, the shapes of the signal wiring pattern 411a and the second power supply pattern 415 can be arbitrarily set.

  Each second power supply pattern 415 is formed in a polygonal shape instead of a rectangle, and is formed so as to match the shape of the signal wiring pattern 411a as much as possible. Each third power supply pattern 416 is connected to the vicinity of the tip of the corresponding second power supply pattern 415, passes between two adjacent signal connection pads 111a, and is not connected to any signal connection pad 111a. Are connected to the first power supply pattern 414.

  As described above, according to the present embodiment, the second conductive pattern is arranged close to the signal wiring pattern 411a, and the second conductive pattern 415 occupies a relatively large area of the first power supply pattern 414 (and the ground). Solid pattern 413). Therefore, interference between the signal wiring patterns 411a is suppressed, and deterioration of signal quality is prevented. In addition, the third power supply pattern 416 that is not connected to any of the connection pads 111 is used for the connection between the tip of the second conductor pattern 415 and the first power supply pattern 414, so that the signal connection pads 111a are connected. There is no need to provide the power connection pad 111b and the ground connection pad 111c. Thereby, since the length of the row | line | column of the connection pad 111c can be shortened, the difference of the length between the wires 114 can be reduced, and the increase in the skew between signals can be avoided.

  Although the present invention has been described with reference to the embodiment, the present invention is not limited to the above embodiment, and various modifications and changes can be made. For example, the present invention can be applied to a semiconductor device having a structure other than the POP structure as long as a wire is used to connect the chip pad and the connection pad. The present invention can also be applied to semiconductor devices other than semiconductor memory devices.

1000 Semiconductor Device 100 Upper Package 101 Wiring Board 102 First Semiconductor Chip 103 Second Semiconductor Chip 104 Solder Ball 105 Adhesive Member 106 Chip Pad 106a Signal Chip Pad 106b Power Supply Chip Pad 106c Ground Chip Pad 107 Adhesive Member 108 Chip Pad 109 Insulating substrate 110 Insulating film 111 Connection pad 111a Signal connection pad 111b Power connection pad 111b1 First power connection pad 111b2 Second power connection pad 111c Ground connection pad 112 Land 113 Through via 114 Wire 115 Sealed body 200 Lower package 201 Wiring board 202 Controller chip 203 Land 204 Solder ball 401 First area 402 Second area 403 Third area 404 4th area 411a Signal wiring pattern 411b, 411b1, 411b2 Power supply wiring pattern 411c Grounding wiring pattern 412 Power supply solid pattern 412a First power supply solid pattern 412b Second power supply solid pattern 413 Grounding solid pattern 414 First power supply pattern 415 Second power supply pattern 416 Third power supply pattern 417 Through via

Claims (10)

A semiconductor chip including first and second chip pads;
A first area in which a plurality of connection pads including first and second connection pads connected in correspondence with the first and second chip pads are formed in a first direction; and the semiconductor A second area on which a chip is mounted; a third area located between the first area and the second area; and a position opposite to the third area with respect to the first area. A fourth area, first and second power supply patterns formed corresponding to the third and fourth areas, respectively, and the first and second power supply patterns across the first area. A wiring board including a third power supply pattern for mutually connecting the power supply patterns,
The semiconductor device, wherein the third power supply pattern is arranged between the first and second connection pads without being connected to any of the plurality of connection pads. The first and second chip pads are disposed along a first side of the semiconductor chip,
The semiconductor chip is mounted on the second area so that the first side is parallel to the first direction.
The semiconductor device according to claim 1.   The semiconductor device according to claim 2, wherein the semiconductor chip is mounted in the second area such that the first side faces the third area. The semiconductor chip includes a plurality of chip pads including the first and second chip pads,
The plurality of chip pads are arranged in a line along the first side, and the first and second chip pads are adjacent to each other.
The semiconductor device according to claim 2, wherein:   At least some of the plurality of connection pads are arranged at a predetermined minimum interval, and an interval between the first connection pad and the second connection pad is wider than the minimum interval. The semiconductor device according to claim 1. The wiring board further includes a plurality of wiring patterns respectively connected to at least a part of the plurality of connection pads and extending to the fourth area;
6. The semiconductor device according to claim 5, wherein the second power supply pattern is arranged at a distance along at least one of both sides of each of the plurality of wirings.   7. The semiconductor device according to claim 1, wherein a width of the third power supply pattern in the first direction is narrower than a width of the connection pad in the first direction. 8.   The first power supply pattern is formed so as to overlap with at least a part of each of the bonding wires connected to the plurality of connection pads in a plan view. The semiconductor device described.   9. The semiconductor device according to claim 1, wherein the plurality of connection pads include a power supply connection pad and a ground connection pad. A first area in which a plurality of connection pads are formed;
A second area for mounting a semiconductor chip including a plurality of chip pads respectively connected to the plurality of connection pads by bonding wires;
A third area formed between the first area and the second area and formed with a first power supply pattern that overlaps a part of each of the bonding wires in plan view;
A fourth area adjacent to the first area and formed with a wiring pattern connected to each of the plurality of connection pads and at least one second power supply pattern disposed therebetween; Including a wiring board comprising,
The first power supply pattern and the second power supply pattern are formed so as to cross the first area, and are connected by a third power supply pattern that is electrically independent from the plurality of connection pads. Yes,
A semiconductor device.

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