JP2015103547A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a size of a semiconductor device mounting a plurality of semiconductor chips.SOLUTION: In a semiconductor device, a memory chip 102a and a memory chip 102b are mounted on a wiring board 106. On the memory chip 102a, a plurality of electrode pads 116 are arranged along a first side L1 and a third side L3. On the memory chip 102b, a plurality of electrode pads 116 are arranged along a fifth side L5 and a seventh side L7. The electrode pad 116 is connected with a connection pad 110 provided on the wiring board 106 via a bonding wire 118. On the wiring board 106, the memory chip 102a and the memory chip 102b are arranged in directions reverse to each other so that a second side L2 and a sixth side L6 are facing each other. In addition, the memory chip 102a and the memory chip 102b are arranged while being offset in a y-direction.

Description

  The present invention relates to a semiconductor device on which a plurality of semiconductor chips are mounted.

  The storage capacity required for semiconductor devices such as DRAM (Dynamic Random Access Memory) is increasing year by year. In recent years, a method of mounting a plurality of semiconductor chips (memory chips) on a single package substrate has also been proposed. A plurality of semiconductor chips may be stacked on the package substrate or may be juxtaposed (see Patent Documents 1 to 3).

JP 2008-130998 A JP 2009-088083 A JP 2009-260373 A

  Usually, in a semiconductor chip, a plurality of electrode pads are arranged along two long sides or short sides. These electrode pads are connected to connection pads on the package substrate by bonding wires. Since it is necessary to form a plurality of connection pads on the package substrate, it is necessary to form a certain margin area around the area where the semiconductor chip is arranged. This margin region is a factor that increases the size of the semiconductor device.

  The semiconductor device according to the present embodiment includes a first side and a second side extending in a first direction, a third side and a fourth side extending in a second direction intersecting the first direction, a first side, A first semiconductor chip having a plurality of first electrode pads arranged along each of the third sides, a fifth side and a sixth side extending in the first direction, and extending in the second direction A second semiconductor chip having a seventh side and an eighth side, and a plurality of second electrode pads arranged along the fifth side and the seventh side, and bonding with the first and second electrode pads; A package substrate having a plurality of connection pads connected via wires. The first and second semiconductor chips are mounted on the package substrate so that the second side and the sixth side face each other.

  According to the present invention, the planar size of a semiconductor device on which a plurality of semiconductor chips are mounted can be reduced.

It is sectional drawing of the semiconductor device in this embodiment. It is a schematic plan view when two memory chips are juxtaposed on the wiring board in the present embodiment. 7 is a schematic plan view showing the arrangement of memory chips in Comparative Example 1. FIG. 12 is a schematic plan view showing the arrangement of memory chips in Comparative Example 2. FIG. It is sectional drawing of a rewiring layer. It is a 1st top view when rewiring is carried out. It is a 2nd top view when rewiring is carried out. In the 1st modification of this embodiment, it is a schematic plan view when two memory chips are juxtaposed on a wiring board. In the 2nd modification of this embodiment, it is a schematic plan view when two memory chips are juxtaposed on a wiring board. In the 3rd modification of this embodiment, it is a schematic plan view when a some power distribution board is combined.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a cross-sectional view of a semiconductor device 100 according to this embodiment. The semiconductor device 100 includes a wiring board 106, two memory chips 102a (first semiconductor chip) and a memory chip 102b (second semiconductor chip) mounted thereon. The wiring substrate 106 (package substrate) is a substrate having a thickness of about 90 μm in which a wiring pattern is formed on the surface of an insulating base material 104 such as a glass epoxy substrate. Both surfaces of the insulating substrate 104 are covered with an insulating film 108 (solder resist film). Most of the wiring pattern is covered with the insulating film 108, but a part is exposed. The exposed wiring pattern is the connection pad 110 and the land 112. The connection pad 110 is disposed so as to surround a region where the memory chips 102a and 102b are disposed (see also FIG. 2 and the like). The connection pad 110 and the land 112 are electrically connected by a through-hole conductor (not shown) penetrating the insulating substrate 104. Solder balls 114 (external terminals) are connected to the lands 114.

  The memory chips 102 a and 102 b are juxtaposed at the center of the wiring board 106 and bonded to the wiring board 106 by an adhesive member 122. These memory chips in this embodiment are assumed to be DRAM (Dynamic Random Access Memory) memory chips having the same size and storage capacity. Each of the memory chips 102a and 102b is a plate-shaped chip having a rectangular surface. In each of the memory chips 102a and 102b, a memory circuit is formed on one surface of a silicon substrate, and a plurality of electrode pads 116 are arranged.

  The electrode pads 116 of each memory chip 102 are connected to the connection pads 110 by bonding wires 118 and are also electrically connected to the solder balls 114 through through-hole conductors and lands 112. The memory chip 102 is covered with a sealing resin 120 that is a thermosetting resin. The sealing resin 120 is, for example, MUF (Mold Underfill). The sealing resin 120 may be an epoxy resin including a filler having a size of less than 10 μm.

  FIG. 2 is a schematic plan view when the memory chips 102a and 102b are juxtaposed on the wiring board 106 in the present embodiment. The memory chip 102a has a first side L1 and a second side L2 as long sides, and has a third side L3 and a fourth side L4 as short sides. A plurality of electrode pads 116 are arranged along the first side L1 and the third side L3. The electrode pad 116 is used for supplying a power supply voltage from the wiring board 106 and transmitting / receiving various control signals and data signals. Similarly, the memory chip 102b has a fifth side L5 and a sixth side L6 as long sides, and has a seventh side L7 and an eighth side L8 as short sides. A plurality of electrode pads 116 are arranged along the fifth side L5 and the seventh side L7. In this way, the package can be thinned by placing the memory chips 102a and 102b flat.

  The electrode pad 116 is connected to a connection pad 110 formed on the wiring substrate 106 via a bonding wire 118. Since the memory chip 102a and the memory chip 102b have the same size and shape, the memory chip 102b is placed in a direction rotated by 180 degrees with respect to the memory chip 102a.

  When the margin necessary for the arrangement of the connection pads 110 is M, the memory chip 102a and the memory chip 102b are shifted by M in the y-axis direction. The magnitude of the shift may be less than M or greater than or equal to M, but it is preferable to shift by M for reasons described later. For this reason, the third side L3 and the eighth side L8 are not aligned on a straight line. For the same reason, the fourth side L4 and the seventh side L7 are not aligned on a straight line. It can be said that the memory chip 102a is shifted toward the fourth side L4 as compared with the memory chip 102b.

  FIG. 3 is a schematic plan view showing the arrangement of the memory chip 102 in the first comparative example. In FIG. 3, electrode pads 116 are arranged along the first side L1 and the second side L2, which are the two long sides of the memory chip 102a. Similarly, in the memory chip 102b, electrode pads 116 are arranged along the fifth side L5 and the sixth side L6, which are two long sides. Therefore, it is necessary to arrange the connection pads 110 for two columns between the memory chip 102a and the memory chip 102b. In the arrangement example of FIG. 3, it is not necessary to secure a margin in the y direction, but a margin of 4M is required in the x direction.

  FIG. 4 is a schematic plan view showing the arrangement of the memory chip 102 in the second comparative example. In FIG. 4, as in the present embodiment, electrode pads 116 are arranged along the first side L1 and the second side L2 of the memory chip 102a, and along the fifth side L5 and the seventh side L7 of the memory chip 102b. Electrode pads 116 are arranged. Unlike the present embodiment, the memory chip 102a and the memory chip 102b are not shifted in the y direction. For this reason, in the arrangement example of FIG. 4, a 2M margin is required in both the y direction and the x direction.

  In FIG. 3, since the electrode pads 116 are provided on both long sides of the memory chip 102, a plurality of electrode pads 116 are arranged near the center of the wiring substrate 106, that is, near the center of the semiconductor package. . On the other hand, when the solder balls 114 of the package are provided on the outer peripheral portion of the package, there is a problem that the wiring connecting the electrode pads 116 and the solder balls 114 becomes long.

  On the other hand, in FIG. 4, electrode pads 116 are arranged along the sides L1 and L3 of the memory chip 102a. That is, the electrode pad 116 is arranged in an L shape on the memory chip 102. When one of the memory chips 102a and 102b is inverted 180 degrees and the memory chips are opposed to each other as shown in FIG. The electrode pad 116 is not disposed in the vicinity of the center. Therefore, according to the layout of FIG. 4, the wiring connecting the electrode pad 116 and the solder ball 114 can be shortened. The same applies to FIG. By shortening the wiring such as the signal wiring, the power supply, and the ground wiring, the signal waveform quality can be maintained and the demand for high speed can be satisfied. Therefore, according to FIG. 2 and FIG. 4, it is possible to provide a semiconductor memory device that can satisfy the demand for thinness and high speed.

  Returning to FIG. In FIG. 2, the memory chip 102a and the memory chip 102b are shifted by M in the y direction. For this reason, the connection pads 110 arranged along the third side L3 of the memory chip 102a do not protrude downward (y-axis negative direction) from the eighth side L8 of the memory chip 102b. Similarly, the connection pads 110 arranged along the seventh side L7 of the memory chip 102b do not protrude upward (y-axis positive direction) from the fourth side L4. As a result, in the arrangement method in this embodiment of FIG. 2, the margin required in the y direction is M, and the margin required in the x direction is 2M.

  Assuming that the length of the first side L1 that is the long side is LL and the length of the third side L3 that is the short side is LS, the area that the wiring board 106 according to the present embodiment should secure to the minimum is (2LS + 2M) × (LL + M). In the case of the comparative example 1 in FIG. 2, (2LS + 4M) × LL, and in the case of the comparative example 2 in FIG. 3, (2LS + 2M) × (LL + 2M). Therefore, the arrangement method in the present embodiment can always reduce the size of the wiring board 106 as compared with the comparative example 2, and if M does not become extremely large (if LS + M> LL is not satisfied), the wiring board as compared with the comparative example 1. The size of 106 can be reduced. Usually, M is sufficiently smaller than LS, and therefore the arrangement method of the present embodiment can reduce the size of the wiring board 106 as compared with Comparative Example 1.

  FIG. 5 is a cross-sectional view of the rewiring layer 126. In the memory chip 102 of this embodiment, the electrode pads 116 are arranged in an L shape, but generally the electrode pads (internal electrodes 128) of the memory chip 102 are along two long sides or short sides. It is often arranged or arranged in the center. In such a case, the planar position of the electrode pad 116 may be moved by the rewiring layer 126.

In the memory chip 102 illustrated in FIG. 5, a rewiring layer 126 is formed on the circuit layer 124. Then, the internal electrode 128 installed in the circuit layer 124 is connected to the electrode pad 116 at another position by the wiring 130 of the rewiring layer 126, so that the planar position for connecting to the bonding wire 118 is different from that of the internal electrode 128. It is moved to the plane position.

  FIG. 6 is a first plan view when rewiring is performed. In the case of FIG. 6, the internal electrodes 128 are arranged along the first side L1 and the second side L2. In a DRAM mounted on a mobile, the internal electrode 128 may be arranged along the two long sides as described above. In this case, the internal electrodes 128 arranged on the second side L2 may be rewired to the third side L3 side by the wiring 130. The internal electrode 128 on the first side L1 side is rewired to the electrode pad 116 on the first side L1 side as it is.

  FIG. 7 is a second plan view when rewiring is performed. In the case of FIG. 7, the internal electrodes 128 are arranged in two rows at the center of the memory chip 102a along the y-axis direction. In this case, it is necessary to redistribute the central internal electrode 128 on the first side L1 side and the third side L3 side, respectively.

  FIG. 8 is a schematic plan view when the memory chips 102a and 102b are juxtaposed on the wiring board 106 in the first modification of the present embodiment. As shown in FIG. 8, the memory chip 102a may be shifted downward (y-axis negative direction) with respect to the memory chip 102b. With such an arrangement method, the space 132 may be secured above the fourth side L4 or below the eighth side L8, and various circuit elements such as discrete passive elements may be arranged here.

  FIG. 9 is a schematic plan view when the memory chips 102a and 102b are juxtaposed on the wiring board 106 in the second modification of the present embodiment. In FIG. 9, the two memory chips 102 are arranged so that the short sides rather than the long sides of the memory chip 102 face each other. Such an arrangement method is also possible when the wiring board 106 has a shape that is long in the x direction.

  FIG. 10 is a schematic plan view and a cross-sectional view when the memory chips 102a and 102b are respectively arranged on the two wiring boards 106a and 102b in the third modification of the present embodiment. The memory chip 102a is mounted on the wiring board 106a, and the memory chip 102b is mounted on another wiring board 106b. A controller chip 134 is mounted on the wiring board 106c, and the wiring board 106a and the wiring board 106c, and the wiring board 106b and the wiring board 106c are connected by a bump 136 or a bonding wire (not shown). The controller chip 134 may be mounted face up on the wiring board 106c or may be mounted face down.

  A single-channel FPGA (Field-Programmable Gate Array) may be formed on each of the wiring boards 106a and 106b, and these may be combined to mount two FPGAs. When a circuit for two channels is formed on one wiring board 106, if any one of the channels is defective, the two-channel package becomes defective even if the other channel is non-defective. However, when two wiring boards 106 corresponding to one channel are combined, such a problem does not occur, and the cost can be reduced.

  The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range.

DESCRIPTION OF SYMBOLS 100 Semiconductor device 102 Memory chip 104 Insulating base material 106 Wiring board 108 Insulating film 110 Connection pad 112 Land 114 Solder ball 116 Electrode pad 118 Bonding wire 120 Sealing resin 122 Adhesive member 124 Circuit layer 126 Rewiring layer 128 Internal electrode 130 Wiring 132 space

Claims (6)

A first side and a second side extending in a first direction; a third side and a fourth side extending in a second direction intersecting the first direction; and the first side and the third side, respectively. A first semiconductor chip having a plurality of first electrode pads arranged along;
The fifth side and the sixth side extending in the first direction, the seventh side and the eighth side extending in the second direction, and the fifth side and the seventh side, respectively. A second semiconductor chip having a plurality of second electrode pads;
A package substrate having a plurality of connection pads connected to the first and second electrode pads via bonding wires;
The semiconductor device, wherein the first and second semiconductor chips are mounted on the package substrate so that the second side and the sixth side face each other.   2. The semiconductor device according to claim 1, wherein the first and second semiconductor chips are shifted from each other in the first direction.   3. The semiconductor device according to claim 2, wherein the first semiconductor chip is arranged to be shifted to the fourth side, and the second semiconductor chip is shifted to the eighth side.   A part of the plurality of connection pads is arranged along the third side, and a part of the connection pad is arranged so as not to protrude in the first direction from the eighth side. Item 4. The semiconductor device according to Item 3.   The semiconductor device according to claim 1, wherein the first direction is a long side direction of the first and second semiconductor chips.   The first semiconductor chip includes a redistribution layer for connecting a plurality of internal electrodes to the plurality of first electrode pads arranged along the first side and the third side. The semiconductor device according to claim 1.

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