JP5785330B2 - メモリエンデュランスのために動作させる装置および方法 - Google Patents
メモリエンデュランスのために動作させる装置および方法 Download PDFInfo
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- JP5785330B2 JP5785330B2 JP2014528595A JP2014528595A JP5785330B2 JP 5785330 B2 JP5785330 B2 JP 5785330B2 JP 2014528595 A JP2014528595 A JP 2014528595A JP 2014528595 A JP2014528595 A JP 2014528595A JP 5785330 B2 JP5785330 B2 JP 5785330B2
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- 230000015654 memory Effects 0.000 title claims description 184
- 238000000034 method Methods 0.000 title claims description 53
- 238000013507 mapping Methods 0.000 description 16
- 230000001627 detrimental effect Effects 0.000 description 10
- 238000010586 diagram Methods 0.000 description 10
- 238000003860 storage Methods 0.000 description 9
- 238000013459 approach Methods 0.000 description 5
- 238000007792 addition Methods 0.000 description 3
- 238000004364 calculation method Methods 0.000 description 3
- 238000013144 data compression Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000007906 compression Methods 0.000 description 2
- 230000006835 compression Effects 0.000 description 2
- 238000013500 data storage Methods 0.000 description 2
- 230000006837 decompression Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000007667 floating Methods 0.000 description 1
- 125000000524 functional group Chemical group 0.000 description 1
- 231100001261 hazardous Toxicity 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004242 micellar liquid chromatography Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920001690 polydopamine Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 210000003813 thumb Anatomy 0.000 description 1
- 238000013519 translation Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
- G11C16/3495—Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/102—External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/349—Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7204—Capacity control, e.g. partitioning, end-of-life degradation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/72—Details relating to flash memory management
- G06F2212/7211—Wear leveling
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- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
Claims (15)
- 第2のデータ状態に比べてメモリセル摩耗にとってより有害である第1のデータ状態によって表される第1の数量のデジットを有するmデジットのデータを受信すること、
前記mデジットのデータをnデジットのデータにエンコードすることであって、前記nデジットのデータは、前記第1のデータ状態によって表される第2の数量のデジットを有し、nはmより大きく、かつ、前記mデジットのデータの考えられる全ての組合せにおいて、前記第2の数量は、前記第1の数量以下である、符号化(encode)すること、および、
前記nデジットのデータを、メモリセルを有する装置に記憶することを含む方法。 - 前記装置から前記nデジットのデータを取出すこと、および、
前記nデジットのデータを前記mデジットのデータに復号することをさらに含む請求項1に記載の方法。 - 前記装置はメモリデバイスを備え、ホストと前記メモリデバイスとの間で前記nデジットのデータを通信することをさらに含み、前記符号化することおよび前記復号することは、前記ホストで起こる請求項2に記載の方法。
- 前記nデジットのデータは、w1〜w2の範囲内で前記第1のデータ状態によって表される、ある数量のデジットを有し、w2は、w1以上であり、
前記nデジットのデータをmデジットのデータに復号することは、
最上位デジットb1で始めて最下位デジットbnまで、各デジットbiについて、数量
前記nデジットのデータに対応する前記mデジットのデータについて等価な整数として値
- 前記方法は、前記nデジットのデータを前記メモリデバイスに記憶することをさらに含み、w1は0より大きく、w2はn以下である請求項4に記載の方法。
- w2はn/2以下である請求項5に記載の方法。
- 前記装置はメモリデバイスを備え、ホストと前記メモリデバイスとの間で前記mデジットのデータを通信することをさらに含み、前記符号化することおよび前記復号することは、前記メモリデバイスで起こる請求項2に記載の方法。
- 前記nデジットのデータは、ある集合Sの考えられるコードワードの1つのコードワードであり、|S|は、集合S内のコードワード要素の数量であり、m=floor(log2|S|)である請求項9に記載の方法。
- 装置であって、
メモリと、
コントローラと
を備え、前記コントローラは、前記メモリに通信可能に結合され、
第2のデータ状態に比べてメモリセル摩耗にとってより有害である第1のデータ状態によって表される第1の数量のデジットを有するmデジットのデータを受信し、
前記mデジットのデータをnデジットのデータにエンコードし、前記nデジットのデータは、前記第1のデータ状態によって表される第2の数量のデジットを有し、nはmより大きく、かつ、前記mデジットのデータの考えられる全ての組合せにおいて、前記第2の数量は、前記第1の数量以下であり、
前記nデジットのデータを、メモリセルを有する前記メモリに記憶する
ように構成される装置。 - 前記nデジットのデータは、異なるnデジットのデータの集合Sの要素であり、mは、floor(log2|S|)以下である請求項11に記載の装置。
- それぞれのmデジットのデータは、列挙コーディングを使用して前記異なるnデジットのデータの集合Sの一意のnデジットのデータに関連付けられる請求項12に記載の装置。
- 前記コントローラは、集合Sの前記nデジットのデータのそれぞれを、対応するmデジットのデータに復号するようにさらに構成される請求項13に記載の装置。
- mはfloor(log2|S|)に等しい、請求項14に記載の装置。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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US13/222,942 | 2011-08-31 | ||
US13/222,942 US8495285B2 (en) | 2011-08-31 | 2011-08-31 | Apparatuses and methods of operating for memory endurance |
PCT/US2012/053107 WO2013033375A1 (en) | 2011-08-31 | 2012-08-30 | Apparatuses and methods of operating for memory endurance |
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Publication Number | Publication Date |
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JP2014529827A JP2014529827A (ja) | 2014-11-13 |
JP5785330B2 true JP5785330B2 (ja) | 2015-09-30 |
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JP2014528595A Active JP5785330B2 (ja) | 2011-08-31 | 2012-08-30 | メモリエンデュランスのために動作させる装置および方法 |
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US (3) | US8495285B2 (ja) |
EP (1) | EP2751659A4 (ja) |
JP (1) | JP5785330B2 (ja) |
KR (1) | KR101508890B1 (ja) |
CN (1) | CN103782266B (ja) |
WO (1) | WO2013033375A1 (ja) |
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US9489294B2 (en) | 2013-06-19 | 2016-11-08 | Sandisk Technologies Llc | Data encoding for non-volatile memory |
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JP6346123B2 (ja) * | 2015-05-25 | 2018-06-20 | 東芝メモリ株式会社 | コントローラ、制御方法 |
US9996299B2 (en) * | 2015-06-25 | 2018-06-12 | Western Digital Technologies, Inc | Memory health monitoring |
US10445251B2 (en) | 2015-07-14 | 2019-10-15 | Western Digital Technologies, Inc. | Wear leveling in non-volatile memories |
US9921969B2 (en) | 2015-07-14 | 2018-03-20 | Western Digital Technologies, Inc. | Generation of random address mapping in non-volatile memories using local and global interleaving |
US10445232B2 (en) | 2015-07-14 | 2019-10-15 | Western Digital Technologies, Inc. | Determining control states for address mapping in non-volatile memories |
US10452560B2 (en) | 2015-07-14 | 2019-10-22 | Western Digital Technologies, Inc. | Wear leveling in non-volatile memories |
US10452533B2 (en) | 2015-07-14 | 2019-10-22 | Western Digital Technologies, Inc. | Access network for address mapping in non-volatile memories |
US10114549B2 (en) | 2016-03-17 | 2018-10-30 | Sandisk Technologies Llc | Error correction code processing and data shaping for reducing wear to a memory |
US9865353B1 (en) * | 2016-08-02 | 2018-01-09 | Kabushiki Kaisha Toshiba | Cell location programming for storage systems |
US10566052B2 (en) | 2017-12-22 | 2020-02-18 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
US10431301B2 (en) | 2017-12-22 | 2019-10-01 | Micron Technology, Inc. | Auto-referenced memory cell read techniques |
KR20210013397A (ko) | 2019-07-24 | 2021-02-04 | 삼성전자주식회사 | 스토리지 장치 |
EP3783611B1 (en) * | 2019-07-24 | 2023-02-22 | Samsung Electronics Co., Ltd. | Storage device that performs state shaping of data |
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2011
- 2011-08-31 US US13/222,942 patent/US8495285B2/en active Active
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2012
- 2012-08-30 EP EP20120829034 patent/EP2751659A4/en not_active Ceased
- 2012-08-30 WO PCT/US2012/053107 patent/WO2013033375A1/en active Application Filing
- 2012-08-30 JP JP2014528595A patent/JP5785330B2/ja active Active
- 2012-08-30 CN CN201280042115.6A patent/CN103782266B/zh active Active
- 2012-08-30 KR KR1020147006477A patent/KR101508890B1/ko active IP Right Grant
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2013
- 2013-07-23 US US13/948,830 patent/US8762630B2/en active Active
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- 2014-05-22 US US14/284,825 patent/US9105350B2/en active Active
Also Published As
Publication number | Publication date |
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US20130054876A1 (en) | 2013-02-28 |
CN103782266A (zh) | 2014-05-07 |
US20130311714A1 (en) | 2013-11-21 |
EP2751659A1 (en) | 2014-07-09 |
KR20140046070A (ko) | 2014-04-17 |
KR101508890B1 (ko) | 2015-04-07 |
EP2751659A4 (en) | 2015-04-22 |
US8495285B2 (en) | 2013-07-23 |
JP2014529827A (ja) | 2014-11-13 |
US9105350B2 (en) | 2015-08-11 |
WO2013033375A1 (en) | 2013-03-07 |
US20140337564A1 (en) | 2014-11-13 |
CN103782266B (zh) | 2017-02-15 |
US8762630B2 (en) | 2014-06-24 |
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