JP5779695B2 - Semiconductor device, display device, and electronic device - Google Patents

Description

The present invention relates to a display device and a driving circuit thereof. Note that in this specification, a display device includes a liquid crystal display device using a liquid crystal element for a pixel and a light-emitting device using a light-emitting element such as an electroluminescence (EL) element.
A driving circuit of a display device refers to a circuit that inputs a video signal to a pixel arranged in the display device and performs processing for displaying a video, such as a shift register circuit, a latch circuit, a buffer circuit, and a level shift circuit And an amplifier circuit including an amplifier and the like.

In recent years, a display device in which a semiconductor thin film is formed on an insulator such as a glass substrate, particularly an electronic circuit using a thin film transistor (hereinafter referred to as TFT) has been used in various fields.
In particular, active matrix display devices such as LCDs (liquid crystal displays) are often used in display devices and are widely used. An active matrix display device using TFTs has hundreds of thousands to millions of pixels arranged in a matrix, and displays the image by controlling the charge of each pixel by the TFT arranged in each pixel. It is carried out.

Furthermore, as a recent technology, in addition to the pixel TFT constituting the pixel, TF is provided in the peripheral region of the pixel portion.
The technology related to polysilicon TFTs that simultaneously form a drive circuit on a substrate using T has been developed, which has greatly contributed to downsizing and low power consumption of the device. A display device has become an indispensable device for a display unit of a mobile information terminal.

By the way, display devices have recently been adopted in display units of various electronic devices, and their fields of use are steadily expanding. Recently, it has been actively adopted in relatively inexpensive electronic devices,
Further cost reduction is desired.

In general, a CMOS circuit in which an N-channel TFT and a P-channel TFT are combined is used as a circuit constituting a driving circuit of a display device. However, a display device uses film formation → photomask exposure → etching. In order to form a multi-layer structure by repeating the above process, the manufacturing process is increased due to the extremely complicated process. Furthermore, when the drive circuit and the pixel portion are integrally formed on the substrate as described above, the yield is greatly affected in that some defects become defects in the entire product.

One method for reducing the manufacturing cost is to reduce the number of steps as much as possible and to be able to manufacture easily and in a short period of time. In view of this, the structure of the driver circuit is not a CMOS structure but a structure using a single polarity TFT of either an N-channel TFT or a P-channel TFT, and a display device is manufactured. As a result, the process of adding impurities to impart conductivity to the semiconductor layer can be simply halved, and the number of photomasks can be reduced, which is very effective. Moreover, since the manufacturing process is simplified, it contributes to the improvement of yield.

FIG. 2 shows an example of an inverter constituted by two N-channel TFTs. TFT20
A two-input type in which signals are input to the gate electrodes 1 and 202, and an inverted signal of one input signal is the other input.

Here, the operation of the inverter shown in FIG. 2 will be briefly described. In this specification, when describing the configuration and operation of the circuit, the names of the three electrodes of the TFT are “gate electrode, input electrode, output electrode” and “gate electrode, source region, drain region”. Use properly.
This is because the gate-source voltage is often considered when explaining the operation of the TFT.
This is because the source region and the drain region of the FT are difficult to clearly distinguish from each other due to the structure of the TFT, and there is a possibility that confusion may occur conversely by unifying the names. When describing input / output of signals, they are called input electrodes and output electrodes. When describing the gate-source potential of a TFT, one of the input electrodes and output electrodes is the source region, and the other is the drain. It will be called an area.

The TFT is ON means that the gate-source voltage of the TFT exceeds the threshold voltage and current flows between the source and drain, and that the TFT is OFF means that the gate-source of the TFT. This is a state in which the inter-voltage is below the threshold voltage and no current flows between the source and drain. Regarding the threshold value, for the sake of simplicity, it is assumed that there is no variation among individual TFTs, the threshold value of the N-channel TFT is uniformly VthN, and the threshold value of the P-channel TFT is uniformly VthP. .

First, when an H level is input to the input terminal (In) and an L level is input to the inverting input terminal (Inb), the TFT 201 is turned off and the TFT 202 is turned on. Therefore, output terminal (Out)
, L level appears, and the potential becomes VSS. On the other hand, when the L level is input to the input terminal (In) and the H level is input to the inverting input terminal (Inb), the TFT 201 is turned on, and TF
T202 is turned OFF. Accordingly, an H level appears at the output terminal (Out).

  At this time, the potential when the output terminal (Out) becomes H level is considered.

In FIG. 2, when the H level is input to the gate electrode of the TFT 201, the TFT 2
The L level is input to the 02 gate electrode. Therefore, the TFT 201 is turned on and the TFT 2
02 turns off. Therefore, the potential of the output terminal (Out) starts to rise, but the output terminal (Out)
When the potential of t) becomes (VDD−VthN), the gate-source voltage of the TFT 201 becomes equal to the threshold value VthN. In other words, because the TFT 201 is turned off at this moment,
The potential of the output terminal (Out) cannot rise any further.

As shown in FIG. 12, a case where a plurality of inverters are connected is considered. 12A, only the first-stage inverter (InvA) is a 1-input 1-output type as shown in FIG. 12B, and the subsequent inverters (InvB) are 2 as shown in FIG. 12C. It is an input 1 output type. T
Since the gate electrode of the FT 1201 is connected to the high potential side power supply VDD and remains ON unless the gate-source voltage of the TFT 1201 falls below the threshold value, the output is completely VSS even if the TFT 1202 is turned ON. However, the current level of the TFT 1202 is sufficiently larger than the current capability of the TFT 1201, so that the L level can be output.

In such a case, even if the amplitude of the input signal is between VDD and VSS, the TFT 120
Due to the influence of the threshold values 1 and 1211, as shown in FIG.

Therefore, the present invention proposes a circuit that is composed of a unipolar TFT and that can operate without causing amplitude attenuation of the output signal as described above.

  In order to solve the above-described problems, the following measures are taken in the present invention.

In the inverter shown in FIG. 2, the output amplitude is attenuated because the potential applied to the gate electrode of the TFT 201 when the L level is input to the input terminal (In) and the H level is input to the inverting input terminal (Inb). Is the potential on the input electrode side of the TFT 201, that is, the high potential side power supply VDD
Therefore, the potential of the output terminal (Out) can only rise up to (VDD−VthN) at the maximum.

That is, when the H level appears at the output terminal (Out), the potential of the gate electrode of the TFT 201 is higher than VDD so that the potential becomes equal to VDD.
VthN) or more.

Therefore, the present invention solves the problem by raising the potential of the gate electrode of the TFT 201 to (VDD + VthN) by holding the charge corresponding to the threshold voltage of the TFT 201 in advance using a capacitor and adding it to the input signal.

The drive circuit for the display device of the present invention is a drive circuit for a display device having first to fourth transistors and capacitance means, and the first to fourth transistors are all of the same conductivity type. The first electrode of the capacitor means is electrically connected to the first signal input terminal, the second electrode is electrically connected to the gate electrode of the first transistor, and the gate of the second transistor The electrode is electrically connected to the second signal input terminal, the input electrode of the first transistor is electrically connected to the first power source, and the output electrode is electrically connected to the signal output terminal. The input electrode of the second transistor is electrically connected to a second power source, the output electrode is electrically connected to the signal output terminal, and the gate electrode and the output electrode of the third transistor are , Both of the above signals The output terminal is electrically connected, the input electrode is electrically connected to the second electrode of the capacitor means, and the gate electrode and the output electrode of the fourth transistor are both the second electrode of the capacitor means. The input electrode is electrically connected to the first electrode of the capacitor means.

The drive circuit for the display device of the present invention is a drive circuit for a display device having first to fourth transistors and capacitance means, and the first to fourth transistors are all of the same conductivity type. The first electrode of the capacitor means is electrically connected to the first signal input terminal, the second electrode is electrically connected to the gate electrode of the first transistor, and the gate of the second transistor The electrode is electrically connected to the second signal input terminal, the input electrode of the first transistor is electrically connected to the first power source, and the output electrode is electrically connected to the signal output terminal. The input electrode of the second transistor is electrically connected to a second power source, the output electrode is electrically connected to the signal output terminal, and the gate electrode and the output electrode of the third transistor are , Both of the above signals The output terminal is electrically connected, the input electrode is electrically connected to the second electrode of the capacitor means, and the gate electrode of the fourth transistor is electrically connected to the second electrode of the capacitor means. The input electrode is electrically connected to the first electrode of the capacitor means, and the output electrode is electrically connected to the signal output terminal.

The capacitor means is a capacitor means for holding a threshold voltage of the fourth transistor,
A potential obtained by adding the held voltage to the potential of a signal input from the first signal input terminal is applied to the gate electrode of the first transistor. As a result, the gate-source voltage of the first transistor is always greater than or equal to the threshold value, and an output can be obtained without causing amplitude attenuation.

In addition, the driving circuit of the display device of the present invention is characterized in that it is constituted by a unipolar transistor such as an N-channel transistor alone or a P-channel transistor. Thus, the manufacturing process of the display device can be simplified.

In the display device according to the aspect of the invention, the capacitor unit may be a capacitor unit using a capacitor between a gate electrode and an input electrode of the fourth transistor. Alternatively, it may be a capacitive means using any two of the active layer material, the material for forming the gate electrode, and the wiring material and the insulating layer between the two materials.

In the display device of the present invention, the signal input to the second signal input terminal is a signal whose polarity is inverted with respect to the signal input to the first signal input terminal. Thereby, even if the signal appearing at the output terminal is H level or L level,
Since no current path is generated in the circuit, current consumption can be reduced.

According to the circuit of the present invention, an output having an amplitude between VDD and VSS can be obtained normally without causing attenuation of amplitude with respect to an input of a signal having an amplitude between VDD and VSS.
Therefore, by using such a method for the driver circuit of the display device, a unipolar TFT can be used, which contributes to process reduction and manufacturing cost reduction.

3A and 3B illustrate a circuit configuration and an operation according to an embodiment of the present invention. The figure explaining the inverter comprised using unipolar TFT, and operation | movement. 6A and 6B illustrate a potential of each node during circuit operation in an embodiment of the present invention. The figure which shows the Example of this invention by the structure different from embodiment. FIG. 6 illustrates a cross-sectional structure of a bottom gate type TFT and a dual gate type TFT. FIG. 11 illustrates an example of an electronic device to which the present invention is applicable. 4A and 4B illustrate an example of a manufacturing process of a liquid crystal display device. 4A and 4B illustrate an example of a manufacturing process of a liquid crystal display device. 10A and 10B are diagrams illustrating an example of a manufacturing process of an active matrix substrate having a circuit including a P-channel TFT. 4A and 4B illustrate an example of a manufacturing process of a light-emitting device. 4A and 4B illustrate an example of a manufacturing process of a light-emitting device. The figure explaining the structure and the structure which connected the inverter comprised using single polarity TFT in multiple steps. FIG. 6 is a diagram showing an example in which a driver circuit of the present invention is configured using a P-channel TFT.

FIG. 1A shows a basic circuit configuration of the present invention. The circuit operates in the same manner as the inverter shown in FIG. 2, is a 2-input 1-output type, and a signal in which the polarity of the signal input to the input terminal (In) is inverted appears at the output terminal (Out). .

  The circuit is composed of TFTs 101 to 104 and capacitor means 105.

The operation of the circuit will be described. 3A and 3B show potentials at each node during operation. First, when an L level is input to the first input terminal (In1) and an H level is input to the second input terminal (In2), the TFT 102 is turned on, and the potential of the output terminal (Out) is pulled down to the VSS side. start. At this time, since the potential of the output terminal (Out) has not dropped to the L level, the TFT 103 is turned on, a current is generated from the output terminal (Out) toward the capacitor means 105, and the gate electrode of the TFT 104 is turned on. Since the potential rises, the TFT 104 is also turned on.
When the potential of the output terminal (Out) further decreases, the voltage between the gate and source of the TFT 103 becomes Vt.
It becomes equal to hN, and the TFT 103 is turned off. At this time, even when the TFT 104 is still ON, the electric charge charged in the capacitor means 105 is discharged through the TFT 104, and the gate-source voltage of the TFT 104 continues to decrease, so it will eventually turn OFF.

As a result, the threshold voltage VthN of the TFT 104 is held in the capacitor means 105. Since the first input terminal (In1) is at the L level and the potential is VSS, the TFT 10
The potential of the first gate electrode is higher than VSS by the voltage held by the capacitor means 105. That is, the potential of the gate electrode of the TFT 101 at this time is (VSS + VthN).
Since the L level appears at the output terminal (Out) and the potential is VSS, the TFT 10
1 has a gate-source voltage of VthN, and the TFT 101 is turned off (FIG. 3A).

Next, the operation when the H level is input to the first input terminal (In1) and the L level is input to the second input terminal (In2) will be described. First, since the second input terminal (In2) is changed from H level to L level, the TFT 102 is turned OFF. On the other hand, the first input terminal (In1) changes from the L level to the H level. At this time, the TFT 103 remains in an OFF state.
The movement of the charge held in the capacitor means 105 does not occur. For the TFT 104, the potential of the source region increases, but the gate-source voltage remains at VthN.
It remains in the OFF state. Therefore, even when the first input terminal changes from the L level to the H level, the voltage between both electrodes of the capacitor means 105 remains held. Therefore, since the potential of the first input terminal (In1) rises from VSS to VDD, the potential of the gate electrode of the TFT 101 rises from (VSS + VthN) to (VDD + VthN). Therefore, the output terminal
An H level appears at (Out), and the potential becomes equal to VDD (FIG. 3B).

With the above operation, an output having an amplitude between VDD and VSS can be obtained normally without causing an amplitude attenuation with respect to an input of a signal having an amplitude between VDD and VSS. Therefore, by using such a method for the driver circuit of the display device, a unipolar TFT can be used, which contributes to process reduction and manufacturing cost reduction.

  Examples of the present invention will be described below.

FIG. 4 shows a configuration in which the connection is partially changed in the circuit shown in FIG. FIG.
In FIG. 4, the output electrode of the TFT 104 is connected to the gate electrode of the TFT 101, whereas in FIG. 4, it is connected to the output terminal (Out).

Since the operation of the circuit is the same as that described in the embodiment, the description is omitted here. However, when considering the gate electrode of the TFT 101 as the circuit configuration, the circuit shown in FIG. 4 can move a certain amount of charge through the TFT 104 even when the TFT 103 is turned off, the circuit shown in FIG.
Since there is no charge movement path accumulated in the 01 gate electrode, the TFT constituting the circuit temporarily
When the threshold value varies, the gate-source voltage of the TFT 101 becomes TFT 10.
There is a possibility that it will not drop until it is equal to the threshold value of 1. Considering these points,
By making the current capability of the TFT 102 sufficiently larger than the current capability of the TFT 101, a normal L level output can be obtained even if the TFT 101 is not completely turned off.

In this embodiment, the pixel portion and T of the drive circuit provided around the pixel portion on the same substrate.
A method for simultaneously manufacturing the FT will be described. In addition, although the manufacturing process of a liquid crystal display device is mentioned as an example, as above-mentioned, this invention is not limited to a liquid crystal display device.

First, as shown in FIG. 7A, a silicon oxide film and silicon nitride are formed on a substrate 5001 made of barium borosilicate glass or aluminoborosilicate glass represented by Corning # 7059 glass or # 1737 glass. A base film 5002 made of an insulating film such as a film or a silicon oxynitride film is formed. Although not particularly illustrated, for the formation of the base film 5002, for example, a silicon oxynitride film formed from SiH ₄ , NH ₃ , and N ₂ O by a plasma CVD method is 10 to 200 [nm] (preferably 50 to 100 [nm]) in thickness, and similarly Si
A silicon oxynitride silicon film formed from H ₄ and N ₂ O is 50 to 200 [nm] (preferably 1
A layer is formed to a thickness of 00 to 150 [nm].

Subsequently, the island-shaped semiconductor layers 5003 to 5005 are semiconductor films having an amorphous structure. A crystalline semiconductor film is formed using a laser crystallization method or a known thermal crystallization method. The island-shaped semiconductor layers 5003 to 5005 are formed to have a thickness of 25 to 80 [nm] (preferably 30 to 60 [nm]). There is no particular limitation on the material of the crystalline semiconductor layer, but it is preferably formed of silicon or a silicon germanium (SiGe) alloy.

In order to manufacture a crystalline semiconductor film by a laser crystallization method, a pulse oscillation type or continuous emission type excimer laser, YAG laser, or YVO ₄ laser is used. In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser oscillator is linearly collected by an optical system and irradiated onto a semiconductor film. Crystallization conditions are appropriately selected by the practitioner. When an excimer laser is used, the pulse oscillation frequency is set to 30 [Hz], and the laser energy density is set to 100 to 400 [mJ / cm ² ] (typically Is 200 to 300 [mJ / cm ² ]). Also,
When using a YAG laser, the second harmonic is used and the pulse oscillation frequency is 1 to 10 [kHz]
The laser energy density is 300 to 600 [mJ / cm ² ] (typically 350 to 500 [m
J / cm ² ]). Then, a laser beam focused in a linear shape with a width of 100 to 1000 [μm], for example, 400 [μm] is irradiated over the entire surface of the substrate, and the overlapping rate of the linear laser at this time (
The overlap ratio is set to 80 to 98 [%].

Subsequently, a gate insulating film 5006 is formed to cover the island-shaped semiconductor layers 5003 to 5005.
The gate insulating film 5006 has a thickness of 40 to 15 by using a plasma CVD method or a sputtering method.
An insulating film containing silicon is formed as 0 [nm]. In this embodiment, a silicon oxynitride film is formed with a thickness of 120 [nm]. Needless to say, the gate insulating film is not limited to such a silicon oxynitride film, and another insulating film containing silicon may be used as a single layer or a stacked structure. For example, when using silicon oxide, TEOS (Tetraethyl
Orthosilicate) and O ₂ are mixed, the reaction pressure is 40 [Pa], the substrate temperature is 300 to 400 [° C.], and the high frequency (13.56 [MHz]) power density is 0.5 to 0.8 [W / cm ^2]. ] Can be formed by discharging. The silicon oxide film thus produced can obtain good characteristics as a gate insulating film by subsequent thermal annealing at 400 to 500 [° C.].

Then, a first conductive film 5007 for forming a gate electrode over the gate insulating film 5006.
And a second conductive film 5008 are stacked. In this embodiment, the first conductive layer 5007 is formed of tantalum (Ta) with a thickness of 50 to 100 [nm], and the second conductive layer 5009 is formed of tungsten (
W) to a thickness of 100 to 300 [nm] (FIG. 7A).

The Ta film is formed by sputtering, and a Ta target is sputtered with Ar.
In this case, when an appropriate amount of Xe or Kr is added to Ar, the internal stress of the Ta film can be relieved and peeling of the film can be prevented. The resistivity of the α-phase Ta film is about 20 [μΩcm] and can be used as a gate electrode, but the resistivity of the β-phase Ta film is about 180 [μΩcm] and is not suitable for the gate electrode. is there. In order to form an α-phase Ta film, tantalum nitride (TaN) having a crystal structure close to that of the α-phase of Ta is formed on the Ta base with a thickness of about 10 to 50 [nm]. A Ta film can be easily obtained.

When forming a W film, it is formed by sputtering using W as a target. Other 6
It can also be formed by a thermal CVD method using tungsten fluoride (WF ₆ ). In any case, in order to use as a gate electrode, it is necessary to reduce the resistance, and the resistivity of the W film is 20 [
[μΩcm] or less is desirable. The resistivity of the W film can be reduced by increasing the crystal grains. However, when there are many impurity elements such as oxygen in W, crystallization is hindered and the resistance is increased. From this, in the case of the sputtering method, by using a W target having a purity of 99.9999 [%] and further forming a W film with sufficient consideration so that impurities are not mixed in the gas phase during film formation, A resistivity of 9 to 20 [μΩcm] can be realized.

Note that in this embodiment, the first conductive film 5007 is Ta, and the second conductive film 5008 is W.
However, it is not particularly limited, and any of them may be formed of an element selected from Ta, W, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. Alternatively, a semiconductor film typified by a polycrystalline silicon film doped with an impurity element such as phosphorus may be used. As an example of another combination other than the present embodiment, a combination in which the first conductive film is TaN, the second conductive film is W, the first conductive film is TaN, and the second conductive film is Al. ,
A combination of TaN as the first conductive film and Cu as the second conductive film is desirable.

Next, a resist mask 5009 is formed, and first electrodes for forming electrodes and wirings are formed.
Etching process is performed. In this embodiment, an ICP (Inductively coupled plasma) etching method is used, and CF ₄ and Cl ₂ are mixed in an etching gas and 1 [Pa].
500 [W] RF (13.56 [MHz]) power is applied to the coil-type electrode at a pressure of 1 to generate plasma. An RF power of 100 [W] is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. When CF ₄ and Cl ₂ are mixed, the W film and the Ta film are etched to the same extent.

Under the above etching conditions, the end portions of the first conductive film and the second conductive film are tapered due to a suitable mask shape by the resist and the effect of the bias voltage applied to the substrate side. The angle of the tapered portion is 15 to 45 °.
In order to perform etching without leaving a residue on the gate insulating film, it is preferable to increase the etching time at a rate of 10 to 20%. The selection ratio of the silicon oxynitride film to the W film is 2 to 2.
4 (typically 3), the surface where the silicon oxynitride film is exposed is etched by about 20 to 50 [nm] by the over-etching process. Thus, the first conductive layers 5010a to 5013a and the second conductive layers 5010b to 5013 are formed by the first etching process.
First-shaped conductive layers 5010 to 5013 made of b are formed. At this time, in the gate insulating film 5006, regions that are not covered with the first shape conductive layers 5010 to 5013 are 20 to 20 regions.
A thinned region is formed by etching about 50 [nm] (FIG. 7B).

Then, a first doping process is performed, and an impurity element imparting N-type is added (FIG. 7B
)). The doping process may be performed by an ion doping method or an ion implantation method. The conditions for the ion doping method are a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ [atoms / cm ² ] and an acceleration voltage of 60 to 100 [keV]. As the impurity element imparting N-type, an element belonging to Group 15, typically phosphorus (P) or arsenic (As), is used here, but P is used. In this case, the conductive layers 5010 to 5013 serve as a mask for the impurity element imparting N-type, and the first impurity regions 5014 to 5016 are formed in a self-aligning manner. This first impurity region 50
14 to 5016 is doped with an impurity element imparting N-type in a concentration range of 1 × 10 ²⁰ to 1 × 10 ²¹ [atoms / cm ³ ].

Next, a second etching process is performed (FIG. 7C). Similarly, using an ICP etching method, CF ₄ , Cl _2, and O ₂ are mixed in an etching gas, and a coil-type electrode is formed at a pressure of 1 [Pa].
An RF power of 00 [W] is supplied to generate plasma. 50 on the substrate side (sample stage)
[W] RF power is applied, and a lower self-bias voltage is applied than in the first etching process. Under such conditions, the second conductive layer W is anisotropically etched, and the first conductive layer Ta is anisotropically etched at a slower etching rate to form the second shape conductive layer. 5017 to 5020 (first conductive layers 5017a to 5020a and second conductive layers 5017
b-5020b). At this time, in the gate insulating film 5006, regions that are not covered with the second shape conductive layers 5017 to 5020 are further etched by about 20 to 50 [nm] to form thinned regions.

The etching reaction of the W film or Ta film with the mixed gas of CF ₄ and Cl ₂ can be estimated from the generated radicals or ion species and the vapor pressure of the reaction product. When the vapor pressures of W and Ta fluorides and chlorides are compared, the vapor pressure of WF ₆ , which is a fluoride of W, is extremely high, and the other WCl ₅ , TaF ₅ , and TaCl ₅ are similar. Therefore, both the W film and the Ta film are etched with a mixed gas of CF ₄ and Cl ₂ . However, an appropriate amount of O ₂
When CF ₄ is added, CF ₄ and O ₂ react to become CO and F, and a large amount of F radicals or F ions are generated. As a result, the etching rate of the W film having a high fluoride vapor pressure is increased. on the other hand,
As for Ta, even if F increases, the etching rate increases relatively little. Further, since Ta is more easily oxidized than W, the surface of Ta is oxidized by adding O ₂ . Since Ta oxide does not react with fluorine or chlorine, the etching rate of the Ta film is further reduced. Therefore, it becomes possible to make a difference in the etching rate between the W film and the Ta film.

Then, a second doping process is performed (FIG. 7C). In this case, doping is performed with an impurity element that imparts N-type as a condition of a high acceleration voltage by lowering the dose than in the first doping process. For example, the acceleration voltage is set to 70 to 120 [keV] with a dose of 1 × 10 ¹³ [atoms / cm ² ], and the first impurity region formed in the island-shaped semiconductor layer in FIG. A new impurity region is formed inside. Doping is performed by using the second conductive layers 5017b to 5020b as masks against the impurity elements and adding the impurity elements to the lower regions of the first conductive layers 5017a to 5020a.
Thus, second impurity regions 5021 to 5023 overlapping with the first conductive layer are formed.

Subsequently, a third etching process is performed (FIG. 8A). Here, the etching gas is Cl
₂ and using an ICP etching apparatus. In this embodiment, the gas flow rate ratio of Cl ₂ is set to 60.
[sccm], RF power of 350 [W] was applied to the coil-type electrode at a pressure of 1 [Pa], plasma was generated, and etching was performed for 70 seconds. Apply RF power to the substrate side (sample stage),
A substantially negative self-bias voltage is applied. By the third etching, the first conductive layer recedes to form third shape conductive layers 5024 to 5027 (first conductive layers 5024a to 5027a and second conductive layers 5024b to 5027b), and the second Impurity regions 5021-5
A part of 023 becomes third impurity regions 5028 to 5030 which do not overlap with the first conductive layer.

Through the above steps, impurity regions are formed in each island-shaped semiconductor layer. The third shape conductive layers 5024 to 5027 overlapping with the island-shaped semiconductor layers function as gate electrodes of the TFTs.

Subsequently, for the purpose of controlling the conductivity type, a step of activating the impurity element added to each island-shaped semiconductor layer is performed. This step is performed by a thermal annealing method using a furnace annealing furnace. In addition, a laser annealing method and a rapid thermal annealing method (RTA method) can be applied. In the thermal annealing method, oxygen concentration is 1 [ppm] or less, preferably 0.1 [ppm] or less in a nitrogen atmosphere at 400 to 700 [° C.], typically 500 to 600 [° C.],
In this embodiment, heat treatment is performed at 500 [° C.] for 4 hours. However, when the wiring material used for 5024 to 5027 is vulnerable to heat, it is desirable to perform thermal activation after forming an interlayer insulating film (mainly silicon) in order to protect the wiring and the like.

Further, a heat treatment is performed at 300 to 450 [° C.] for 1 to 12 hours in an atmosphere containing 3 to 100% hydrogen to perform a step of hydrogenating the island-shaped semiconductor layer. This step is a step of terminating dangling bonds in the semiconductor layer with thermally excited hydrogen. As another method of thermal hydrogenation for hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be used.

Next, as shown in FIG. 8B, a first interlayer insulating film 5031 is formed using a silicon oxynitride film with a thickness of 100 to 200 [nm]. After a second interlayer insulating film 5032 made of an organic insulating material is formed thereon, contact holes are opened in the first interlayer insulating film 5031, the second interlayer insulating film 5032, and the gate insulating film 5006. Then, a film made of a wiring material is formed, and the wirings 5033 to 5036 and the pixel electrode 5037 are formed by patterning.

As the second interlayer insulating film 5032, a film made of an organic resin such as polyimide, polyamide, acrylic, or BCB (benzocyclobutene) is used. In particular, the second interlayer insulating film 50
Since 32 has a strong meaning of flattening, acrylic having excellent flatness is desirable. In this embodiment, the acrylic film is formed with a film thickness that can sufficiently flatten the step formed by the TFT. Preferably, it may be 1 to 5 [μm] (more preferably 2 to 4 [μm]).

The contact hole is formed by dry etching or wet etching, and N
Type impurity regions 5014 to 5016, and source signal lines (not shown), gate signal lines (not shown), current supply lines (not shown), and gate electrodes 5024 to 5026 (not shown).
) Each contact hole is formed.

Further, as the wirings 5033 to 5036, the Ti film is 100 [nm], and the Al film containing Ti is 30.
A three-layer laminated film continuously formed by a sputtering method with a thickness of 0 [nm], a Ti film of 150 [nm], and patterned into a desired shape is formed. Of course, other conductive materials may be used. The pixel electrode 5037 is formed using a highly reflective material when the display device is a reflective type. in this case,
You may form simultaneously with wiring. On the other hand, in the case of the transmission type, indium tin oxide (Indium
It is formed using a transparent conductive material such as Tin Oxide (ITO). A substrate completed up to the state of FIG. 8B is referred to as an active matrix substrate in this specification.

Subsequently, a counter substrate 5038 is prepared. A light shielding film 5039 is formed over the counter substrate 5038. The light shielding film is formed with a thickness of 100 [nm] to 200 [nm] using chromium (Cr) or the like.

On the other hand, a counter electrode 5040 is formed in the pixel portion. The counter electrode is formed using a transparent conductive material such as ITO. In order to keep the visible light transmittance high, it is desirable to form the counter electrode with a thickness of 100 [nm] to 120 [nm].

Alignment films 5041 and 5042 are formed on the active matrix substrate and the counter substrate. The film thickness of the alignment films 5041 and 5042 is desirably 30 [nm] to 80 [nm]. As the alignment film, for example, SE7792 manufactured by Nissan Chemical Co., Ltd. can be used. When an alignment film having a high pretilt angle is used, the occurrence of disclination can be suppressed when driving a liquid crystal display device driven by an active matrix method.

Subsequently, the alignment films 5041 and 5042 are rubbed. The rubbing direction is preferably left-handed TN (Twisted Nematic) orientation when the liquid crystal display device is completed.

Although not particularly shown in the present embodiment, it is possible to improve the uniformity of the cell gap by forming spacers in the pixels by scattering or patterning. In this example, a photosensitive resin film was formed and patterned to form a spacer having a height of 4.0 [μm].

Subsequently, the active matrix substrate and the counter substrate are bonded to each other with a sealant 5043. As the sealant, XN-21S manufactured by Mitsui Chemicals, which is a thermosetting sealant, was used. Filler is mixed in the sealant. The height of the filler is 4.0 [μm]. Thereafter, after the sealant is cured, the active matrix substrate and the counter substrate are simultaneously divided into a desired size.

Subsequently, liquid crystal 5044 is injected. As the liquid crystal material, a material having a low viscosity is desirable in consideration of high-speed response. In this embodiment, nematic liquid crystal with easy alignment control is used. Of course, a ferroelectric liquid crystal or an antiferroelectric liquid crystal capable of high-speed response may be used.

After the liquid crystal injection is completed, the injection port is sealed with a UV curable resin or the like. Thereafter, a polarizing plate is attached by a known method. Finally, a connector (flexible printed circuit: FPC) for connecting a terminal routed from an element or circuit formed on the substrate and an external signal terminal is attached to complete the product (FIG. 8C). . In this specification, such a state that can be shipped is referred to as a liquid crystal display device.

Further, according to the steps shown in this embodiment, the number of photomasks necessary for the production of the active matrix substrate is four (an island semiconductor layer pattern, a first wiring pattern (a gate wiring, an island source wiring, a capacitor wiring). ), A contact hole pattern, a second wiring pattern (including a pixel electrode and a connection electrode)). As a result, the process can be shortened, and the manufacturing cost can be reduced and the yield can be improved.

In this embodiment, the top gate type TFT is described as an example of the TFT type. In addition, a gate electrode is formed below the active layer as shown in FIG. The bottom gate type TFT or a dual gate type TFT having gate electrodes on the upper and lower sides so as to sandwich the active layer as shown in FIG. 5B can be used.

The process shown in the second embodiment has been described as an example in which the pixel and the peripheral driving circuit are configured using N-channel TFTs, but the present invention can also be implemented using P-channel TFTs.

In the case of an N-channel TFT, an impurity region called an overlap region is provided in a region overlapping with the gate electrode in order to suppress hot carrier deterioration and the like. On the other hand, in the case of a P-channel TFT, since the influence of hot carrier deterioration is small, it is not necessary to provide an overlap region, and in this case, it can be manufactured by a simpler process.

As shown in FIG. 9A, according to the fourth embodiment, a base film 6 is formed on an insulating substrate 6001 such as glass.
Next, island-shaped semiconductor layers 6003 to 6005, a gate insulating film 6006, and conductive layers 6007 and 6008 are formed. Here, the conductive layers 6007 and 6008 have a laminated structure here, but may be a single layer.

Next, as shown in FIG. 9B, a resist mask 6009 is formed, and a first etching process is performed. In Example 4, anisotropic etching was performed using the selection ratio depending on the material of the conductive layer having a laminated structure. However, in this case, it is not necessary to provide a region to be an overlap region. Just do it. At this time, the gate insulating film 6006
In, a region that is thinned by about 20 [nm] to 50 [nm] is formed by etching.

Subsequently, a first doping process for adding an impurity element imparting P-type to the island-shaped semiconductor layer is performed. Using the conductive layers 6010 to 6013 as masks against the impurity elements, impurity regions are formed in a self-aligning manner. As an impurity element imparting P-type, boron (B) or the like is typical. Here, an ion doping method using diborane (B ₂ H ₆ ) is used so that the impurity concentration in the semiconductor layer is 2 × 10 ²⁰ to 2 × 10 ²¹ [atoms / cm ³ ].

The resist mask is removed to obtain the state of FIG. Thereafter, it is manufactured according to the steps after FIG. Thus, the present invention can be implemented using a P-channel TFT.

Note that the circuit configuration is the same as that in the case of using an N-channel TFT as shown in FIG. 1, but the power source is the high potential side power source VDD and the low potential side in FIG. The connection is made by replacing the power supply VSS.

In this embodiment, a manufacturing process of a light-emitting device using a light-emitting element such as an EL element in a pixel portion will be described.

In accordance with the manufacturing process shown in Example 2, as shown in FIGS.
Up to the interlayer insulating film is formed.

Subsequently, as shown in FIG. 10A, a contact hole is opened. The shape of the contact hole is formed by dry etching or wet etching so as to reach the impurity region, the source signal line, the gate signal line, the current supply line, and the gate electrode, respectively.

Next, a transparent conductive film typified by ITO or the like is formed as the anode 7001 of the EL element, and is patterned into a desired shape. A laminated film made of Ti, Ti containing Ti and Ti is formed,
The wiring electrodes 7002 to 7005 and the pixel electrode 7006 are formed by patterning in a desired shape. The film thickness of each layer may be the same as in Example 2. The pixel electrode 7006 is formed so as to overlap with the previously formed anode 7001 and is in contact.

Subsequently, an insulating film made of an organic resin material such as acrylic is formed, and an anode 7001 of the EL element is formed.
A third interlayer insulating film 7007 is formed by forming an opening at a position corresponding to. Here, when the opening is formed, it is desirable that the side wall has a gently tapered shape. When the side wall of the opening is not sufficiently tapered, care must be taken because deterioration of the EL layer, step breakage, and the like due to the step become significant problems.

Next, after the EL layer 7008 is formed, the EL element cathode 7009 is replaced with cesium (Cs) 2.
A thickness of [nm] or less and silver (Ag) are formed to a thickness of 10 [nm] or less. EL element cathode 7
By making the thickness of 009 extremely thin, light generated in the EL layer is transmitted through the cathode 7009 and emitted.

Next, a protective film 7010 is formed for the purpose of protecting the EL element. Then, after performing operations such as attaching an FPC, the light emitting device is completed.

In this embodiment, the details of the structure of the EL element in the light emitting device shown in FIG.
0 (B). The anode 7101 of the EL element is made of a transparent conductive film typified by ITO. 71
02 is an EL layer including a light emitting layer. The cathodes of the EL elements are all made very thin C
An s film 7103 and an Ag film 7104 are formed. Reference numeral 7105 denotes a protective film.

By forming the cathode side of the EL element with a very thin film thickness, light generated in the EL layer 7102 is transmitted upward through the cathodes 7103 and 7104. That is, since the region where the TFT is formed does not press the area of the light emitting surface, the aperture ratio can be almost 100 [%].

Here, since the emission direction is the side on which the cathode is formed, if it is not desired to transmit light to the anode side formed of ITO, the second interlayer insulating film 7000 is made of an opaque film such as black. Is desirable.

In the above process, the structure in which the upper side of the EL layer is the cathode and the lower side is the anode has been described.
By forming the pixel electrode on the lower side of the L layer with TiN or the like and the electrode on the upper side of the EL layer with ITO or the like, it is possible to use the upper side of the EL layer as an anode and the lower side of the EL layer as a cathode. is there.

Although the aperture ratio is slightly reduced, the lower side of the EL layer is the anode, the upper side of the EL layer is the cathode, and the EL
The lower electrode of the layer is formed of ITO or the like, and the electrode on the upper side of the EL layer is formed using MgAg or the like, unlike the present example, so that the TFT generates the light generated in the EL layer. It is of course possible to adopt a type in which the light is emitted to the side of the substrate that is being used, that is, downward.

In this embodiment, a process for manufacturing a light-emitting device by a method different from that in Embodiment 4 will be described.

In accordance with the manufacturing process shown in Example 2, as shown in FIGS.
Up to the interlayer insulating film is formed.

Subsequently, as shown in FIG. 11A, a contact hole is opened. The contact hole is formed using dry etching or wet etching so as to reach the N-type impurity region, the source signal line, the gate signal line, the current supply line, and the gate electrode.

Next, the wirings 7201 to 7204 and the pixel electrode 7205 serving as the anode of the EL element are connected to T
It is formed as a laminated film of an i film, an Al film containing Ti, a Ti film, and a transparent conductive film.

Subsequently, an insulating film made of an organic resin material such as acrylic is formed, and the EL element anode 7205 is formed.
A third interlayer insulating film 7206 is formed by forming an opening at a position corresponding to. Here, when the opening is formed, it is desirable that the side wall has a gently tapered shape. When the side wall of the opening is not sufficiently tapered, care must be taken because deterioration of the EL layer, step breakage, and the like due to the step become significant problems.

Next, after the EL layer 7207 is formed, the cathode 7208 of the EL element is replaced with 2 cesium (Cs).
A thickness of [nm] or less and silver (Ag) are formed to a thickness of 10 [nm] or less. EL element cathode 7
By making the thickness of 009 extremely thin, light generated in the EL layer is transmitted through the cathode 7009 and emitted.

Next, a protective film 7209 is formed for the purpose of protecting the EL element. Then, after performing operations such as attaching an FPC, the light emitting device is completed.

In this embodiment, the details of the structure of the EL element in the light emitting device shown in FIG.
Shown in 1 (B). The anode of the EL element is composed of a metal film 7301 made of a laminated film of Ti, Al, and Ti, and a transparent conductive film 7302 typified by ITO. Reference numeral 7303 denotes an EL layer including a light emitting layer. As the cathode of the EL element, the Cs film 7304 and the Ag film 73, both of which are extremely thin, are formed.
05. Reference numeral 7306 denotes a protective film.

The light emitting device manufactured in this example has an aperture ratio of about 10 like the light emitting device shown in Example 6.
It has the advantage that it can be 0%. Furthermore, in the formation of the wiring electrode and the pixel electrode, Ti,
It is possible to pattern a metal film made of a stack of Al and Ti and a transparent conductive film using a common photomask, so that the photomask can be reduced and the process can be simplified.

In the above process, the structure in which the upper side of the EL layer is the cathode and the lower side is the anode has been described.
By forming the pixel electrode on the lower side of the L layer with TiN or the like and the electrode on the upper side of the EL layer with ITO or the like, it is possible to use the upper side of the EL layer as an anode and the lower side of the EL layer as a cathode. is there.

Although the aperture ratio is slightly reduced, the lower side of the EL layer is the anode, the upper side of the EL layer is the cathode, and the EL
The lower electrode of the layer is formed of ITO or the like, and the electrode on the upper side of the EL layer is formed using MgAg or the like, unlike the present example, so that the TFT generates the light generated in the EL layer. Of course, it is possible to adopt a type in which the light is emitted to the substrate side, that is, the lower side.

The present invention can also be implemented using a P-channel TFT. In this embodiment, the configuration and operation will be described.

FIG. 13A shows the configuration. The circuit includes TFTs 1301 to 1304 and capacitor means 1305.
A signal with the polarity of the signal input to the input terminal (In) inverted appears at the output terminal (Out).

The operation of the circuit will be described. First, when an H level is input to the first input terminal (In1) and an L level is input to the second input terminal (In2), the TFT 1302 is turned on and the output terminal (Out)
Begins to be pulled up to the VDD side. At this time, since the potential of the output terminal (Out) has not fully increased to the H level, the TFT 1303 is ON, and the capacitor means 130
Since a current is generated from 5 toward the output terminal (Out) and the potential of the gate electrode of the TFT 1304 is lowered, the TFT 1304 is also turned on. When the potential of the output terminal (Out) further increases, TF
The gate-source voltage of T1303 becomes equal to VthP, and the TFT 1303 is turned off. At this time, even when the TFT 1304 is still ON, the electric charge charged in the capacitor means 1305 is discharged through the TFT 104, and the gate-source voltage of the TFT 1304 continues to decrease, so it is turned OFF.

Thereby, the threshold voltage VthP of the TFT 1304 is held in the capacitor 1305. Since the first input terminal (In1) is at the H level and the potential is VDD, the TFT
The potential of the gate electrode 1301 is lower than VDD by the voltage held by the capacitor 1305. That is, the potential of the gate electrode of the TFT 1301 at this time is (VDD−Vth
P). Since an H level appears at the output terminal (Out) and the potential is VDD, the gate-source voltage of the TFT 1301 is VthP, and the TFT 1301 is turned off.

Next, an operation when an L level is input to the first input terminal (In1) and an H level is input to the second input terminal (In2) will be described. First, since the second input terminal (In2) changes from L level to H level, the TFT 1302 is turned OFF. On the other hand, the first input terminal (In1) is H
Level changes to L level. At this time, since the TFT 1303 remains in an OFF state, the charge held in the capacitor means 1305 does not move. Regarding the TFT 1304, the potential of the source region drops, but the gate-source voltage remains at VthP, and thus remains in the OFF state. Therefore, even when the first input terminal changes from the H level to the L level, the voltage between both electrodes of the capacitor means 1305 remains held. Accordingly, the potential of the first input terminal (In1) drops from VDD to VSS, and thus the TFT 1301.
The potential of the gate electrode drops from (VDD−VthP) to (VSS−VthP). Therefore, an L level appears at the output terminal (Out), and the potential becomes equal to VSS.

With the above operation, even when a P-channel TFT is used, VDD-VSS
With respect to the input of a signal having an amplitude between, VDD-VS is normally performed without causing amplitude attenuation.
An output having an amplitude between S can be obtained.

The present invention can be applied to manufacture of display devices used in various electronic devices. Examples of such electronic devices include portable information terminals (electronic notebooks, mobile computers, mobile phones, etc.), video cameras, digital cameras, personal computers, televisions, mobile phones, and the like. An example of them is shown in FIG.

FIG. 6A illustrates a liquid crystal display or an OLED display, which includes a housing 3001, a support base 3002, a display portion 3003, and the like. The present invention can be applied to a driver circuit of a display device including the display portion 3003.

FIG. 6B illustrates a video camera, which includes a main body 3011, a display portion 3012, and an audio input portion 3013.
The operation switch 3014, the battery 3015, the image receiving unit 3016, and the like. The present invention can be applied to a driver circuit of a display device including the display portion 3012.

FIG. 6C illustrates a laptop personal computer, which includes a main body 3021, a housing 3022,
A display portion 3023, a keyboard 3024, and the like are included. The present invention relates to the display unit 302.
3 can be applied to a driving circuit of a display device having 3.

FIG. 6D illustrates a portable information terminal, which includes a main body 3031, a stylus 3032, and a display portion 3033.
, Operation buttons 3034, an external interface 3035, and the like. The present invention can be applied to a driver circuit of a display device having the display portion 3033.

FIG. 6E shows a sound reproducing device, specifically an in-vehicle audio device.
The display unit 3042, operation switches 3043 and 3044, and the like are included. The present invention can be applied to a driver circuit of a display device including the display portion 3042. In this embodiment, the in-vehicle audio device is taken as an example, but it may be used for a portable or home audio device.

FIG. 6F illustrates a digital camera, which includes a main body 3051, a display portion (A) 3052, and an eyepiece unit 305.
3, an operation switch 3054, a display portion (B) 3055, a battery 3056, and the like. The present invention can be applied to a driver circuit of a display device including the display portion (A) 3052 and the display portion (B) 3055.

FIG. 6G illustrates a mobile phone, which includes a main body 3061, an audio output unit 3062, and an audio input unit 3063.
, A display portion 3064, an operation switch 3065, an antenna 3066, and the like.
The present invention can be applied to a driver circuit for a display device having the display portion 3064.

It should be noted that the examples shown in the present embodiment are only examples and are not limited to these applications.

Claims (12)

On the substrate, the first to fourth transistors and the capacitor means are provided.
The first to fourth transistors are all of the same conductivity type,
A first electrode of the capacitor means is electrically connected to a gate of the first transistor;
A gate of the second transistor is electrically connected to the first signal input terminal;
One of a source or a drain of the first transistor and one of a source or a drain of the third transistor are electrically connected to a signal output terminal,
One of a source and a drain of the second transistor is electrically connected to a first power source;
The other of the source and the drain of the second transistor is electrically connected to the signal output terminal;
The other of the source and the drain of the third transistor is electrically connected to the first electrode of the capacitor means,
One of the source and the drain of the fourth transistor is electrically connected to the first electrode of the capacitor means;
The other of the source and the drain of the fourth transistor is electrically connected to the second signal input terminal;
The semiconductor device, wherein the second electrode of the capacitor means is electrically connected to the second signal input terminal. In claim 1,
The other of the source and the drain of the first transistor is electrically connected to a second power supply. In claim 1 or 2,
A semiconductor device, wherein the gate of the third transistor is electrically connected to one of a source and a drain of the third transistor. In any one of Claims 1 thru | or 3,
A gate of the fourth transistor is electrically connected to one of a source and a drain of the fourth transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the second electrode of the capacitor means.   An electronic apparatus comprising the semiconductor device according to claim 1. In claim 5,
The electronic device is a liquid crystal display device, a light emitting device, a video camera, a personal computer, a portable information terminal, a sound reproducing device, a digital camera, or a mobile phone. A driving circuit having first to fourth transistors and a capacitor on a substrate;
A pixel portion having a fifth transistor on the substrate;
The first to fourth transistors are all of the same conductivity type,
A first electrode of the capacitor means is electrically connected to a gate of the first transistor;
A gate of the second transistor is electrically connected to the first signal input terminal;
One of a source or a drain of the first transistor and one of a source or a drain of the third transistor are electrically connected to a signal output terminal,
One of a source and a drain of the second transistor is electrically connected to a first power source;
The other of the source and the drain of the second transistor is electrically connected to the signal output terminal;
The other of the source and the drain of the third transistor is electrically connected to the first electrode of the capacitor means,
One of the source and the drain of the fourth transistor is electrically connected to the first electrode of the capacitor means;
The other of the source and the drain of the fourth transistor is electrically connected to the second signal input terminal;
The display device, wherein the second electrode of the capacitor means is electrically connected to the second signal input terminal. In claim 7,
The other of the source and the drain of the first transistor is electrically connected to a second power source. In claim 7 or 8,
A display device, wherein a gate of the third transistor is electrically connected to one of a source and a drain of the third transistor. In any one of Claims 7 thru | or 9,
A gate of the fourth transistor is electrically connected to one of a source and a drain of the fourth transistor;
The other of the source and the drain of the fourth transistor is electrically connected to the second electrode of the capacitor means.   An electronic apparatus comprising the display device according to claim 7. In claim 11,
The electronic device is a liquid crystal display device, a light emitting device, a video camera, a personal computer, a portable information terminal, a sound reproducing device, a digital camera, or a mobile phone.

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