JP5779265B2 - Semiconductor device - Google Patents

Description

  Embodiments described herein relate generally to a semiconductor device.

  Generally, when a current flows through a semiconductor element or a peripheral circuit, an electric field and a magnetic field are induced around the current, and unnecessary electromagnetic noise is generated. Unnecessary electromagnetic noise affects the operation of other circuits and elements. As an example, electromagnetic noise emitted from a semiconductor device mounted on a mobile communication device such as a mobile phone may enter an antenna and cause radio wave reception failure.

  In order to shield such electromagnetic noise and protect the semiconductor element, there is a method of providing a shielding plate that covers the circuit module. However, the method of covering the circuit module with the shielding plate has a problem that the circuit module cannot be reduced in size.

  On the other hand, there is a semiconductor device (semiconductor package) in which a shielding film is formed on the outer periphery of the semiconductor element itself. If such a semiconductor device is incorporated in a circuit module, the circuit module can be reduced in size. As for semiconductor elements, high-speed operation is required more and more, and highly reliable semiconductor devices that shield electromagnetic noise more are required.

JP 2010-103574 A

  The problem to be solved by the present invention is to provide a semiconductor device with higher reliability than the point that electromagnetic noise is not radiated to the outside.

The semiconductor device of the embodiment, the insulating substrate, a plurality of wires provided on the insulating substrate, a copper or tungsten cut surfaces exposed at the side surface of the front Symbol insulating substrate, and a circuit board having the a semiconductor element mounted on a circuit board, a sealing resin layer which seals the front Symbol semiconductor element, a conductive shield layer covering the sealing resin layer, which are connected to the respective front Symbol plurality of wirings comprising an external connection terminal.

And the cutting surface, and the conductive shield layer, are connected. Any of the plurality of wirings and the external connection terminal connected to any of the plurality of wirings can be at a ground potential. The external connection terminal that can be a ground potential is electrically connected to the cut surface via any of the plurality of wirings . The distance between the external connection terminals that can be ground potential is less than half the wavelength of the electromagnetic wave to be shielded.

It is a cross-sectional schematic diagram explaining the outline | summary of the semiconductor device which concerns on 1st Embodiment. 2A and 2B are schematic plan views of the semiconductor device according to the first embodiment, in which FIG. 1A is a schematic plan view on the upper surface side of the circuit board, and FIG. 2B is a schematic plan view on the lower surface side of the circuit board. 2A and 2B are schematic plan views of the semiconductor device according to the first embodiment, in which FIG. 1A is a schematic plan view of a circuit board according to a first modification, and FIG. 2B is a schematic plan view of a circuit board according to a second modification; . It is a cross-sectional schematic diagram explaining the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a simulation result for demonstrating the shielding effect of electromagnetic noise. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 2nd Embodiment. It is a figure explaining the plane schematic diagram and shielding effect of a semiconductor device concerning a 3rd embodiment. It is a cross-sectional schematic diagram of the semiconductor device which concerns on 4th Embodiment.

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate. Moreover, each embodiment described below can be combined suitably.

(First embodiment)
FIG. 1 is a schematic cross-sectional view for explaining the outline of the semiconductor device according to the first embodiment.
In FIG. 1, in addition to the semiconductor device 1 according to the first embodiment, a mounting substrate 100 on which the semiconductor device 1 is mounted is displayed.

  The semiconductor device 1 is an FBGA (Fine pitch Ball Grid Array) type semiconductor package. The semiconductor device 1 includes a circuit board 10. The circuit board 10 is also referred to as an interposer board. The circuit board 10 includes an insulating base 11, a plurality of wires 12 constituting a first wiring layer provided on the outer periphery on the upper surface side of the insulating base 11, and a second provided on the lower surface side of the insulating base 11. And a plurality of wirings 13 constituting a wiring layer. The circuit board 10 further includes a plurality of vias 14 penetrating from the upper surface (first main surface) to the lower surface (second main surface) of the insulating base material. A solder resist layer 15 that covers a part of the first wiring layer 12 is formed on the upper surface of the circuit board 10. A solder resist layer 16 that covers a part of the second wiring layer 13 is formed on the lower surface of the circuit board 10. Each of the plurality of wirings 13 constituting the second wiring layer is a land-like wiring layer. An external connection terminal 17, which is a solder ball, is connected to each of the plurality of wirings 13 constituting the second wiring layer. A lead wire 19 extends from the outer external connection terminal 17 to the outside of the circuit board 10. The lead wire 19 is connected to the via 14 exposed on the side surface 10 w of the circuit board 10. The lead wire 19 is a connection line that connects the outer peripheral connection terminal 17 and the via 14 closest to the outer periphery connection terminal 17. The external connection terminal 17 is connected to the wiring layer 101 provided on the upper surface side of the mounting substrate 100.

  A semiconductor element 20 is mounted on the upper surface side of the circuit board 10. One end of a wire (bonding wire) 21 is connected to the upper surface of the semiconductor element 20. The other end of the wire 21 is connected to the first wiring layer 12. The wire 21 is a conductive member and electrically connects at least one of the plurality of wirings 12 constituting the first wiring layer and an electrode (not shown) provided on the surface of the semiconductor element.

  The outer periphery of the semiconductor element 20 and the wire 21 are sealed with a sealing resin layer 30 provided on the upper surface side of the circuit board 10. A die bonding material 22 is formed in the gap between the semiconductor element 20 and the circuit board 10. The sealing resin layer 30 and a part of the side surface 10 w of the circuit board 10 are covered with the conductive shield layer 40. The conductive shield layer 40 is connected to the via 14 provided on the side surface (outer end) 10 w of the circuit board 10. At least one of the vias 14 exposed on the side surface 10w of the circuit board 10 can be at a ground (GND) potential. Thereby, the electric potential of the conductive shield layer 40 covering the outer periphery of the semiconductor element 20, the wire 21, the upper surface side of the circuit board 10, and a part of the side surface 10w of the circuit board 10 can be set to the ground (GND) electric potential. .

  The semiconductor element 20 is, for example, a storage element such as a flash memory or a DRAM, an arithmetic element such as a microprocessor, or a signal processing element. The material of the wire 21 is, for example, gold (Au), aluminum (Al), copper (Cu), or the like. The first wiring layers 12 and 13 are a conductive paste containing copper (Cu) foil, silver (Ag), or copper (Cu), and the surface is made of nickel (Ni), gold (Au), or the like as necessary. Plating treatment is applied. The via 14 is, for example, a columnar electrode. The via 14 may be a columnar electrode in which all materials are made of a conductive material. In addition to the columnar electrode, the via 14 may include a cylindrical cylindrical electrode and a resin embedded in the hollow of the cylindrical electrode. Good. The material of the via 14 is copper (Cu), tungsten (W), or the like.

  The conductive shield layer 40 is desirably made of a material having a resistivity as low as possible in order to block high-frequency noise emitted from the semiconductor element 20. As a material of the conductive shield layer 40, for example, silver (Ag), copper (Cu), nickel (Ni) or the like is selected. More specifically, the conductive shield layer 40 is a silver (Ag) -containing layer obtained by curing a silver (Ag) paste, and its sheet resistance is adjusted to 0.1 (Ω / □) or less. The thickness of the conductive shield layer 40 is several tens of μm (micrometer), and more preferably 10 to 90 μm.

  2A and 2B are schematic plan views of the semiconductor device according to the first embodiment. FIG. 2A is a schematic plan view on the upper surface side of the circuit board, and FIG. 2B is a schematic plan view on the lower surface side of the circuit board. . FIG. 2 is a view of the circuit board 10 as viewed from a direction perpendicular to the upper surface (or lower surface) of the insulating base material 11.

  As shown in FIG. 2A, a plurality of vias 14 are provided on the upper surface side of the circuit board 10. The plurality of vias 14 penetrate from the upper surface to the lower surface of the insulating base material 11. A rectangular area surrounded by reference numeral 23 is an element mounting area 23 of the semiconductor element 20. A plurality of vias 14 are arranged outside the device mounting region 23 or the device mounting region 23. The plurality of wirings 12 constituting the first wiring layer are provided outside the element mounting region 23. A lead line 18 is provided from the via 14 in the element mounting region 23 to the first wiring layer 12. The lead line 18 is a signal line, a ground wiring, or the like of the semiconductor element 20. The lead wire 18 is a conductive paste containing copper (Cu) foil, silver (Ag), or copper (Cu).

  As shown in FIG. 2B, a plurality of external connection terminals 17 are provided in rows and columns on the lower surface side of the circuit board 10. Each of the plurality of external connection terminals 17 is electrically connected to the lead line 18 on the upper surface side via the via 14. That is, the external connection terminal 17 is electrically connected to the first wiring layer 12 via the second wiring layer 13, the via 14, and the lead line 18. In FIG. 2B, the wiring layer 13 illustrated in FIG. 1 is not displayed, but actually, the wiring layer 13 is in contact with the external connection terminal 17 (see FIG. 1).

  In the semiconductor device 1, a group composed of a plurality of external connection terminals 17 which is smaller than the number of the plurality of external connection terminals 17 can be at the ground potential. For example, after the semiconductor device 1 is mounted on the mounting substrate 100, some of the external connection terminals 17 become the ground potential by the ground wiring provided in the mounting substrate 100. In the figure, an external connection terminal that can be a ground potential is designated as an external connection terminal 17g by using a reference numeral 16g. In other words, a group of the plurality of wirings 13 constituting the second wiring layer, which is smaller than the number of the plurality of wirings 13 constituting the second wiring layer, can be at the ground potential. Further, the second wiring layer 13 in contact with the external connection terminal 17g can be at the ground potential.

  In FIG. 2B, each of the external connection terminals 17g (or the second wiring layer 13 in contact with the external connection terminals 17g) having the ground potential is located at the four corners of the element mounting region 23. In other words, each of the external connection terminals 17g (or the second wiring layer 13 in contact with the external connection terminals 17g) is located at a corner of the semiconductor element.

  Further, in the circuit board 10, the group of the plurality of vias 14 that is smaller than the number of the plurality of vias 14 provided on the entire main surface of the circuit board 10 is disposed so as to be exposed on the side surface 10 w of the circuit board 10. . Each of the plurality of vias 14 arranged on the side surface 10w is cut on the side surface of the circuit board 10 by a dicing blade used during the manufacturing process, and has an exposed surface. In the semiconductor device 1, the exposed surfaces of the plurality of vias 14 disposed on the side surface 10 w and the conductive shield layer 40 are connected.

  In addition, a lead wire 19 extends from the external connection terminal 17g having the ground potential (or the second wiring layer 13 in contact with the external connection terminal 17g). The lead wire 19 is a conductive paste containing copper (Cu) foil, silver (Ag), or copper (Cu).

  The lead lines 19 are further connected to some of the plurality of vias 14 arranged on the side surface 10w. In FIG. 2B, the via connected to the lead-out line 19 is designated as a via 14g using a reference numeral 14g. As a result, the plurality of vias 14g arranged on the side surface 10w of the circuit board 10 can be at the ground potential.

  In the semiconductor device 1, each of the external connection terminals 17g (or the second wiring layer 13 in contact with the external connection terminals 17g) is electrically connected to each of the plurality of vias 14g that are further part of the vias 14 disposed on the side surface 10w. By being connected to the conductive shield layer 40, the conductive shield layer 40 can be at the ground potential. That is, in the semiconductor device 1, a plurality of contacts between the conductive shield layer 40 and the ground potential are provided. The lead line 19 for supplying the ground potential to the via 14g may be provided on the upper surface side of the circuit board 10.

  Further, the number and arrangement of the external connection terminals 17g (or the second wiring layers 13 in contact with the external connection terminals 17g) that become the ground potential are not limited to the example described above. An example is shown below.

  3A and 3B are schematic plan views of the semiconductor device according to the first embodiment. FIG. 3A is a schematic plan view of a circuit board according to a first modification, and FIG. 3B is a plan view of a circuit board according to a second modification. It is a schematic diagram. 3A and 3B illustrate the lower surface side of the circuit board 10.

  In the circuit board 10 shown in FIG. 3A, each of the external connection terminals 17g (or the second wiring layer 13 in contact with the external connection terminals 17g) having a ground potential is provided at the center of one side of the element mounting region 23. positioned. In other words, each of the external connection terminals 17g (or the second wiring layer 13 in contact with the external connection terminals 17g) is located between adjacent corners of the semiconductor element 20.

  A lead wire 19 extends from the external connection terminal 17g having the ground potential (or the second wiring layer 13 in contact with the external connection terminal 17g). The lead wire 19 is further connected to a plurality of vias 14g arranged on the side surface 10w. The via 14 g is connected to the conductive shield layer 40.

  In the circuit board 10 shown in FIG. 3B, the configuration of FIG. 2B and the configuration of FIG. 3A are combined. In other words, each of the external connection terminals 17g (or the second wiring layer 13 in contact with the external connection terminals 17g) having a ground potential is located between the corners of the semiconductor element 20 and the adjacent corners.

  The distance at which the external connection terminals 17g (or the second wiring layer 13 in contact with the external connection terminals 17g) are adjacent to each other is adjusted to be half or less the wavelength of electromagnetic noise emitted from the semiconductor element 20 or the like.

Next, a manufacturing process of the semiconductor device 1 will be described.
FIG. 4 is a schematic cross-sectional view illustrating the manufacturing process of the semiconductor device according to the first embodiment.

  First, as shown in FIG. 4A, the semiconductor device 1 before separation is formed. At this stage, the circuit board 10 is in a state before cutting, and a plurality of semiconductor devices 1 are connected.

  Next, the dicing blade 90 is inserted into the circuit board 10 along the dicing line DL. At this stage, so-called half dicing is performed so that the dicing blade 90 does not reach the lower surface side of the circuit board 10. That is, insertion of the dicing blade 90 is stopped halfway in the depth direction of the via 14 in the vicinity of the dicing line DL, and the cut surface in which the via 14 is cut in the thickness direction of the circuit board 10 is exposed. This state is shown in FIG.

  The cut surface of the via 14 is not necessarily the center of the via 14, and a part of the via 14 is included in the cut surface. In order to increase the contact area between the via 14 and the conductive shield layer 40, it is desirable that the cut surface of the via 14 be closer to the center of the via 14.

  Subsequently, after the sealing resin layer 30 is cured, the conductive shield layer 40 is coated on the sealing resin layer 30 as shown in FIG. The conductive shield layer 40 is also embedded in the recess 90h formed by half dicing.

  The conductive shield layer 40 is formed by, for example, a transfer method, a screen printing method, a spray coating method, a jet dispensing method, an ink jet method, an aerosol method, an electroless plating method, an electrolytic plating method, or a vacuum processing method.

  By burying the conductive shield layer 40 in the recess 90 h, the conductive shield layer 40 contacts the cut surface of the via 14. Thereafter, the conductive shield layer 40 is cured as necessary.

  Next, as shown in FIG. 4D, dicing for singulation is performed to form the semiconductor device 1.

The effect of the semiconductor device 1 will be described.
FIG. 5 is a simulation result for explaining the shielding effect of electromagnetic noise.

  In FIG. 5A, the horizontal axis represents the noise frequency (MHz) emitted from the semiconductor element 20 and the like, and the vertical axis represents the shielding effect (dB) for shielding noise. The higher the vertical axis, the greater the shielding effect.

  Each of the lines (1) to (4) in FIG. 5 (a) is a simulation result calculated according to each of the patterns (1) to (4) in FIG. 5 (b).

  In the pattern (1), one external connection terminal 17 g is electrically connected to the conductive shield layer 40. That is, there is one place where the conductive shield layer 40 is in contact with the ground potential.

  In the pattern (2), in addition to the pattern (1), the external connection terminals 17g arranged at the corners (four corners) of the semiconductor element 20 are electrically connected to the conductive shield layer 40. That is, there are five places where the conductive shield layer 40 is in contact with the ground potential.

  In the pattern (3), in addition to the pattern (1), the external connection terminals 17g arranged between adjacent corners of the semiconductor element 20 are electrically connected to the conductive shield layer 40. That is, there are five places where the conductive shield layer 40 is in contact with the ground potential.

  In the pattern (4), in addition to the pattern (1), the external connection terminals 17g disposed between the corners (four corners) of the semiconductor element 20 and the adjacent corners of the semiconductor element 20 are electrically conductive. The shield layer 40 is electrically connected. That is, there are nine places where the conductive shield layer 40 is in contact with the ground potential.

  When the noise frequency is 50 to 900 (MHz), the line (1) shows 6 to 9 (dB), while the lines (2) and (3) rise to 13 to 14 (dB). To do. Furthermore, in the line of (4), it has risen to about 15 (dB). For example, at 900 (MHz) having the highest noise frequency, (2) and (3) rise about 6 (dB) with respect to (1), and (4) is about about 1 (1). It rises by 8 (dB). Thus, the shielding effect improves as the number of portions where the conductive shield layer 40 is in contact with the ground potential increases.

  In the semiconductor device 1, the via 14 disposed on the side surface 10 w of the circuit board 10 penetrates the circuit board 10 in the thickness direction, so that leakage of electromagnetic waves from the entire side surface of the circuit board 10 is suppressed.

  Further, in the semiconductor device 1, a plurality of portions where the conductive shield layer 40 is in contact with the ground potential are provided, and the interval between these portions is adjusted to be half or less of the wavelength of electromagnetic noise emitted from the semiconductor element 20 or the like. Therefore, electromagnetic noise can be more reliably shielded by the conductive shield layer 40.

  When the conductive shield layer 40 has only one location in contact with the ground potential, noise may easily leak from between the circuit board 10 and the conductive shield layer 40. For example, when the semiconductor element 20 emits noise from a predetermined location, if the predetermined location is separated from the location where the conductive shield layer 40 is in contact with the ground potential, the circuit board 10 and the conductive shield layer 40 are separated. There is a possibility that noise is likely to leak from between.

  On the other hand, in the semiconductor device 1, a plurality of portions where the conductive shield layer 40 is in contact with the ground potential are provided, and the conductive shield layer 40 is uniformly set to the ground potential. Thereby, electromagnetic noise can be more reliably shielded by the conductive shield layer 40.

(Second Embodiment)
FIG. 6 is a schematic cross-sectional view of a semiconductor device according to the second embodiment.
The basic structure of the semiconductor device 2 is the same as that of the semiconductor device 1. However, in the circuit board 10 according to the second embodiment, the via 14 provided on the side surface 10 w of the circuit board 10 is not exposed on the side surface 10 w of the circuit board 10. In the circuit board 10 according to the second embodiment, the wiring layer 14m on the via 14g provided in the vicinity of the side surface 10w of the circuit board 10 is exposed on the side surface 10w of the circuit board 10. The material of the wiring layer 14m is the same as that of the via 14g. The land-like wiring layer 14m connected to the via 14g is connected to the conductive shield layer 40. The wiring layer 14m is electrically connected to the external connection terminal 17g having the ground potential (or the second wiring layer 13 in contact with the external connection terminal 17g).

  That is, each of the external connection terminals 17g (or the second wiring layer 13 in contact with the external connection terminals 17g) is electrically connected to the wiring layer 14m on the side surface 10w, so that the conductive shield layer 40 becomes the ground potential. Can do. In the semiconductor device 2, a plurality of contacts between the conductive shield layer 40 and the ground potential are provided via the wiring layer 14m. Such a semiconductor device 2 also provides the same effects as the semiconductor device 1.

(Third embodiment)
FIG. 7 is a schematic plan view of the semiconductor device according to the third embodiment and a diagram for explaining a shielding effect. FIG. 7A is a schematic plan view of a circuit board of a semiconductor device, and FIG. 7B is a diagram for explaining a shielding effect.
FIG. 7A illustrates a plane on the lower surface side of the circuit board 10.

In the circuit board 10 according to the third embodiment, as a second wiring layer, ring-shaped wiring is provided on the outer periphery of the external connection terminals 17 (or the second wiring layer 13 in contact with the external connection terminals 17) arranged vertically and horizontally. A layer 19r is provided. That is, the circuit board 10 is further provided with a ring-shaped wiring layer 19r surrounding the external connection terminal 17 (or the second wiring layer 13 in contact with the external connection terminal 17) provided on the lower surface side of the insulating base 11. ing. The wiring layer 19r is electrically connected to one of the external connection terminals 17g (or the second wiring layer 13 in contact with the external connection terminals 17g).
For example, if the external connection terminal 17g becomes the ground potential, all of the wiring layer 19r and the via 14g become the ground potential.

  The external connection terminal 17g and the wiring layer 19r are effective when they are electrically connected at an interval narrower than half the wavelength of electromagnetic noise, and the shielding effect is higher when they are connected at a narrower interval. In addition, the wiring layer 19r and the via 14g are effective when electrically connected at an interval narrower than a half of the wavelength of electromagnetic noise, and the shielding effect is higher when connected at a narrower interval. The line width of the ring-shaped wiring layer 19r is effective when it is 0.035 mm or more. However, when the width is increased to about 0.5 mm, the electromagnetic wave shielding effect is further enhanced.

In FIG. 7B, the distance between the external connection terminal 17g and the wiring layer 19r is 1.6 mm or less, the distance between the wiring layer 19r and the via 14g is 0.4 mm, and the line width of the wiring layer 19r is as follows. The shielding effect when 0.5 mm is shown. The horizontal axis represents the noise frequency (MHz) emitted from the semiconductor element 20 or the like, and the vertical axis represents the shielding effect (dB) for shielding noise. The higher the vertical axis, the greater the shielding effect.
The circuit board according to the third embodiment has a higher magnetic field shielding effect than the first and second embodiments.

(Fourth embodiment)
FIG. 8 is a schematic cross-sectional view of a semiconductor device according to the fourth embodiment.
The semiconductor device 3 according to the fourth embodiment includes a circuit board 10. The circuit board 10 includes an insulating base material 11, a plurality of wirings 12 constituting a first wiring layer provided on the upper surface side of the insulating base material 11, and a second wiring layer provided on the lower surface side of the insulating base material. A plurality of wirings 13 to be configured. The semiconductor device 3 further includes a semiconductor element 20 mounted on the upper surface side of the circuit board 10, a sealing resin layer 30 provided on the upper surface of the circuit board 10, and a sealing resin. The conductive shield layer 40 that covers the layer 30 and part of the edge of the circuit board 10 is included.

  In the semiconductor device 3, a plurality of wirings 50 constituting a second wiring layer different from the plurality of wirings 12 constituting the first wiring layer and the plurality of wirings 13 constituting the second wiring layer are provided on the lower side of the circuit board 10. Are provided in plurality. The plurality of wirings 50 constituting the second wiring layer are not electrically connected to the conductive shield layer 40, and are provided on the lower surface side of the insulating base 11 where the plurality of wirings 13 constituting the second wiring layer are not provided. It is provided in the area. For example, when the first wiring layer 12 and the lead wire 18 are subjected to electrolytic plating treatment such as nickel (Ni) or gold (Au) on the upper surface side of the circuit board 10, the plurality of wirings 50 constituting the second wiring layer are provided. Functions as a plating wiring. Accordingly, the third wiring layer 50 is electrically connected to any of the plurality of wirings 12 constituting the first wiring layer.

  By routing the wiring 50 of the second wiring layer to the lower side of the circuit board 10, the degree of freedom in wiring design on the upper surface side of the circuit board 10 is improved. Further, since the plurality of 50 constituting the second wiring layer are provided below the circuit board 10, the plurality of wirings 50 constituting the second wiring layer and the conductive shield layer 40 are in contact (conduction). do not do. Accordingly, even if the wiring 50 of the second wiring layer exists after the first wiring layer 12 and the lead wire 18 are plated, the wiring 50 of the second wiring layer and the conductive shield layer 40 do not contact each other. . That is, it is not necessary to remove the wiring 50 of the second wiring layer by the etching process, and the cost of the manufacturing process is not increased. The plurality of wirings 50 are wired to the end of the circuit board 10 so as to be exposed on the side surface 10w.

  Also in the semiconductor device 3, as illustrated, a plurality of vias 14 penetrating from the upper surface to the lower surface of the insulating base material 11 are further provided in the circuit board 10, and a plurality of vias smaller than the number of the plurality of vias 14 are provided. The first group may be exposed on the side surface 10 w of the circuit board 10. In this case, each exposed surface of the first group of vias 14 is connected to the conductive shield layer. Some of the vias 14 exposed on the side surface 10w are vias 14g that are ground potentials.

  All of the external connection terminals 17 (17g) described in the first to fourth embodiments can be removed as necessary, and each of the plurality of wirings 13 constituting the second wiring layer is provided on the lower surface side of the circuit board 10. The exposed semiconductor devices 1 to 3 having an LGA (Land Grid Array) structure are also included in the embodiment.

  Moreover, you may remove as needed about what is not electrically connected to the external connection terminal 17g among several via | veer 14 arrange | positioned at the side surface 10w of the circuit board 10. FIG. Such a form is also included in the embodiment.

  The embodiment has been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the embodiments as long as they include the features of the embodiments. Each element included in each of the specific examples described above and their arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.

  In addition, in the category of the idea of the embodiment, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the embodiment. . In addition, each element included in each embodiment can be combined as much as technically possible, and a combination thereof is also included in the scope of the embodiment as long as it includes the features of the embodiment.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  1, 2, 3 Semiconductor device, 10 circuit board, 10w side surface, 11 insulating substrate, 12 wiring layer, 13 wiring layer, 14, 14g via, 14m wiring layer, 15, 16 solder resist layer, 17, 17g external connection terminal , 18, 19 Lead line, 19r, 50, 101 Wiring layer, 20 Semiconductor element, 21 Wire, 22 Die bonding material, 23 Element mounting area, 30 Sealing resin layer, 40 Conductive shield layer, 90 Dicing blade, 90h Recess , 100 mounting board, DL dicing line

Claims (8)

A circuit board having an insulating base, a plurality of wirings provided on the insulating base, and a cut surface of copper or tungsten exposed on a side surface of the insulating base;
A semiconductor element mounted on the circuit board;
A sealing resin layer for sealing the semiconductor element;
A conductive shield layer covering the sealing resin layer;
An external connection terminal connected to each of the plurality of wirings;
With
The cut surface and the conductive shield layer are connected,
Any of the plurality of wirings and the external connection terminal connected to any of the plurality of wirings can be a ground potential.
The external connection terminal that can be a ground potential is electrically connected to the cut surface through any of the plurality of wirings,
The external connection terminals that can be at ground potential can be at ground potential.
Possible the cutting face each other, and which can be ground potential said external connection terminal and grayed
A semiconductor device in which a distance between the cut surface that can be a land potential and an adjacent wavelength is equal to or less than half the wavelength of the electromagnetic wave to be shielded. 2. The semiconductor device according to claim 1, wherein the external connection terminal that can be a ground potential is located at least between a corner portion of the semiconductor element and an adjacent corner portion of the semiconductor element. The semiconductor device according to claim 1, wherein the position of the external connection terminal that can be a ground potential is a location where the conductive shield layer is in contact with the ground potential. The semiconductor device according to claim 1, wherein a die bonding material is formed between the semiconductor element and the circuit board. On the lower side of the circuit board, further comprising another wiring layer surrounding the external connection terminal,
5. The semiconductor device according to claim 1, wherein the another wiring layer is electrically connected to the external connection terminal that can be a ground potential. 6. The semiconductor according to claim 5, wherein the external connection terminal capable of having a ground potential and the another wiring layer are arranged at an interval narrower than a half of a wavelength of an electromagnetic wave to be shielded. apparatus. The circuit board has a first surface on which the semiconductor element is mounted, and a second surface opposite to the first surface,
The semiconductor device according to claim 1, wherein the external connection terminal is disposed on the second surface side. A circuit board having an insulating base, a plurality of wirings provided on the insulating base, and a cut surface of copper or tungsten exposed on a side surface of the insulating base;
A semiconductor element mounted on the circuit board;
A sealing resin layer for sealing the semiconductor element;
A conductive shield layer covering the sealing resin layer;
An external connection terminal connected to each of the plurality of wirings;
With
The cut surface and the conductive shield layer are connected,
Any of the plurality of wirings and the external connection terminal connected to any of the plurality of wirings can be a ground potential,
The external connection terminal that can be a ground potential is electrically connected to the cut surface through any of the plurality of wirings,
The external connection terminals that can be at ground potential can be at ground potential.
Possible the cutting face each other, and which can be ground potential said external connection terminal and grayed
The distance between the cut surface that can be a land potential and the adjacent distance is a semiconductor device having a frequency that is not more than half the wavelength of an electromagnetic wave having a frequency of 50 MHz to 2.5 GHz.

Images