JP2012160579A - Semiconductor device and manufacturing method of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which increases a connection area between a conductive shield layer and ground wiring and thereby improving the reliability.SOLUTION: A semiconductor device 1 includes: a circuit board 10 having an insulation substrate 11, multiple first wiring layers provided on a first main surface of the insulation substrate, multiple second wiring layers provided on a second main surface of the insulation substrate, and multiple vias 14 penetrating from the first main surface of the insulation substrate to a lower surface thereof; a semiconductor element 20 mounted on the first main surface of the insulation substrate in the circuit board; a sealing resin layer 30 sealing the semiconductor element; and a conductive shield layer 40 covering the sealing resin layer. Any of the multiple first wiring layers are exposed at the end part side of the circuit board, and the conductive shield layer extends toward the semiconductor element and gets into the sealing resin layer to electrically connect with the first wiring layer exposed at the end part side of the circuit board.

Description

  Embodiments described herein relate generally to a semiconductor device and a method for manufacturing the same.

  A semiconductor device is required to suppress leakage of unnecessary electromagnetic waves to the outside. For example, semiconductor devices used for portable communication devices and the like are required to suppress leakage of unnecessary electromagnetic waves to the outside in order to suppress adverse effects on communication characteristics. For this reason, a semiconductor device having a shield function is required. Some semiconductor devices having a shield function have a structure in which a conductive shield layer is provided along the outer surface of a sealing resin layer for sealing a semiconductor element mounted on a circuit board.

  In addition, there is a semiconductor device in which a conductive shield layer is connected to a ground wiring of a circuit board in order to suppress leakage of unnecessary electromagnetic waves from the side surface of the circuit board. However, when the connection area between the conductive shield layer and the ground wiring of the circuit board is reduced, leakage of unnecessary electromagnetic waves cannot be sufficiently suppressed, and the reliability of the semiconductor device is lowered. Accordingly, such a semiconductor device is required to have a higher reliability by further increasing the connection area between the conductive shield layer and the ground wiring.

JP 2010-103574 A JP 2006-287016 A

  The problem to be solved by the present invention is to provide a more reliable semiconductor device and a manufacturing method for manufacturing the semiconductor device.

  The semiconductor device according to the embodiment is provided on the insulating substrate, the plurality of first wiring layers provided on the first main surface side of the insulating substrate, and the second main surface side of the insulating substrate. A circuit board having a plurality of second wiring layers and a plurality of vias penetrating from the first main surface of the insulating base material to the lower surface; and in the circuit board, the first of the insulating base material A semiconductor element mounted on the main surface side, a sealing resin layer that seals the semiconductor element, and a conductive shield layer that covers the sealing resin layer. One of the plurality of first wiring layers is exposed at an end portion side of the circuit board, and the conductive shield layer extends in the sealing resin layer toward the semiconductor element side. , And electrically connected to the first wiring layer exposed on the end side of the circuit board.

  The semiconductor device according to the embodiment is provided on the insulating substrate, the plurality of first wiring layers provided on the first main surface side of the insulating substrate, and the second main surface side of the insulating substrate. A circuit board having a plurality of second wiring layers and a plurality of via connection portions penetrating from the first main surface to the second main surface of the insulating base; and the insulating base in the circuit board A semiconductor element mounted on the first main surface side, a sealing resin layer that seals the semiconductor element, and a conductive shield layer that covers the sealing resin layer. Any of the plurality of via connection portions is exposed on the end side of the circuit board, and the conductive shield layer extends in the sealing resin layer toward the semiconductor element side, It is electrically connected to the via connection exposed at the end of the circuit board.

The method of manufacturing a semiconductor device according to the embodiment includes an insulating base, a plurality of first wiring layers provided on the first main surface side of the insulating base, and a second main surface side of the insulating base. A circuit board having a plurality of second wiring layers provided and a plurality of via connection portions penetrating from the first main surface of the insulating base material to the second main surface of the circuit board. Preparing a plurality of substrates provided continuously in a direction substantially parallel to the main surface, mounting a semiconductor element on the first main surface side in each of the plurality of circuit substrates, and In each of the plurality of circuit boards, a mask member is formed on a predetermined surface of the plurality of first wiring layers, and the semiconductor element and the plurality of first wiring layers are sealed with a sealing resin layer. Stopping the sealing resin layer between each of the adjacent circuit boards Splitting, exposing the mask member from the sealing resin layer, forming a groove in the substrate between each of the adjacent circuit substrates, and exposing the first wiring layer from the substrate; Removing the mask member and exposing the predetermined surface of the first wiring layer on which the mask member is formed; covering the sealing resin layer with a conductive shield layer; And a step of bringing the conductive shield layer into contact with the predetermined surface of the first wiring layer.
Is provided.

The method of manufacturing a semiconductor device according to the embodiment includes an insulating base, a plurality of first wiring layers provided on the first main surface side of the insulating base, and a second main surface side of the insulating base. A circuit board having a plurality of second wiring layers provided and a plurality of via connection portions penetrating from the first main surface of the insulating base material to the second main surface of the circuit board. Preparing a plurality of substrates provided continuously in a direction substantially parallel to the main surface, mounting a semiconductor element on the first main surface side in each of the plurality of circuit substrates, and In each of the plurality of circuit boards, a step of forming a mask member on a predetermined surface of any of the plurality of via connection portions, and sealing the semiconductor element and the plurality of first wiring layers with a sealing resin layer And dividing the sealing resin layer between each of the adjacent circuit boards Exposing the mask member from the sealing resin layer, forming a groove in the substrate between each of the adjacent circuit substrates, and exposing the via connection portion from the substrate; and the mask member And exposing the predetermined surface of the via connection portion on which the mask member is formed, and covering each sealing resin layer with a conductive shield layer, while exposing the exposed via connection portion. And the step of bringing the conductive shield layer into contact with the predetermined surface.
Is provided.

2A and 2B are schematic cross-sectional views for explaining the outline of the semiconductor device according to the first embodiment, in which FIG. 1A is an overall view and FIG. 1B is an enlarged view; 1 is a schematic plan view illustrating a semiconductor device according to a first embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 1st Embodiment. It is a schematic diagram of the semiconductor device which concerns on 2nd Embodiment, (a) is a cross-sectional schematic diagram, (b) is a plane schematic diagram. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 2nd Embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 2nd Embodiment. It is a perspective schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 3rd Embodiment. It is a schematic diagram of the semiconductor device which concerns on 4th Embodiment, (a) is a cross-sectional schematic diagram, (b) is a plane schematic diagram. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 4th Embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 4th Embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 5th Embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 5th Embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 6th Embodiment. It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 6th Embodiment. It is a schematic diagram for demonstrating the base | substrate of the semiconductor device used in the manufacturing process of the semiconductor device which concerns on 7th Embodiment, (a) is a surface schematic diagram of a base | substrate, (b) is X- of (a). It is a cross-sectional schematic diagram of X 'position, (c) is a cross-sectional schematic diagram of YY' position of (a). It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 7th Embodiment. It is a schematic diagram for demonstrating another base | substrate of the semiconductor device used in the manufacturing process of the semiconductor device which concerns on 7th Embodiment, (a) is a surface schematic diagram of a base | substrate, (b) is (a). It is a cross-sectional schematic diagram of XX 'position, (c) is a cross-sectional schematic diagram of YY' position of (a). It is a schematic diagram for demonstrating the base | substrate of the semiconductor device used in the manufacturing process of the semiconductor device which concerns on 8th Embodiment, (a) is a lower surface schematic diagram of a base | substrate, (b) is X- of (a). It is a cross-sectional schematic diagram of X 'position, (c) is a cross-sectional schematic diagram of YY' position of (a). It is a cross-sectional schematic diagram for demonstrating the manufacturing process of the semiconductor device which concerns on 8th Embodiment. It is a schematic diagram for demonstrating another base | substrate of the semiconductor device used in the manufacturing process of the semiconductor device which concerns on 8th Embodiment, (a) is a bottom surface schematic diagram of a base | substrate, (b) is (a). It is a cross-sectional schematic diagram of XX 'position, (c) is a cross-sectional schematic diagram of YY' position of (a).

  Hereinafter, embodiments will be described with reference to the drawings. In the following description, the same members are denoted by the same reference numerals, and the description of the members once described is omitted as appropriate. Moreover, each embodiment described below can be combined suitably.

(First embodiment)
1A and 1B are schematic cross-sectional views for explaining a semiconductor device according to the first embodiment. FIG. 1A is an overall view and FIG. 1B is an enlarged view.
FIG. 2 is a schematic plan view illustrating the semiconductor device according to the first embodiment.

FIG. 1A shows a cross section taken along line XX ′ of FIG. 2, and FIG. 1B shows a portion surrounded by a broken line 100 of FIG.
The semiconductor device 1 according to the first embodiment is an FBGA (Fine pitch Ball Grid Array) type semiconductor package. The semiconductor device 1 includes a circuit board 10. The circuit board 10 is also referred to as an interposer board. The circuit board 10 includes an insulating base material 11 as a base, a plurality of wiring layers 12 provided on the outer periphery on the upper surface side of the insulating base material 11, a plurality of wiring layers 15 provided inside the wiring layer 12, And a plurality of wiring layers 13 provided on the lower surface side of the insulating base material 11. The side surface of the wiring layer 12 is exposed from the circuit board 10 on the side surface (end side) 10 w of the circuit board 10. The potential of the wiring layer 12 can be a ground (GND) potential. A solder resist layer 16 for covering a part of each wiring layer is formed on the upper and lower surfaces of the circuit board 10. In the embodiment, the first wiring layer is configured by the wiring layer 12 or the wiring layer 15. The second wiring layer is constituted by the wiring layer 13.

  The circuit board 10 further includes a plurality of vias (via connection portions) 14 penetrating from the upper surface (first main surface) to the lower surface (second main surface) of the insulating base material 11. The number of vias 14 is not limited to the number illustrated, and a plurality of vias 14 are provided on the circuit board 10. One of the wiring layers 12 is connected to one of the external connection terminals 17 through a via in the circuit board 10.

  Each of the plurality of wiring layers 13 is a land electrode. An external connection terminal 17 that is a solder ball is connected to each of the plurality of wiring layers 13. Each of the plurality of external connection terminals 17 is mounted on a mounting board (not shown), for example. The semiconductor device 1 may have an LGA (Land Grid Array) structure in which the external connection terminals 17 are removed.

  A semiconductor element 20 is mounted on the upper surface side of the circuit board 10. One end of a wire (bonding wire) 21 is connected to the upper surface of the semiconductor element 20. The other end of the wire 21 is connected to the wiring layer 15. The wire 21 electrically connects at least one of the wiring layers 15 and an electrode (not shown) provided on the surface of the semiconductor element.

  The outer periphery of the semiconductor element 20 and the wire 21 are sealed with a sealing resin layer 30 provided on the upper surface side of the circuit board 10. A die bonding material (mounting material) 22 is formed in the gap between the semiconductor element 20 and the circuit board 10.

  The upper surface and side surfaces of the sealing resin layer 30 are covered with the conductive shield layer 40. The conductive shield layer 40 penetrates into the sealing resin layer 30 from the side surface of the sealing resin layer 30 toward the semiconductor element 20 side above the wiring layer 12. Further, the conductive shield layer 40 is in contact with the wiring layer 12. For example, the protruding portion 40 p extends from the inner surface of the conductive shield layer 40. The conductive shield layer 40 is electrically connected to the wiring layer 12 exposed on the end side of the circuit board 10 so as to extend into the sealing resin layer 30 toward the semiconductor element 20 side. When the protrusion 40 p enters the side surface of the sealing resin layer 30, the conductive shield layer 40 comes into contact with the upper surface and the side surface of the wiring layer 12.

  The wiring layer 12 exposed on the end side of the circuit board 10 is configured to have a ground potential. When the potential of the wiring layer 12 becomes the ground potential, the potential of the conductive shield layer 40 can be set to the ground potential through the wiring layer 12. A plurality of contacts between the wiring layer 12 and the conductive shield layer 40 are provided on each side of the semiconductor device 1 (see FIG. 2). The number and position of the contacts between the ground potential and the conductive shield layer 40 are not limited to the above-described example. Further, the distance between the contact points of the wiring layer 12 at the ground potential and the conductive shield layer 40 is adjusted to half or less the wavelength of unnecessary electromagnetic waves (also referred to as electromagnetic noise or noise radio waves) emitted from the semiconductor element 20 or the like. Has been.

  The semiconductor element 20 is a storage element such as a flash memory or a DRAM, or an arithmetic element such as a microprocessor. The wire 21 is, for example, a metal wire such as gold (Au), aluminum (Al), or copper (Cu).

  The wiring layer 12, the wiring layer 13, and the wiring layer 15 are a conductive paste containing copper (Cu) foil, silver (Ag), or copper (Cu), and the like. In this case, the surface is plated with nickel (Ni), gold (Au) or the like as necessary. The via 14 is, for example, a columnar electrode. The via 14 may be a columnar electrode in which all materials are made of a conductive material. In addition to the columnar electrode, the via 14 may include a cylindrical cylindrical electrode and a resin embedded in the hollow of the cylindrical electrode. Good. The material of the via 14 is copper (Cu), tungsten (W), or the like.

  For the conductive shield layer 40, a material having a resistivity as low as possible is selected in order to block high-frequency noise emitted from the semiconductor element 20. Examples of the material of the conductive shield layer 40 include silver (Ag), copper (Cu), nickel (Ni), and the like. More specifically, the conductive shield layer 40 is a silver (Ag) -containing layer obtained by curing a silver (Ag) paste, and its sheet resistance is adjusted to 0.1 (Ω / □) or less. The thickness of the conductive shield layer 40 is several tens of μm, and more preferably 10 to 90 μm.

Next, a manufacturing process of the semiconductor device 1 will be described.
3 and 4 are schematic cross-sectional views for explaining the manufacturing process of the semiconductor device according to the first embodiment.
FIG. 3 illustrates a manufacturing process in three stages (a) to (c). On the right side of each stage, an enlarged view of a portion surrounded by a broken line 100 on the left side is shown.

  First, as illustrated in FIG. 3A, a substrate 10 </ b> A in which a plurality of circuit boards 10 are continuously provided in a direction parallel to the main surface of the circuit board 10 is prepared. Subsequently, the semiconductor element 20 is mounted on each of the plurality of circuit boards 10. Then, at least one of the plurality of wiring layers 15 and the semiconductor element 20 are electrically connected via a wire 21. At this stage, the circuit board 10 is in a state before cutting, and a plurality of semiconductor elements 20 are mounted on the board 10A. Thereby, the insulating base material 11, the plurality of wiring layers 12 provided on the first main surface side of the insulating base material 11, and the plurality of wiring layers provided on the second main surface side of the insulating base material 11 13 and a plurality of via connection portions penetrating from the first main surface to the second main surface of the insulating base material 11 in a direction substantially parallel to the main surface of the circuit board. A plurality of substrates 10A provided continuously are prepared. Further, in each of the plurality of circuit boards 10, the semiconductor element 20 is mounted on the first main surface side.

  Subsequently, a mask member 50 is formed on a predetermined surface of any of the plurality of wiring layers 12 in each of the plurality of circuit boards 10. For example, the mask member 50 is formed on at least a part of the upper surface of any one of the plurality of wiring layers 12. The mask member 50 is provided on each of the plurality of circuit boards 10. For example, the mask member 50 is provided on each of the plurality of wiring layers 12 shown in FIG. Thereby, at least a part of the upper surface of each wiring layer 12 is covered with the mask member 50.

  The material of the mask member 50 is any one of a biodegradable resin, a water-soluble resin, a hydrolyzable resin, an enzyme-decomposable resin, and an organic acid-soluble resin. Polyvinyl alcohol (PVA) is selected as the biodegradable resin and the water-soluble resin. As the biodegradable resin and the hydrolyzable resin, poly L-lactic acid resin (PLLA) and starch resin are selected. Polybutylene succinate lactate resin (PBSL) is selected as the hydrolyzable resin and the enzyme degradable resin. As the organic acid-soluble resin, a copolymer nylon or polyamide obtained by exchange reaction of polyamide and polyamidepoamine is selected. If necessary, the mask member 50 may contain an ultraviolet absorber.

  Next, as shown in FIG. 3B, the plurality of semiconductor elements 20, the wires 21, the wiring layer 12, and the mask member 50 are sealed with a sealing resin layer 30.

  Next, as shown in FIG. 3C, the sealing resin layer 30 between each of the adjacent circuit boards 10 is divided to expose the mask member 50 from the sealing resin layer 30, and the adjacent circuit boards. A groove is formed in the substrate 10A between each of the ten, and the wiring layer 12 is exposed from the substrate 10A. For example, the sealing resin layer 30 between the adjacent circuit boards 10 is divided, and the grooves 30t are formed to such an extent that cutting grooves are formed on the upper surface of the board 10A. The groove 30t is formed by so-called half-cut dicing. In the half-cut dicing process, the sealing resin layer 30 is divided, but the circuit board 10 is not completely divided. By forming the groove 30t, the side surface of the mask member 50 is exposed from the sealing resin layer 30, and the side surface of the wiring layer 12 is exposed from the substrate 10A. Inside the groove 30t, the side surfaces of the sealing resin layer 30, the mask member 50, and the wiring layer 12 are flush with each other. Thereafter, the sealing resin layer 30 is cured as necessary.

Next, as shown in FIG. 4A, the mask member 50 is removed. Thereby, the predetermined surface of the wiring layer 12 on which the mask member is formed is exposed.
For example, when the material of the mask member 50 is polybutylene succinate lactate resin, the mask member 50 is removed by using both alkaline decomposition and enzymatic decomposition using a mixed solution of an alkaline aqueous solution and a lipase enzyme solution.

  When the material of the mask member 50 is a resin such as polylactic acid, the mask member 50 is removed by alkaline aqueous solution decomposition and hydrolysis. The polylactic acid resin has a property of hydrolyzing with an alkaline aqueous solution. Polylactic acid resins are resistant to acidic aqueous solutions, but are easily removed with alkaline aqueous solutions.

Thus, depending on the material of the mask member 50, the mask member 50 is removed by alkaline decomposition and hydrolysis with an alkaline aqueous solution, or alkaline decomposition and enzymatic decomposition are combined using a mixed solution of an alkaline aqueous solution and a lipase enzyme solution. Then, the mask member 50 is removed. That is, in the embodiment, the mask member 50 is removed by alkali decomposition and enzyme decomposition, or alkaline aqueous solution decomposition and hydrolysis.
When the mask member 50 is removed, at least a part of the upper surface of the wiring layer 12 is exposed.

  Next, as shown in FIG. 4B, the conductive shield layer 40 is brought into contact with the predetermined surface of the exposed wiring layer 12 while covering each sealing resin layer 30 with the conductive shield layer 40. For example, the conductive shield layer 40 is formed on the upper surface and the side surface of each sealing resin layer 30. The conductive shield layer 40 is formed by, for example, a transfer method, a screen printing method, a spray coating method, a jet dispensing method, an ink jet method, an aerosol method, an electroless plating method, an electrolytic plating method, or a vacuum processing method.

  The conductive shield layer 40 embedded in the groove 30t also enters the portion (space) from which the mask member 50 has been removed. That is, the protrusion 40p extends from the inner surface of the conductive shield layer 40, and the protrusion 40p enters the portion from which the mask member 50 has been removed. As a result, the conductive shield layer 40 comes into contact with the upper surface and side surfaces of the wiring layer 12. Thereafter, the external connection terminal 17 is formed.

  Next, as shown in FIG. 4C, the conductive shield layer 40 formed in the groove 30t and the substrate 10A under the groove 30t are divided by dicing. That is, the continuous circuit board 10 is divided into pieces, and the semiconductor device 1 is formed.

  The conductive shield layer 40 may be covered with a protective film having excellent corrosion resistance and migration resistance as necessary. A polyimide resin or the like is used as the protective film. About the electroconductive shield layer 40 and a protective film, it hardens | cures by baking or ultraviolet irradiation as needed.

  According to the semiconductor device 1, the conductive shield layer 40 contacts not only the side surface of the wiring layer 12 but also the upper surface and side surfaces of the wiring layer 12. Therefore, the contact area between the conductive shield layer 40 and the ground wiring (that is, the wiring layer 12) is remarkably increased as compared with the embodiment in which the conductive shield layer 40 is in contact only with the side surface of the wiring layer 12. As a result, unnecessary electromagnetic waves from the semiconductor element 20 and the like are efficiently shielded by the conductive shield layer 40. In particular, when the thickness of the wiring layer 12 is thin and the area of the upper surface of the wiring layer 12 is significantly larger than the area of the side surface, the conductive shield layer 40 comes into contact with the upper surface of the wiring layer 12, so The contact area with the conductive shield layer 40 is remarkably increased.

  Further, according to the semiconductor device 1, the conductive shield layer 40 is recessed from the sealing resin layer 30 above the wiring layer 12. Therefore, an anchor effect occurs in the portion where the conductive shield layer 40 is inserted. Due to the anchor effect, the conductive shield layer 40 and the wiring layer 12 are mechanically firmly connected. That is, in the semiconductor device 1, the mechanical connection reliability between the conductive shield layer 40 and the wiring layer 12 is improved.

  Further, according to the semiconductor device 1, the contact area between the conductive shield layer 40 and the ground wiring is increased only by inserting the conductive shield layer 40 into the sealing resin layer 30 above the wiring layer 12. . Accordingly, an increase in the area of the semiconductor device 1 is suppressed.

  Thus, the leakage of unnecessary electromagnetic waves is efficiently suppressed from the semiconductor device 1 including the circuit board 10. Thereby, the reliability of the semiconductor device 1 is further improved.

(Second Embodiment)
5A and 5B are schematic views of the semiconductor device according to the second embodiment. FIG. 5A is a schematic cross-sectional view, and FIG. 5B is a schematic plan view. FIG. 5A shows the XX ′ cross section of FIG.

  The basic configuration of the semiconductor device 2 according to the second embodiment is the same as that of the semiconductor device 1. However, in the semiconductor device 2, the protrusion 40 p of the conductive shield layer 40 extends in a line shape from the upper surface of the wiring layer 12 to the upper surface of the sealing resin layer 30. The conductive shield layer 40 extends in a line shape in the resin sealing layer 30 and is in contact with the wiring layer 12 exposed on the end side of the circuit board 10. In other words, the conductive shield layer 40 penetrates from the upper surface of the wiring layer 12 to the upper surface of the sealing resin layer 30 in a line shape.

  6 and 7 are schematic cross-sectional views for explaining the manufacturing process of the semiconductor device according to the second embodiment.

  The manufacturing process of the semiconductor device 2 is the same as the manufacturing process of the semiconductor device 1 except that the mask member 51 having a shape different from that of the mask member 50 is used. The mask member 51 includes a core material containing a metal or a resin, and a layer in which the resin of the material of the mask member 50 is formed on the surface of the core material. Alternatively, the entire material of the mask member 51 may be the same as that of the mask member 50.

  First, as shown in FIG. 6A, after preparing the substrate 10 </ b> A, the semiconductor element 20 is mounted on each of the circuit substrates 10. Subsequently, at least one of the plurality of wiring layers 15 and the semiconductor element 20 are electrically connected via a wire 21.

  Subsequently, a mask member 51 is formed on at least a part of the upper surface of any one of the plurality of wiring layers 12. The mask member 51 is provided on each of the plurality of circuit boards 10. For example, the mask member 51 is provided on each of the plurality of wiring layers 12 shown in FIG. The mask member 51 is a bar that extends from the upper surface of the wiring layer 12 to the upper surface of the sealing resin layer 30 formed in a later step.

  Next, as shown in FIG. 6B, the plurality of semiconductor elements 20, the wires 21 and the mask member 51 are sealed with a sealing resin layer 30. That is, the height of the mask member 51 and the height of the sealing resin layer 30 are substantially equal.

  Next, as shown in FIG. 6C, the sealing resin layer 30 between each of the adjacent circuit boards 10 is divided, and a groove 30t is formed to such an extent that a cutting groove is formed on the upper surface of the board 10A. To do. The groove 30t is formed by so-called half-cut dicing. By forming the groove 30 t, the side surface of the wiring layer 12 and the side surface of the mask member 51 are exposed from the sealing resin layer 30. In the groove 30t, the side surfaces of the sealing resin layer 30, the mask member 51, and the wiring layer 12 are flush with each other. Thereafter, the sealing resin layer 30 is cured as necessary.

Next, as shown in FIG. 7A, the mask member 51 is removed.
When the mask member 51 has a core material and a resin layer, and the material of the resin layer is polybutylene succinate lactate resin, combined use of alkaline decomposition and enzymatic decomposition with a mixed solution of an alkaline aqueous solution and a lipase enzyme solution Then, the resin layer is removed. When the material of the resin layer is a resin such as polylactic acid, the resin layer is removed by alkaline aqueous solution decomposition and hydrolysis. The polylactic acid resin has a property of hydrolyzing with an alkaline aqueous solution. Polylactic acid resins are resistant to acidic aqueous solutions, but are easily removed with alkaline aqueous solutions. Further, the remaining core material is removed from the sealing resin layer 30.

When the entire material of the mask member 51 is the same as that of the mask member 50, the method of removing the mask member 51 is the same as the method of removing the mask member 50.
When the mask member 51 is removed, at least a part of the upper surface of the wiring layer 12 is exposed.

  Next, as shown in FIG. 7B, the conductive shield layer 40 is formed on the upper surface and the side surface of each sealing resin layer 30. The conductive shield layer 40 embedded in the groove 30t also enters the portion from which the mask member 51 has been removed. That is, the protruding portion 40p extends from the inner surface of the conductive shield layer 40, and the protruding portion 40p enters the portion from which the mask member 51 has been removed. As a result, the conductive shield layer 40 comes into contact with the upper surface and side surfaces of the wiring layer 12. Thereafter, the external connection terminal 17 is formed.

  Next, as shown in FIG. 7C, the conductive shield layer 40 formed in the groove 30t and the substrate 10A under the groove 30t are divided by dicing. That is, the continuous circuit board 10 is divided into pieces, and the semiconductor device 2 is formed.

  According to the semiconductor device 2, the conductive shield layer 40 contacts not only the side surface of the wiring layer 12 but also the upper surface and side surfaces of the wiring layer 12. Therefore, the contact area between the conductive shield layer 40 and the ground wiring (that is, the wiring layer 12) is remarkably increased as compared with the embodiment in which the conductive shield layer 40 is in contact only with the side surface of the wiring layer 12. As a result, unnecessary electromagnetic waves from the semiconductor element 20 and the like are efficiently shielded by the conductive shield layer 40. In the semiconductor device 2, the thickness of a part of the side surface of the conductive shield layer 40 is increased by providing the line-shaped protrusion 40 p. Therefore, in the semiconductor device 2, unnecessary electromagnetic waves from the semiconductor element 20 and the like are shielded by the conductive shield layer 40 more efficiently than the semiconductor device 1.

  Further, according to the semiconductor device 2, the conductive shield layer 40 is recessed from the sealing resin layer 30 above the wiring layer 12. Therefore, an anchor effect occurs in the portion where the conductive shield layer 40 is inserted. Due to the anchor effect, the conductive shield layer 40 and the wiring layer 12 are mechanically firmly connected. That is, in the semiconductor device 2, the mechanical connection reliability between the conductive shield layer 40 and the wiring layer 12 is improved.

  Further, according to the semiconductor device 2, the contact area between the conductive shield layer 40 and the ground wiring is increased only by inserting the conductive shield layer 40 into the sealing resin layer 30 above the wiring layer 12. . Accordingly, an increase in the area of the semiconductor device 2 is suppressed.

  Thus, the leakage of unnecessary electromagnetic waves is efficiently suppressed from the semiconductor device 2 including the circuit board 10. Thereby, the reliability of the semiconductor device 2 is further improved.

(Third embodiment)
Regarding the mask members 50 and 51 described above, the embodiment includes a manufacturing method of a semiconductor device in which the mask member 50 and the mask member 51 are used together, in addition to a manufacturing process used independently.

  FIG. 8 is a schematic perspective view for explaining the manufacturing process of the semiconductor device according to the third embodiment.

  FIG. 8A shows a state after the mask members 50 and 51 are arranged on the wiring layer 12, and FIG. 8B shows the sealing resin layer 30 and the circuit board after half-cut dicing. Ten states are illustrated.

  As shown in FIG. 8A, mask members 50 and mask members 51 may be alternately arranged on the wiring layer 12 of the circuit board 10. When half-cut dicing is performed after forming the sealing resin layer 30 in this state, the side surfaces of the wiring layer 12 and the side surfaces of the mask members 50 and 51 are formed as shown in FIG. 8B. 30 is exposed. Thereafter, the mask members 50 and 51 are removed, and the conductive shield layer 40 is formed as in the first and second embodiments. Such a manufacturing process is also included in the embodiment of the present invention.

(Fourth embodiment)
9A and 9B are schematic views of a semiconductor device according to the fourth embodiment. FIG. 9A is a schematic cross-sectional view, and FIG. 9B is a schematic plan view. FIG. 9A shows the XX ′ cross section of FIG. 9B.

  The circuit board 10 of the semiconductor device 3 according to the fourth embodiment includes an insulating base material 11, a plurality of wiring layers 12, a plurality of wiring layers 15, and a plurality of wiring layers 13. The circuit board 10 further includes a plurality of vias 14 penetrating from the upper surface to the lower surface of the insulating base material 11.

  In the fourth embodiment, the via 14 is exposed on the side surface 10 w of the circuit board 10. The via connection portion exposed on the end side of the circuit board 10 is configured to have a ground potential. That is, the potential of the via 14 exposed on the side surface 10w of the circuit board 10 can be set to the ground potential.

  The upper surface and side surfaces of the sealing resin layer 30 are covered with the conductive shield layer 40. The conductive shield layer 40 penetrates into the sealing resin layer 30 from the side surface of the sealing resin layer 30 toward the semiconductor element 20 side above the via 14. Further, the conductive shield layer 40 is in contact with the via 14 exposed on the side surface 10 w of the circuit board 10. For example, the protruding portion 40 p extends from the inner surface of the conductive shield layer 40. The conductive shield layer 40 is electrically connected to the via connection exposed at the end of the circuit board 10 so as to extend into the sealing resin layer 30 toward the semiconductor element 20. When the protrusion 40 p enters the side surface of the sealing resin layer 30, the conductive shield layer 40 comes into contact with the upper surface and the side surface of the via 14 exposed at the side surface 10 w of the circuit board 10.

  When the potential of the via 14 exposed on the side surface 10w of the circuit board 10 becomes the ground potential, the potential of the conductive shield layer 40 can be set to the ground potential through the via 14 that is at the ground potential. A plurality of contacts between the via 14 at the ground potential and the conductive shield layer 40 are provided on each side of the semiconductor device 3 (see FIG. 9B). The distance between the contacts of the via 14 at the ground potential and the conductive shield layer 40 is adjusted to be half or less of the wavelength of the unnecessary electromagnetic wave emitted from the semiconductor element 20 or the like.

  The exposed surface of the via 14 exposed on the side surface 10w of the circuit board 10 is formed by, for example, half-cut dicing. A cut surface in which the via 14 is cut in the thickness direction of the circuit board 10 is exposed on the side surface 10 w of the circuit board 10.

  The cut surface of the via 14 is not necessarily the center of the via 14, and a part of the via 14 is included in the cut surface. In order to increase the contact area between the via 14 and the conductive shield layer 40, it is desirable that the cut surface of the via 14 be closer to the center of the via 14.

  10 and 11 are schematic cross-sectional views for explaining the manufacturing process of the semiconductor device according to the fourth embodiment.

  First, as shown to Fig.10 (a), after preparing the board | substrate 10A, the semiconductor element 20 is mounted in each of the circuit boards 10. FIG. Subsequently, at least one of the plurality of wiring layers 15 and the semiconductor element 20 are electrically connected via a wire 21. That is, the insulating base material 11, the plurality of wiring layers 12 provided on the first main surface side of the insulating base material 11, and the plurality of wiring layers 13 provided on the second main surface side of the insulating base material 11. And a plurality of via connection portions penetrating from the first main surface to the second main surface of the insulating base material 11 in a direction substantially parallel to the main surface of the circuit board 10 A plurality of substrates 10A provided continuously are prepared. Further, in each of the plurality of circuit boards 10, the semiconductor element 20 is mounted on the first main surface side.

  Subsequently, in each of the plurality of circuit boards 10, a mask member 50 is formed on a predetermined surface of any of the plurality of via connection portions. For example, the mask member 50 is formed on at least a part of the upper surface of any one of the plurality of vias 14. The mask member 50 is provided on each of the plurality of circuit boards 10.

  Next, as shown in FIG. 10B, the plurality of semiconductor elements 20, the wires 21, the wiring layer 12, and the mask member 50 are sealed with a sealing resin layer 30.

  Next, as shown in FIG. 10C, the sealing resin layer 30 between each of the adjacent circuit boards 10 is divided, the mask member 50 is exposed from the sealing resin layer 30, and the adjacent circuit boards are exposed. A groove is formed in the substrate 10A between each of the ten, and the via connection portion is exposed from the substrate 10A. For example, the sealing resin layer 30 between the adjacent circuit boards 10 is divided, and the grooves 30t are formed to such an extent that cutting grooves are formed on the upper surface of the board 10A. The groove 30t is formed by so-called half-cut dicing. By forming the groove 30t, the side surface of the mask member 50 is exposed from the sealing resin layer 30, and the side surface of the via 14 is exposed from the substrate 10A. Inside the groove 30t, the side surfaces of the sealing resin layer 30, the mask member 50, and the via 14 are flush with each other. Thereafter, the sealing resin layer 30 is cured as necessary.

Next, as shown in FIG. 11A, the mask member 50 is removed. Thereby, the predetermined surface of the via connection portion where the mask member 50 is formed is exposed.
When the mask member 50 is removed, at least a part of the upper surface of the via 14 is exposed.

  Next, as shown in FIG. 11B, the conductive shield layer 40 is brought into contact with the predetermined surface of the exposed via connection portion while covering each sealing resin layer 30 with the conductive shield layer 40. For example, the conductive shield layer 40 is formed on the upper surface and the side surface of each sealing resin layer 30. The conductive shield layer 40 embedded in the groove 30t also enters the portion where the mask member 50 has been removed. That is, the protrusion 40p extends from the inner surface of the conductive shield layer 40, and the protrusion 40p enters the portion from which the mask member 50 has been removed. As a result, the conductive shield layer 40 comes into contact with the upper surface and the side surface of the via 14. Thereafter, the external connection terminal 17 is formed.

  Next, as shown in FIG. 11C, the conductive shield layer 40 formed in the groove 30t and the substrate 10A under the groove 30t are divided by dicing. That is, the continuous circuit board 10 is divided into pieces, and the semiconductor device 3 is formed.

  Also in the semiconductor device 3, the same effect as the semiconductor device 1 is obtained. However, since the conductive shield layer 40 is in contact with the side surface of the via 14, the contact area between the conductive shield layer 40 and the ground wiring (that is, the via 14) is further increased as compared with the semiconductor device 1. As a result, unnecessary electromagnetic waves from the semiconductor element 20 and the like are shielded more efficiently by the conductive shield layer 40. Further, in the manufacturing process of the semiconductor device 3, the mask member 51 may be used instead of the mask member 50. Thereby, the conductive shield layer 40 extends in a line shape in the resin sealing layer 30 and comes into contact with the via connection portion exposed on the end side of the circuit board 10.

(Fifth embodiment)
Next, a modification of the method for manufacturing a semiconductor device according to the embodiment will be described.
12 and 13 are schematic cross-sectional views for explaining the manufacturing process of the semiconductor device according to the fifth embodiment.

  First, as shown in FIG. 12A, a substrate 10 </ b> A in which a plurality of circuit boards 10 are continuously provided in a direction parallel to the main surface of the circuit board 10 is prepared. Subsequently, the semiconductor element 20 is mounted on each of the plurality of circuit boards 10. Then, at least one of the plurality of wiring layers 15 and the semiconductor element 20 are electrically connected via a wire 21. At this stage, the circuit board 10 is in a state before cutting, and a plurality of semiconductor elements 20 are mounted on the board 10A.

  Subsequently, a mask member 50 is formed on at least a part of the upper surface of any one of the plurality of wiring layers 12. The mask member 50 is provided on each of the plurality of circuit boards 10. For example, the mask member 50 is provided on each of the plurality of wiring layers 12. Thereby, at least a part of the upper surface of each wiring layer 12 is covered with the mask member 50.

  Next, as shown in FIG. 12B, the plurality of semiconductor elements 20, the wiring layer 12, the wires 21, and the like are sealed with a sealing resin layer 30. Thereby, the sealing resin layer 30 is formed on the upper surface side of the substrate 10A. Subsequently, the lower surface side of the substrate 10A is brought into contact with the base. The base includes a dicing sheet (dicing tape) 200. An adhesive layer may be provided on the surface of the dicing sheet 200 as necessary.

  Next, as illustrated in FIG. 12C, the sealing resin layer 30 and the substrate 10 </ b> A between the adjacent circuit boards 10 are divided, and further, a groove 200 t is formed on the upper surface of the dicing sheet 200. That is, each of the sealing resin layer 30 and the circuit board 10 is separated into pieces, and grooves 200t are formed in the dicing sheet 200 between the separated circuit boards 10.

  In addition, the distance between each circuit board 10 separated into pieces is 250 micrometers, for example. The thickness of the sealing resin layer 30 is, for example, 600 μm. The thickness of the circuit board 10 is, for example, 100 μm.

  The sealing resin layer 30 and the circuit board 10 are separated into pieces and the grooves 200t are formed by dicing using a dicing blade (not shown). Any one of the wiring layers 12 is exposed on the side surface 10w of the circuit board 10 due to the separation. In addition, the side surfaces of the sealing resin layer 30 and the wiring layer 12 are flush with each other. Thereafter, the sealing resin layer 30 is cured as necessary.

Next, as shown in FIG. 13A, the mask member 50 is removed.
Next, as shown in FIG. 13B, the upper surface of each sealing resin layer 30 is covered with the conductive shield layer 40, the side surfaces of each sealing resin layer 30, and each circuit board 10. At least a part of the side surface of the substrate is covered with the conductive shield layer 40. FIG. 13A illustrates a screen printing method using the squeegee plate 300. The screen printing method may be performed under atmospheric pressure or may be performed under reduced pressure.

  The conductive shield layer 40 embedded in the groove 30t also enters the portion (space) from which the mask member 50 has been removed. That is, the protrusion 40p extends from the inner surface of the conductive shield layer 40, and the protrusion 40p enters the portion from which the mask member 50 has been removed. As a result, the conductive shield layer 40 comes into contact with the upper surface and side surfaces of the wiring layer 12.

  Further, between each of the separated sealing resin layer 30 and the circuit board 10, the conductive shield layer 40 is penetrated from the sealing resin layer 30 toward the groove 200 t. At this time, since the groove 200t is provided in the dicing sheet 200, the groove 200t functions as an air escape path. Thereby, the conductive shield layer 40 smoothly enters between the individual circuit boards 10.

  That is, the air between each of the encapsulated sealing resin layer 30 and the circuit board 10 is pushed downward by the conductive shield layer 40 coming from above, and is surrounded by the groove 200t and the conductive shield layer 40. 200 s. The conductive shield layer 40 reliably contacts the wiring layer 12 exposed on the side surface 10 w of the circuit board 10. Thereby, the conductive shield layer 40 and the wiring layer 12 are electrically connected.

  If the groove 200t is not formed, the following problems are caused. For example, between the individual circuit boards 10, when the conductive shield layer 40 penetrates in the direction from the sealing resin layer 30 toward the circuit board 10, the individual circuit boards 10 are separated. There is no air escape route that exists between each of the. Therefore, the air between each of the circuit boards 10 separated into pieces cannot be sufficiently pushed downward by the conductive shield layer 40 coming from above, and the vicinity of the side surface of the sealing resin layer 30 or the circuit board 10 In the vicinity of the side surface 10w, a void may remain.

  In particular, when a void is formed between the conductive shield layer 40 and the wiring layer 12, the wiring layer 12 and the conductive shield layer 40 may not be in sufficient contact. That is, the conductive shield layer 40 and the wiring layer 12 may not be electrically connected. As a result, even if the conductive shield layer 40 is provided, there is a possibility that unnecessary electromagnetic waves cannot be sufficiently shielded.

  On the other hand, in the embodiment, since air is contained in the groove 200t below the wiring layer 12, no void is formed in the vicinity of the side surface of the sealing resin layer 30 or in the vicinity of the side surface 10w of the circuit board 10. Thereby, the wiring layer 12 and the conductive shield layer 40 are reliably in contact with each other.

  Thus, in the embodiment, when covering at least part of the side surface of the sealing resin layer 30 and the side surface of the circuit board 10 with the conductive shield layer 40, the sealing resin layer 30 is formed between the adjacent sealing resin layers 30. The conductive shield layer 40 is penetrated from above to below the gap 30s. Further, the conductive shield layer 40 is made to enter the groove 200t until the conductive shield layer 40 contacts the wiring layer 12.

  Next, after removing the dicing sheet 200 and forming the external connection terminals 17 on the lower surface side of the circuit board 10, as shown in FIG. 13C, the conductive shield layer 40 is divided by dicing. That is, the continuous conductive shield layer 40 is separated into pieces, and the semiconductor device 1 is formed.

  According to such a manufacturing method, the conductive shield layer 40 reliably contacts the wiring layer 12 on the side surface 10 w of the circuit board 10. Thereby, in the semiconductor device 1, leakage of unnecessary electromagnetic waves is efficiently suppressed. Therefore, the reliability of the semiconductor device 1 is further improved.

  In the fifth embodiment, the circuit board 10 exemplified in the first embodiment has been described as an example. However, the circuit board 10 exemplified in the fourth embodiment may be used.

(Sixth embodiment)
14 and 15 are schematic cross-sectional views for explaining the manufacturing process of the semiconductor device according to the sixth embodiment.

First, the state shown in FIG. 14A is the same as the state shown in FIG.
Next, as shown in FIG. 14B, the plurality of semiconductor elements 20, the wiring layer 12, the wires 21, and the like are sealed with a sealing resin layer 30. Thereby, the sealing resin layer 30 is formed on the upper surface side of the substrate 10A. Subsequently, the lower surface side of the substrate 10A is brought into contact with the base. The base includes a dicing sheet 200 and a sheet member 201 provided on the dicing sheet 200. The sheet member 201 is, for example, a resin plate member. An adhesive layer may be provided on the main surface of the sheet member 201 as necessary.

  Next, as illustrated in FIG. 14C, the sealing resin layer 30 and the substrate 10 </ b> A between the adjacent circuit boards 10 are divided, and further, a groove 201 t is formed on the upper surface of the sheet member 201. That is, the sealing resin layer 30 and the circuit board 10 are separated into individual pieces, and the grooves 201t are formed in the sheet member 201 between the separated circuit boards 10.

  The sealing resin layer 30 and the circuit board 10 are separated into pieces and the grooves 201t are formed by dicing. Any one of the wiring layers 12 is exposed on the side surface 10w of the circuit board 10 due to the separation. In addition, the side surfaces of the sealing resin layer 30 and the wiring layer 12 are flush with each other. Thereafter, the sealing resin layer 30 is cured as necessary.

Next, as shown in FIG. 15A, the mask member 50 is removed.
Next, as shown in FIG. 15B, the upper surface of each sealing resin layer 30 is covered with the conductive shield layer 40, the side surfaces of each sealing resin layer 30, and each circuit board 10. At least a part of the side surface of the substrate is covered with the conductive shield layer 40. FIG. 15A illustrates a screen printing method using the squeegee plate 300. The screen printing method may be performed under atmospheric pressure or may be performed under reduced pressure.

  The conductive shield layer 40 embedded in the groove 30t also enters the portion (space) from which the mask member 50 has been removed. That is, the protrusion 40p extends from the inner surface of the conductive shield layer 40, and the protrusion 40p enters the portion from which the mask member 50 has been removed. As a result, the conductive shield layer 40 comes into contact with the upper surface and side surfaces of the wiring layer 12.

  Further, between each of the separated sealing resin layer 30 and the circuit board 10, the conductive shield layer 40 is penetrated from the sealing resin layer 30 toward the groove 201 t. At this time, the sheet member 201 is provided with a groove 201t. The groove 201t functions as an air escape path. Thereby, the conductive shield layer 40 smoothly enters between the individual circuit boards 10.

  That is, the air between each of the encapsulated sealing resin layer 30 and the circuit board 10 is pushed downward by the conductive shield layer 40 coming from above, and is surrounded by the groove 201t and the conductive shield layer 40. In the space 201s. The conductive shield layer 40 reliably contacts the wiring layer 12 exposed on the side surface 10 w of the circuit board 10. Thereby, the conductive shield layer 40 and the wiring layer 12 are electrically connected.

  Next, after removing the dicing sheet 200 and the sheet member 201 and forming the external connection terminals 17 on the lower surface side of the circuit board 10, as shown in FIG. 15C, the conductive shield layer 40 is divided by dicing. That is, the continuous conductive shield layer 40 is separated into pieces, and the semiconductor device 1 is formed.

  According to such a manufacturing method, the conductive shield layer 40 reliably contacts the wiring layer 12 on the side surface 10 w of the circuit board 10. Thereby, in the semiconductor device 1, leakage of unnecessary electromagnetic waves is efficiently suppressed. Therefore, the reliability of the semiconductor device 1 is further improved.

  In the sixth embodiment, the circuit board 10 exemplified in the first embodiment has been described as an example. However, the circuit board 10 exemplified in the fourth embodiment may be used.

(Seventh embodiment)
16A and 16B are schematic views for explaining the base of the semiconductor device used in the manufacturing process of the semiconductor device according to the seventh embodiment. FIG. 16A is a schematic diagram of the surface of the base, and FIG. ) Is a schematic cross-sectional view at the position XX ′, and FIG. 8C is a schematic cross-sectional view at the position YY ′ in FIG.

  In FIG. 16A, the positions of the individual sealing resin layers 30 (or the circuit board 10) are also displayed.

  In the seventh embodiment, a base including a dicing sheet 200 and a sheet member 202 is used in the process of separating the sealing resin layer 30 and the circuit board 10 into individual pieces by dicing. The sheet member 202 is provided on the dicing sheet 200.

  The sheet member 202 is, for example, a resin plate. An adhesive layer may be provided on the upper and lower surfaces of the sheet member 202 as necessary.

  Further, the sheet member 202 includes a sheet base material 202b and a layer 202a provided on the sheet base material 202b. The layer 202a is provided with a plurality of grooves serving as air escape routes. For example, the sheet includes a groove 202x that extends substantially parallel to the direction in which the gap 30s formed between the adjacent sealing resin layers 30 extends, and 202y that extends substantially perpendicular to the direction in which the gap 30s extends. The member 202 is provided.

FIG. 17 is a schematic cross-sectional view for explaining the manufacturing process for the semiconductor device according to the seventh embodiment.
If such a base including the sheet member 202 is used in the dicing process, the conductive shield layer 40 may be penetrated from the top to the bottom between each of the separated sealing resin layer 30 and the circuit board 10. The air existing between each of the separated sealing resin layer 30 and the circuit board 10 is efficiently exhausted through the grooves 202x and 202y in the layer 202a (see arrows in FIG. 17B). Thereby, the conductive shield layer 40 smoothly enters between each of the circuit boards 10 separated into pieces.

  That is, the air between each of the encapsulated sealing resin layer 30 and the circuit board 10 is pushed downward by the conductive shield layer 40 coming from above, and further exhausted into the grooves 202x and 202y of the layer 202a. . The conductive shield layer 40 reliably contacts the wiring layer 12 exposed on the side surface 10 w of the circuit board 10. Thereby, the conductive shield layer 40 and the wiring layer 12 are electrically connected. Such a manufacturing process is also included in the embodiment.

  Further, the sheet member provided on the dicing sheet 200 is not limited to the above-described form, and dot-shaped convex portions may be provided periodically.

  18A and 18B are schematic views for explaining another base of the semiconductor device used in the manufacturing process of the semiconductor device according to the seventh embodiment. FIG. 18A is a schematic diagram of the surface of the base, and FIG. It is a cross-sectional schematic diagram of the XX 'position of (a), (c) is a schematic cross-sectional diagram of the YY' position of (a).

  In FIG. 18A, the positions of the individual sealing resin layers 30 (or circuit boards 10) are also displayed.

  In the embodiment, a base including the dicing sheet 200 and the sheet member 203 can be used in the process of separating the sealing resin layer 30 and the circuit board 10 into individual pieces by dicing. The sheet member 203 is provided on the dicing sheet 200.

  The sheet member 203 is, for example, a resin plate. An adhesive layer may be provided on the upper and lower surfaces of the sheet member 203 as necessary.

  The sheet member 203 includes a sheet base material 203b and a layer 202a provided on the sheet base material 203b. On the layer 203a, convex portions 203d are periodically provided in a dot shape.

  If such a sheet member 203 is used, even if the conductive shield layer 40 penetrates from the top to the bottom between each of the encapsulated sealing resin layer 30 and the circuit board 10, it is separated into pieces. The air existing between the sealing resin layer 30 and the circuit board 10 can be efficiently exhausted through the gap between the convex portions 203d. Such a base is also included in the embodiment.

  Note that the layers 202a and 203a may be made of a porous body without providing the grooves 202x and 202y and the protrusions 203d.

(Eighth embodiment)
19A and 19B are schematic views for explaining the base of the semiconductor device used in the manufacturing process of the semiconductor device according to the eighth embodiment. FIG. 19A is a schematic diagram of the bottom surface of the base, and FIG. ) Is a schematic cross-sectional view at the position XX ′, and FIG. 8C is a schematic cross-sectional view at the position YY ′ in FIG.

  In FIG. 19A, the positions of the individual sealing resin layers 30 (or circuit boards 10) are also displayed.

  In the eighth embodiment, a base including a dicing sheet 200 and a sheet member 204 is used in the process of separating the sealing resin layer 30 and the circuit board 10 into individual pieces by dicing. The sheet member 204 is provided on the dicing sheet 200.

  The sheet member 204 is, for example, a resin plate. An adhesive layer may be provided on the upper surface and the lower surface main surface of the sheet member 204 as necessary.

  Further, the sheet member 204 includes a sheet base material 204a and a layer 204b provided under the sheet base material 204a. The layer 204b is provided with a plurality of grooves serving as air escape routes. For example, a sheet 204 includes a groove 204x extending substantially parallel to a direction in which a gap 30s formed between adjacent sealing resin layers 30 extends, and 204y extending substantially perpendicular to a direction in which the gap 30s extends. The member 204 is provided.

  FIG. 20 is a schematic cross-sectional view for explaining the manufacturing process for the semiconductor device according to the eighth embodiment.

  When such a base including the sheet member 204 is used in the dicing process, as shown in FIG. 20A, a groove 204t is formed on the sheet base material 204a with a dicing blade (not shown). The surface of the layer 204b is exposed by forming the groove 204t. When the surface of the layer 204b is exposed, the groove 204t formed by the dicing blade communicates with the grooves 204x and 204y in the layer 204b.

  That is, a passage is formed from the gap 30s to the groove 204t and further to the grooves 204x and 204y in the layer 204b. As a result, even if the conductive shield layer 40 is inserted from the top to the bottom between each of the separated sealing resin layer 30 and the circuit board 10, the separated sealing resin layer 30 and the circuit are separated. Air existing between each of the substrates 10 is efficiently exhausted through the grooves 204x and 204y in the layer 204b (see arrows in FIG. 20B). Thereby, the conductive shield layer 40 smoothly enters between each of the circuit boards 10 separated into pieces.

  That is, the air between each of the encapsulated sealing resin layer 30 and the circuit board 10 is pushed downward by the conductive shield layer 40 coming from above and further exhausted into the grooves 204x and 204y of the layer 204b. . The conductive shield layer 40 reliably contacts the wiring layer 12 exposed on the side surface 10 w of the circuit board 10. Thereby, the conductive shield layer 40 and the wiring layer 12 are electrically connected.

  Moreover, the sheet member provided on the dicing sheet 200 is not limited to the above-described form, and dot-shaped convex portions may be provided periodically.

  FIG. 21 is a schematic diagram for explaining another base of the semiconductor device used in the manufacturing process of the semiconductor device according to the eighth embodiment. FIG. 21A is a schematic diagram of the bottom surface of the base, and FIG. It is a cross-sectional schematic diagram of the XX 'position of (a), (c) is a schematic cross-sectional diagram of the YY' position of (a).

  In FIG. 21A, the position of the separated sealing resin layer 30 (or circuit board 10) is also displayed.

  In the eighth embodiment, a ground including the dicing sheet 200 and the sheet member 205 can be used in the process of separating the sealing resin layer 30 and the circuit board 10 into individual pieces by dicing. The sheet member 205 is provided on the dicing sheet 200.

  The sheet member 205 is, for example, a resin plate. An adhesive layer may be provided on the upper and lower surfaces of the sheet member 205 as necessary.

  Further, the sheet member 205 includes a sheet base material 205a and a layer 205b provided under the sheet base material 205a. On the layer 205b, convex portions 205d are periodically provided in a dot shape.

  Even when such a sheet member 205 is used, if the groove 204t described above is formed and the surface of the layer 205b is exposed, the groove 204t communicates with the gap between the convex portions 205d in the layer 205b. Therefore, even if the conductive shield layer 40 is inserted from the top to the bottom between the singulated sealing resin layer 30 and the circuit board 10, the singulated sealing resin layer 30 and the circuit board are separated. The air existing between each of 10 can be efficiently exhausted through the gap between the convex portions 203d. Such a substrate is also included in the embodiment.

  If such a sheet member 205 is used, even if the conductive shield layer 40 penetrates from the top to the bottom between each of the encapsulated sealing resin layer 30 and the circuit board 10, the sheet member 205 is separated. Air existing between the sealing resin layer 30 and the circuit board 10 is efficiently exhausted to the layer 205b (see FIG. 21B). Thereby, the conductive shield layer 40 smoothly enters between each of the circuit boards 10 separated into pieces.

  That is, the air between each of the encapsulated sealing resin layer 30 and the circuit board 10 is pushed downward by the conductive shield layer 40 coming from above and further exhausted to the layer 205b. The conductive shield layer 40 reliably contacts the wiring layer 12 exposed on the side surface 10 w of the circuit board 10. Thereby, the conductive shield layer 40 and the wiring layer 12 are electrically connected. Such a manufacturing process is also included in the embodiment.

  Note that the layers 204b and 205b may be made of a porous body without providing the grooves 204x and 204y and the protrusions 205d.

  The embodiment has been described above with reference to specific examples. However, the embodiments are not limited to these specific examples. In other words, those specific examples that have been appropriately modified by those skilled in the art are also included in the scope of the embodiments as long as they include the features of the embodiments. Each element included in each of the specific examples described above and their arrangement, material, condition, shape, size, and the like are not limited to those illustrated, and can be appropriately changed.

  In addition, each element included in each of the above-described embodiments can be combined as long as technically possible, and combinations thereof are also included in the scope of the embodiment as long as they include the features of the embodiment. In addition, in the category of the idea of the embodiment, those skilled in the art can conceive various changes and modifications, and it is understood that these changes and modifications also belong to the scope of the embodiment. .

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

1, 2, 3 Semiconductor device 10 Circuit board 10A Substrate 10w Side surface 11 Insulating base material 12 Wiring layer (first wiring layer)
13 Wiring layer (second wiring layer)
14 Via (via connection part)
DESCRIPTION OF SYMBOLS 15 Wiring layer 16 Solder resist layer 17 External connection terminal 20 Semiconductor element 21 Wire 22 Die bonding material 30 Sealing resin layer 30s Gap 30t Groove 40 Conductive shield layer 40p Projection part 50, 51 Mask member 100 Broken line 200 Dicing sheet 200s Space 200t Groove 201, 202, 203, 204, 205 Sheet member 201s Space 201t, 204t, 202x, 202y, 204x, 204y Groove 202a, 203a, 204b, 205b Layer 202b, 203b, 204a, 205a Sheet base material 203d, 205d Protrusion 300 Squeegee board

Claims (10)

An insulating base, a plurality of first wiring layers provided on the first main surface side of the insulating base, and a plurality of second wiring layers provided on the second main surface side of the insulating base; A circuit board having a plurality of vias penetrating from the first main surface of the insulating base material to the lower surface;
In the circuit board, a semiconductor element mounted on the first main surface side of the insulating base material,
A sealing resin layer for sealing the semiconductor element;
A conductive shield layer covering the sealing resin layer;
With
Any of the plurality of first wiring layers is exposed on an end side of the circuit board,
The conductive shield layer is electrically connected to the first wiring layer exposed on the end side of the circuit board so as to extend into the sealing resin layer toward the semiconductor element side. A semiconductor device characterized by that.   2. The conductive shield layer extends in a line shape in the resin sealing layer, and is in contact with the first wiring layer exposed on the end side of the circuit board. The semiconductor device described.   3. The semiconductor device according to claim 1, wherein the first wiring layer exposed on the end side of the circuit board is configured to have a ground potential. 4. An insulating base, a plurality of first wiring layers provided on the first main surface side of the insulating base, and a plurality of second wiring layers provided on the second main surface side of the insulating base; A circuit board having a plurality of via connection portions penetrating from the first main surface to the second main surface of the insulating base,
In the circuit board, a semiconductor element mounted on the first main surface side of the insulating base material,
A sealing resin layer for sealing the semiconductor element;
A conductive shield layer covering the sealing resin layer;
With
Any of the plurality of via connection portions is exposed on the end side of the circuit board,
The conductive shield layer is electrically connected to the via connection portion exposed on the end side of the circuit board so as to extend in the sealing resin layer toward the semiconductor element side. A semiconductor device characterized by comprising:   5. The conductive shield layer extends in a line shape in the resin sealing layer and contacts the via connection portion exposed on the end side of the circuit board. Semiconductor device.   The semiconductor device according to claim 4, wherein the via connection portion exposed on the end portion side of the circuit board is configured to have a ground potential. An insulating base, a plurality of first wiring layers provided on the first main surface side of the insulating base, and a plurality of second wiring layers provided on the second main surface side of the insulating base; A circuit board having a plurality of via connection portions penetrating from the first main surface to the second main surface of the insulating base material in a direction substantially parallel to the main surface of the circuit board. Preparing a plurality of continuously provided substrates;
In each of the plurality of circuit boards, a step of mounting a semiconductor element on the first main surface side;
Forming a mask member on a predetermined surface of any of the plurality of first wiring layers in each of the plurality of circuit boards;
Sealing the semiconductor element and the plurality of first wiring layers with a sealing resin layer;
The sealing resin layer between each of the adjacent circuit boards is divided, the mask member is exposed from the sealing resin layer, and a groove is formed in the board between each of the adjacent circuit boards. Forming and exposing the first wiring layer from the substrate;
Removing the mask member and exposing the predetermined surface of the first wiring layer on which the mask member is formed;
Covering the respective sealing resin layers with a conductive shield layer, and contacting the conductive shield layer to the predetermined surface of the exposed first wiring layer;
A method for manufacturing a semiconductor device, comprising: An insulating base, a plurality of first wiring layers provided on the first main surface side of the insulating base, and a plurality of second wiring layers provided on the second main surface side of the insulating base; A circuit board having a plurality of via connection portions penetrating from the first main surface to the second main surface of the insulating base material in a direction substantially parallel to the main surface of the circuit board. Preparing a plurality of continuously provided substrates;
In each of the plurality of circuit boards, a step of mounting a semiconductor element on the first main surface side;
Forming a mask member on a predetermined surface of any of the plurality of via connection portions in each of the plurality of circuit boards;
Sealing the semiconductor element and the plurality of first wiring layers with a sealing resin layer;
The sealing resin layer between each of the adjacent circuit boards is divided, the mask member is exposed from the sealing resin layer, and a groove is formed in the board between each of the adjacent circuit boards. And exposing the via connection from the substrate;
Removing the mask member and exposing the predetermined surface of the via connection portion where the mask member is formed;
Covering each sealing resin layer with a conductive shield layer, and contacting the conductive shield layer to the predetermined surface of the exposed via connection portion;
A method for manufacturing a semiconductor device, comprising:   9. The semiconductor device according to claim 7, wherein the mask member includes any one of a biodegradable resin, a water-soluble resin, a hydrolyzable resin, an enzyme-decomposable resin, and an organic acid-soluble resin. Production method.   The method for manufacturing a semiconductor device according to claim 7, wherein the mask member is removed by alkali decomposition and enzymatic decomposition, or by alkaline aqueous solution decomposition and hydrolysis.

Images