JP5774764B2 - Memory control device, semiconductor device, system board, and information processing device - Google Patents

Description

  Embodiments described herein relate generally to a memory control device, a semiconductor device, a system board, and an information processing device.

  It is desired that portable information processing devices such as tablet terminals and smartphones operate using limited power effectively. Therefore, reducing the power consumption of the information processing apparatus is an important issue.

  When the processor is in a standby state (waiting for an interrupt) while waiting for input from the device, the information processing device stops power consumption by stopping the high-frequency oscillator that is the clock source for processing the task. Can be reduced. Further, the information processing apparatus can further reduce power consumption by stopping the supply of power to the memory from which data is read and written by the processor in the standby state.

JP 2004-326153 A

  However, when the processor is interrupted and the information processing device returns from the standby state, the processor can read / write data from / to the memory by first moving the high-frequency oscillator and initializing the memory after the clock has stabilized. There is a problem that it takes time to become.

  A problem to be solved by the present invention is to provide a memory control device, a semiconductor device, a system board, and an information processing device capable of reducing power consumption and shortening the time required for a processor to read and write data from and to a memory. Is to provide.

The memory control device of the embodiment controls a memory from which data can be read or written by a processor. The memory controller, an interrupt to the processor occurs, the pre-Symbol memory to said memory for supplying a first clock supplying a signal for initializing, and supplies the second clock wherein for the memory, at least one of the signals to test feed for the signal or write for the reading of data by the processor. The second clock is a clock generated by an oscillation circuit that starts operation when an interrupt to the processor occurs, and has a higher frequency than the first clock.

1 is an external view of an information processing apparatus including a memory controller according to an embodiment. The block diagram which shows the hardware structural example of information processing apparatus. The block diagram which shows the structural example of the principal part of information processing apparatus. The timing chart explaining the operation | movement of the conventional standby cancellation | release. 6 is a timing chart illustrating conventional memory initialization processing. 6 is a timing chart for explaining an operation for canceling standby in the embodiment. FIG. 3 is an exemplary block diagram illustrating a configuration example of the memory controller according to the embodiment. 6 is a timing chart illustrating memory initialization processing according to the embodiment. 6 is a timing chart for explaining another example of the memory initialization process according to the embodiment. 6 is a timing chart for explaining the operation of the memory controller according to the embodiment. 6 is a timing chart for explaining the operation of the memory controller according to the embodiment. 6 is a timing chart for explaining the operation of the memory controller according to the embodiment.

  FIG. 1 is a diagram illustrating an appearance of an information processing apparatus 1 including a memory controller according to the present embodiment. The information processing apparatus 1 is configured as a tablet information terminal.

  The information processing apparatus 1 includes a display unit 2a on the terminal surface. For the display unit 2a, for example, a low power consumption reflective liquid crystal display or electronic paper is used. Moreover, the information processing apparatus 1 includes a solar cell 3 in a portion other than the display unit 2a on the terminal surface. In addition, the information processing apparatus 1 includes a touch panel 2b that functions as a pointing device on the surface of the display unit 2a. Furthermore, the information processing apparatus 1 includes a keyboard 4 at a position that does not overlap the display unit 2a on the terminal surface. The keyboard 4 may be realized by overlapping a transparent touch panel 2b on the surface of the solar cell 3. Further, it may be realized as a mechanical keyboard 4 using a transparent material or a material with few light-shielding portions.

  FIG. 2 is a block diagram illustrating a hardware configuration example of the information processing apparatus 1. The information processing apparatus 1 includes a SoC (System on a Chip) 10, a main memory 5, a secondary storage 6, a solar battery 3, a power storage unit 7, a PMIC (Power Management Integrated Circuit) as main hardware configurations. 8, each module includes a display unit 2 a, a touch panel 2 b, a keyboard 4, and a communication interface (communication I / F) 9.

  The information processing apparatus 1 operates with electric power generated by the solar cell 3. However, the peak power consumption of the entire information processing apparatus 1 at the time of operation (when some kind of processing is being performed) cannot be provided by only the power generated by the solar battery 3. For this reason, the power storage unit 7 is charged with surplus power generated by the solar cell 3 during idling (time for waiting for a response from the user, time when the information processing apparatus 1 is not used, etc.). In operation, the PMIC 8 adjusts the electric power accumulated in the power storage unit 7 and the electric power generated by the solar cell 3 to a necessary voltage in the PMIC 8 and supplies the voltage to each module of the information processing apparatus 1. Such power control is called peak assist or peak shift.

  The power storage unit 7 can be realized by a battery such as a lithium ion battery or an electric double layer capacitor alone or in combination. For example, a combination is possible in which the electric power generated by the solar cell 3 is first stored in an electric double layer capacitor, and the stored electric power is further charged in a lithium ion battery.

  The PMIC 8 is a module that supplies power to each module such as the SoC 10 and the main memory 5. The PMIC 8 converts the power supplied from the solar cell 3 and the power storage unit 7 into a voltage required by each module such as the SoC 10 and the main memory 5 and supplies the voltage to each module. The PMIC 8 also has a function of turning on / off the power supply to each module.

  The SoC 10 is a system LSI (semiconductor device) in which a processor (CPU: Central Processing Unit) 11 serving as a core for controlling the entire information processing device 1 and the memory controller (memory control device) 100 according to the present embodiment are mounted on a semiconductor substrate. ). Details of specific configuration examples of the SoC 10 and the memory control device 100 will be described later.

  The main memory 5 is a memory in which data is read and written by the CPU 11 of the SoC 10, and is a main storage unit used as a work area when the CPU 11 executes various processes. The main memory 5 includes, for example, DDR SDRAM (Double Date Rate Synchronous Dynamic Random Access Memory), DDR2 SDRAM (Double Date Rate 2 Synchronous Dynamic Random Access Memory), DDR3 SDRAM (Double Date Rate 3 Synchronous Dynamic Random Access Memory), LPDDR. A DRAM having a synchronous interface such as an SDRAM (Low Power Double Date Rate Synchronous Dynamic Random Access Memory) or an LPDDR2 SDRAM (Low Power Double Date Rate 2 Synchronous Dynamic Random Access Memory) can be used.

  The secondary storage 6 is an auxiliary storage unit using a nonvolatile memory that stores data and programs required by the information processing apparatus 1. As the secondary storage 6, for example, a flash memory can be used. An SD card or SSD can be used as the secondary storage 6.

  The information processing apparatus 1 includes a display unit 2a, a touch panel 2b, a keyboard 4, and a communication I / F 9 as input / output devices. The communication I / F 9 is an interface for performing communication using, for example, a wireless LAN (Local Area Network). The communication method is not limited to the wireless LAN, and any method such as a wired LAN, Bluetooth (registered trademark), ZigBee (registered trademark), infrared communication, visible light communication, optical line network, telephone line network, and the Internet can be used.

  FIG. 3 is a block diagram illustrating a configuration example of a main part of the information processing apparatus 1, in which the SoC 10, the main memory 5, and the PMIC 8 are extracted and illustrated. Each of these modules is mounted on a motherboard (system board) of the information processing apparatus 1, for example.

  As described above, the SoC 10 includes the CPU 11 and the memory controller 100. The CPU 11 and the memory controller 100 are connected by a bus 12 formed on a chip. The SoC 10 is connected to the external main memory 5 by the memory controller 100. Power for operating the SoC 10 and the main memory 5 is supplied from the PMIC 8. Although not shown in FIG. 3, a controller for input / output devices such as the display unit 2 a, the touch panel 2 b, the keyboard 4, and the communication I / F 9 may be provided inside the SoC 10.

  The SoC 10 includes a low frequency oscillator 13 and a high frequency oscillator 14 in order to generate a clock for operating a system mounted on the chip. The low-frequency oscillator 13 oscillates, for example, by connecting a crystal oscillator of 32 KHz. The high-frequency oscillator 14 oscillates, for example, by connecting a crystal oscillator of 24 MHz.

  The output of the low-frequency oscillator 13 is supplied as a subclock to the CPU 11 and the memory controller 100, and is used for starting up a system mounted on the chip and for operating in a standby state. On the other hand, the output of the high-frequency oscillator 14 is further increased in frequency by a PLL (Phase Locked Loop) 15 and supplied to the CPU 11 and the memory controller 100, and used as a main clock when the CPU 11 executes various processes.

  Furthermore, the SoC 10 includes a power state management unit 16 that performs control so that the SoC 10 enters a standby state with low power consumption during idling. When there is no task to be executed immediately and the CPU 11 waits for an interrupt from the input / output device, the CPU 11 issues a WFI (Wait for Interrupt) instruction and waits for an interrupt. At this time, in order to reduce power consumption while waiting for an interrupt, the power state management unit 16 puts the SoC 10 into a standby state. Many SoCs provide a plurality of types of standby states in which the power consumption in the standby state and the cost required for transition to and recovery from the standby state are different. Among them, in the standby state with low power consumption, the power state management unit 16 performs power gating of each module in the SoC 10 or stops the high-frequency oscillator 14 to stop the main clock supply. At this time, the power state management unit 16 may stop not only the high-frequency oscillator 14 but also the PLL 15 at the same time. At this time, the power state management unit 16 instructs the PMIC 8 to stop the supply of power to the main memory 5 or operates the main memory 5 with the first power consumption more than the first power consumption. By instructing the memory controller 100 to switch to a standby state (deep power down or self-refresh) with a small second power consumption, the power consumption can be significantly reduced.

  When detecting the occurrence of an interrupt from the input / output device, the power state management unit 16 cancels the power gating of each module in the SoC 10 and cancels the high frequency oscillator 14 or the PLL 15 if they are stopped. Restart the operation. Further, at this time, the power state management unit 16 instructs the PMIC 8 to resume the supply of power to the main memory 5 or operates with the first power consumption from the state where the main memory 5 is on standby with the second power consumption. The memory controller 100 is instructed to switch to the state to be performed.

  The power state management unit 16 outputs a standby signal indicating whether the SoC 10 is in a standby state or not, and instructs the PMIC 8 to stop or restart the supply of power to the main memory 5 using the standby signal. Alternatively, the memory controller 100 may be instructed to switch between a state in which the main memory 5 operates with the first power consumption and a state in which the main memory 5 stands by with the second power consumption. In this case, the PMIC 8 stops supplying power to the main memory 5 when the standby signal is turned on, and resumes supplying power to the main memory when the standby signal is turned off. Further, in this case, the memory controller 100 sends a signal (command) to the main memory 5 when the standby signal is turned from off to on, and waits at the second power consumption, and when the standby signal is turned off from the main memory 5 A signal (command) is sent to 5 so as to operate with the first power consumption. As another implementation method, the power state management unit 16 may instruct the PMIC 8 or the memory controller 100 using a dedicated signal line without using the standby signal.

  The power state management unit 16 may be called a power reset manager, a general power controller, or a low-leakage wake-up unit. The CPU 11 may incorporate some or all of the functions of the power state management unit 16.

  When the volatile memory such as the DRAM described above is used as the main memory 5, the data disappears when the supply of power to the main memory 5 is stopped. There is no problem even if it disappears if it enters. Also, if there is data that should not be erased, store the data in another volatile memory so that the memory does not stop supplying power even in the standby state, or the data is stored in another non-volatile memory. You may make it memorize. Further, a non-volatile memory such as PCM or MRAM may be used as the main memory 5 so that the data is not lost even when the supply of power to the main memory 5 is stopped.

  When a DRAM is used as the main memory 5 and the main memory 5 is set to a standby state with the second power consumption in the standby state, the main memory 5 is set in a standby state with the second power consumption. A refresh mode or a deep power down mode can be used.

  Note that the sub-clock generated by the low-frequency oscillator 13 cannot be stopped because it is necessary for timer counting during the standby state, monitoring of interrupts, state transition from the standby state to the operating state, and the like. Since the power consumption of the low frequency oscillator 13 is smaller than the power consumption of the high frequency oscillator 14, there is no problem.

  In the SoC 10 of this embodiment, upon receiving an interrupt from the input / output device, the power state management unit 16 cancels the standby state, starts the operation of the high-frequency oscillator 14 (and the PLL 15), and instructs the PMIC 8 to perform main processing. When the supply of power to the memory 5 is started, or when the memory controller 100 is instructed to return the main memory 5 from the standby state with the second power consumption to the state operating with the first power consumption, the memory controller 100 However, by starting the initialization process of the main memory 5 without waiting for the main clock to stabilize, the time until the CPU 11 can process an interrupt is shortened.

  Here, as a comparative example with respect to the present embodiment, a conventional general standby release operation will be described with reference to FIG. FIG. 4 is a timing chart when a conventional general SoC receives an interrupt and transitions from a standby state to an operating state. The conventional general SoC configuration is the same as that of the SoC 10 of the present embodiment shown in FIG. 3, but the subclock generated by the low frequency oscillator 13 is not supplied to the memory controller 100, and the memory controller 100 The difference from the present embodiment is that the operation based on the sub-clock is not performed. In the following, for convenience, the constituent elements of the comparative example corresponding to the present embodiment will be described with reference numerals added with a subscript n to the reference numerals of the constituent elements of the present embodiment.

  When an interrupt from one of the input / output devices to the CPU 11n is input at time T1, the standby state is canceled by the power state management unit 16 that detects the interrupt. In the conventional general SoC 10n, a standby signal indicating a standby state is defined, and when the standby state is canceled, the standby signal becomes a low level. Accordingly, the power state management unit 16 of the SoC 10n first starts the operation of the high-frequency oscillator 14n (and PLL 15n if necessary) and waits for the oscillation of the high-frequency oscillator 14n to stabilize. The output of the high-frequency oscillator 14n enters the PLL 15n, where the frequency is increased and used as the main clock. When the supply of power to the main memory 5n is stopped in the standby state, the power state management unit 16 of the SoC 10n instructs the PMIC 8n at the timing when the standby state is canceled at time T1. Then, the supply of power to the main memory 5n is started.

  When the main clock is stabilized at time T2, the CPU 11n is ready for interrupt processing. However, since the initialization of the main memory 5n is not completed at this stage, the CPU 11n instructs the memory controller 100n to initialize the main memory 5n. At this time, when the main memory 5n is in a standby state with the second power consumption in the standby state, the memory controller 100n receiving the instruction from the CPU 11n first sets the main memory 5n with the first power consumption. Make it work. At time T3, the memory controller 100n that has received an instruction from the CPU 11n starts the initialization process of the main memory 5n. When the initialization of the main memory 5n is completed at time T4, the main memory 5n is in a state where data can be read and written. It becomes. Thereafter, the CPU 11n executes an interrupt process using the main memory 5n. As the memory controller 100n, there is a memory controller that starts the initialization process of the main memory 5n in response to an instruction from the CPU 11n as described above. There is also a memory controller that starts the initialization process of the main memory 5n according to an instruction from the unit 16.

  Here, the initialization process of the main memory 5n is the first after the standby state is released and the supply of power to the main memory 5n is started, or from the state where the main memory 5n waits at the second power consumption. This is a process for initializing the main memory 5n to a state in which data can be read and written by the CPU 11n after returning to the state of operating with the power consumption. Specifically, the initialization process of the main memory 5n is related to the burst length and signal delay in the control register in the main memory 5n after a predetermined time has elapsed since the start of power supply to the main memory 5n. A control register in the main memory 5n after a predetermined time has elapsed since the process of setting parameters or the like, or after the main memory 5n returns from the standby state at the second power consumption to the state at which the main memory 5n operates at the first power consumption. Is a process for setting parameters such as burst length and signal delay.

  Here, assuming that a DDR3 SDRAM is used as the main memory 5n and the power supply to the main memory 5n is stopped in the standby state, refer to FIG. 5 for the initialization processing of the conventional general main memory 5n. While explaining. FIG. 5 is a timing chart for explaining the initialization process of the main memory 5n by the conventional general memory controller 100n.

  When the main memory 5n is a memory having a synchronous interface such as DDR3 SDRAM, the memory controller 100n synchronizes with the memory clock while supplying the memory clock to the main memory 5n as shown in FIG. Then, a command (first control signal) for initializing the main memory 5n is supplied. At this time, the conventional general memory controller 100n supplies the main memory 5n as a memory clock with the main clock described above as it is or with the main clock frequency-converted internally by a PLL or flip-flop. For this reason, the memory clock cannot be supplied to the main memory 5n until the main clock is stabilized, and the initialization process of the main memory 5n cannot be performed.

  That is, the conventional general memory controller 100n waits for the main clock to stabilize after the standby state is released and the supply of power to the main memory 5n is started. When the main clock becomes stable at time T11, the memory controller 100n starts supplying the memory clock to the main memory 5n, and then, after the CKE (Clock Enable) signal becomes high level at time T12, the memory controller 100n is predetermined. During a predetermined time, a NOP (No Operation) command is continuously supplied to the main memory 5n in synchronization with the memory clock. The CKE signal is a signal indicating whether or not the memory clock is valid. If the CKE signal is high, it indicates that the memory clock is valid. If the CKE signal is low, the memory clock is invalid. Indicates that there is.

  Thereafter, when a predetermined time elapses at time T13, the memory controller 100n sends an MRS (Mode Register Set) command for setting parameters relating to the burst length and signal delay to the control register in the main memory 5n, the memory clock Synchronously with the main memory 5n. When initialization of the main memory 5n is completed at time T14, the memory controller 100n thereafter supplies a command (second control signal) according to data read / write by the CPU 11n to the main memory 5n in synchronization with the memory clock. To do. FIG. 5 shows an example in which a READ command for requesting data reading is supplied to the main memory 5n.

  As described above, the conventional general memory controller 100n starts the supply of power to the main memory 5n after the standby state is released, and starts the initialization process of the main memory 5n after the main clock is stabilized. It was like that. Therefore, it takes time until the CPU 11n can read / write data from / to the main memory 5n, that is, the delay time from when an interrupt is input from any input / output device until the CPU 11n starts interrupt processing is long. There was a problem of becoming.

  Next, the standby release operation in this embodiment will be described with reference to FIG. FIG. 6 is a timing chart when the SoC 10 of this embodiment receives an interrupt and transitions from the standby state to the operating state.

  When an interrupt is input from any of the input / output devices at time T21, the standby state is canceled by the power state management unit 16 of the SoC 10, and the standby signal becomes low level. Accordingly, the power state management unit 16 of the SoC 10 first starts the operation of the high-frequency oscillator 14 (and PLL 15 if necessary). When the supply of power to the main memory 5 is stopped in the standby state, the power state management unit 16 of the SoC 10 instructs the PMIC 8 at the timing when the standby state is canceled at time T21. Then, the supply of power to the main memory 5 is started.

  Since the memory controller 100 of this embodiment is supplied with the subclock generated by the low frequency oscillator 13 as described above, the memory controller 100 can operate with the subclock before the main clock is stabilized. Therefore, when the standby state is canceled at time T21, the memory controller 100 according to the present embodiment performs initialization processing of the main memory 5 according to an instruction from the power state management unit 16 without waiting for the main clock to stabilize. Start. At this time, if the main memory 5 is in a standby state with the second power consumption during the standby state, the memory controller 100 first causes the main memory 5 to operate with the first power consumption. When the initialization of the main memory 5 is completed at time T22, the main memory 5 is in a state where the CPU 11 can read and write data.

  After that, when the main clock becomes stable at time T23, the CPU 11 becomes ready for interrupt processing. At this time, since the initialization of the main memory 5 has already been completed and data can be read and written, the CPU 11 can start interrupt processing at this stage. As described above, in this embodiment, after the standby state is canceled and the supply of power to the main memory 5 is started, the initialization process of the main memory 5 is performed without waiting for the main clock to stabilize. Therefore, it is possible to reduce the delay time until the CPU 11 starts interrupt processing after an interrupt is input from any one of the input / output devices and the standby state is canceled.

  Note that the example shown in FIG. 6 assumes that the time required for the initialization process of the main memory 5 is shorter than the time required for the main clock to stabilize, but the time required for the initialization process of the main memory 5. However, if the time is longer than the time until the main clock is stabilized, the CPU 11 needs to wait for the start of the interrupt processing until the initialization of the main memory 5 is completed after the main clock is stabilized. However, even in this case, the delay time until the CPU 11 starts the interrupt process is smaller than in the case where the initialization process of the main memory 5n is started after the main clock is stabilized as in the prior art.

  FIG. 7 is a block diagram showing a configuration example of the memory controller 100 of the present embodiment for realizing the standby release operation as shown in FIG. In addition to the CPU 11 being connected to the memory controller 100 of the present embodiment via the bus 12, two types of clocks, a high-frequency main clock and a low-frequency subclock, and a standby state from the power state management unit 16 are provided. Signal.

  As the main clock, a clock obtained by increasing the frequency of the output of the high-frequency oscillator 14 of the SoC 10 with the PLL 15 is used. The main clock is stopped in the standby state. On the other hand, the output of the low frequency oscillator 13 of the SoC 10 is used as it is as the sub clock. As the sub clock, a clock obtained by raising the frequency of the output of the low frequency oscillator 13 of the SoC 10 using a PLL different from the PLL 15 may be used. The sub clock does not stop even when it enters the standby state. The frequencies of the main clock and the sub clock input to the memory controller 100 are determined within a range where the main memory 5 connected to the memory controller 100 can operate.

  The standby signal from the power state management unit 16 is at a high level (also referred to as on, asserted, active, etc.) in the standby state, as in the prior art, and low level (or off, deasserted, Inactive).

  As shown in FIG. 7, the memory controller 100 and the main memory 5 are connected by signal lines determined by the specifications of each memory interface. Signal lines connecting the memory controller 100 and the main memory 5 are roughly divided into a data signal line, a memory clock signal line, and a control signal line. The data signal line is a signal line through which data read from and written to the main memory 5 by the CPU 11 is transmitted, and has a width of 16 bits or 32 bits. The memory clock signal line is a signal line through which a main clock for synchronizing transmission and reception of data and control signals between the memory controller 100 and the main memory 5 is transmitted. The control signal line is a signal line for transmitting an address, bank designation, command, and the like, and includes a plurality of signal lines corresponding to the type of signal to be transmitted.

  As an example, the memory controller 100 of the present embodiment includes an initialization circuit 101, a read / write control circuit 102, a clock switching circuit 103, and a control signal switching circuit 104, as shown in FIG.

  The initialization circuit 101 operates with a sub-clock having a low frequency. When the power state management unit 16 turns off the standby signal and is notified of the release of the standby state, the control signal necessary for the initialization process of the main memory 5 is performed. At least a part of the first half of the first control signal (for example, NOP command) is generated and supplied to the control signal switching circuit 104. At this time, when the main memory 5 is in a standby state with the second power consumption in the standby state, the initialization circuit 101 controls the control signal (first control) required for the initialization process of the main memory 5. At the beginning of the signal), a control signal (command) for switching the main memory 5 to a state of operating with the first power consumption is inserted and supplied to the control signal switching circuit 104. In addition, when the standby circuit is notified of the cancellation of the standby state, the initialization circuit 101 converts the input sub clock as it is, or the sub clock internally converted by the PLL, flip-flop, or the like to the clock switching circuit 103. To supply. Hereinafter, the low-frequency clock supplied from the initialization circuit 101 to the clock switching circuit 103 is referred to as a first clock. When the sub clock is used as the first clock without frequency conversion, the sub clock input to the memory controller 100 may be directly input to the clock switching circuit 103.

  The read / write control circuit 102 operates with a high-frequency main clock, and sends a control signal (second control signal) for reading / writing data to / from the main memory 5 according to a memory access instruction supplied from the CPU 11 via the bus 12. The data is generated and supplied to the control signal switching circuit 104, and data read / written by the CPU 11 is transmitted / received to / from the main memory 5 using a data signal line. The read / write control circuit 102 generates a control signal (second control signal) for reading / writing data from / to the main memory 5 when initialization of the main memory 5 is not completed even when the main clock is stabilized. In addition, a part of the latter half of the control signal (first control signal) necessary for the initialization process of the main memory 5 (for example, MRS command) is generated and supplied to the control signal switching circuit 104. In addition, the read / write control circuit 102 supplies the input clock to the clock switching circuit 103 as it is or a signal obtained by internally converting the main clock using a PLL or flip-flop. Hereinafter, the high-frequency clock supplied from the read / write control circuit 102 to the clock switching circuit 103 is referred to as a second clock. When the main clock is directly used as the second clock without frequency conversion, the main clock input to the memory controller 100 may be directly input to the clock switching circuit 103.

  Since the read / write control circuit 102 operates with the main clock as in the conventional general memory controller 100n, the read / write control circuit 102 cannot operate until the main clock stabilizes after the standby state is released.

  When the main memory 5 is put on standby with the second power consumption in the standby state, for example, a standby signal is also connected to the read / write control circuit 102. Then, the read / write control circuit 102 that has detected that the standby signal has been switched from OFF to ON performs a control signal (command) for switching to a state of waiting with the second power consumption to the main memory 5. As another implementation method, when the CPU 11 enters the standby state, the CPU 11 instructs the memory controller 100 to send a control signal (command) for switching the main memory 5 to the standby state with the second power consumption. is there. In this case, it is not necessary to connect the standby signal to the read / write control circuit 102. When the supply of power to the main memory 5 is stopped in the standby state, it is not necessary to connect a standby signal to the read / write control circuit 102.

  The clock switching circuit 103 receives the first clock having a low frequency from the initialization circuit 101 and the second clock having a high frequency from the read / write control circuit 102, and the first clock until the second clock is stabilized. Is supplied to the main memory 5 as a memory clock, and after the second clock is stabilized, the second clock is supplied to the main memory 5 as a memory clock.

  The control signal switching circuit 104 starts supplying the first control signal generated by the initialization circuit 101 to the main memory 5 when the clock switching circuit 103 supplies the first clock to the main memory 5 as a memory clock. To do. The control signal switching circuit 104 continues to supply the first control signal generated by the initialization circuit 101 to the main memory 5, and the memory clock supplied from the clock switching circuit 103 to the main memory 5 is changed from the first clock to the second clock. If the initialization of the main memory 5 is not completed even after switching to, the first control signal generated by the read / write control circuit 102 is supplied to the main memory 5 thereafter. Then, the control signal switching circuit 104 is after the clock switching circuit 103 switches the memory clock supplied to the main memory 5 from the first clock to the second clock and after the initialization of the main memory 5 is completed. The second control signal generated by the read / write control circuit 102 is supplied to the main memory 5.

  As a method for the memory controller 100 to know that the second clock is stable, for example, the power state management unit 16 transmits a notification that the second clock is stable to the memory controller 100, and the main clock in the SoC 10 is effective. A method of using a signal indicating that the second clock is stable, a method of determining that the second clock is stable when a predetermined time has elapsed from the cancellation of standby, and a memory controller when the CPU 11 starts executing interrupt processing. And a method of instructing 100.

  Next, assuming the case where DDR3 SDRAM is used as the main memory 5 and the supply of power to the main memory 5 is stopped in the standby state, the initialization process of the main memory 5 by the memory controller 100 according to the present embodiment is illustrated. This will be described with reference to FIG. FIG. 8 is a timing chart for explaining the initialization process of the main memory 5 by the memory controller 100 of the present embodiment.

  When the standby state is canceled at time T31 and the supply of power from the PMIC 8 to the main memory 5 is started, the memory controller 100 of the present embodiment first supplies the first clock having a low frequency to the main memory 5 as a memory clock. To do. The first clock is generated based on the sub clock as described above, or the sub clock is used as it is. Then, a high-level CKE signal indicating that the memory clock is valid at time T32 is supplied to the main memory 5, and thereafter, a NOP command (first operation) is synchronized with the memory clock for a predetermined time. 1 control signal) continues to be supplied.

  When the main clock is stabilized, the memory controller 100 switches the memory clock supplied to the main memory 5 from the first clock having a low frequency to the second clock having a high frequency at time T33. The second clock is generated based on the main clock as described above, or the main clock is used as it is. If the initialization of the main memory 5 is not completed at this stage, the memory controller 100 continues the initialization process based on the main clock, and switches the remaining commands necessary for the initialization process to the second clock. The main memory 5 is supplied in synchronization with the memory clock. In the example shown in FIG. 8, the MRS command (first control signal) is supplied to the main memory 5 in synchronization with the memory clock switched to the second clock.

  When initialization of the main memory 5 is completed at time T34, the memory controller 100 then synchronizes a command (second control signal) according to data read / write by the CPU 11 with the memory clock switched to the second clock. To the main memory 5. FIG. 8 shows an example in which a READ command for requesting data reading is supplied to the main memory 5. If the initialization of the main memory 5 is completed at the time when the memory clock supplied to the main memory 5 is switched from the first clock to the second clock (time T33), immediately after that, Commands corresponding to reading and writing can be supplied to the main memory 5.

  In the example shown in FIG. 8, when the memory clock supplied to the main memory 5 is switched from the first clock having a low frequency to the second clock having a high frequency, the CKE signal remains at a high level. However, as shown in FIG. 9, when the frequency of the memory clock is switched, the CKE signal is temporarily set to a low level, and then the CKE signal is returned to a high level.

  FIG. 10 is a timing chart for explaining the operation of the memory controller 100 when the initialization process shown in FIG. 8 is executed.

  The initialization circuit 101 receives the sub clock and the standby signal. When the standby state is canceled at time T31 and the standby signal becomes low level, the initialization circuit 101 generates the frequency based on the sub clock or uses the sub clock as it is. A low first clock is input to the clock switching circuit 103. In addition, when the standby state is canceled, the initialization circuit 101 generates a command necessary for initialization of the main memory 5 and inputs the command to the control signal switching circuit 104. Specifically, the initialization circuit 101 generates a NOP command and inputs it to the control signal switching circuit 104 for a predetermined time after the CKE signal becomes high level at time T32.

  The read / write control circuit 102 receives the main clock, and starts operating when the main clock is stabilized. The clock read / write control circuit 102 generates a second clock having a high frequency generated based on the main clock or using the main clock as it is. To enter. If the initialization of the main memory 5 is not completed when the main clock starts operation stably, the read / write control circuit 102 (in the example of FIGS. 8 and 10), the remaining commands required for initialization MRS command) is generated and input to the control signal switching circuit 104. When the initialization of the main memory 5 is completed at time T34, the read / write control circuit 102 generates a command (READ command in the examples of FIGS. 8 and 10) corresponding to the data read / write by the CPU 11 to generate a control signal switching circuit. 104 is input.

  The clock switching circuit 103 receives the first clock and the second clock, and supplies the first clock to the main memory 5 as the memory clock until the main clock is stabilized. Then, after the main clock is stabilized (after time T33), the clock switching circuit 103 supplies the second clock to the main memory 5 as a memory clock.

  The control signal switching circuit 104 receives the command generated by the initialization circuit 101 and the command generated by the read / write control circuit 102, and uses the command generated by the initialization circuit 101 as the first clock until the main clock is stabilized. And is supplied to the main memory 5 in synchronization. Then, after the main clock is stabilized (after time T33), the control signal switching circuit 104 supplies the command generated by the read / write control circuit 102 to the main memory 5 in synchronization with the second clock.

  In the examples of FIGS. 8 and 10, assuming that the time required for the initialization process of the main memory 5 is longer than the time until the main clock is stabilized after the standby state is canceled, The read / write control circuit 102 generates the latter half of the command required for initialization. However, when initialization of the main memory 5 is completed before the main clock is stabilized, it is necessary for initialization of the main memory 5. All the commands are generated by the initialization circuit 101, and the read / write control circuit 102 only needs to generate commands corresponding to the data read / write by the CPU 11.

  When a DDR3 SDRAM is used as the main memory 5, the memory controller 100 continues to supply the NOP command to the main memory 5 for a predetermined time after the CKE signal goes high, and when the predetermined time elapses, the MRS command Is supplied to the main memory 5. 8 and 10, for the sake of simplicity, when the main clock supplied to the main memory 5 is switched from the first clock to the second clock, the command supplied to the main memory 5 is changed from the NOP command to the MRS command. It is illustrated to be switched, but this is not the case.

  That is, if the predetermined time is longer than the time until the main clock is stabilized, the read / write control circuit 102 generates a NOP command until the predetermined time elapses, as shown in FIG. When the time elapses, an MRS command is generated. After that, when initialization of the main memory 5 is completed, a READ command corresponding to data read / write by the CPU 11 is generated. In this case, the control signal switching circuit 104 sends the NOP command generated by the initialization circuit 101 to the main memory 5 until the main clock is stabilized and the memory clock supplied to the main memory 5 is switched from the first clock to the second clock. After the main clock is stabilized, the NOP command generated by the read / write control circuit 102 is supplied to the main memory 5 until the predetermined time elapses. When the predetermined time elapses, the MRS command generated by the read / write control circuit 102 is supplied to the main memory 5. When the initialization of the main memory 5 is completed, the READ command generated by the read / write control circuit 102 is transferred to the main memory. 5 is supplied.

  On the other hand, if the predetermined time is shorter than the time until the main clock is stabilized, the initialization circuit 101 generates an MRS command after the predetermined time has elapsed, as shown in FIG. If the initialization of the main memory 5 is not completed when the memory clock that is stably supplied to the main memory 5 is switched from the first clock to the second clock, the initialization of the main memory 5 is performed. Until completion, the read / write control circuit 102 generates an MRS command. In this case, the control signal switching circuit 104 receives the NOP command and the MRS command generated by the initialization circuit 101 until the main clock is stabilized and the memory clock supplied to the main memory 5 is switched from the first clock to the second clock. After the main clock 5 is sequentially supplied to the main memory 5 and the main clock is stabilized, the MRS command generated by the read / write control circuit 102 is supplied to the main memory 5 until the initialization of the main memory 5 is completed. When completed, the READ command generated by the read / write control circuit 102 is supplied to the main memory 5.

  The operation of the memory controller 100 when releasing the standby state has been described above. When the SoC 10 enters the standby state, the power state management unit 16 of the SoC 10 instructs the PMIC 8 to supply power to the main memory 5. Or the memory controller is instructed to shift the main memory 5 from a state where it operates with the first power consumption to a state where it waits with the second power consumption.

  As described above, the memory controller 100 according to the present embodiment starts from the state where the standby state is canceled and the supply of power to the main memory 5 is started or the main memory 5 waits at the second power consumption. Since the main memory 5 initialization process is started without waiting for the main clock to stabilize, the delay until the CPU 11 starts the interrupt process after the standby state is released. Time can be reduced.

  In the above-described embodiment, an example in which a DRAM is used as the main memory 5 has been described. However, in addition to the DRAM, for example, an SRAM (Static Random Access Memory), an FeRAM (Ferroelectric Random Access Memory), and a PCM (Phase Change Memory). ), MRAM (Magnetoresistive Random Access Memory), ReRAM (Resistance Random Access Memory), NOR Flash, and other random access memories can be used as the main memory 5. In this case, the command necessary for initializing the main memory 5 differs depending on the type of the interface of the memory used as the main memory 5. 5 may be supplied.

  In addition, the above-described embodiment is an application example to the memory controller 100 connected to the main memory 5, but the applied memory controller is not limited to this example, and is connected to a memory other than the main memory 5. Application to a memory controller is also possible.

  As described above in detail with specific examples, according to the memory controller 100 of the present embodiment, the time until the processor can read and write data from and to the memory while reducing power consumption. It can be shortened.

  As mentioned above, although embodiment of this invention was described, embodiment described here is shown as an example and is not intending limiting the range of invention. The novel embodiments described herein can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. The embodiments and modifications described herein are included in the scope and gist of the invention, and are also included in the invention described in the claims and the equivalents thereof.

1 Information processing device 5 Main memory 8 PMIC
10 SoC
11 CPU
DESCRIPTION OF SYMBOLS 100 Memory controller 103 Clock switching circuit 104 Control signal switching circuit

Claims (8)

A memory control device for controlling a memory capable of at least one of reading and writing data by a processor,
When an interrupt to the processor occurs, a signal for initializing the memory is supplied to the memory that is supplying a first clock;
Supplying at least one of a signal for reading data or a signal for writing by the processor to the memory supplying a second clock;
The memory control device, wherein the second clock is a clock generated by an oscillation circuit that starts operation when an interrupt to the processor occurs, and has a higher frequency than the first clock. A memory control device for controlling a memory from which data can be read by a processor,
When an interrupt to the processor occurs, a signal for initializing the memory is supplied to the memory that is supplying a first clock;
Supplying a signal for reading data by the processor to the memory supplying a second clock;
The memory control device, wherein the second clock is a clock generated by an oscillation circuit that starts operation when an interrupt to the processor occurs, and has a higher frequency than the first clock. A processor and a memory control device for controlling a memory capable of at least one of reading and writing data by the processor are semiconductor devices mounted on a semiconductor substrate,
The memory control device
When an interrupt to the processor occurs, a signal for initializing the memory is supplied to the memory that is supplying a first clock;
Supplying at least one of a signal for reading data or a signal for writing by the processor to the memory supplying a second clock;
The second clock is a clock generated by an oscillation circuit that starts operation when an interrupt to the processor occurs, and has a higher frequency than the first clock. A processor and a memory control device that controls a memory from which data can be read by the processor are semiconductor devices mounted on a semiconductor substrate,
The memory control device
When an interrupt to the processor occurs, a signal for initializing the memory is supplied to the memory that is supplying a first clock;
Supplying a signal for reading data by the processor to the memory supplying a second clock;
The second clock is a clock generated by an oscillation circuit that starts operation when an interrupt to the processor occurs, and has a higher frequency than the first clock. A system board on which a processor, a memory capable of reading or writing data by the processor, and a memory control device for controlling the memory are mounted;
The memory control device
When an interrupt to the processor occurs, a signal for initializing the memory is supplied to the memory that is supplying a first clock;
Supplying at least one of a signal for reading data or a signal for writing by the processor to the memory supplying a second clock;
The second clock is a clock generated by an oscillation circuit that starts operation when an interrupt to the processor occurs, and has a higher frequency than the first clock. A system board on which a processor, a memory from which data can be read by the processor, and a memory control device that controls the memory are mounted,
The memory control device
When an interrupt to the processor occurs, a signal for initializing the memory is supplied to the memory that is supplying a first clock;
Supplying a signal for reading data by the processor to the memory supplying a second clock;
The second clock is a clock generated by an oscillation circuit that starts operation when an interrupt to the processor occurs, and has a higher frequency than the first clock. An information processing apparatus including a processor, a memory capable of reading or writing data by the processor, and a memory control device that controls the memory,
The memory control device
When an interrupt to the processor occurs, a signal for initializing the memory is supplied to the memory that is supplying a first clock;
Supplying at least one of a signal for reading data or a signal for writing by the processor to the memory supplying a second clock;
The information processing apparatus, wherein the second clock is a clock generated by an oscillation circuit that starts operation when an interrupt to the processor occurs, and has a higher frequency than the first clock. An information processing device including a processor, a memory from which data can be read by the processor, and a memory control device that controls the memory,
The memory control device
When an interrupt to the processor occurs, a signal for initializing the memory is supplied to the memory that is supplying a first clock;
Supplying a signal for reading data by the processor to the memory supplying a second clock;
The information processing apparatus, wherein the second clock is a clock generated by an oscillation circuit that starts operation when an interrupt to the processor occurs, and has a higher frequency than the first clock.

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