JP5773807B2 - Arithmetic circuit, physical quantity sensor and detector circuit using the same - Google Patents

Description

  The present invention relates to an arithmetic circuit, a physical quantity sensor and a detection circuit using the arithmetic circuit, and more particularly to an arithmetic circuit using a translinear principle.

  The calculation related to the analog quantity can be performed using a digital calculation circuit or an analog calculation circuit. In a configuration using a digital arithmetic circuit, an input signal which is an analog signal is converted into digital data by an A / D converter (ADC: Analog-to-Digital Converter) and input to the digital arithmetic circuit. The digital arithmetic circuit gives the arithmetic result as digital data.

  The calculation accuracy of digital calculation is affected by the resolution of the ADC. In particular, in the calculation of a nonlinear function, the influence of the quantization error due to the ADC is also nonlinear. Therefore, when setting the resolution of the ADC, it is necessary to consider not only the required accuracy but also the order of the function and the range of the input signal. For example, when it is attempted to obtain a predetermined accuracy by a function calculation including a power of input data x, it is necessary to reduce the quantization error of x as x increases and the order of x increases. Become heavier. An increase in the number of input data bits also increases the burden on the digital arithmetic circuit.

  On the other hand, in the configuration using the analog arithmetic circuit, the arithmetic is performed by analog signal processing. That is, the input signal is input to the analog arithmetic circuit as an analog signal, and the analog arithmetic circuit generates a physical quantity such as voltage and current corresponding to the arithmetic result. Therefore, this configuration does not cause a problem associated with A / D conversion of the input signal. The obtained physical quantity may be output and used as an analog signal or may be converted into digital data by an ADC and output.

One analog operation circuit uses a translinear circuit. A translinear circuit is an analog circuit using the translinear principle. The translinear principle is the number of semiconductor junctions having a polarity in the clockwise direction (CW) and the semiconductor junction having a polarity in the counterclockwise direction (CCW) in a loop coupled so as to go around the base and emitter of a plurality of transistors. Are equal, the product of the collector current of the transistor in which the base current flows in the clockwise direction is equal to the product of the collector current of the transistor in which the base current flows in the counterclockwise direction. The following equation represents the translinear principle, where the left side is the product of the collector currents I _Ci of N transistors having a base-emitter junction with a clockwise (CW) polarity, and the right side is counterclockwise (CCW). It is the product of the collector currents I _Cj of N transistors with polar base-emitter junctions. Here, i and j are both natural numbers of N or less.

A translinear circuit can realize a multiplication circuit, a division circuit, a square circuit, a square root circuit, and the like. FIG. 12 is a circuit diagram showing an example of a conventional translinear circuit. Four transistors Q1 to Q4 constitute a translinear loop. The circuit receives the collector currents I1 to I3 of the transistors Q1 to Q3 as an input current and takes out the collector current of the transistor Q4 as an output current Iout. Iout is expressed by the following equation.
Iout = I1 / I2 / I3 (2)

  That is, in this example, a circuit that performs multiplication of I1 and I2 and division by I3 is realized by a translinear circuit. The circuit of FIG. 12 converts the current Iout into a voltage with the resistor R, A / D converts the voltage, and outputs a calculated value Dout indicating the calculation result.

JP-A-11-120273

  Generally, a semiconductor integrated circuit (IC) manufactured by a complementary metal oxide semiconductor (CMOS) process has lower power consumption and higher integration density than an IC manufactured by a bipolar process. Is easy. However, since the translinear principle uses the characteristics of bipolar transistors as described above, an IC incorporating a translinear circuit is not manufactured by a standard CMOS process. Therefore, even if the circuit constituting the IC includes a circuit portion that can be constituted by CMOS in addition to the translinear circuit, the IC is basically manufactured by using a bipolar process, and the CMOS process related to power consumption and integration density is performed. There was a problem that the benefits could not be enjoyed.

  Here, if a Bi-CMOS (Bipolar Complementary Metal Oxide Semiconductor) process is used, a translinear circuit using bipolar transistors and other CMOS circuits can be formed on the same semiconductor substrate. However, the Bi-CMOS process in which a bipolar transistor and a CMOS having different structures are formed on the same substrate is more complicated and complicated than a standard CMOS process, resulting in an increase in manufacturing cost. .

  The present invention has been made to solve the above problems, and provides an arithmetic circuit that can be configured as a semiconductor device by a CMOS process while having the advantages of an analog arithmetic circuit using the translinear principle. It is an object to provide a physical quantity sensor and a detection circuit using the same.

  The arithmetic circuit according to the present invention is a loop that traces the base and emitter of an even number of transistors that are input transistors or output transistors, and the forward and reverse directions of the diodes formed by the base-emitter junction are the same number on the loop. An arithmetic circuit that performs a target calculation expressed by a translinear loop and outputs a calculation result as a calculated value of a digital value. In the circuit having the translinear loop, the direction of the diode is connected to the connection of the translinear loop. A modified loop circuit in which a potential comparison circuit is connected between the emitter of the transistor in the forward direction and the emitter of the transistor in the reverse direction, and a potential comparison circuit is connected to the divided portion, and the emitter of the input transistor Connected to each other to supply an input current to be input to the target calculation. A current supply means; a control circuit that generates a trial value for the calculated value; a trial current generation means that is connected to the emitter of the output transistor and generates and supplies a trial current having a magnitude corresponding to the trial value; And the potential comparison circuit compares the potentials on both sides of the divided portion and generates a comparison output according to the result, and the control circuit generates a potential at the divided portion based on the comparison output. The trial value corresponding to the equilibrium state is searched and output as the calculated value.

  In another arithmetic circuit according to the present invention, the potential comparison circuit includes, as the comparison output, a comparator that outputs one of two types of output states according to the magnitude relationship between the potentials on both sides of the divided portion. The control circuit receives a clock pulse, sequentially increments or decrements the count value for each clock pulse, outputs the count value as the trial value, and changes the output state of the comparison output. And a determination circuit that detects and uses the trial value corresponding to the change as the operation value.

  In another arithmetic circuit according to the present invention, the potential comparison circuit includes, as the comparison output, a voltage-current conversion circuit that generates a current according to a potential difference between both sides of the divided portion, and the control circuit includes: A capacitor for charging the current of the comparison output, a switch for selectively discharging the capacitor in an on state, and a voltage between terminals of the capacitor are input, and an on / off state of the switch is set according to the output. A hysteresis comparator that alternately repeats charging / discharging of the capacitor, a counter that sequentially increases or decreases a count value for each output pulse of the hysteresis comparator, and outputs the count value as the trial value, and the hysteresis comparator The potential equilibrium state is determined based on the period of change in output of the Having a determination circuit of the calculated value of the trial value corresponding to time.

  The physical quantity sensor according to the present invention detects a target physical quantity with a detection sensitivity corresponding to the excitation intensity in an excited state, outputs a detection signal obtained by amplitude-modulating a carrier wave of the excitation frequency, and the sensor using the oscillation signal. A drive circuit for exciting and driving a part, and a detection circuit for synchronously detecting the detection signal with the oscillation signal by a synchronous detection circuit and generating an output signal corresponding to the target physical quantity from a detection output, and the synchronous detection The circuit includes any one of the arithmetic circuits according to the present invention that performs the target calculation for performing synchronous detection by taking the product of the detection signal and the oscillation signal and outputs the calculation value, and based on the calculation value The detection output is obtained.

  The detection circuit according to the present invention uses any of the arithmetic circuits according to the present invention to detect a detection signal that is a signal obtained by amplitude-modulating a carrier wave having an intensity and a frequency based on the oscillation signal. The objective calculation for synchronous detection using a product is performed, and the modulation signal of the amplitude modulation is extracted based on the calculation value.

  In the CMOS process, a bipolar transistor can be formed by utilizing the structure of a parasitic transistor generated in a semiconductor substrate as a by-product in the process. Since the bipolar transistor has a structure in which a semiconductor substrate is used as a collector, if a circuit using the translinear principle is used by using this bipolar transistor, there is a restriction that the collector of each transistor becomes a common potential. According to the present invention, an arithmetic circuit having the advantages of an analog arithmetic circuit using the translinear principle can be configured under the restriction. For example, as an advantage similar to that of an analog arithmetic circuit, an ADC for an input signal is unnecessary, and the above-described problem that the quantization error of the ADC increases nonlinearly according to the arithmetic contents described above for the digital arithmetic circuit does not occur.

1 is a schematic block configuration diagram of a vibration gyroscope that is a physical quantity sensor using an arithmetic circuit according to an embodiment of the present invention. FIG. 3 is a schematic circuit diagram schematically illustrating a configuration example of an AGC unit. 1 is a schematic block configuration diagram of a synchronous detection circuit using an arithmetic circuit according to an embodiment of the present invention. It is a schematic timing diagram of the synchronous detection circuit using the arithmetic circuit which concerns on embodiment of this invention. It is typical sectional drawing which shows the structure of the bipolar transistor formed in an n-type semiconductor substrate using a CMOS process. It is a circuit diagram which shows the basic composition of an example of the arithmetic circuit used for a synchronous detection circuit. It is a typical block diagram which shows an example of a structure of an electric potential comparison circuit and a control circuit. It is a schematic circuit diagram which shows the other example of a structure of an electric potential comparison circuit and a control circuit. FIG. 7 is a circuit diagram showing a configuration in which the arithmetic circuit shown in FIG. 6 can operate in four quadrants. FIG. 10 is a circuit diagram illustrating a modification of the arithmetic circuit illustrated in FIGS. 6 and 9. It is a schematic circuit diagram of the other example of the arithmetic circuit which is embodiment of this invention. It is a circuit diagram which shows the example of the conventional translinear circuit.

  Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.

  FIG. 1 is a schematic block diagram of a vibration gyroscope 30 that is a physical quantity sensor using an arithmetic circuit according to the embodiment. The gyroscope 30 includes a sensor element 32, a drive circuit 34, and a detection circuit 36.

  The sensor element 32 includes a vibrator 40 made of a piezoelectric material such as quartz, drive electrodes 42 and 44 paired with each other, and detection electrodes 46 and 48 paired with each other. The drive electrodes 42 and 44 apply the oscillation signal from the drive circuit 34 to the vibrator 40 and excite the vibrator 40 by the inverse piezoelectric effect. When an angular velocity is applied to the excited vibrator 40, the vibrator 40 vibrates due to Coriolis force and generates electric charges due to the piezoelectric effect. The detection electrodes 46 and 48 take out the electric charge generated by the vibration as a current and output it to the detection circuit 36.

  The drive circuit 34 includes a current-voltage conversion circuit (hereinafter referred to as an I / V conversion circuit) 50 and an amplifier 52, and forms a feedback oscillation circuit together with the vibrator 40 to generate a drive signal that is an oscillation signal having a predetermined frequency. The drive circuit 34 applies the drive signal S1 to the drive electrode 42 of the vibrator 40, monitors the current flowing out of the drive electrode 44 according to the vibration of the vibrator 40, and feedback-controls the amplitude of the drive signal.

  The I / V conversion circuit 50 receives the feedback current S2 flowing out from the drive electrode 44, performs current-voltage conversion, and outputs it to the amplifier 52 as a feedback signal S3.

  The amplifying unit 52 includes a variable gain amplifying circuit 54 and an automatic gain control (AGC) unit 56.

  The AGC unit 56 generates a DC monitor voltage Vi corresponding to the amplitude of the feedback signal S3, and based on the monitor voltage Vi and the reference signal, the gain of the variable gain amplifier circuit 54 is adjusted so as to stabilize the excitation level of the oscillation circuit. A signal S4 to be controlled is generated. The AGC unit 56 of the present embodiment uses the reference voltage Vref input from the reference voltage generation circuit 58 as a reference signal, and generates a signal S4 based on the difference between the monitor voltage Vi and the reference voltage Vref. Note that a current signal may be used as the reference signal. In this case, the current signal can be used as a reference current Iref corresponding to the amplitude of the oscillation signal by the synchronous detection circuit 72 described later.

  The gain of the variable gain amplifier circuit 54 is controlled by the control signal S4 from the AGC unit 56, and amplifies the feedback signal S3 with the gain.

  The detection circuit 36 includes a detection amplification unit 70, a synchronous detection circuit 72, and an LPF 76. The detection circuit 36 processes the detection signals S5 and S6 output from the sensor element 32 and outputs an output signal corresponding to an angular velocity that is a physical quantity to be detected. Is generated.

  The detection amplification unit 70 is connected to the detection electrodes 46 and 48, and converts the detection signals S5 and S6 input from them into voltage values, respectively. The detection amplification unit 70 includes a differential amplification circuit, and performs differential amplification on the detection signals S5 and S6 converted into voltages.

  The synchronous detection circuit 72 receives the output signal S7 (amplified signal X) of the detection amplifier 70, performs synchronous detection (product detection) based on the oscillation signal Y of the drive circuit 34, and generates a detection output S8. In the present embodiment, the feedback signal S3 output from the I / V conversion circuit 50 is used as the oscillation signal Y of the drive circuit 34, and the phase of the signal S3 is adjusted and input to the synchronous detection circuit 72. The synchronous detection circuit 72 uses the reference voltage Vref input from the reference voltage generation circuit 58, as will be described later. The synchronous detection circuit 72 outputs the detection output S8 as digital data.

  The LPF 76 is composed of a digital filter, removes high frequency components from the digital signal output from the synchronous detection circuit 72, extracts an angular velocity output S 9 that is a signal corresponding to the angular velocity applied to the transducer 40, and outputs it from the output terminal 78. To do.

  The drive circuit 34 and the detection circuit 36 are formed as an IC using a silicon substrate or the like. In the IC, in addition to the output terminal 78 described above, terminals (or pads) 80 and 82 for connecting the drive circuit 34 to the drive electrodes 42 and 44 and the detection circuit 36 are connected to the detection electrodes 46 and 48. Terminals (or pads) 84 and 86 are provided. A control terminal 88 for inputting the reference voltage Vref is also provided.

  The reference voltage generation circuit 58 receives a voltage supply from the power supply voltage and generates a reference voltage Vref that does not depend on the power supply voltage.

FIG. 2 is a schematic schematic circuit diagram showing a configuration example of the AGC unit 56. The AGC unit 56 includes an effective value circuit 100 and a control voltage generation circuit 102. The effective value circuit 100 receives the feedback signal S3 and generates an effective value voltage of the feedback signal S3 as a DC monitor voltage Vi corresponding to the amplitude. The control voltage generation circuit 102 generates a control signal S4 based on the difference between the monitor voltage Vi and the reference voltage Vref. The control voltage generation circuit 102 includes, for example, an inverting amplifier circuit using an operational amplifier 104. The inverting input terminal (−) of the operational amplifier 104 is connected to the input resistance Ri between the rms value circuit 100, the feedback resistance Rf is connected to the output terminal of the operational amplifier 104, and the reference voltage Vref is input. A resistor Rref is connected between the terminals. The non-inverting input terminal (+) of the operational amplifier 104 is grounded. When the voltage of the control signal S4 output from the output terminal of the operational amplifier 104 is expressed as Vo, the following equation is established from Kirchhoff's current conservation law at the inverting input terminal (−).
Vi / Ri + Vref / Rref = -Vo / Rf (3)

  Usually, Rf is sufficiently larger than Ri and Rref. Therefore, assuming that the right side of equation (3) is 0, equation (3) indicates that monitor voltage Vi indicating the excitation level is substantially proportional to | Vref |. This indicates that the excitation level of the oscillation circuit is set with reference to Vref.

  Note that when the reference current (Iref) is used as the reference signal, the control voltage generation circuit 102 is configured such that the reference voltage Vref is connected to the inverting input terminal (−) of the operational amplifier 104 shown in FIG. Instead of the applied configuration, the reference current Iref is supplied to the inverting input terminal (−). Iref is supplied in the direction of drawing from the inverting input terminal (−), and is configured to cancel the current flowing from the effective value circuit 100 to the inverting input terminal (−).

  As described above, the reference voltage generation circuit 58 is designed to keep the reference voltage Vref constant, but in reality, Vref changes due to variations in temperature, power supply voltage, and the like. This change in the reference voltage Vref changes the signal level of the drive signal, the signal levels of the detection signals S5 and S6 of the sensor element 32 change accordingly, and further the signal level of the angular velocity output S9 changes. The synchronous detection circuit 72 in this embodiment reduces the fluctuation of the angular velocity output S9 caused by the fluctuation of the reference signal such as the reference voltage Vref and the reference current that should be the reference signal.

  FIG. 3 is a schematic block diagram of the synchronous detection circuit 72. The synchronous detection circuit 72 includes voltage-current conversion circuits (hereinafter referred to as V / I conversion circuits) 110a, 110b, 110c, an arithmetic circuit 112, sample hold circuits 114a, 114b, and a phase shifter 116. As already described, the synchronous detection circuit 72 is supplied with the amplified signal X from the detection amplifier 70, the oscillation signal Y from the drive circuit 34, and the reference voltage Vref from the reference voltage generation circuit 58. The amplified signal X is input to the sample hold circuit 114a, and the oscillation signal Y is input to the sample hold circuit 114b and the phase shifter 116. The reference voltage Vref is input to the V / I conversion circuit 110c.

  FIG. 4 is a schematic timing chart of the synchronous detection circuit 72. The phase shifter 116 generates a clock CK having a phase shifted by 90 ° with respect to the input oscillation signal Y. For example, the phase shifter 116 shifts one period from the H (High) level period to the L (Low) level period of the clock CK by 90 ° with respect to one period from the positive period to the negative period of the voltage signal Y. Set with advanced phase. The generated clock CK is input to the triggers of the sample and hold circuits 114a and 114b. The falling timing of the clock CK corresponds to the peak point of the voltage of the oscillation signal Y, and the sample hold circuit 114b samples and holds the voltage at the peak point. The sample hold circuit 114a samples and holds the voltage of the amplified signal X at the same timing as the sample hold circuit 114b, that is, at a timing synchronized with the peak of the oscillation signal Y.

  The V / I conversion circuits 110a and 110b receive the hold voltages of the signals X and Y from the sample hold circuits 114a and 114b, respectively, convert the voltage signals X and Y into current signals Ix and Iy, and input them to the arithmetic circuit 112. . Since the reference voltage Vref is a DC signal, it is directly input to the V / I conversion circuit 110c without passing through the sample-and-hold circuit. The V / I conversion circuit 110c converts the reference voltage Vref into a current signal Iref and calculates the arithmetic circuit 112. Enter.

The arithmetic circuit 112 receives the current signal Ix corresponding to the detection signal of the sensor element 32, the current signal Iy corresponding to the oscillation signal of the drive circuit 34, and the reference current Iref corresponding to the amplitude of the oscillation signal, and is expressed by the following equation: Output data Dout, which is digital data representing the output current Iout.
Iout = Ix / Iy / Iref (4)

  In the operation shown in FIG. 4, Dout is obtained for each cycle of the oscillation signal Y. However, when a single calculation of Dout requires a time longer than the cycle of the signal Y, In this configuration, the signals X and Y are sampled every plural cycles of the signal Y by dividing the clock CK.

The arithmetic circuit 112 uses the translinear principle, and can be said to constitute a translinear loop in a pseudo manner as will be described later. The part using the translinear principle is configured using a bipolar transistor as in the original translinear loop. In this embodiment, the bipolar transistor is formed by a CMOS process. FIG. 5 is a schematic view showing the structure of the bipolar transistor, and shows a cross section perpendicular to the semiconductor substrate. FIG. 5 shows an example in which the semiconductor substrate for forming an IC is an n-type substrate (hereinafter referred to as n-sub) 200 to which n-type impurities are introduced and n-type conductivity (first conductivity type) is given. Yes. A p-type well (p-well) 202, which is a semiconductor region made of p-type conductivity (second conductivity type), is formed on the surface of the n-sub 200 by introducing p-type impurities. Further, an n-type region 204 is formed in the p well 202. As a result, an npn-type transistor having the n-sub 200 as the collector (C), the p-well 202 as the base (B), and the n-type region 204 as the emitter (E) is formed. Incidentally, in the CMOS process, the p-well 202 is formed by a step of forming a region that becomes a channel of the n-type MOS transistor. Specifically, a mask having an opening in the region where the p-well 202 is formed is formed of a photoresist or the like. It is formed by ion implantation and thermal diffusion of p-type impurities. The n-type region 204 is formed by the step of forming the diffusion layer regions of the source and drain of the n-channel MOS transistor. Specifically, the n-type region 204 is formed by ion-implanting n-type impurities after forming a mask. In the bipolar transistor formed by this CMOS process, the collector is fixed at the substrate potential Vsub. For an n-type substrate, Vsub can be a positive potential V ₊ .

FIG. 6 is a circuit diagram showing a basic configuration of an example of the arithmetic circuit 112 using the above-described bipolar transistor made by a CMOS process. The arithmetic circuit 112 operates by being supplied with power supplies V ₊ and V ₋ . The potentials of these power sources are V ₊ > V ₋ . The arithmetic circuit 112 has four transistors Q1 to Q4. These transistors Q1 to Q4 form a translinear loop if the emitter of Q2 and the emitter of Q4 are autonomously at the same potential. However, in this embodiment, the emitter of Q2 and the emitter of Q4 are divided, and their potential relationship is different from the original translinear loop in that it is controlled from outside the loop. Because of this difference, the transistors Q1 to Q4 and their control mechanism are referred to as quasi-translinear loops.

  In the configuration of FIG. 6, the transistors Q <b> 1 to Q <b> 3 are input transistors supplied from outside the arithmetic circuit 112 as input for calculation in the arithmetic circuit 112. This is an output transistor. The collectors of the transistors Q1 to Q4 are the n-sub 200 as described above, and are set to the common potential Vsub. For this reason, there is a restriction that the collectors of the transistors Q1 to Q4 cannot be used for supplying the input current or extracting the output current.

The arithmetic circuit 112 has current sources I1 to I3 as current input means for supplying an input current to the emitters of the transistors Q1 to Q3. In the circuit shown in FIG. 6, current sources I1-I3 supply currents Ix, Iy, Iref to the emitters of transistors Q1-Q3 using output currents of V / I conversion circuits 110a, 110b, 110c, respectively. Here, the current sources I1 to I3 supply the input current from the collector to the emitter. For example, when the current Iref generated by the V / I conversion circuit 110c is directed to flow into the V / I conversion circuit 110c, the output terminal of the V / I conversion circuit 110c is connected to the emitter of Q3 as the current source I3. Good. On the other hand, when Iref is oriented flowing from V / I conversion circuit 110c is the current example, by using a current mirror circuit, Q3 the emitter and the power supply V in predetermined negative voltage _- to replicate path connecting the . The other input currents Ix and Iy are similarly configured.

  A current output type D / A converter (DAC: Digital-to-Analog Converter) 210 is connected to the emitter of the transistor Q4 to supply current to the emitter of Q4.

  The bases of Q1 and Q3 are connected to the n-sub 200, the emitter of Q1 and the base of Q2 are connected by, for example, wiring formed on the substrate, and the emitter of Q3 and the base of Q4 are similarly connected by wiring. That is, Q1 and Q2 constitute a Darlington connection, and Q3 and Q4 also constitute a Darlington connection. Here, Q1 to Q4 are all npn-type, and on the translinear loop composed of transistors of the same type in this way, the emitter of the transistor whose direction of the diode is the reverse direction to the emitter of the transistor whose direction is the forward direction. There is a place to connect the.

  In the present embodiment, the connection between Q2 and Q4 corresponds to this point. As described above, the translinear loop composed of Q1 to Q4 is completed by connecting the emitter of Q2 and the emitter of Q4 so as to have the same potential autonomously. On the other hand, the quasi-translinear loop in the arithmetic circuit 112 has a circuit configuration (modified loop circuit) in which the connection of the translinear loop is divided at the corresponding portion and the potential comparison circuit 212 is connected to the divided portion. ing. The potential comparison circuit 212 compares the potentials on both sides of the divided portion and generates a comparison output corresponding to the result.

  Further, the arithmetic circuit 112 has a control circuit 214. The control circuit 214 controls the current DAC 210 based on the output of the potential comparison circuit 212 and outputs the calculation result of the above expression (4) expressed by the original translinear loop as a digital value. The control circuit 214 sets a value assumed as a calculation value, which is digital data representing the calculation result, and evaluates whether the value is a calculation value. If the value is not a calculation value, the value is changed and evaluated. To search for the calculated value. Here, a value to be set as a trial as an operation value is called a trial value.

Specifically, the control circuit 214 generates a trial value Nt and inputs it to the current DAC 210. The current DAC 210 generates a current (trial current) It corresponding to the trial value and supplies it to the emitter of the output transistor Q4. Here, the trial current It is given by the following equation, where the discretized current of the current DAC 210 (current per 1 LSB) is ΔI.
It = Nt · ΔI (5)

If the trial current It is equal to Iout represented by the equation (4), the quasi-translinear loop can be regarded as the same state as the state where the translinear principle of the equation (1) is established. That is, a state equivalent to the original translinear loop is realized, and the emitter potential Vα of Q4 and the emitter potential Vβ of Q2 are in an equilibrium state. On the other hand, if It is less than Iout, the base-emitter voltage V _{BE of} Q4 is smaller than that of the translinear loop, and Vα is higher than Vβ. Conversely, if It is greater than Iout, Vα is lower than Vβ.

  The potential comparison circuit 212 receives the Vα and Vβ and generates a comparison output. The control circuit 214 detects a trial value corresponding to the equilibrium state of Vα and Vβ from the comparison output, and calculates this as the operation value Dout. Output from the circuit 112.

  The arithmetic circuit 112 uses the translinear principle, but can be manufactured by a standard CMOS process instead of a bipolar process or a Bi-CMOS process. That is, not only the current DAC 210, the potential comparison circuit 212, and the control circuit 214 but also the bipolar transistors Q1 to Q4 related to the translinear principle are manufactured by the CMOS process as described above. Therefore, the detection circuit 36 or an IC incorporating the drive circuit 34 and the detection circuit 36 can be manufactured by a CMOS process, and power consumption can be reduced, integration density can be improved, and manufacturing cost can be reduced.

  FIG. 7 is a schematic block diagram showing an example of the configuration of the potential comparison circuit 212 and the control circuit 214. The potential comparison circuit 212 uses a comparator 220. The control circuit 214 includes a counter 222 and a register 224.

  The comparator 220 receives the potentials Vα and Vβ, and outputs one of two types of potentials of H level and L level depending on the magnitude relationship between them. Here, as the comparison output Vcmp, the comparator 220 outputs an L level when Vα> Vβ, and outputs an H level when Vα ≦ Vβ.

  The counter 222 receives an external clock signal CLK and counts the clock pulses. The count value of the counter 222 is input to the current DAC 210 as the trial value Nt and also output to the register 224. For example, the counter 222 periodically repeats the count-up operation in the operation state of the gyroscope 30.

  For example, the register 224 loads the count value at the rising edge of the register clock RCK and sets it as output data Dout of the arithmetic circuit 112. The comparison output Vcmp is input as the register clock RCK. That is, the register 224 functions as a determination circuit that detects a change in the output state of the comparison output and uses the trial value Nt corresponding to the change as the operation value Dout.

By the count-up operation of the counter 222, the trial value Nt increases from 0 by 1, and the trial current It supplied from the current DAC 210 to Q4 increases by ΔI. At the same time, V _BE of Q4 increases sequentially, and Vα decreases sequentially. Basically, Vα> Vβ at the start of the count-up, and Vα approaches Vβ as the count-up proceeds. In this state, the comparison output Vcmp is at the L level. When the count-up further proceeds and when It ≧ Iout with respect to Iout represented by the equation (4), Vα ≦ Vβ is established, and the comparison output Vcmp rises to the H level when passing through the equilibrium state. The register 224 to which the rising edge is input to RCK holds Nt at this time. The value held in the register 224 is output from the arithmetic circuit 112 as the arithmetic value Dout representing the arithmetic result for the inputs Ix, Iy, and Iref.

  Note that the comparator 220, the counter 222, and the register 224 may be configured to search the calculation value Dout by causing the counter 222 to perform a countdown operation.

  Further, the control circuit 214 may generate the trial value Nt by the binary search method and search for the calculated value Dout.

  FIG. 8 is a schematic circuit diagram showing another example of the configuration of the potential comparison circuit 212 and the control circuit 214. The potential comparison circuit 212 uses a V / I conversion circuit 240. The control circuit 214 includes a capacitor C, a switch SW, a hysteresis comparator 242, a counter 244, a register 246, and a balance detection circuit 248.

The V / I conversion circuit 240 is composed of a transconductance amplifier (OTA) and outputs a current Icmp corresponding to the input voltage difference ΔV to the differential input terminals (+) and (−). Specifically, when transconductance is expressed in gm,
Icmp = gm · ΔV
It is. The current Icmp becomes a comparison output of the potential comparison circuit 212. The differential input terminal (+) receives a potential Vα, the differential input terminal (−) receives a potential Vβ,
ΔV = Vα−Vβ
It is.

  The capacitor C is connected between the output terminal of the V / I conversion circuit 240 and the ground GND, and charges the current Icmp.

  The switch SW selectively discharges the capacitor C in the on state. Specifically, the switch SW is connected in parallel to the capacitor C and shorts both ends of the capacitor C in the on state. For example, the switch SW is formed of a MOS transistor, and is turned on / off by the output voltage Vsch of the hysteresis comparator 242 applied to the gate. Here, the switch SW is turned on when Vsch is at H level, and is turned off when Vsch is at L level.

  The hysteresis comparator 242 receives the inter-terminal voltage Vcap of the capacitor C, switches the on / off state of the switch SW in accordance with the output voltage Vsch, and alternately repeats charging / discharging of the capacitor C. The hysteresis comparator 242 sets the two threshold values VthH and VthL to VthH> VthL> 0, and switches Vsch from L level to H level when Vcap becomes VthH or more, and changes Vsch from H level to L level when Vcap becomes VthL or less. Switch to.

  The balance detection circuit 248 is a circuit that detects the arrival of Vα and Vβ in an equilibrium state based on the period of change in the output of the hysteresis comparator 242. The balance detection circuit 248 receives Vsch from the hysteresis comparator 242, determines that the potential is in a balanced state when Vsch does not change for a predetermined time, and raises the output Veq from L level to H level.

  The counter 244 and the register 246 have the same configuration as the counter 222 and the register 224 configured as shown in FIG. The counter 244 counts up the output pulse of the hysteresis comparator 242 from zero. The register 246 receives the output Veq of the balance detection circuit 248 as the register clock RCK. Incidentally, a determination circuit in which the balance detection circuit 248 and the register 246 determine the arrival of the potential equilibrium state based on the change cycle of the output of the hysteresis comparator 242, and sets the trial value Nt corresponding to the arrival as the calculation value Dout. Configure.

  At the start of the search for the calculation value Dout, the count value of the counter 244 is reset to 0, and basically Vα> Vβ. The V / I conversion circuit 240 outputs Icmp corresponding to ΔV. The capacitor C, the switch SW, and the hysteresis comparator 242 constitute an oscillation circuit, and periodically generate pulses at the output of the hysteresis comparator 242.

The counter 244 counts up the output pulse of the hysteresis comparator 242. In addition, the trial value Nt increases from 0 by 1, and the trial current It supplied from the current DAC 210 to Q4 increases by ΔI. At the same time, V _BE of Q4 increases sequentially, and Vα decreases sequentially. As the count-up proceeds, Vα approaches Vβ, and Icmp decreases. As Icmp decreases, the time required for charging the capacitor C increases and the period of the output pulse of the hysteresis comparator 242 increases. Ideally, Vα and Vβ finally balance and oscillation stops. The trial value Nt in this state corresponds to the calculated value Dout.

  In practice, Vα can only be changed discretely, so oscillation generally does not stop completely, and even when Vα equal to Vβ can be set, it takes a long time to completely stop oscillation. obtain. Therefore, the balance detection circuit 248 sets the predetermined time τ, and determines that the potential is balanced when the period from the most recent output pulse of the hysteresis comparator 242 reaches τ. For example, τ can be set based on the time constant of charging at Icmp with respect to the allowable value of (Vα−Vβ). Since the adjustment accuracy of Vα depends on ΔI of the current DAC 210, τ can also be set according to ΔI.

  When the balance detection circuit 248 detects the arrival of the potential equilibrium state, Veq is raised from the L level to the H level, and the register 224 to which the rise is inputted to RCK holds Nt at this time. The value held in the register 224 is output from the arithmetic circuit 112 as the arithmetic value Dout.

  In the configuration shown in FIG. 8, the control circuit 214 does not require an external clock signal CLK.

  The control mechanism and operation of the quasi-translinear loop in the arithmetic circuit 112 of the synchronous detection circuit 72 has been described above.

  Incidentally, the detection signal of the sensor element 32 is proportional to the excitation level of the sensor element 32 by the drive circuit 34. As described with respect to equation (3), the excitation level of the drive signal S1 is basically proportional to Vref. In other words, the product (Ix · Iy) of the currents Ix and Iy corresponding to the amplified signal X and the oscillation signal Y is proportional to the square of Vref, but the synchronous detection circuit 72 uses the arithmetic circuit 112 to increase Iref proportional to Vref. The result of dividing by is taken out as Iout. That is, Iout is simply proportional to Vref (ie, to the first power). Therefore, the angular velocity output S9 obtained based on this Iout is less susceptible to the error of the reference voltage Vref than the conventional synchronous detection multiplied by the oscillation signal Y.

  As described above, the synchronous detection circuit 72 using the arithmetic circuit 112 can reduce the influence of the error of the reference voltage Vref and reduce noise due to the higher-order vibration mode, so that the accuracy of the angular velocity output can be improved.

  Actually, the synchronous detection circuit 72 is configured to be operable in four quadrants. That is, regardless of the signs of the amplified signal X and the oscillation signal Y, the directions of the collector currents of the transistors Q1 and Q2 are fixed, and the synchronous detection circuit 72 is always operated regardless of the phases of the signals X and Y.

FIG. 9 is a circuit diagram showing a configuration in which the arithmetic circuit 112 shown in FIG. 6 can operate in four quadrants. The circuit of FIG. 9 differs from the circuit of FIG. 6 in that the input currents Ix, Iy, and Iref generated by the V / I conversion circuits 110a to 110c are input to the arithmetic circuit 112 and to the output transistor Q4. It is in the way of supplying current. The current source I1 connected to the emitter of Q1 supplies (Ix + Iref), and the current source I2 connected to the collector of Q2 supplies (Iy + Iref). In order to perform the four-quadrant operation, Iref is set so that (Ix + Iref)> 0 and (Iy + Iref)> 0. A current source I3 connected to the emitter of Q3 supplies Iref as in FIG. The input currents (Ix + Iref), (Iy + Iref) and Iref are generated using the output currents of the V / I conversion circuits 110a to 110c, and are replicated at the positions of the current sources I1 to I3 using, for example, a current mirror circuit. When the collector current of Q4 is expressed as Iη, the following equation is established according to the translinear principle for the translinear loop to be simulated by the quasi-translinear loop of the arithmetic circuit 112.
(Ix + Iref) · (Iy + Iref) = Iη · Iref (6)

The following equation is derived from equations (4) and (6).
Iη = Iout + Ix + Iy + Iref (7)

  That is, Iη is a current obtained by superimposing a current (Ix + Iy + Iref) on Iout expressed by the equation (4).

The output emitter of transistor Q4 and the power source V _- current source I5 is connected between the current DAC210 is provided as a parallel current supply means thereto. The current source I5 supplies a current (Ix + Iy) to the emitter of the transistor Q4. Similarly to the current sources I1 to I3, the current source I5 supplies a current from the base of Q4 toward the emitter. In this configuration, the control circuit 214 searches for a trial value Nt at which the trial current It has a magnitude corresponding to the current (Iout + Iref). Here, by adding Iref, (Iout + Iref)> 0 can be established, and the trial value Nt can be searched in a range of 0 or more regardless of the polarity of Iout, and the current DAC 210 is 0 or more. In this range, the trial current It can be generated. In this configuration, the calculated value Dout corresponding to Iout is obtained by subtracting the offset corresponding to Iref from the searched trial value Nt.

  Here, a transistor for obtaining an output current can be freely selected from a group of transistors constituting the translinear loop. For example, in the circuit configurations of FIGS. 6 and 9, the input current is supplied to Q1 to Q3 and the output current is extracted from Q4. However, the output current can be extracted from Q3 of Q1 to Q4 of the circuit. . FIG. 10 is a circuit diagram of the arithmetic circuit 112 having the configuration described above, and shows a configuration capable of four-quadrant operation, similar to the configuration of FIG. In the circuit of FIG. 10, the current source I5 and the current DAC 210 connected to the emitter of Q4 in the circuit of FIG. 9 are connected to the emitter of Q3, and the current source connected to the emitter of Q3 in the circuit of FIG. I3 is connected to the emitter of Q4. Also in this circuit, the potential comparison circuit 212 is connected between the emitters of Q2 and Q4, and the control circuit 214 is based on the output of the potential comparison circuit 212 and is a trial value corresponding to the potential equilibrium state between the emitters of Q2 and Q4. By searching for Nt, a calculated value Dout representing the current component Iout in the output transistor Q3 can be obtained.

  As described above, the synchronous detection circuit 72 having the effects of the present invention described with reference to the circuit of FIG. 6 can also be realized by the configurations of FIGS.

  In addition, this invention is not limited to embodiment mentioned above, A various deformation | transformation is possible. For example, although the arithmetic circuit 112 in FIGS. 6, 9, and 10 has been described using an npn transistor formed on an n-type substrate, a pnp transistor is similarly formed on a p-type substrate using a CMOS process. The arithmetic circuit 112 can be formed using the pnp transistor.

  The arithmetic circuit 112 is merely an example of an arithmetic circuit to which the present invention is applied. For example, the present invention can also be applied to an arithmetic circuit having a configuration for performing other analog operations. For example, the number of transistors constituting the translinear loop may be four or more.

  FIG. 11 is a schematic circuit diagram of another example of the arithmetic circuit according to the embodiment of the present invention. Since the arithmetic circuit 260 has a configuration similar to that of the arithmetic circuit 112 shown in FIG. 6, the same components as those in the circuit of FIG. 6 are denoted by the same reference numerals, and the differences will be mainly described below. In this arithmetic circuit 260, Q1 and Q2 are input transistors, and Q3 and Q4 are output transistors. An input current Ix is supplied to the emitter of the input transistor Q1, and an input current Iy is supplied to the emitter of Q2.

  A current DAC 210 is connected to the emitters of the output transistors Q3 and Q4. The current DAC 210 receives the trial value Nt from the control circuit 214 and generates two systems of the same trial current It.

The translinear loop to be simulated by the quasi-translinear loop of the arithmetic circuit 260 is
Iout ² = Ix ・ Iy
That is, an operation for obtaining the square root of the product of Ix and Iy and outputting it as Iout is expressed. The arithmetic circuit 260 configured for this calculation can obtain and output an arithmetic value Dout representing Iout in the same manner as the arithmetic circuit 112 shown in FIG.

  30 gyroscope, 32 sensor element, 34 drive circuit, 36 detection circuit, 40 transducer, 42, 44 drive electrode, 46, 48 detection electrode, 50 I / V conversion circuit, 52 amplification unit, 54 variable gain amplification circuit, 56 AGC unit, 58 reference voltage generation circuit, 70 detection amplification unit, 72 synchronous detection circuit, 76 LPF, 78 output terminal, 88 control terminal, 100 rms value circuit, 102 control voltage generation circuit, 104 operational amplifier, 110a, 110b, 110c , 240 V / I conversion circuit, 112, 260 arithmetic circuit, 114a, 114b sample hold circuit, 116 phase shifter, 200 n-type substrate, 202 p-well, 204 n-type region, 210 current DAC, 212 potential comparison circuit, 214 control circuit, 220 comparator, 222, 244 count 224, 246 registers, 242 hysteresis comparator, 248 balance detection circuit.

Claims (5)

The purpose of this is a loop that traces the base and emitter of an even number of transistors that are input transistors or output transistors, and is represented by a translinear loop in which the direction of the diode formed by the base-emitter junction is the same number on the loop. An arithmetic circuit that performs an operation and outputs the operation result as a digital operation value,
In the circuit having the translinear loop, the connection of the translinear loop is divided between the emitter of the transistor whose forward direction is the diode and the emitter of the transistor whose reverse direction is the reverse direction, and A modified loop circuit that has been modified to connect the potential comparison circuit;
An input current supply means connected to the emitter of the input transistor and for supplying an input current to each of which is an input of the target calculation;
A control circuit for generating a trial value for the calculated value;
Trial current generating means connected to the emitter of the output transistor and generating and supplying a trial current having a magnitude corresponding to the trial value;
Have
The potential comparison circuit compares the potentials on both sides of the divided portion and generates a comparison output according to the result,
The control circuit searches for the trial value corresponding to the potential equilibrium state at the divided location based on the comparison output and outputs the trial value as the calculated value.
An arithmetic circuit characterized by. The arithmetic circuit according to claim 1,
The potential comparison circuit includes, as the comparison output, a comparator that outputs one of two types of output states according to the magnitude relationship between the potentials on both sides of the divided portion,
The control circuit includes:
A counter that receives a clock pulse, sequentially increases or decreases the count value for each clock pulse, and outputs the count value as the trial value;
A determination circuit that detects a change in the output state of the comparison output and uses the trial value corresponding to the change as the operation value;
An arithmetic circuit comprising: The arithmetic circuit according to claim 1,
The potential comparison circuit includes, as the comparison output, a voltage-current conversion circuit that generates a current corresponding to a potential difference between both sides of the divided portion,
The control circuit includes:
A capacitor for charging the current of the comparison output;
A switch for selectively discharging the capacitor in an ON state;
A hysteresis comparator that receives the voltage between the terminals of the capacitor and switches the on / off state of the switch according to the output to alternately and repeatedly charge / discharge the capacitor;
A counter that sequentially increases or decreases the count value for each output pulse of the hysteresis comparator and outputs the count value as the trial value;
A determination circuit that determines whether the potential equilibrium state has been reached based on a period of change in the output of the hysteresis comparator, and a determination circuit that uses the trial value corresponding to the arrival time as the calculated value;
An arithmetic circuit comprising: A sensor unit that detects a target physical quantity with detection sensitivity according to the excitation intensity in an excited state, and outputs a detection signal obtained by amplitude-modulating a carrier wave of the excitation frequency;
A drive circuit for exciting and driving the sensor unit by an oscillation signal;
A detection circuit that synchronously detects the detection signal with the oscillation signal by a synchronous detection circuit, and generates an output signal corresponding to the target physical quantity from a detection output;
Have
4. The arithmetic circuit according to claim 1, wherein the synchronous detection circuit performs a target operation for performing synchronous detection by taking a product of the detection signal and the oscillation signal and outputs the calculated value. 5. And obtaining the detection output based on the calculated value,
A physical quantity sensor characterized by   A product of the detection signal and the oscillation signal by using the arithmetic circuit according to any one of claims 1 to 3 for a detection signal that is a signal obtained by amplitude-modulating a carrier wave having an intensity and frequency based on the oscillation signal. A detection circuit that performs the target calculation for synchronous detection and extracts the modulation signal of the amplitude modulation based on the calculation value.

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