JP5772776B2 - Power supply control device - Google Patents

Description

  The present invention relates to a power supply control device that controls energization to a load.

  Conventionally, a diode for reverse connection protection is provided to prevent a current from flowing to a load when a battery is reversely connected. However, a circuit provided with a diode for protection against reverse connection has a problem that a voltage drop in the diode is large when the batteries are connected in series. In order to improve this point, Patent Document 1 below proposes a circuit in which two FETs are combined so that the polarity of a parasitic diode is reversed. In this case, when the batteries are connected in series, the current branches and flows to the FET body and the parasitic diode, so that the voltage drop of the parasitic diode can be kept low.

JP-A-11-146558

A switching loss occurs when the FET switches from on to off and when the FET switches from off to on. For this reason, if the two FETs are turned on and off at the same timing, a switching loss occurs in the same way in the two FETs. For this reason, when an overload current is generated, the reverse connection protection FET having no protection circuit may be destroyed.
The present invention has been completed based on the above-described circumstances, and reduces switching loss and prevents (suppresses) FETs having no protection circuit from being destroyed even when an overload current is generated. Objective.

  The present invention is a power supply control device for controlling power supply from a power supply to a load, and is provided for an energization path to the load, and includes a first FET having a protection circuit and a reverse connection of the power supply A parasitic diode is connected in series with the first FET in the direction of reverse connection, and the second FET without a protection circuit is driven, and the first FET and the second FET are driven. A control circuit for controlling on / off of the first FET and the second FET by outputting respective signals, and when the control circuit starts to supply power to the load, the second FET The drive signal for turning on the first FET is output to the gate of the first FET after a predetermined time Ta has elapsed since the drive signal for turning on the second FET is output to the gate of the FET. Power to To stop feeding, the output of the drive signal for the first FET after a predetermined time from the stop of Tb, characterized in place of stopping the output of the drive signal for the second FET.

  The switching loss occurs when a current flows through the FET in a period in which the FET shifts from the off state to the on state in response to the input of the drive signal. Further, in response to the stop of input of the drive signal, the current is generated when a current flows during a period in which the FET shifts from the on state to the off state. Therefore, switching loss can be reduced by preventing current from flowing through the FET during the transition period from the on state to the off state and from the off state to the on state.

  Since the power supply control device of the present invention has two FETs connected in series, no current flows if the FET whose parasitic diode is reversely connected to the power supply is off. Therefore, when the timing to turn on and off both FETs is shifted and power supply to the load is started, the drive signal is input to the second FET side first, and the drive signal is input to the first FET side with a delay. To do. In this way, while the second FET is switched from the off state to the on state, the first FET is off and no current flows. Therefore, the switching loss of the second FET that does not have a protection circuit can be reduced.

  On the other hand, when stopping the power supply to the load, the output of the drive signal to the second FET is stopped after a lapse of a fixed time after the output of the drive signal to the first FET is stopped. If it does in this way, after the 1st FET switches from an ON state to an OFF state, and current stops flowing, the 2nd FET switches from an ON state to an OFF state. Therefore, the switching loss of the second FET without the protection circuit can be reduced.

The predetermined time Ta is equal to or longer than the transition period Tr in which the second FET shifts from the off state to the on state in response to the input of the drive signal. In this way, the drain current can be completely interrupted during the transition period Tr in which the second FET shifts from the off state to the on state. Therefore, the switching loss of the second FET that does not have a protection circuit can be reduced.

The predetermined time Tb is equal to or longer than the transition period Tf in which the first FET shifts from the on state to the off state in response to the stop of input of the drive signal. In this way, the drain current can be completely interrupted during the transition period Tr in which the second FET shifts from the on state to the off state. Therefore, the switching loss of the second FET that does not have a protection circuit can be reduced.

  Switching loss can be reduced, and it is possible to prevent the second FET for reverse connection protection (for preventing energization at the time of reverse power connection) having no protection circuit from being broken.

Circuit diagram of a power supply control device applied to the first embodiment Explanation of switching loss in FET The figure which shows the relationship between the on-off timing of FET11 and 21, load current, and switching loss Circuit diagram of a power supply control device applied to the second embodiment Circuit diagram showing another example of power supply control device

<Embodiment 1>
Embodiment 1 of the present invention will be described with reference to FIGS.
The present embodiment exemplifies a power supply control device 1 that controls power supply to an electrical load such as a headlight mounted on an automobile.

1. Circuit Configuration of Power Supply Control Device 1 As shown in FIG. 1, the power supply control device 1 includes an intelligent power switch 10 and a second FET 21. The intelligent power switch 10 includes a first FET 11, a protection circuit 15 that protects the first FET 11, and a control circuit 17 in the same semiconductor envelope (package).

  The first FET 11 is an N-channel, E-mode power MOSFET (insulated gate field effect transistor), which has a drain D connected to the power supply line Lv and a source S connected to the source S of the second FET 21. Yes. Similar to the first FET 11, the second FET 21 is an N-channel, E-mode power MOSFET (insulated gate field effect transistor). A load is connected between the drain D of the second FET 21 and the ground line Lg. Thus, the parasitic diode 11a of the first FET 11 has the cathode facing the power supply line Lv, whereas the parasitic diode 21a of the second FET 21 has the cathode facing the ground line Lg. The polarity of 12 is reversed.

  Thus, in this embodiment, the first FET 11 and the second FET 21 are connected in series between the in-vehicle battery B as the power source and the load R so that the polarities of the parasitic diodes 11a and 21a are opposite to each other. ing. The second FET 21 has a direction in which the parasitic diode 21a is reversely connected when the in-vehicle battery B as the power source is reversely connected, that is, the positive side of the reversely connected in-vehicle battery B, and the reverse side connection of the power source. It is provided for reverse connection protection (for backflow prevention). Further, the second FET 21 is configured not to have a protection circuit. When the polarity of the power supply voltage is positive, the first FET 11 functions as a switch that opens and closes the energization path Lr for the load R. When the polarity of the power supply voltage is negative, the second FET 21 functions as a switch that opens and closes the energization path Lr for the load R. The intelligent power switch 10 is provided with a control terminal C. A gate G of the second FET 21 is connected to the control terminal C.

  The control circuit 17 performs on / off control of the first FET 11 and the second FET 21 in response to an input signal from the outside. While the drive signal S1 is output from the control circuit 17 to the gate G, the first FET 11 is turned on. When the output of the drive signal S1 is stopped, the first FET 11 is turned off. Similarly, the second FET 21 is turned on while the drive signal S2 is being output from the control circuit 17 to the gate G through the control terminal C, and when the output of the drive signal S2 is stopped, the second FET 21 is turned off. It becomes. The protection circuit 15 is for protecting the first FET 11, and is, for example, an overcurrent protection circuit or an overheat protection circuit.

2. 1. Description of operation when battery is reversely connected As shown by a broken line in FIG. 1, when battery B is reversely connected, that is, when a negative electrode is connected to power supply line Lv and a positive electrode is connected to ground line Lg, control circuit 17 However, the second FET 21 is controlled to be turned off. Thereby, it is possible to prevent current from flowing from the reversely connected battery B to the load R. The reason is that the direction of the parasitic diode 21a is reverse (reverse connection) with respect to the reversely connected battery B, so that load current does not flow if the second FET 21 is off. . In order to turn off the second FET 21 when the battery is reversely connected, the voltage of the gate G of the second FET 21 is always fixed to the ground during reverse connection.

3. Explanation of operation at the time of power supply control for the load R When the battery B is sequentially connected as shown by a solid line in FIG. 1, the control circuit 17 turns on and off the first FET 11 and the second FET 21 to load R Control the supply of power to. That is, when the first FET 11 is turned on, the energization path Lr is closed and power can be supplied from the battery B to the load R. However, it is preferable that the second FET 21 is also turned on to reduce the power generated by the parasitic diode 21a. When the first FET 11 is turned off, the energization path Lr is opened and the power supply from the battery B to the load R can be cut off. However, if the second FET 21 is also turned off, the power consumption of the intelligent power switch can be suitably reduced.

  By the way, a switching loss occurs in the FET with the on / off switching. Specifically, when the FET is switched from OFF to ON, a switching loss occurs due to the drain current Id flowing during the period Tr during which the FET shifts from the OFF state to the ON state in response to the input of the drive signal S. Further, when switching from the on state to the off state, a switching loss occurs due to the drain current Id flowing during the period Tf during which the FET shifts from the on state to the off state in response to the stop of input of the drive signal (see FIG. 2). ).

  In order to reduce the switching loss that occurs in the second FET 21 that does not have a protection circuit, when the control circuit 17 starts supplying power to the load R, the drive signal S2 is applied to the gate G of the second FET 21. After a certain time Ta has elapsed from the output, the drive signal S1 is output to the gate G of the first FET 11. In the example of FIG. 3, the drive signal S1 is output to the gate G of the first FET 11 at a time point t2 after a predetermined period Ta from the output start time point t1 of the drive signal S2. The fixed time Ta is preferably longer than the transition period Tr in which the second FET 21 shifts from the off state to the on state in response to the input of the drive signal S2.

  As described above, when the drive signal S1 is output to the gate G of the first FET 11 after a certain time Ta (Ta> Tr) has elapsed since the drive signal S2 is output to the second FET 21, the second FET 21 During the transition period Tr in which the off state is switched to the on state, the first FET 11 is completely off. Therefore, the load current Ir (drain current) does not flow through the second FET 21 during the transition period Tr. Therefore, the switching loss of the second FET 21 having no protection circuit can be reduced.

  Further, when stopping the power supply to the load R, the control circuit 17 stops the output of the drive signal S2 to the second FET 21 after a certain time Tb from stopping the output of the drive signal S1 to the first FET 11. To do. In the example of FIG. 2, the output of the drive signal S2 to the gate G of the second FET 21 is stopped at a time t4 after a certain period Tb from the output start time t3 of the drive signal S1. The fixed time Tb is preferably longer than the transition period Tf in which the first FET 11 shifts from the on state to the off state in response to the stop of the input of the drive signal S1.

  As described above, if the output of the drive signal S2 to the second FET 21 is stopped after a certain time Tb (Tb> Tf) has elapsed since the output of the drive signal S1 to the first FET 11 is stopped, After the FET 11 is completely turned off and the load current Ir is cut off, the second FET 21 shifts from the on state to the off state. Therefore, the switching loss of the second FET 21 having no protection circuit can be reduced.

  As described above, in the power supply control device 1 according to the first embodiment, the switching loss of the second FET 21 that does not have the protection circuit can be reduced, and when the overload current occurs, the second FET 21 that does not have the protection circuit Can be destroyed.

<Embodiment 2>
Next, a second embodiment of the present invention will be described with reference to FIG. In the power supply control device 1 of the first embodiment, the polarities of the parasitic diodes 11a and 21a of the two FETs 11 and 21 are reversed by connecting the sources S to each other.

  The power supply control device 50 according to the second embodiment has a circuit configuration in which the polarities of the parasitic diodes 11a and 21a of the two FETs 11 and 21 are reversed by connecting the drains D to each other. The source S of the first FET 11 is connected to the load R, and the source S of the second FET 21 is connected to the power supply line Lg.

  Similarly to the power supply control device 1 of the first embodiment, when the battery B is reversely connected, the control circuit 17 controls the second FET 21 in the off state. Thereby, it is possible to prevent current from flowing from the reversely connected battery B to the load R.

  When the control circuit 17 starts supplying power to the load R, the control circuit 17 supplies the gate G of the first FET 11 after a predetermined time Ta has elapsed after the drive signal S2 is output to the gate G of the second FET 21. A drive signal S2 is output. On the other hand, when stopping the power supply to the load R, the output of the drive signal S2 to the second FET 21 is stopped after a predetermined time Tb after the output of the drive signal S1 to the first FET 11 is stopped. Therefore, as in the first embodiment, the switching loss of the second FET 21 that does not have the protection circuit can be reduced, and the second FET 21 that does not have the protection circuit can be prevented from being destroyed when an overload current is generated.

<Other embodiments>
The present invention is not limited to the embodiments described with reference to the above description and drawings. For example, the following embodiments are also included in the technical scope of the present invention.

  (1) In the first embodiment, the configuration in which the second FET 21 is provided separately from the intelligent power switch 10 is shown, but as shown in FIG. 5, the configuration in which the second FET 21 is incorporated in the intelligent power switch 10, The first FET 11, the second FET 21, the protection circuit 15, and the control circuit 17 may be formed in the same semiconductor envelope (package).

1 ... Power supply control device 10 ... Intelligent power switch 11 ... First FET
11a ... Parasitic diode 15 ... Protection circuit 17 ... Control circuit 21 ... Second FET
21a ... Parasitic diode B ... Battery Lv ... Power supply line Lg ... Ground line

Claims (3)

A power supply control device for controlling power supply from a power source to a load,
A first FET provided for a current path to the load and having a protection circuit;
A second FET that is connected in series to the first FET in a direction in which a parasitic diode is connected in the reverse direction when the power supply is reversely connected, and does not have a protection circuit;
A control circuit for controlling on / off of the first FET and the second FET by outputting drive signals to the first FET and the second FET, respectively,
When starting to supply power to the load, the control circuit outputs the drive signal for turning on the second FET to the gate of the second FET, and after the predetermined time Ta has elapsed, A drive signal for turning on the first FET to the gate of the FET of
When stopping the power supply to the load, the output of the drive signal to the second FET is stopped after a predetermined time Tb after the output of the drive signal to the first FET is stopped. Supply control device.   2. The power supply control device according to claim 1, wherein the predetermined time Ta is equal to or longer than a transition period Tr in which the second FET shifts from an off state to an on state in response to an input of a drive signal. .   3. The fixed time Tb is equal to or longer than a transition period Tf in which the first FET shifts from an on state to an off state in response to stop of input of a drive signal. Power supply control device.

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