JP2005217774A5 - - Google Patents
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- JP2005217774A5 JP2005217774A5 JP2004021840A JP2004021840A JP2005217774A5 JP 2005217774 A5 JP2005217774 A5 JP 2005217774A5 JP 2004021840 A JP2004021840 A JP 2004021840A JP 2004021840 A JP2004021840 A JP 2004021840A JP 2005217774 A5 JP2005217774 A5 JP 2005217774A5
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- switching
- switching means
- driving
- monitoring
- input signal
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Claims (15)
駆動側スイッチング手段のスイッチング制御用の入力信号を監視する監視手段と、
監視手段が監視する駆動側スイッチング手段をオン状態からオフ状態に遷移させる入力信号の印加時を基準に、環流側スイッチング手段を、駆動側スイッチング手段のターンオフ時間を含む時間の経過後に、オン状態となるようにスイッチング駆動するためのディレイ時間を設定するディレイ手段とを含むことを特徴とするスイッチング回路。 A driving side switching means for performing switching control for intermittently supplying a path for supplying a current supplied from a power source to a load, and a circulation side switching means for performing switching control for intermittently supplying a path for supplying a circulating current from the load, A switching circuit in which a load is connected to a connection portion between the driving side switching means and the reflux side switching means,
Monitoring means for monitoring an input signal for switching control of the driving side switching means;
With reference to the time of application of an input signal for transitioning the driving side switching means monitored by the monitoring means from the ON state to the OFF state, the circulating side switching means is set to the ON state after a lapse of time including the turn-off time of the driving side switching means. And a delay means for setting a delay time for switching driving.
前記監視手段は、該入力用抵抗を介して印加される入力信号を監視することを特徴とする請求項1または2記載のスイッチング回路。 An input signal for switching control of the driving side switching means is applied via an input resistor,
3. The switching circuit according to claim 1, wherein the monitoring means monitors an input signal applied via the input resistor.
前記ディレイ手段は、該監視用抵抗と該比較器の入力端子の入力容量とで形成される回路であることを特徴とする請求項5記載のスイッチング回路。 The monitoring means includes a monitoring resistor for guiding the input signal to the input terminal of the comparator,
6. The switching circuit according to claim 5, wherein the delay means is a circuit formed by the monitoring resistor and an input capacitance of an input terminal of the comparator.
前記負荷は該複数の接続端子を有し、各接続端子は各組合せの前記環流用スイッチング手段と前記駆動用スイッチング手段との接続部にそれぞれ接続され、
前記監視手段は、各組合せの駆動用スイッチング手段のスイッチング制御用の入力信号をそれぞれ監視することを特徴とする請求項1〜10のいずれか1つに記載のスイッチング回路。 A plurality of combinations of the driving switching means and the reflux switching means are provided,
The load has the plurality of connection terminals, and each connection terminal is connected to a connection portion between the circulating switching means and the driving switching means in each combination,
11. The switching circuit according to claim 1, wherein the monitoring unit monitors an input signal for switching control of each combination of driving switching units.
該駆動ロジックによるPWM制御でのデューティが0に近くなり、前記環流用スイッチング手段に対するスイッチング制御が逆相PWM制御となる領域では、逆相PWM制御を禁止する指定が可能な逆相PWM禁止手段とをさらに含むことを特徴とする請求項1〜13のいずれか1つに記載のスイッチング回路。 Drive logic for generating an input signal to be applied to the drive side switching means to perform PWM control; and
In the region where the duty in the PWM control by the drive logic is close to 0 and the switching control for the circulating flow switching means is the reverse phase PWM control, The switching circuit according to claim 1, further comprising:
前記スイッチング回路は、 The switching circuit is
前記駆動側スイッチング手段へのスイッチング制御用の入力信号を監視する監視手段と、 Monitoring means for monitoring an input signal for switching control to the driving side switching means;
該監視手段が監視する該駆動側スイッチング手段をオン状態からオフ状態に遷移させる入力信号の印加時を基準に、前記環流側スイッチング手段を、該駆動側スイッチング手段のターンオフ時間を含む時間の経過後に、オン状態となるようにスイッチング駆動するためのディレイ時間を設定するディレイ手段とを備えることを特徴とする電動式パワーステアリングの制御装置。 With reference to the time of application of an input signal for transitioning the drive-side switching means monitored by the monitoring means from an on state to an off-state, the reflux-side switching means is moved after a time period including a turn-off time of the drive-side switching means. And a delay means for setting a delay time for switching driving so as to be in an on state.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004021840A JP2005217774A (en) | 2004-01-29 | 2004-01-29 | Switching circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004021840A JP2005217774A (en) | 2004-01-29 | 2004-01-29 | Switching circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005217774A JP2005217774A (en) | 2005-08-11 |
JP2005217774A5 true JP2005217774A5 (en) | 2007-03-15 |
Family
ID=34905347
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004021840A Pending JP2005217774A (en) | 2004-01-29 | 2004-01-29 | Switching circuit |
Country Status (1)
Country | Link |
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JP (1) | JP2005217774A (en) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7477082B2 (en) * | 2007-05-15 | 2009-01-13 | Freescale Semiconductor, Inc. | Method and circuit for driving H-bridge that reduces switching noise |
JP2011250603A (en) * | 2010-05-27 | 2011-12-08 | Jtekt Corp | Motor controller and electric power steering device |
JP6307829B2 (en) * | 2013-10-04 | 2018-04-11 | セイコーエプソン株式会社 | Circuit device and electronic device |
DE112016007541T5 (en) * | 2016-12-22 | 2019-09-19 | Mitsubishi Electric Corporation | Semiconductor device, inverter and automobile |
CN110431429B (en) * | 2017-03-14 | 2022-02-22 | 日本电产株式会社 | Power semiconductor switching element damage prediction device, power semiconductor switching element damage prediction method, AC-DC converter, DC-DC converter |
WO2023188626A1 (en) * | 2022-03-28 | 2023-10-05 | ローム株式会社 | Drive circuit and drive device |
WO2023209966A1 (en) * | 2022-04-28 | 2023-11-02 | 国立大学法人東京大学 | Gate drive device, and gate drive system |
WO2024047991A1 (en) * | 2022-09-01 | 2024-03-07 | ローム株式会社 | Switch drive device and inverter circuit |
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2004
- 2004-01-29 JP JP2004021840A patent/JP2005217774A/en active Pending
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