WO2024047991A1

WO2024047991A1 - Switch drive device and inverter circuit

Info

Publication number: WO2024047991A1
Application number: PCT/JP2023/020984
Authority: WO
Inventors: 燦栄二ノ宮; 沙慧杉本
Original assignee: ローム株式会社
Priority date: 2022-09-01
Filing date: 2023-06-06
Publication date: 2024-03-07

Abstract

A switch drive device 100 comprises: an upper driver 110H that switches an upper switch of a power circuit 200 on/off by receiving input of an upper control signal HS and outputting a upper drive signal HG; a lower driver 110L that switches a lower switch of the power circuit 200 on/off by receiving input of a lower control signal LS and outputting a lower drive signal LG; a first detection circuit 120L that detects falling of a switch voltage which appears at a connection node between the upper switch and the lower switch after the upper control signal HS has been switched to an off logic level (for example, a low level) and that generates a first detection signal S16; and a first control circuit 130L that switches the lower control signal LS to an on logic level (for example, a high level) after at least a first delay time has elapsed, using the first detection signal S16 as a trigger.

Description

Switch drive device, inverter circuit

The present disclosure relates to a switch drive device and an inverter circuit using the same.

In a switch drive device that turns on/off the upper switch and lower switch of a half-bridge output stage or full-bridge output stage in a complementary manner, there is a dead time in which both the upper switch and the lower switch are turned off to prevent through current. (=simultaneous ON prevention period) is provided.

Incidentally, Patent Document 1 can be mentioned as an example of the conventional technology related to the above.

Japanese Patent Application Publication No. 2007-143262

However, in the conventional switch drive device, there is room for consideration regarding the dead time setting method.

For example, the switch driving device disclosed herein includes an upper driver configured to receive an input of an upper control signal and output an upper drive signal to turn on/off an upper switch of a power circuit. a lower driver configured to receive a lower control signal and output a lower drive signal to turn on/off a lower switch of the power circuit; and the upper control signal is at an off logic level. After switching, the switch voltage appearing at the connection node between the upper switch and the lower switch has fallen, the switch current flowing through the upper switch has fallen, or the upper drive signal has reached an off logic level. a first detection circuit configured to generate a first detection signal by detecting that the first detection signal has been switched to the lower side control signal; a first control circuit configured to switch to an on logic level.

Note that other features, elements, steps, advantages, and characteristics will become clearer from the detailed description and accompanying drawings that follow.

According to the present disclosure, it is possible to provide a switch driving device that can appropriately set dead time, and an inverter circuit using the same.

FIG. 1 is a diagram showing an example of the configuration of an inverter circuit. FIG. 2 is a diagram showing a general method for setting dead time. FIG. 3 is a diagram showing an example of the configuration of a power circuit. FIG. 4 is a diagram showing an example of a module configuration. FIG. 5 is a diagram showing an equivalent circuit of the module as seen from the switch driving device. FIG. 6 is a diagram illustrating a new dead time setting method (for example, under heavy load). FIG. 7 is a diagram showing a new dead time setting method (for example, when the load is light). FIG. 8 is a diagram showing a first embodiment (outline) of a switch driving device. FIG. 9 is a diagram showing a first embodiment (simplified) of the switch driving device. FIG. 10 is a diagram showing the first embodiment (details) of the switch driving device. FIG. 11 is a diagram showing the dead time setting operation in the first embodiment. FIG. 12 is a diagram showing a second embodiment (outline) of the switch driving device. FIG. 13 is a diagram showing a second embodiment (simplified) of the switch driving device. FIG. 14 is a diagram showing the second embodiment (details) of the switch driving device. FIG. 15 is a diagram showing the dead time setting operation in the second embodiment. FIG. 16 is a diagram showing a third embodiment (outline) of a switch driving device. FIG. 17 is a diagram showing a third embodiment (simplified) of the switch driving device. FIG. 18 is a diagram showing the third embodiment (details) of the switch driving device. FIG. 19 is a diagram showing the dead time setting operation in the third embodiment.

<Inverter circuit>
FIG. 1 is a diagram showing an example of the configuration of an inverter circuit. The inverter circuit 1 of this configuration example is a type of power converter that receives input of DC power from a DC power supply 2 and outputs AC power to a load 3. Referring to the figure, the inverter circuit 1 includes a switch drive device 100 and a power circuit 200.

The switch driving device 100 is a semiconductor device (so-called gate driver IC [integrated circuit]) for driving the power circuit 200.

The power circuit 200 receives a gate drive signal from the switch drive device 100 and outputs AC power to the load 3. Referring to the figure, power circuit 200 includes transistors Q1 to Q4. Transistors Q1-Q4 may be SiC devices, for example.

The drain of the transistor Q1 is connected to the positive terminal of the DC power supply 2. The source of transistor Q1 is connected to the first end of load 3. The gate of transistor Q1 is connected to switch driving device 100. Transistor Q1 connected in this way functions as the upper switch of the first phase forming a full-bridge output stage.

The drain of the transistor Q2 is connected to the first end of the load 3. The source of transistor Q2 is connected to the negative terminal (ground terminal) of DC power supply 2. The gate of transistor Q2 is connected to switch driving device 100. Transistor Q2 connected in this way functions as the lower switch of the first phase forming a full-bridge output stage.

The drain of the transistor Q3 is connected to the positive terminal of the DC power supply 2. The source of transistor Q3 is connected to the second end of load 3. The gate of transistor Q3 is connected to switch driver 100. Transistor Q3 connected in this way functions as the upper switch of the second phase forming a full-bridge output stage.

The drain of the transistor Q4 is connected to the second end of the load 3. The source of transistor Q4 is connected to the negative terminal (ground terminal) of DC power supply 2. The gate of transistor Q4 is connected to switch driving device 100. Transistor Q4 connected in this way functions as the lower switch of the second phase forming a full-bridge output stage.

Note that body diodes D1 to D4 are attached to the transistors Q1 to Q4, respectively, with the drains of the transistors Q1 to Q4 serving as cathodes, and the sources of the transistors Q1 to Q4 serving as anodes.

By the way, when the load 3 connected to the inverter circuit 1 is an inductive load (such as a motor coil), the normal current increases due to the induced electromotive force of the load 3 immediately after all of the transistors Q1 to Q4 are turned off. A return current may flow in the opposite direction.

For example, consider a case where transistors Q1 and Q4 are both in an on state, and transistors Q2 and Q3 are both in an off state. In this case, in the power circuit 200, a normal current flows through a current path L1 from the positive end of the DC power supply 2 to the negative end of the DC power supply 2 via the transistor Q1, the load 3, and the transistor Q4.

Next, consider a case where both transistors Q1 and Q3 are switched to the off state from the state where the above-mentioned normal current is flowing. In this case, in the power circuit 200, a return current flows through a current path L2 from the negative end of the DC power supply 2 to the positive end of the DC power supply 2 via the body diode D2, the load 3, and the body diode D3.

Although not shown in the drawing, when the transistors Q2 and Q3 turn off, a current flows back through the current path from the negative end of the DC power supply 2 to the positive end of the DC power supply 2 via the body diode D4, the load 3, and the body diode D1. Current can flow.

Therefore, in the switch driving device 100, it is important that the dead time DT (=simultaneous on prevention period) for turning off both the upper switch and the lower switch is appropriately set.

<Dead time setting method (general)>
FIG. 2 is a diagram showing a general method of setting dead time DT. In this figure, in order from the top, the gate-source voltage Vgs (Q1) of the transistor Q1, the drain-source current Ids (Q1) of the transistor Q1, the drain-source voltage Vds (Q1) of the transistor Q1, and The gate-source voltage Vgs(Q2) of transistor Q2 is depicted.

In the general dead time setting method, at time t101, the gate-source voltage Vgs (Q1) of transistor Q1 changes from high level (=on logic level of transistor Q1) to low level (=off logic level of transistor Q1). The measurement of the dead time DT is started at the timing when the dead time DT starts to decrease.

Note that at this point, the gate-source voltage Vgs (Q1) of the transistor Q1 has not fallen below the plateau voltage Vp. Therefore, transistor Q1 still remains on. That is, the drain-source current Ids(Q1) of the transistor Q1 continues to flow as before time t101. Further, the drain-source voltage Vds (Q1) of the transistor Q1 is maintained at approximately 0V.

At time t102, when the measurement of dead time DT is completed, the gate-source voltage Vgs (Q2) of transistor Q2 changes from a low level (=off logic level of transistor Q2) to a high level (=on logic level of transistor Q1). ) begins to rise towards.

By the way, the gate-source voltage Vgs (Q1) of the transistor Q1 has a slow falling speed during the transition from the high level to the low level (near the plateau voltage Vp). Therefore, if the above dead time DT is short, as shown at time t103, the gate-source voltage Vgs(Q2) of the transistor Q2 increases before the drain-source current Ids(Q1) of the transistor Q1 reaches 0A. The plateau voltage Vp is reached. As a result, both transistors Q1 and Q2 are turned on, so that an excessive through current may flow.

Note that although not shown in the drawings, a through current may flow in the transistors Q3 and Q4 with the same behavior as described above.

FIG. 3 is a diagram showing an example of the configuration of the power circuit 200. Power circuit 200 of this configuration example includes

modules

210 and 220.

The module 210 includes the aforementioned transistors Q1 and Q2 and forms the first phase of a full-bridge output stage. Module 220 includes the aforementioned transistors Q3 and Q4 and forms the second phase of the full-bridge output stage.

The transistor Q1 includes three unit transistors Q1a, Q1b, and Q1c connected in parallel between the positive end of the DC power supply 2 and the first end of the load 3. Body diodes D1a, D1b and D1c are associated with unit transistors Q1a, Q1b and Q1c, respectively.

The transistor Q2 includes three unit transistors Q2a, Q2b, and Q2c connected in parallel between the first end of the load 3 and the negative end of the DC power supply 2. Body diodes D2a, D2b and D2c are associated with unit transistors Q2a, Q2b and Q2c, respectively.

Transistor Q3 includes three unit transistors Q3a, Q3b, and Q3c connected in parallel between the positive end of DC power supply 2 and the second end of load 3. Body diodes D3a, D3b and D3c are associated with unit transistors Q3a, Q3b and Q3c, respectively.

Transistor Q4 includes three unit transistors Q4a, Q4b, and Q4c connected in parallel between the second end of load 3 and the negative end of DC power supply 2. Body diodes D4a, D4b and D4c are associated with unit transistors Q4a, Q4b and Q4c, respectively.

FIG. 4 is a diagram showing an example of the configuration of the module 210. As shown in this figure, the unit transistors Q1a to Q1c and Q2a to Q2c have connections between their respective source pads and the metal frame, between their respective gate pads and the metal frame, and between their respective source pads. , a large number of wires are bonded.

Although not illustrated again, the module 220 has the same configuration as the module 210. Therefore, the module 220 can be understood by replacing the unit transistors Q1a to Q1c and Q2a to Q2c in the figure with unit transistors Q3a to Q3c and Q4a to Q4c, respectively.

FIG. 5 is a diagram showing an equivalent circuit of the module 210 (or 220) as seen from the switch driving device 100. As shown in this figure, when viewed from the switch driving device 100, the module 210 includes a gate resistor Rg and N unit transistors (according to FIGS. 3 and 4, three unit transistors Q1a to Q1c or Q2a to Q2c) can be understood as an RC time constant circuit formed by the respective input capacitance Ciss.

That is, the input capacitance (=combined capacitance value) of the module 210 seen from the switch driving device 100 is Ciss×N. Therefore, the greater the number N of unit transistors in parallel forming each of the transistors Q1 and Q2, the longer the discharge time of the input capacitance Ciss×N becomes, and as a result, the fall of the gate-source voltage Vgs becomes slower.

Therefore, under the constraint that the freewheeling current can only flow through the module 210 for a short time (for example, 500 ns), if the dead time DT described above is set to a short time (for example, 2 μs), the transistors Q1 and Q2 The risk of simultaneous on-on will increase.

<Dead time setting method (new)>
6 and 7 are diagrams each showing a new method of setting the dead time DT. In each figure, from the top, the gate-source voltage Vgs (Q1) of the transistor Q1, the drain-source current Ids (Q1) of the transistor Q1, and the drain-source voltage Vds (Q1) of the transistor Q1 are shown. Each is depicted.

Note that FIG. 6 shows behavior under heavy load, for example. Further, FIG. 7 shows behavior under light load, for example. Focusing on the off time α until the gate-source voltage Vgs (Q1) of the transistor Q1 falls below the plateau voltage Vp, in FIG. 6, α=Tp1 (for example, Tp1=1 μs), and in FIG. 7, α=Tp2 (for example, Tp2=2μs).

At time t201, the gate-source voltage Vgs (Q1) of transistor Q1 begins to decrease from high level to low level. However, at this point, the gate-source voltage Vgs (Q1) of the transistor Q1 has not fallen below the plateau voltage Vp. Therefore, transistor Q1 still remains on. In other words, the drain-source current Ids(Q1) of the transistor Q1 continues to flow as before time t201. Further, the drain-source voltage Vds (Q1) of the transistor Q1 is maintained at approximately 0V.

At time t202 or t202', when the gate-source voltage Vgs(Q1) of the transistor Q1 falls below the plateau voltage Vp, the drain-source current Ids(Q1) of the transistor Q1 begins to decrease. Further, the drain-source voltage Vds (Q1) of the transistor Q1 begins to rise.

Therefore, in the new dead time setting method, for example, when the rise of the drain-source voltage Vds (Q1) of the transistor Q1 or the fall of the drain-source current Ids (Q1) of the transistor Q1 is detected, , time measurement of delay time Td (for example, 500 ns) is started.

Thereafter, at time t203, when the measurement of the delay time Td is completed, the gate-source voltage Vgs (Q2) of the transistor Q2 (not shown) begins to rise from the low level to the high level.

With the series of dead time setting methods described above, an appropriate dead time DT (=α+Td) is always variably secured according to the off time α of the transistor Q1. Therefore, even if the off time α of the transistor Q1 becomes longer due to a change in the output current flowing through the load 3, it is difficult for the transistors Q1 and Q2 to turn on at the same time. Therefore, generation of excessive through current is prevented.

Below, we will propose an embodiment for implementing the novel setting method of dead time DT described above.

<First embodiment>
FIG. 8 is a diagram showing a first embodiment (outline) of the switch driving device 100. In particular, this figure depicts functional blocks of the switch driving device 100 in the first embodiment.

The switch driving device 100 of this embodiment includes an upper driver 110H, a lower driver 110L,

detection circuits

120L and 120H, and control

circuits

130L and 130H.

The upper driver 110H receives the upper control signal HS from the control circuit 130H and amplifies it to generate the upper drive signal HG. Then, the upper driver 110H outputs the upper drive signal HG to the power circuit 200 to turn on/off the transistor Q1 (or the transistor Q3, hereinafter the same) of the power circuit 200.

The lower driver 110L receives the lower control signal LS from the control circuit 130L and amplifies it to generate the lower drive signal LG. Then, the lower driver 110L outputs the lower drive signal LG to the power circuit 200 to turn on/off the transistor Q2 (or the transistor Q4, hereinafter the same) of the power circuit 200.

The detection circuit 120L (=corresponding to the first detection circuit) detects that the transistor Q1 actually transitions to the off state after the upper control signal HS is switched to low level (=off logic level), and outputs the detection signal S16. (=corresponding to the first detection signal) is generated.

For example, the detection circuit 120L detects that the switch voltage Vsw appearing at the connection node between the transistor Q1 and the transistor Q2 falls, and generates the detection signal S16.

Note that the fall of the switch voltage Vsw can be understood as a fall of the drain-source voltage Vds (Q2) of the transistor Q2 or a rise of the drain-source voltage Vds (Q1) of the transistor Q1.

The control circuit 130L uses the detection signal S16 as a trigger to switch the lower control signal LS to a high level (=on logic level) after at least a delay time Td1 (=corresponding to the first delay time) has elapsed. That is, the control circuit 130L adjusts the on-timing of the lower driver 110L by applying appropriate delay processing to the detection signal S16.

The detection circuit 120H (=corresponding to a second detection circuit) detects that the transistor Q2 actually transitions to the off state after the lower control signal LS is switched to low level (=off logic level), and outputs a detection signal. S12 (=corresponding to the second detection signal) is generated.

For example, the detection circuit 120H detects that the lower drive signal LG has switched to a low level (=off logic level) and generates the detection signal S12.

Note that the fall of the lower drive signal LG can be understood as the fall of the gate-source voltage Vgs (Q2) of the transistor Q2.

The control circuit 130H uses the detection signal S12 as a trigger and switches the upper control signal HS to a high level (=on logic level) after at least a delay time Td2 (=corresponding to the second delay time) has elapsed. That is, the control circuit 130H adjusts the on-timing of the upper driver 110H by applying appropriate delay processing to the detection signal S12.

FIG. 9 is a diagram showing a first embodiment (simplified) of the switch driving device 100. In particular, this figure simply depicts the internal configuration of some of the functional blocks in FIG. 8 mentioned earlier.

The upper driver 110H receives the upper control signal HS from the control circuit 130H and outputs the upper drive signal HG to the gate of the transistor Q1. The transistor Q1 is turned on when the upper drive signal HG is at a high level, and is turned off when the upper drive signal HG is at a low level.

The lower driver 110L receives the lower control signal LS from the control circuit 130L and outputs the lower drive signal LG to the gate of the transistor Q2. The transistor Q2 is turned on when the lower drive signal LG is at a high level, and turned off when the lower drive signal LG is at a low level.

The detection circuit 120L monitors the switch voltage Vsw to detect the fall of the drain-source voltage Vds (Q2) of the transistor Q2 (and the rise of the drain-source voltage Vds (Q1) of the transistor Q1). A detection signal S16 is generated.

The detection circuit 120H generates the detection signal S12 by monitoring the lower drive signal LG and detecting the fall of the gate-source voltage Vgs (Q2) of the transistor Q2.

The control circuit 130L receives the detection signal S16 from the detection circuit 120L and outputs the lower control signal LS to the lower driver 110L. In accordance with this figure, the control circuit 130L includes a control section 131L, a delay section 132L, and an AND gate 133L.

The control unit 131L (=corresponds to the first control unit) generates the control signal S15 (=corresponds to the first control signal).

The delay unit 132L (=corresponding to a first delay unit) delays the detection signal S16 by the delay time Td1 to generate a delayed signal S17 (=corresponding to a first delay signal).

The AND gate 133L (corresponding to the first calculation section) performs an AND operation on the control signal S15 and the delay signal S17 to generate an AND signal S18. The AND signal S18 becomes a high level when both the control signal S15 and the delay signal S17 are at a high level, and becomes a low level when at least one of the control signal S15 and the delay signal S17 is at a low level. The AND signal S18 is output to the lower driver 110L as the lower control signal LS.

The control circuit 130H receives the detection signal S12 from the detection circuit 120H and outputs the upper control signal HS to the upper driver 110H. In accordance with this figure, the control circuit 130H includes a control section 131H, a delay section 132H, and an AND gate 133H.

The control unit 131H (=corresponding to a second control unit) generates a control signal S11 (=corresponding to a second control signal).

The delay unit 132H (=corresponding to a second delay unit) delays the detection signal S12 by the delay time Td2 to generate a delayed signal S13 (=corresponding to a second delay signal). Note that the delay time Td2 may be the same value as the delay time Td1 (for example, 500 ns).

The AND gate 133H (corresponding to a second calculation unit) performs a logical product operation on the control signal S11 and the delayed signal S13 to generate a logical product signal S14. The AND signal S14 becomes high level when both the control signal S11 and the delayed signal S13 are high level, and becomes low level when at least one of the control signal S11 and the delayed signal S13 is low level. The AND signal S14 is output to the upper driver 110H as the upper control signal HS.

FIG. 10 is a diagram showing the first embodiment (details) of the switch driving device 100. In particular, this figure depicts in detail the internal configuration of the functional blocks in FIGS. 8 and 9 previously mentioned.

The detection circuit 120H includes a comparator CMP1.

Comparator CMP1 generates a detection signal S12 by comparing the lower drive signal LG input to the inverting input terminal (-) and a predetermined threshold voltage V11 input to the non-inverting input terminal (+). . Therefore, the detection signal S12 becomes a low level when the lower drive signal LG is higher than the threshold voltage V11, and becomes a high level when the lower drive signal LG is lower than the threshold voltage V11.

Note that at a change point where the logic level of the lower drive signal LG switches, a high frequency component is superimposed on the lower drive signal LG. Therefore, it is desirable that the threshold voltage V11 is set to an appropriate value so that the comparator CMP1 is unlikely to malfunction. For example, when the lower drive signal LG is pulse-driven between 5V and 0V, the threshold voltage V11 may be set to 2V.

The detection circuit 120L includes resistors R1 and R2 and a comparator CMP2.

The first end of the resistor R1 is connected to the application end of the switch voltage Vsw. The second end of the resistor R1 and the first end of the resistor R2 are both connected to the application end of the divided voltage V12. A second end of the resistor R2 is connected to a ground terminal. The resistors R1 and R2 connected in this manner function as a voltage dividing circuit that divides the switch voltage Vsw to generate a divided voltage V12 (=Vsw×R2/(R1+R2)). Note that if the switch voltage Vsw is within the input dynamic range of the comparator CMP2, the resistors R1 and R2 may be omitted.

The comparator CMP2 generates the detection signal S16 by comparing the divided voltage V12 input to the inverting input terminal (-) and the threshold voltage V13 input to the non-inverting input terminal (+). Therefore, the detection signal S16 becomes a low level when the divided voltage V12 is higher than the threshold voltage V13, and becomes a high level when the divided voltage V12 is lower than the threshold voltage V13.

For example, the logic level of the detection signal S16 is switched at the timing when the switch voltage Vsw falls below VDD/2 (for example, 200 to 400 V) with respect to the power supply voltage VDD (for example, 400 to 800 V) applied to the positive terminal of the DC power supply 2. The voltage division ratio of the divided voltage V12 and the threshold voltage V13 may be set.

Note that at a change point where the logic level of the switch voltage Vsw changes, a high frequency component is superimposed on the switch voltage Vsw (and thus the divided voltage V12). Therefore, it is desirable that the threshold voltage V13 is set to an appropriate value so that the comparator CMP2 is unlikely to malfunction. For example, when the power supply voltage VDD is 400V and the voltage division ratio of the divided voltage V12 is 1/400, the threshold voltage V13 may be set to 0.5V.

The control circuit 130 is a functional block that includes the previously mentioned

control circuits

130L and 130H. Referring to the figure, the control circuit 130 includes a control section 131, delay

sections

132L and 132H, AND

gates

133L and 133H, and NOR

gates

134 and 135. The control circuit 130 may be, for example, an MCU (micro controller unit).

The control unit 131 is a functional unit that includes the previously mentioned

control units

131L and 131H. Referring to the figure, the control section 131 includes a delay section 131a, an AND gate 131b, and a NOR gate 131c.

The delay unit 131a delays the reference control signal S1 to generate a delayed control signal S2.

The AND gate 131b performs an AND operation on the reference control signal S1 and the delayed control signal S2 to generate the previously mentioned control signal S11. Therefore, the control signal S11 is at a high level when both the reference control signal S1 and the delayed control signal S2 are at a high level, and is at a low level when at least one of the reference control signal S1 and the delayed control signal S2 is at a low level. becomes.

The NOR gate 131c performs a NOR operation on the reference control signal S1 and the delayed control signal S2 to generate the previously mentioned control signal S15. Therefore, the control signal S15 is at a high level when both the reference control signal S1 and the delayed control signal S2 are at a low level, and is at a low level when at least one of the reference control signal S1 and the delayed control signal S2 is at a high level. becomes.

The delay unit 132L delays the detection signal S16 by a delay time Td1 (for example, 500 ns) to generate a delayed signal S17.

The delay unit 132H generates a delayed signal S13 by delaying the detection signal S12 (latch detection signal S19 in this figure) by a delay time Td2 (for example, 500 ns).

The AND gate 133L performs an AND operation on the control signal S15 and the delayed signal S17 to generate an AND signal S18 (=corresponding to the lower control signal LS).

The AND gate 133H performs an AND operation on the control signal S11 and the delayed signal S13 to generate an AND signal S14 (=corresponding to the upper control signal HS).

The first input terminal of the NOR gate 134 is connected to the application terminal of the detection signal S12. The second input terminal of the NOR gate 134 and the output terminal of the NOR gate 135 are both connected to the application terminal of the latch detection signal S19. A first input terminal of NOR gate 135 is connected to an output terminal of NOR gate 134. A second input terminal of the NOR gate 135 is connected to an application terminal of the control signal S15.

The NOR

gates

134 and 135 connected in this way function as an RS flip-flop that generates the latch detection signal S19 according to the detection signal S12 and the control signal S15. For example, the latch detection signal S19 is set to a high level at a pulse edge of the detection signal S12, and reset to a low level at a pulse edge of the control signal S15. Therefore, protection is applied so that the high levels of the detection signal S12 and the control signal S15 do not overlap.

The upper driver 110H receives the upper control signal HS and outputs the upper drive signal HG. Note that a gate resistor RgH may be connected between the output end of the upper driver 110H and the gate of the transistor Q1.

The lower driver 110L receives the lower control signal LS and outputs the lower drive signal LG. Note that a gate resistor RgL may be connected between the output end of the lower driver 110L and the gate of the transistor Q2.

FIG. 11 is a diagram showing the dead time setting operation in the first embodiment. In this figure, the control signal S11, the detection signal S12, the delayed signal S13, the AND signal S14, the control signal S15, the detection signal S16, the delayed signal S17, and the AND signal S18 are depicted in order from the top.

At time t1, when the AND signal S18 (=lower control signal LS) falls to a low level, the lower drive signal LG (not shown) begins to decrease.

Thereafter, at time t2, when the off-time α2 of the transistor Q2 has elapsed, the lower drive signal LG falls below the plateau voltage Vp and further below the threshold voltage V11. As a result, the detection signal S12 rises to high level. On the other hand, the delay signal S13 is maintained at a low level until a delay time Td2 (for example, 500 ns) elapses after the detection signal S12 rises to a high level.

Therefore, even if the control signal S11 rises to a high level at time t3, the AND signal S14 is maintained at a low level until the delayed signal S13 rises to a high level.

Thereafter, at time t4, when the delay signal S13 rises to a high level, the AND signal S14 (=upper control signal HS) also rises to a high level. That is, during the period from when the AND signal S18 falls to a low level until when the AND signal S14 rises to a high level (=times t1 to t4), the off transition of the transistor Q2 is instructed and the on transition of the transistor Q1 occurs. This corresponds to the dead time DT2 until the command is given.

Note that when the detection signal S12 falls to a low level at time t5, the delayed signal S13 falls to a low level at a time t8 after a delay time Td2. Furthermore, at time t6, when the control signal S11 falls to a low level, the AND signal S14 also falls to a low level without delay.

At time t6, when the AND signal S14 (=upper control signal HS) falls to a low level, the upper drive signal HG (not shown) begins to decrease.

Thereafter, at time t7, when the off time α1 of transistor Q1 has elapsed, the upper drive signal HG falls below the plateau voltage Vp, and furthermore, the switch voltage Vsw (and thus the divided voltage V12) falls below the threshold voltage V13. As a result, the detection signal S16 rises to high level. On the other hand, the delay signal S17 is maintained at a low level until a delay time Td1 (for example, 500 ns) has elapsed after the detection signal S16 rises to a high level.

Therefore, even if the control signal S15 rises to a high level at time t8, the AND signal S18 is maintained at a low level until the delayed signal S17 rises to a high level.

After that, at time t9, when the delay signal S17 rises to a high level, the AND signal S18 (=lower control signal LS) also rises to a high level. That is, during the period from when the AND signal S14 falls to a low level to when the AND signal S18 rises to a high level (=times t6 to t9), the off transition of the transistor Q1 is instructed and the on transition of the transistor Q2 occurs. This corresponds to the dead time DT1 until the instruction is given.

Note that when the detection signal S16 falls to a low level at time t10, the delayed signal S17 falls to a low level at time t12 after a delay time Td1. Furthermore, at time t11, when the control signal S15 falls to a low level, the AND signal S18 also falls to a low level without delay.

With the series of dead time setting methods described above, appropriate dead times DT1 (=α1+Td1) and DT2 (=α2+Td2) are always variably secured according to the off-times α1 and α2 of transistors Q1 and Q2, respectively. .

Therefore, even if the off-times α1 and α2 of transistors Q1 and Q2 become longer due to changes in the output current flowing through load 3 or variations in gate resistances RgH and RgL, transistors Q1 and Q2 simultaneously Hard to turn on. Therefore, generation of excessive through current is prevented.

<Second embodiment>
FIG. 12 is a diagram showing a second embodiment (outline) of the switch driving device 100. The switch driving device 100 of this embodiment is based on the first embodiment (FIG. 8) described above, but includes a detection circuit 120L' in place of the detection circuit 120L.

Similar to the previously described detection circuit 120L, the detection circuit 120L' detects that the transistor Q1 actually transitions to the off state after the upper control signal HS is switched to low level, and generates the detection signal S16'.

For example, the detection circuit 120L' detects that the switch current flowing through the transistor Q1, that is, the drain-source current Ids (Q1) of the transistor Q1 falls, and generates the detection signal S16'.

FIG. 13 is a diagram showing a second embodiment (simplified) of the switch driving device 100. In the switch driving device 100 of this embodiment, the detection circuit 120L' is connected between the sources of the transistors Q2 and Q4 and the ground terminal, and detects the fall of the drain-source current Ids (Q4) of the transistor Q4. , and in turn, detects the fall of the drain-source current Ids (Q1) of the transistor Q1 to generate a detection signal S16'.

FIG. 14 is a diagram showing the second embodiment (details) of the switch driving device 100. In particular, this figure depicts in detail the internal configuration of the functional blocks in FIGS. 12 and 13 mentioned above. Furthermore, as shown in this figure, a capacitor 4 may be connected between the positive and negative ends of the DC power supply 2.

The detection circuit 120L' includes a resistor R3, an amplifier AMP1, and a comparator CMP3.

The first end of the resistor R3 is connected to the source of the transistor Q2. A second end of resistor R3 is connected to a ground terminal. Note that when the transistor Q1 is in the on state and the transistor Q2 is in the off state, the drain-source current Ids (Q1) of the transistor Q1 flows from the positive terminal of the DC power supply 2 to the transistor Q1, the load 3 (and the load 3). The current flows through the illustrated transistor Q4) and resistor R3 to the negative terminal of the DC power supply 2. Therefore, the resistor R3 connected in this manner generates a detection voltage V21 (=Ids(Q1)×R3) according to the drain-source current Ids(Q1) of the transistor Q1.

The non-inverting input terminal (+) of the amplifier AMP1 is connected to the first terminal of the resistor R3. The inverting input terminal (-) of the amplifier AMP1 is connected to the second terminal of the resistor R3. The amplifier AMP1 connected in this way amplifies the detection voltage V21 appearing across the resistor R3 to generate an amplified voltage V22.

The comparator CMP3 compares the amplified voltage V22 input to the inverting input terminal (-) and the threshold voltage V23 input to the non-inverting input terminal (+) to generate a detection signal S16'. Therefore, the detection signal S16' becomes low level when the amplified voltage V22 is higher than the threshold voltage V23, and becomes high level when the amplified voltage V22 is lower than the threshold voltage V23.

FIG. 15 is a diagram showing the dead time setting operation in the second embodiment. In this figure, the control signal S11, the detection signal S12, the delayed signal S13, the AND signal S14, the control signal S15, the detection signal S16', the delayed signal S17, and the AND signal S18 are depicted in order from the top. .

The content of this figure is the same as that of the first embodiment (FIG. 11) described earlier, except that the detection signal S16 is replaced with the detection signal S16'. Focusing on the difference from the first embodiment (FIG. 11), at time t7, when the off time α1 of the transistor Q1 has elapsed, the upper drive signal HG (not shown) falls below the plateau voltage Vp. Therefore, the drain-source current Ids (Q1) of the transistor Q1 falls, and the detection voltage V22 falls below the threshold voltage V23. As a result, the detection signal S16' rises to high level.

With the dead time setting method of the second embodiment, as in the first embodiment, appropriate dead times DT1 (=α1+Td1) and DT2 are always set according to the off times α1 and α2 of the transistors Q1 and Q2, respectively. (=α2+Td2) are each variably secured.

<Third embodiment>
FIG. 16 is a diagram showing a third embodiment (outline) of the switch driving device 100. The switch driving device 100 of this embodiment is based on the first embodiment (FIG. 8) described above, but includes a detection circuit 120L'' in place of the detection circuit 120L.

Similar to the previously described detection circuit 120L, the detection circuit 120L'' detects that the transistor Q1 actually transitions to the off state after the upper control signal HS is switched to low level, and generates the detection signal S16''.

For example, the detection circuit 120L'' detects that the upper drive signal HG has switched to a low level (=off logic level) and generates the detection signal S16''.

Note that the fall of the upper drive signal HG can be understood as the fall of the gate-source voltage Vgs (Q1) of the transistor Q1.

FIG. 17 is a diagram showing a third embodiment (simplified) of the switch driving device 100. In the switch driving device 100 of this embodiment, the detection circuit 120L'' generates the detection signal S16'' by monitoring the upper drive signal HG and detecting the fall of the gate-source voltage Vgs (Q1) of the transistor Q1. do.

FIG. 18 is a diagram showing the third embodiment (details) of the switch driving device 100. In particular, this figure depicts in detail the internal configuration of the functional blocks in FIGS. 16 and 17.

The detection circuit 120L'' includes an amplifier AMP2 and a comparator CMP4.

The amplifier AMP2 has a differential voltage between the upper drive signal HG inputted to the non-inverting input terminal (+) and the switch voltage Vsw inputted to the inverting input terminal (-) (=gate-to-source voltage Vgs of the transistor Q1). (Q1)) to generate an amplified voltage V31.

The comparator CMP4 compares the amplified voltage V31 input to the inverting input terminal (-) and the threshold voltage V32 input to the non-inverting input terminal (+) to generate a detection signal S16''. Therefore, the detection signal S16'' becomes a low level when the amplified voltage V31 is higher than the threshold voltage V32, and becomes a high level when the amplified voltage V31 is lower than the threshold voltage V32.

Control circuit 130 includes NOR

gates

136 and 137 in addition to the aforementioned components 131-135.

The first input terminal of the NOR gate 136 is connected to the application terminal of the detection signal S16''. The second input terminal of the NOR gate 136 and the output terminal of the NOR gate 137 are both connected to the application terminal of the latch detection signal S20. A first input terminal of the NOR gate 137 is connected to an output terminal of the NOR gate 136. A second input terminal of the NOR gate 137 is connected to an application terminal of the control signal S11.

The NOR

gates

136 and 137 connected in this manner function as an RS flip-flop that generates the latch detection signal S20 in response to the detection signal S16'' and the control signal S11. For example, the latch detection signal S20 is " is set to high level at the pulse edge of control signal S11, and reset to low level at the pulse edge of control signal S11. Therefore, protection is applied so that the high levels of the detection signal S16'' and the control signal S11 do not overlap.

FIG. 19 is a diagram showing the dead time setting operation in the third embodiment. In this figure, the control signal S11, detection signal S12, delay signal S13, AND signal S14, control signal S15, detection signal S16'', delay signal S17, and AND signal S18 are depicted in order from the top. .

The contents of this figure are the same as the first embodiment (FIG. 11) described earlier, except that the detection signal S16 is replaced with the detection signal S16''. Focusing on the differences from the first embodiment (FIG. 11) Then, at time t7, when the off time α1 of the transistor Q1 has elapsed, the upper drive signal HG falls below the plateau voltage Vp, and furthermore, the amplified voltage V31 falls below the threshold voltage V32.As a result, the detection signal S16'' becomes high level. stand up.

With the dead time setting method of the third embodiment, the dead time DT1 ( =α1+Td1) and DT2 (=α2+Td2) are each variably secured.

<Summary>
Below, the various embodiments described above will be described in general.

For example, the switch driving device disclosed herein includes an upper driver configured to receive an input of an upper control signal and output an upper drive signal to turn on/off an upper switch of a power circuit. a lower driver configured to receive a lower control signal and output a lower drive signal to turn on/off a lower switch of the power circuit; and the upper control signal is at an off logic level. After switching, the switch voltage appearing at the connection node between the upper switch and the lower switch has fallen, the switch current flowing through the upper switch has fallen, or the upper drive signal has reached an off logic level. a first detection circuit configured to generate a first detection signal by detecting that the first detection signal has been switched to the lower side control signal; A first control circuit configured to switch to an on logic level (first configuration).

In the switch driving device according to the first configuration, the first detection circuit has a configuration (a second detection circuit) that generates the first detection signal by comparing the switch voltage or its divided voltage with a predetermined threshold voltage. configuration).

Further, in the switch driving device according to the first configuration, the first detection circuit generates the first detection signal by comparing a detection voltage corresponding to the switch current or an amplified voltage thereof with a predetermined threshold voltage. configuration (third configuration).

In the switch driving device according to the first configuration, the first detection circuit compares a differential voltage between the upper drive signal and the switch voltage or an amplified voltage thereof with a predetermined threshold voltage to detect the first detection circuit. A configuration (fourth configuration) that generates a signal may also be used.

Further, in the switch driving device according to any one of the first to fourth configurations, the first control circuit includes a first control section configured to generate a first control signal, and a first control section configured to generate a first control signal; a first delay unit configured to generate a first delayed signal by delaying by a first delay time; and a first delay unit configured to perform a logical operation on the first control signal and the first delayed signal to generate the lower control signal. A configuration (fifth configuration) including a first calculation unit configured as shown in FIG.

Further, in the switch driving device according to any one of the first to fifth configurations, detecting that the lower drive signal is switched to the off logic level after the lower control signal is switched to the off logic level; a second detection circuit configured to generate a second detection signal; and configured to switch the upper control signal to an on logic level after at least a second delay time has elapsed using the second detection signal as a trigger. The configuration may further include a second control circuit (sixth configuration).

Further, in the switch driving device according to the sixth configuration, the second detection circuit has a configuration (seventh configuration) that generates the second detection signal by comparing the lower drive signal with a predetermined threshold voltage. It's okay.

Further, in the switch driving device according to the sixth or seventh configuration, the second control circuit includes a second control section configured to generate a second control signal, and a second control section configured to generate a second control signal, and a second control section configured to generate a second control signal; a second delay unit configured to generate a second delayed signal by delaying by a time; and configured to perform a logical operation on the second control signal and the second delayed signal to generate the upper control signal. A configuration (eighth configuration) including a second calculation section may also be adopted.

Furthermore, the inverter circuit disclosed in this specification has a configuration (ninth configuration) including the switch driving device according to any of the first to eighth configurations described above and the power circuit.

In the inverter circuit according to the ninth configuration, the power circuit may be configured as a module including the upper switch and the lower switch (a tenth configuration).

In the inverter circuit according to the ninth or tenth configuration, the upper switch and the lower switch may each include a plurality of unit transistors connected in parallel (an eleventh configuration).

Furthermore, in the inverter circuit according to any one of the ninth to eleventh configurations, the upper switch and the lower switch may each be a SiC device (twelfth configuration).

<Other variations>
Note that the various technical features disclosed in this specification can be modified in addition to the above-described embodiments without departing from the gist of the technical creation. In other words, the above embodiments should be considered to be illustrative in all respects and not restrictive, and the technical scope of the present disclosure is defined by the claims, and the technical scope of the present disclosure is defined by the claims. It should be understood that all changes that come within the meaning and range of equivalence of the claims are included.

1 Inverter circuit 2 DC power supply 3 Load 4 Capacitor 100 Switch drive device

110H Upper driver

110L Lower driver 120H Detection circuit (lower Vgs)
120L detection circuit (lower Vds)
120L' detection circuit (lower Ids)
120L" detection circuit (upper Vgs)
130, 130H, 130L control circuit (MCU)
131, 131H, 131L Control section 131a Delay section 131b AND gate 131c NOR

gate

132H,

132L Delay section

133H, 133L Arithmetic section (AND gate)
134, 135, 136, 137 NOR gate 200

power circuit

210, 220 module AMP1, AMP2 amplifier input capacity CMP1, CMP2, CMP3, CMP4 comparator D1, D1A -D1C Body Diode D2, D2C body Ide D3, D3A ~ D3C Body diode D4, D4a to D4c Body diode L1 Current path (normal current)
L2 current path (reflux current)
Q1, Q3 transistor (upper switch)
Q2, Q4 transistor (lower switch)
Q1a~Q1c Unit transistor Q2a~Q2c Unit transistor Q3a~Q3c Unit transistor Q4a~Q4c Unit transistor R1, R2, R3 Resistance Rg, RgH, RgL Gate resistance

Claims

an upper driver configured to turn on/off an upper switch of the power circuit by receiving an input of an upper control signal and outputting an upper drive signal;
a lower driver configured to turn on/off a lower switch of the power circuit by receiving a lower control signal and outputting a lower drive signal;
After the upper control signal is switched to an off logic level, a switch voltage appearing at a connection node between the upper switch and the lower switch falls, a switch current flowing through the upper switch falls, or , a first detection circuit configured to detect that the upper drive signal switches to an off logic level and generate a first detection signal;
a first control circuit configured to switch the lower control signal to an on logic level after at least a first delay time has elapsed using the first detection signal as a trigger;
A switch driving device comprising:
The switch driving device according to claim 1, wherein the first detection circuit generates the first detection signal by comparing the switch voltage or its divided voltage with a predetermined threshold voltage.
The switch driving device according to claim 1, wherein the first detection circuit generates the first detection signal by comparing a detection voltage corresponding to the switch current or its amplified voltage with a predetermined threshold voltage.
The switch drive according to claim 1, wherein the first detection circuit generates the first detection signal by comparing a differential voltage between the upper drive signal and the switch voltage or an amplified voltage thereof with a predetermined threshold voltage. Device.
The first control circuit includes:
a first controller configured to generate a first control signal;
a first delay unit configured to delay the first detection signal by the first delay time to generate a first delay signal;
a first calculation unit configured to perform a logical operation on the first control signal and the first delay signal to generate the lower control signal;
The switch driving device according to any one of claims 1 to 4, comprising:
a second detection circuit configured to detect that the lower drive signal switches to an off logic level after the lower control signal switches to an off logic level and generate a second detection signal;
a second control circuit configured to switch the upper control signal to an on logic level after at least a second delay time has elapsed using the second detection signal as a trigger;
The switch driving device according to any one of claims 1 to 5, further comprising:.
The switch driving device according to claim 6, wherein the second detection circuit generates the second detection signal by comparing the lower drive signal with a predetermined threshold voltage.
The second control circuit includes:
a second controller configured to generate a second control signal;
a second delay unit configured to delay the second detection signal by the second delay time to generate a second delay signal;
a second calculation unit configured to perform a logical operation on the second control signal and the second delay signal to generate the upper control signal;
The switch driving device according to claim 6 or 7, comprising:
A switch driving device according to any one of claims 1 to 8,
the power circuit;
Including inverter circuit.
The inverter circuit according to claim 9, wherein the power circuit is a module including the upper switch and the lower switch.
The inverter circuit according to claim 9 or 10, wherein the upper switch and the lower switch each include a plurality of unit transistors connected in parallel.
The inverter circuit according to any one of claims 9 to 11, wherein the upper switch and the lower switch are each SiC devices.