JP5768762B2 - Signal input circuit - Google Patents

Description

  The present invention relates to a signal input circuit including an input state determination circuit having a differential pair in an input stage and one of transistors constituting the differential pair connected to an input terminal.

  Conventionally, in an ECU (Electronic Control Unit), which is a vehicle control unit, for example, a high or low level signal is input in response to the on / off of an external switch, the switch is turned on to prevent corrosion of the switch contact. In this case, a larger current than usual is applied (for example, see Patent Document 1).

JP 2002-343171 A

  By the way, in the above ECU or the like, in order to determine whether or not the external switch is turned on, an input signal level is compared by a built-in comparator, and an output signal of the comparator is input to an internal circuit. is there. In such a configuration, when it is assumed that a large current for preventing corrosion of the contact is passed, it is necessary to separately add a circuit for that purpose.

  FIG. 12 shows an example of an assumed configuration. The ECU 1 includes a power terminal 2, an external input terminal 3, and a ground terminal 4. The power terminal 2 is connected to a power source, and the ground terminal 4 is connected to the ground. A contact 5a of a normally open type external switch 5 is connected to the external input terminal 3. When the external switch 5 is turned on, the external input terminal 3 is brought to the ground level (low level) via the contact 5b. Become.

  The external input terminal 3 is connected to an input terminal of a comparator 6 built in the ECU 1. The comparator 6 includes a current source 7, an input differential pair 8, and a current mirror circuit 9 connected in series between the power supply terminal 2 and the ground terminal 4. The input differential pair 8 is composed of PNP transistors 8 a and 8 b, and their emitters are connected to the current source 7. The base of the PNP transistor 8a is connected to the external input terminal 3 through the resistance element 10, and a threshold voltage VT for input determination is given to the base of the PNP transistor 8b.

  The collectors of the PNP transistors 8a and 8b are connected to the collectors of the NPN transistors 9a and 9b constituting the current mirror circuit 9, respectively. The emitters of the NPN transistors 9a and 9b are connected to the ground terminal 4, and the bases are commonly connected to the collector of the NPN transistor 9b. The collector of the NPN transistor 9a is connected to the output stage of a well-known comparator (not shown).

  The contact corrosion prevention circuit 11 is connected between the power supply terminal 2 and the external input terminal 3 and includes, for example, a PNP transistor 12, a resistance element 13, a buffer circuit 14, and an output ON / OFF control unit 15. The emitter and collector of the PNP transistor 12 are connected to the power supply terminal 2 and the external input terminal 3, respectively, and the base is connected to the output ON / OFF circuit 15 via the buffer circuit 14. The resistance element 13 is connected between the power supply terminal 2 and the base of the PNP transistor 12.

In the above configuration, for example, when the external switch 5 is turned on by a user operation and the external input terminal 3 becomes a low level lower than the threshold voltage VT, a collector current flows through the NPN transistor 9a. Then, the output signal of the comparator 6 becomes high level via the output stage unit. Here, when the external switch 5 is turned on, the current I2 that flows through the base of the PNP transistor 8a is 1 / h _FE times the constant current value I1 that the current source 7 flows, and is an extremely small value.

  The output ON / OFF circuit 15 outputs a signal for turning on the PNP transistor 12 for a certain period of time, for example, every several tens of milliseconds. If the output ON / OFF circuit 15 outputs a low level signal to the base of the PNP transistor 12 during the period when the external switch 5 is turned on, the contact 5a of the external switch 5 is supplied from the power source through the PNP transistor 12. , 5b, a large current I4 flows. By this energization action, corrosion of the contacts 5a and 5b can be prevented.

  However, assuming that the contact corrosion prevention circuit 11 as described above is added according to the number of external switches 5 connected to the ECU 1, there are a plurality of external switches 5 that are generally used. Space increases, leading to an increase in size of the ECU 1 and an increase in cost.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide an input state determination circuit having a differential pair in an input stage, and to prevent contact corrosion of an external switch with a simpler configuration. An object of the present invention is to provide a signal input circuit through which a current can flow.

  According to the signal input circuit of the present invention, the input state determination circuit has a differential pair in the input stage, and one of the transistors constituting the differential pair is connected to the input terminal. When an external switch connected to the input terminal is turned on, a signal is output to the next stage circuit based on the circuit operation caused by the current flowing through the current path including the input terminal. In this configuration, a cut-off switch for cutting off the operating current flowing through the differential pair is provided, and on / off of the cut-off switch is controlled by the switch control means.

  That is, if the operating current flowing through the differential pair is cut off by the cut-off switch, the change in the input state at the input terminal is not transmitted through the differential pair, so the input state determination circuit does The operation of judging is not performed. In this state, since the differential pair transistor whose base is connected to the input terminal is equivalent to a PN junction, the PN junction becomes forward-biased when the external switch is turned on, and the normal current path including the input terminal A larger current flows than during operation. Therefore, a large current can be passed through the contacts of the external switch, and corrosion of the contacts can be prevented.

  In the configuration described above, a cutoff switch is provided in the input state determination circuit, and a large current can be passed to the contact point of the external switch through the differential pair by controlling on / off of the switch. Therefore, the number of circuit elements added to supply a current for preventing contact corrosion is reduced, and an increase in circuit scale can be suppressed.

1 is a circuit configuration diagram showing a comparator built in an ECU as a center according to the first embodiment. Timing chart of each signal Partial equivalent diagram of FIG. 1 showing the second embodiment FIG. 3 equivalent view showing the third embodiment FIG. 3 equivalent view showing the fourth embodiment FIG. 3 equivalent view showing the fifth embodiment FIG. 3 equivalent view showing the sixth embodiment FIG. 3 equivalent view showing the seventh embodiment FIG. 3 equivalent view showing the eighth embodiment FIG. 3 equivalent diagram showing the ninth embodiment. FIG. 3 equivalent diagram showing the tenth embodiment. 3 equivalent diagram showing the prior art

(First embodiment)
In the following, the same parts as those in FIG. In FIG. 1, a comparator 22 (input state determination circuit) built in the ECU 21 (control device) includes an N-channel MOSFET 23 (cut-off switch, first switch) between the collector and base of an NPN transistor 9b forming the current mirror circuit 9. And an N-channel MOSFET 24 (cut-off switch, second switch) is inserted between the base and emitter of the NPN transistor 9b.

  The gate of the N-channel MOSFET 23 is directly connected to the output terminal of an output ON / OFF circuit 25 (switch control means) instead of the output ON / OFF circuit 15, and the gate of the N-channel MOSFET 23 is connected to the output terminal as a NOT gate 26. Connected through. The output terminal of the output stage unit 27 serving as the output terminal of the comparator 22 is connected to the input terminal D of the D flip-flop 29 (latch circuit) via the analog switch 28 (gate circuit) of the next stage. It is assumed that the output stage unit 27 includes a level shift circuit that converts the high level of the signal to, for example, 5V.

  The output ON / OFF circuit 25 is composed of a logic circuit including a timer and the like. The output ON / OFF circuit 25 controls ON / OFF of the N-channel MOSFETs 23 and 24 and outputs a signal CLK1 to the control terminal of the analog switch 28. The signal CLK2 (trigger signal) is output to the clock terminal CK. The analog switch 28 and the D flip-flop 29 constitute a filter circuit (filter means) 30.

  Next, the operation of this embodiment will be described. The output ON / OFF circuit 25 uses the switching signal output to the N-channel MOSFET 23 of the comparator 22 as a signal that becomes a high level by 0.2 ms in a 20 ms cycle (see FIG. 2A). Note that the timing of each signal shown in FIG. 2 is different from the actual time scale for convenience of explanation. The output ON / OFF circuit 25 outputs signals CLK1 and CLK2 in synchronization with the switching signal (see FIGS. 2B and 2C). The signal CLK1 becomes high level before and after the intermediate phase in the period when the switching signal becomes high level, and the signal CLK2 becomes high level in the second half in the period when the signal CLK1 becomes high level.

During the period when the switching signal is at a high level, the N-channel MOSFETs 23 and 24b are turned on and off, respectively, and the comparator 22 operates normally. Therefore, when the external switch 5 is turned on by a user operation and the external input terminal 3 becomes a low level lower than the threshold voltage VT, the output signal of the comparator 22 becomes a high level. At this time, the current flowing through the base of the PNP transistor 8a is 1 / h _FE times the current I2 as described above.

  If the external switch 5 is turned on as shown in FIG. 2 (d) within a period in which the comparator 22 is operating and the signal CLK1 is at a high level, the output signal of the comparator 22 is an analog switch. 28 to the D flip-flop 29. Then, triggered by the signal CLK2, the output terminal Q (signal Q2) of the D flip-flop 29 becomes high level (see FIGS. 2F to 2H).

  On the other hand, during the period when the switching signal is at a low level, the N-channel MOSFETs 23 and 24 are turned off and on, respectively, so that the comparator 22 does not operate. In this state, since the collector of the PNP transistor 8a is open, the emitter and base PN junctions are equivalent to diodes. At this time, when the external switch 5 is turned on (see FIG. 2D), the PN junction is in a forward bias state, so that the base current I5 is substantially equal to the current I1. Accordingly, the large current I5 flows through the contacts 5a and 5b of the external switch 5, and this energization action prevents corrosion of the contacts 5a and 5b (see FIG. 2 (e)).

  As described above, according to this embodiment, when the external switch 5 that includes the input differential pair 8 and is connected to the external input terminal 3 is turned on, a current flows through the current path including the external input terminal 3. The comparator 22 that outputs a signal to the next-stage circuit based on the circuit operation according to FIG. 5 includes N-channel MOSFETs 23 and 24 for cutting off the operating current flowing through the input differential pair 8, and the output ON / OFF circuit 25 ON / OFF of the N-channel MOSFETs 23 and 24 is controlled.

  When the operating current flowing through the input differential pair 8 is cut off by the N-channel MOSFETs 23 and 24, when the external switch 5 is turned on, the external input terminal 3 is connected via the emitter and base of the PNP transistor 8a. A larger current than that during normal operation is caused to flow in the current path including the contacts 5a and 5b of the external switch 5. Thereby, corrosion of the contacts 5a and 5b can be prevented. Therefore, the number of circuit elements added to supply a current for preventing contact corrosion is reduced, and an increase in circuit scale can be suppressed.

  In this case, in order to supply the operating current, a current mirror circuit 9 composed of NPN transistors 9a and 9b is provided, an N-channel MOSFET 23 is connected between the collector and base of the NPN transistor 9b, and an N-channel MOSFET 24 is connected to the NPN transistor. The N-channel MOSFET 24 is turned on while the N-channel MOSFET 23 is turned off by connecting between the base and the emitter of the transistor 9b. As a result, when the supply of current to the bases of the NPN transistors 9a and 9b is stopped, the potential of the base can be set to a low level to prevent malfunction.

  Further, the filter circuit 30 filters the output signal of the comparator 22 so that the circuit of the next stage can be read during the period when the output ON / OFF circuit 25 turns on the N-channel MOSFET 23. Therefore, only a signal output during a period in which the comparator 22 performs a normal operation can be input to the next-stage circuit, and input of a meaningless signal can be prevented.

  In this case, the filter circuit 30 latches the analog switch 28 that passes the output signal of the comparator 22 during the period when the N-channel MOSFET 23 is turned on, and the signal output through the analog switch 28 by the signal CLK2. The output ON / OFF circuit 25 includes a flip-flop 29 and outputs a signal CLK2 within a period during which the N-channel MOSFET 23 is turned on. Therefore, the signal input to the D flip-flop 29 can be latched by the trigger signal CLK2 during the period in which the analog switch 28 is conductive, and can be read into the next stage circuit.

(Second embodiment)
Hereinafter, a different part from 1st Example is demonstrated. In the ECU 31 shown in FIG. 3, the configuration of the comparator 32 (input state determination circuit) is different from that of the first embodiment. That is, the emitters of the PNP transistors 33a and 33b (differential pair) are connected to the bases of the PNP transistors 8a and 8b, respectively. The base of the PNP transistor 33a is connected to the external input terminal 3 through the resistance element 10, and the threshold voltage VT is applied to the base of the PNP transistor 33b. The emitters of the PNP transistors 33a and 33b are connected to the power supply terminal 3 via current sources 34a and 34b.

  The collectors of the PNP transistors 33a and 33b are connected to the drains of N-channel MOSFETs 35a and 35b (cut-off switches), respectively. The sources of the N-channel MOSFETs 35 a and 35 b are connected to the ground terminal 4, and the gates are commonly connected to the gate of the N-channel MOSFET 23. The comparator output stage 27 and the filter circuit 30 are not shown.

  Next, the operation of the second embodiment will be described. The N channel MOSFETs 35 a and 35 b are turned on / off by the output ON / OFF circuit 25 together with the N channel MOSFET 23. Therefore, when the external switch 5 is turned on when the N-channel MOSFETs 23, 35a and 35b are turned off, the collectors of the PNP transistors 33a and 8a are opened, and the base current I6 of the PNP transistor 33a is substantially equal to the current I1. The current I7 of 34a is added. Accordingly, the current I6 flows through the contacts 5a and 5b of the external switch 5, and this energization action prevents corrosion of the contacts 5a and 5b.

(Third embodiment)
The third embodiment is a modification of the first embodiment. In the comparator 36 (input state determination circuit) of the third embodiment, instead of the N-channel MOSFETs 23 and 24, N-channel MOSFETs 37a and 37b (cut-off switches), collectors of the PNP transistors 8a and 8b, and NPN transistors 9a and 9b are used. It is configured to be inserted between each collector. Further, the NOT gate 26 is deleted, and the gates of the N-channel MOSFETs 37 a and 37 b are commonly connected to the output terminal of the output ON / OFF circuit 25.

  Next, the operation of the third embodiment will be described. The output ON / OFF circuit 25 outputs a switching signal in the same manner as in the first embodiment. During the period when the signal is at a high level, the N-channel MOSFETs 37a and 37b are turned on and the comparator 36 operates normally. On the other hand, since the N-channel MOSFETs 37a and 37b are turned off during the period when the switching signal is at the low level, the comparator 36 does not operate. If the external switch 5 is turned on in this state, a large current I5 flows from the emitter of the PNP transistor 8a to the base side, that is, the contacts 5a and 5b of the external switch 5, as in the first embodiment. Corrosion of the contacts 5a and 5b is prevented by the energization action.

  As described above, according to the third embodiment, the N-channel MOSFETs 37a and 37b are inserted between the collectors of the PNP transistors 8a and 8b and the collectors of the NPN transistors 9a and 9b, respectively. By turning it off, the operating current flowing through the differential pair 8 is interrupted, and the same effect as in the first embodiment can be obtained.

(Fourth embodiment)
In the ECU 41 shown in FIG. 5, the input stage is composed of a differential pair 42 composed of NPN transistors 42a and 42b. The collectors of the NPN transistors 42a and 42b are connected to the power supply terminal 2 through the drains and sources of P-channel MOSFETs 43a and 43b (cut-off switches), respectively. The gates of the P-channel MOSFETs 43a and 43b are connected to the output terminal of the output ON / OFF circuit 25 ′.

  The emitter of the NPN transistor 42a is connected to the emitters of the PNP transistors 44a and 44b, and the emitter of the NPN transistor 42b is connected to the emitters of the PNP transistors 45a and 45b. The base of the NPN transistor 42a is connected to the external input terminal 3 via the resistance element 10, and a threshold voltage VT is applied to the base of the PNP transistor 42b. In this case, the contact 5b of the external switch 5 is connected to a power source instead of the ground.

  The PNP transistors 44a and 44b and the PNP transistors 45a and 45b constitute mirror pairs 44 and 45, respectively, and their bases are commonly connected to the collectors of the PNP transistors 44a and 45a. The collectors of the PNP transistors 44a and 45a are connected to the ground via the current source 46, and the collectors of the PNP transistors 44b and 45b are connected to the collectors of the NPN transistors 9a and 9b, respectively. The above constitutes the comparator 47 (input state determination circuit).

Next, the operation of the fourth embodiment will be described. When the gates of the P-channel MOSFETs 43a and 43b are set to the high level by the output ON / OFF circuit 25 ′, the P-channel MOSFETs 43a and 43b are turned off and the collectors of the NPN transistors 42a and 42b are opened. When the external switch 5 is turned on in this state, a base current flows through the NPN transistor 42a. In this case, the base current is not 1 / h _FE times the emitter current, and is substantially the same value as the emitter current I8. Therefore, a large current can be passed through the contacts 5a and 5b of the external switch 5, and these corrosions can be prevented.

  As described above, according to the fourth embodiment, the P-channel MOSFETs 43a and 43b are connected between the power source and the comparator 47 to stop supplying the operating current to the differential pair 42. Therefore, the present invention can also be applied to a configuration in which the differential pair 42 includes NPN transistors 42a and 42b, and the external input terminal 3 becomes high level when the external switch 5 is turned on.

(5th Example)
The fifth embodiment is a modification of the third embodiment. As shown in FIG. 6, in the ECU 21B, the N-channel MOSFETs 37a and 37b are deleted, and an N-channel MOSFET 48 (cut-off switch) is connected between the emitters of the NPN transistors 9a and 9b and the ground terminal 4 instead. Thus, the comparator 36A is configured. Then, ON / OFF of the N-channel MOSFET 48 is controlled by an output ON / OFF circuit. In the case of the fifth embodiment configured as described above, the same effect as in the first and third embodiments can be obtained.

  Here, according to the configuration of the fifth embodiment, since the operation control transistor is only the N-channel MOSFET 48, there is an advantage that the number of elements is smaller than that of the third embodiment. However, in the third embodiment, since the operation current is cut off at the collector of the NPN transistor 9a directly connected to the input terminal of the output stage 27, the potential fluctuation of the collector does not occur. On the other hand, in the fifth embodiment, there is room for the collector potential of the NPN transistor 9a to fluctuate slightly when the N-channel MOSFET 48 is turned off (however, the fluctuation is absorbed in the level shift circuit). Does not affect the actual operation).

(Sixth embodiment)
The sixth embodiment is a modification of the second embodiment. In the comparator 32 of the second embodiment, four N-channel MOSFETs 23, 24, 35a, and 35b are used as shut-off switches. However, as shown in FIG. By removing the N-channel MOSFET and connecting the N-channel MOSFET 48 between the emitters of the NPN transistors 9a and 9b and the collectors of the PNP transistors 33a and 33b and the ground terminal 4 in the same manner as in the fifth embodiment, the comparator 32A Is configured. The output ON / OFF circuit 25 controls ON / OFF of the N-channel MOSFET 48. According to the sixth embodiment configured as described above, the same effect as that of the second embodiment can be obtained by using only one N-channel MOSFET 48.

(Seventh embodiment)
The seventh embodiment is a modification of the third embodiment. As shown in FIG. 8, in the ECU 41A, the P-channel MOSFET 43b is deleted and only the P-channel MOSFET 43a is used. The collector of the NPN transistor 42b is also connected to the drain of the P-channel MOSFET 43a. Also in the case of the seventh embodiment configured as described above, the same effect as that of the third embodiment can be obtained.

(Eighth embodiment)
The eighth embodiment is a modification of the first embodiment. As shown in FIG. 9, the ECU 21C is configured by replacing the current mirror circuit 9 in the ECU 21 with a current mirror circuit 49 including N-channel MOSFETs 49a and 49b, thereby forming a comparator 22A. In the case of the eighth embodiment configured as described above, the same effect as that of the first embodiment can be obtained.

(Ninth embodiment)
In the first to eighth embodiments, the comparator is used as the input state determination circuit built in the ECU. However, in the ninth embodiment, when the ECU 51 includes the operational amplifier 52 (input state determination circuit), the operational amplifier The present invention is applied to 52. A sensor 53 (for example, a current sensor) is connected to the external input terminal 3 via an external switch 5. A non-inverting input terminal of the operational amplifier 52 is connected to the external input terminal 3, and an inverting input terminal is connected to the operational amplifier 52. Connected to the output terminal. Thereby, a voltage follower is configured.

  That is, when the external switch 5 is turned on while the cutoff switch is turned on, the voltage output from the sensor 53 is input to the non-inverting input terminal of the operational amplifier 52, and the operational amplifier 52 as a voltage follower is connected to the non-inverting input terminal. A voltage corresponding to this potential is output to the next-stage circuit. The configuration of the input stage portion of the operational amplifier 52 is the same as that of the comparator 22 and the like, and the configuration of the output stage portion 27 is merely replaced with one corresponding to the operational amplifier (not shown because it is well known). Therefore, the configuration in which the cutoff switch is connected as in the first to eighth embodiments can be applied to the operational amplifier 52.

When the external switch 5 is turned on while the cutoff switch is turned off, a large current flowing out from the non-inverting input terminal of the operational amplifier 52 flows into the sensor 53, but the sensor 53 can withstand the large current flow. It is presupposed that a path for discharging current is provided on the ground side. When a configuration corresponding to the filter circuit 30 is arranged between the output terminal of the operational amplifier 52 and the next-stage circuit, a sample hold circuit may be arranged instead of the D flip-flop 29.
As described above, according to the ninth embodiment, the present invention can be applied even when the operational amplifier 52 is used as the input state determination circuit.

(Tenth embodiment)
The ECU 54 of the tenth embodiment uses an operational amplifier 52 as in the ninth embodiment, and a resistance element 55 is inserted between the inverting input terminal and the output terminal, and between the inverting input terminal and the ground terminal 4. A non-inverting amplifier circuit 57 is configured by connecting the resistance element 56. That is, when the external switch 5 is turned on while the cutoff switch is on, the voltage output from the sensor 53 is input to the non-inverting input terminal of the operational amplifier 52, and the non-inverting amplifier circuit 57 is connected to the non-inverting input terminal. The potential is amplified at an amplification factor determined by the resistance values of the resistance elements 55 and 56 and output to the next stage circuit. Also in the tenth embodiment configured as described above, the same effect as in the ninth embodiment can be obtained.

The present invention is not limited to the embodiments described above or shown in the drawings, and the following modifications or expansions are possible.
The cutoff switch may be composed of a bipolar transistor.
The filter circuit 30 may be provided as necessary.
The N-channel MOSFETs 23 and 24 in the second embodiment may be replaced with N-channel MOSFETs 37a and 37b as in the third embodiment.
Also in the embodiments other than the eighth embodiment, the current mirror circuit 9 may be constituted by a MOSFET.

  In the drawing, 3 is an external input terminal, 5 is an external switch, 8 is an input differential pair, 9 is a current mirror circuit, 22 is a comparator (input state determination circuit), 23 is an N-channel MOSFET (cut-off switch, first switch) ), 24 is an N-channel MOSFET (cut-off switch, second switch), 25 is an output ON / OFF circuit (switch control means), 28 is an analog switch (gate circuit), 29 is a D flip-flop (latch circuit), 30 Indicates a filter circuit (filter means).

Claims (8)

An input state determining circuit (22) having a differential pair (8, 42) in an input stage, and one of transistors (8a, 42a) constituting the differential pair is connected to an input terminal (3);
When the external switch (5) connected to the input terminal is turned on, the input state determination circuit is connected to the next stage circuit based on a circuit operation caused by a current flowing through a current path including the input terminal. Output signal,
An interruption switch (23, 24, 37a, 37b, 43, 48) for interrupting an operating current flowing through the differential pair;
Switch control means (25) for controlling on / off of the shut-off switch,
A signal input circuit configured to cause a larger current to flow in a current path including the input terminal than in a normal operation when the external switch is turned on in a state where the operating current is cut off. . In order to supply the operating current, a current mirror circuit (9) composed of bipolar transistors is provided,
The cutoff switch includes a first switch (23) connected between one collector and a base of the bipolar transistor;
The second switch (24) is connected between the base and emitter of the bipolar transistor and is turned on by the switch control means during a period in which the first switch (23) is turned off. The signal input circuit according to claim 1. In order to supply the operating current, a current mirror circuit (49) composed of a MOSFET is provided,
The cutoff switch includes a first switch (23) connected between one drain and gate of the MOSFET,
The second switch (24) connected between the gate and source of the MOSFET and turned on by the switch control means during a period in which the first switch is turned off. 1. The signal input circuit according to 1. A current mirror circuit for supplying the operating current;
2. The signal input circuit according to claim 1, wherein the shut-off switch (37a, 37b) is connected between the differential pair and the current mirror circuit.   2. The signal input circuit according to claim 1, wherein the shut-off switch (43, 48) is connected between the input state determination circuit and a power source or a ground.   6. A filter means (30) for filtering the output signal of the input state determination circuit so that the circuit of the next stage can be read during a period in which the operating current is flowing. The signal input circuit according to any one of the above.   7. The signal input circuit according to claim 6, wherein the switch control means outputs a trigger signal for the next stage circuit to read the output signal within a period during which the operating current flows. The input state determination circuit is configured as a comparator (22),
The filter means includes a gate circuit (28) that allows an output signal of the input state determination circuit to pass during a period in which the operating current flows;
8. The signal input circuit according to claim 7, comprising a latch circuit (29) for latching a signal output through the gate circuit by the trigger signal.

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