JP5759750B2 - Semiconductor device and semiconductor integrated circuit design method - Google Patents

Description

  The present invention relates to a semiconductor device including a semiconductor integrated circuit and a method for designing a semiconductor integrated circuit.

  Among semiconductor devices, for example, there is a semiconductor device in which a memory die called KGD (Known Good Die) is mounted on an ASIC die, and these dies are accommodated in one package.

  In the case of this type of semiconductor device, it is necessary to make a connection for power supply to the bonding pad of the memory die in addition to the connection for signal transmission with the ASIC die.

  However, if the bonding pad of the memory die and the package (package finger or bonding pad) are directly connected, the height of the bonding wire is increased, which may increase the height of the package. For this reason, the memory die and the package are not directly connected but connected via the pads of the ASIC chip. Further, when the position of the bonding pad of the memory die changes, the risk of contact between adjacent bonding wires increases.

  Here, as shown in Patent Document 1, die bonding pads are arranged in a staggered manner, that is, bonding pads at a plurality of positions where the distances from one side of the die are alternately or cyclically different. The die required for the arrangement of a plurality of necessary bonding pads is arranged, thereby increasing the number of bonding pads per unit length of one side of the die by narrowing the dimension of the IO cell in the direction along one side of the die. Reducing the dimensions of these has been done.

  When the technique of arranging bonding pads in a staggered manner is applied to an ASIC die that constitutes a semiconductor device in which a plurality of dies are accommodated in one package, the memory die and the package are connected via the ASIC die. Then, it is necessary to use the bonding pads of a plurality of IO cells of the ASIC die, which increases the number of necessary IO cells and increases the die size.

  Patent Document 2 discloses a semiconductor integrated circuit device in which a second semiconductor integrated circuit chip having a smaller size is mounted on a first semiconductor integrated circuit chip. Here, a conductive wire is formed on the first semiconductor integrated circuit chip to mediate wiring between the lead frame of the package and the second semiconductor integrated circuit chip, and one end and the other end of the conductive wire are formed. Has been proposed in which each is used as a pad for connection to the package and the second semiconductor integrated circuit chip.

  However, if the proposal of Patent Document 2 is applied to a chip in which bonding pads for IO cells are arranged in a staggered pattern, the distance between the package and one end of the conductive wire becomes large, and the bonding wire has a high height. This will return to the problem that the size may increase.

JP 2008-166495 A Japanese Patent Laid-Open No. 2003-23135

  SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor device and a method for designing a semiconductor integrated circuit that can be connected while effectively using an IO region and effectively suppressing an increase in the height of a package. .

The semiconductor device of the present invention that achieves the above object includes a plurality of first IO cells and at least one type of second IO cells, respectively, along the first side of the surface of the first semiconductor substrate. A semiconductor device including a first semiconductor integrated circuit having a first IO region in which different types of IO cells are arranged adjacent to each other,
Each of the first IO cells arranged in the first IO region has a first bonding pad arranged at a predetermined distance from the first side,
Each of the second IO cells arranged in the first IO region has a first bonding of the first IO cell at a position farther from the first side than the first bonding pad of the first IO cell . Having a third bonding pad disposed away from the pad in a direction perpendicular to its first side; and
At least one of the first IO cells includes a third bonding pad disposed adjacent to the third bonding pad in addition to the first bonding pad disposed at a predetermined distance from the first side . The first bonding is arranged at a position farther from the first side than the bonding pad and away from the third bonding pad of the second IO cell arranged adjacent to the bonding pad in a direction perpendicular to the first side. Replaced by a third IO cell having a second bonding pad connected to the pad by wiring ;
The second bonding pad is connected to the first bonding pad via an IO cell and is connected to a wiring connected to supply power to a part of the first semiconductor integrated circuit. Are also connected .

  Here, the IO cell in the present invention is a concept including not only a cell responsible for signal input and output but also a cell responsible for power input and mediation.

In addition to the first semiconductor integrated circuit, the semiconductor device of the present invention has a second IO region in which a plurality of fourth IO cells are arranged on the surface of the second semiconductor substrate. A second semiconductor integrated circuit laminated on the surface of the semiconductor substrate so as to expose the first IO region;
The fourth IO cell includes a power supply IO cell having a power supply bonding pad connected to the second bonding pad of the third IO cell by a power supply bonding wire, and the second semiconductor integrated circuit includes A first bonding pad of the three IO cells, a wiring connected to supply power to a part of the first semiconductor integrated circuit, a second bonding pad, a power bonding wire, and the power supply It may be operated by a power source supplied through the bonding pad for use.

In this case, the fourth IO cell has a signal bonding pad connected to the third bonding pad of the second IO cell arranged adjacent to the third IO cell by a signal bonding wire. It includes a signal IO cell and operates when at least one of signal transmission and reception between the first semiconductor integrated circuit and the second semiconductor integrated circuit is performed via the signal bonding wire. May be.

Further, in the semiconductor device of the present invention, the second bonding pad of the third IO cell arranged in the first IO region and the second IO cell arranged adjacent to the third IO cell . 3 bonding pads are preferably arranged so as to overlap in a direction parallel to the first side.

The semiconductor integrated circuit design method of the present invention is a method for designing a layout of a semiconductor integrated circuit using a CAD system including a cell library,
A first IO cells from a rectangular first short side of the arrangement region of a first bonding pads disposed on a position of the first distance,
The first IO cell and the first short side are positioned at a second distance greater than the first distance from the first short side of the arrangement region having the same dimensions as the first IO cell arrangement region. when placed aligned, at least one second IO having a third bonding pads spaced apart in a direction perpendicular to the first bonding pad and a first short side of the first IO cell Cell,
The first arranged in the position of the first distance from the first short side of the rectangular arrangement region whose short side length is the same as the short side length of the arrangement region of the first and second IO cells. A third of the at least one type of second IO cells from the first short side of which is larger than the second distance of the shortest second IO cell. The third bonding pad of the second IO cell and the first short side thereof when the second IO cell with the shortest second distance is aligned with the first short side at the position of the distance The second bonding pad, the first bonding pad, and the second bonding pad that are arranged apart from each other in a direction perpendicular to the first power supply are supplied to a part of the first semiconductor integrated circuit via the IO cell. third I and a wiring connected to supply And registers the cell in the cell library,
Each of the plurality of first and second IO cells and at least one third IO cell are in contact with a straight line in which the first short side of each arrangement region is parallel to one side of the die of the semiconductor integrated circuit. The long side of each placement region is in contact with the long side of the placement region of adjacent IO cells, and different types of IO cells are adjacent to each other in a direction parallel to one side of the die, and at least one first 3 IO cells are formed so that the second IO cells having the third bonding pads are adjacent to each other at the second distance shorter than the third distance, thereby forming an IO region. Features.

  According to the semiconductor device and semiconductor integrated circuit design method of the present invention, an increase in the height dimension of the package can be effectively suppressed while effectively using the IO region.

It is a schematic diagram of the semiconductor device as a comparative example. It is a mimetic diagram of a semiconductor device of one embodiment of the present invention. It is a schematic cross section of a 3rd IO cell. 1 is a block diagram showing an outline of a CAD system for carrying out an embodiment of a method for designing a semiconductor integrated circuit of the present invention. 5 is a flowchart illustrating a method for designing a semiconductor integrated circuit according to an embodiment of the present invention.

  Hereinafter, a comparative example will be described first, and then an embodiment of the present invention will be described.

  FIG. 1 is a schematic diagram of a semiconductor device as a comparative example.

  The semiconductor device 10 includes an ASIC die 20 and a memory die 30. Here, only one finger 40 on the package side is shown. The finger 40 shown here is a power supply finger that supplies power to the memory die 30.

  The ASIC die 20 has an IO region 21 in which a plurality of first IO cells 211 and a plurality of second IO cells 212 are alternately arranged along one side 201 thereof. Each of the first IO cells 211 has a bonding pad 221 disposed at a predetermined distance from one side 201 of the ASIC die 20, and each of the second IO cells 212 is a first IO cell 211. A bonding pad 222 is provided at a position farther from one side 201 of the ASIC die 20 than the bonding pad. The bonding pad 222 of the second IO cell 212 is arranged away from the bonding pad 221 of the first IO cell 211 in a direction perpendicular to one side 201 of the ASIC die 20.

  The bonding pads 221 of the first IO cells 211 and the bonding pads 222 of the second IO cells 212 are arranged so as to overlap in a direction parallel to one side 201 of the ASIC die 20 (IO cell arrangement direction). Has been.

  Here, FIG. 1 shows three first IO cells 211 and three bonding pads 221 corresponding to the three first IO cells 211. As for the second IO cell 212, FIG. 1 also shows three second IO cells 212 and three bonding pads 222 corresponding to the three second IO cells. Of these bonding pads 221, 222, the center bonding pad 221a of the three bonding pads 221 of the three first IO cells 211 and the three bonding pads 222 of the three second IO cells 212. The center bonding pad 222 a is used for supplying power to the memory die 30. Therefore, the two bonding pads 221a and 222a are connected to each other by a bridge metal 223. Of the IO cells 211 and 212 on the ASIC die shown in FIG. 1, each of the IO cells 211 and 212 except for the IO cell 211 having the bonding pad 221a and the IO cell 212 having the bonding pad 222a is used for signal input and / Or IO cell for output.

  Further, in this IO region 21, a power supply ring 23 that goes around the ASIC die 20 is formed at a position further away from the bonding pad 222 of the second IO cell 212 when viewed from one side 201 of the ASIC die 20. Yes.

  The memory die 30 is mounted on the ASIC die 20 at a position inside the IO area 21 of the ASIC die 20.

  This memory die 30 also has an IO region 31 in which a plurality of IO cells 311 are arranged along one side 301, and a bonding pad 321 is formed in each IO cell 311. In the example shown here, the bonding pads 321 provided in each IO region 311 of the memory die 30 are arranged in a line along one side 301 rather than in a staggered arrangement. In FIG. 1, three IO cells 311 are representatively shown as the IO cells 311 of the memory die 30, but the central IO cell of the three IO cells 311 is supplied with power. This is a power supply IO cell 311 a transmitted to the inside of the memory die 30. In addition, the IO cells 311 on both sides of the power supply IO cell 311a are IO cells responsible for signal input and / or output.

  Only one package-side finger 40 shown in FIG. 1 is used to supply power to the memory die 30. Therefore, the finger 40 and the bonding pad 221a are connected by the bonding wire 51, and the bonding pad 222a connected to the bonding pad 221a by the bridge metal 223 and the power supply IO on the memory die 30 are connected. The bonding pads 321 of the cells 311a are connected by bonding wires 52. The bonding pads 321 of the IO cells 311 on both sides of the power supply IO cell 311a on the memory die 30 are connected to the bonding pads 222 of the ASIC die 20 by bonding wires 53, and the semiconductor integrated circuit and the memory die 30 on the ASIC die 20 are connected. It is used for signal input / output with the upper semiconductor integrated circuit.

  In the case of the comparative example shown in FIG. 1, in order to supply one power source to the memory die 30, one first IO cell 211 and one second IO cell 212 of the ASIC die 20 are provided. It is necessary to use it. This increases the number of necessary IO cells and may increase the die size.

  Based on the above description of the comparative example, an embodiment of the present invention will be described next.

  FIG. 2 is a configuration diagram of a semiconductor device according to an embodiment of the present invention. Here, components that are common to the components of the semiconductor device of the comparative example shown in FIG. 1 are given the same reference numerals as those shown in FIG. The explanation will focus on the points.

  A semiconductor device 10 'shown in FIG. 2 includes an ASIC die 20' shown in FIG. 2 instead of the ASIC die 20 shown in FIG. The difference between the ASIC die 20 ′ and the ASIC die 20 shown in FIG. 1 is that one of the first IO cells 211 in the ASIC die 20 shown in FIG. 1 is replaced with a third IO cell 213 for power supply. This is a change.

  The third IO cell 213 is arranged adjacent to the first bonding pad 224a arranged at the same distance as the bonding pad 221 of the first IO cell 211 from one side 201 of the ASIC die 20 ′. The second IO cell 212 is further away from the one side 201 of the ASIC 20 ′ than the bonding pad 222 of the second IO cell 212, and is separated from the bonding pad 222 of the adjacent second IO cell 212 in the direction perpendicular to the first side 201. The second bonding pad 224b is disposed. That is, the second bonding pads 224b of the third IO cells 213 and the bonding pads 222 of the second IO cells 212 arranged adjacent to each other are arranged in a staggered manner.

  The first and second bonding pads 224a and 224b of the third IO cell 213 are connected to each other by wiring.

  FIG. 3 is a schematic cross-sectional view of a third IO cell.

First and second bonding pads 224a and 224b are disposed on the upper surface of the third IO cell 213, and wirings of two wiring layers M2 and M3 extend therein. In the present embodiment, the first and second bonding pads 224a, 224b are connected to each other by a wiring 261 of the wiring layers M 2.

Further, in the present embodiment, the wiring 261 of the wiring layer M 2 is one of the wiring 251 of the wiring layers M 3, is used as the power supply line to the semiconductor integrated circuit formed on the ASIC die 20 'wiring 251a In addition, they are connected via vias 271. That is, in this embodiment, the semiconductor integrated circuit formed on the ASIC die 20 ′ and the semiconductor integrated circuit on the memory die 30 are operated by the same power source from the finger 40.

  According to the semiconductor device 10 ′ of the embodiment shown in FIGS. 2 and 3, it is sufficient to use one IO cell 213 on the ASIC die 20 ′ to supply power to the memory die 30, reducing the number of necessary IO cells, This can lead to a reduction in die size. Further, as described above, the second bonding pads 224b of the third IO cells 213 and the bonding pads 222 of the second IO cells 212 arranged adjacent to each other are arranged in a staggered manner. Therefore, even when the number of bonding pads per unit length of one side of the die is increased, the bonding pads 222 of the second IO cells 212 arranged adjacent to the third IO cells 213, and the memory die There is a high possibility that the signal input / output bonding wires 53 that connect the bonding pads 321 of the IO cells 311 on both sides of the power supply IO cells 311a on the 30 will come into contact with the power supply bonding wires 51. No.

  Next, an embodiment of a semiconductor integrated circuit design method of the present invention will be described.

  FIG. 4 is a block diagram showing an outline of a CAD system for carrying out one embodiment of a method for designing a semiconductor integrated circuit of the present invention.

  The CAD system 60 includes a calculation unit 61, a storage unit 62, an operation unit 63, a display unit 64, and an input / output unit 65.

  The operation unit 63 includes a keyboard, a mouse, and the like that receive operations from the operator. In the calculation unit 61, a CAD program is executed in response to an operator operation from the operation unit 63. The storage unit 62 stores a CAD program executed by the calculation unit 61. The storage unit 62 also stores various electronic circuits on the electronic data, cells formed by combinations of a plurality of electronic circuits, and the like. The display unit 64 is responsible for displaying an image according to an instruction from the calculation unit 61. The display unit 64 displays, for example, a circuit in the middle of design or a circuit after design. The input / output unit 65 includes, for example, a communication circuit that performs communication via a LAN, a disk drive that accesses a portable storage medium such as a CD / DVD, and the like. And so on.

  The CAD system itself has been widely used conventionally, and further description thereof is omitted here.

  FIG. 5 is a flowchart showing a method for designing a semiconductor integrated circuit according to an embodiment of the present invention. This design method is executed by the CAD system 60 of FIG. 4 that has been operated by the operator.

  The flowchart shown in FIG. 5 has a step (S01) of registering in the cell library and a step (S02) of forming an IO region. In actual design, it is necessary to design not only the IO area but also the entire semiconductor integrated circuit. However, since the interest in this embodiment is only the design of the IO area of the ASIC die, Only the design of the IO area will be described.

  In the step of registering in the cell library (S01), the first IO cell, the second IO cell, and the third IO cell are registered in the cell library configured in the storage unit 62.

  Here, the first IO cell is electronic data corresponding to the first IO cell 211 shown in FIG. In other words, this first IO cell is an IO cell having a bonding pad 221 arranged at a first distance from the first short side of the rectangular arrangement region.

  The second IO cell is electronic data corresponding to the second IO cell 212 shown in FIG. The second IO cell 212 is located at a second distance greater than the first distance from the first short side of the placement region having the same dimensions as the placement region of the first IO cell 211. When the IO cell 211 and the first short side are aligned, the IO having the bonding pad 221 of the first IO cell 211 and the bonding pad 222 disposed away from the first short side in a direction perpendicular to the first short side. Cell.

  Further, the third IO cell is electronic data corresponding to the third IO cell 213 shown in FIG. The third IO cell 213 has the short side length from the first short side of the rectangular arrangement region that is the same as the short side length of the arrangement region of the first and second IO cells 211 and 212. The first IO pad 212 has a first bonding pad 224a disposed at the first distance, and the second IO cell 212 and the second IO cell 212 are disposed at a third distance greater than the second distance from the first short side. When the first short sides are aligned, the bonding pad 222 of the second IO cell 212 is separated from the second bonding pad 224b disposed in the direction perpendicular to the first short side, This is an IO cell having a wiring 261 (see FIG. 3) for connecting the bonding pad 224a and the second bonding pad 224b.

  In step S01 of FIG. 5, the first IO cell, the second IO cell, and the third IO cell are registered in the cell library in the storage unit 62.

  These IO cells may be those designed by the operator's operation or the like in the CAD system itself shown in FIG. 5, or those designed by other devices etc. are received via the input / output unit 65. There may be.

In the IO area forming step (S02) of the flowchart of FIG. 5 , an IO area is formed as follows using the first, second, and third IO cells registered in the cell library.

  That is, in this step S02, a plurality of first and second IO cells and at least one third IO cell are respectively connected to a semiconductor integrated circuit die (here, the first short side of each arrangement region). 2 is in contact with a straight line parallel to one side 201 of the ASIC die 20 ′), the long side of each placement region is in contact with the long side of the placement region of an adjacent IO cell, and one side of the die An IO region is formed by disposing different types of IO cells adjacent to each other in a direction parallel to the first and second IO cells adjacent to the at least one third IO cell.

  By forming the IO region in this way, the IO region 21 on the ASIC die 20 'shown in FIG. 2 is formed on the electronic data.

  In the above embodiment, as shown in FIG. 2, the second IO cell 212 is one type of IO cell in which the bonding pad 222 has a uniform distance from one side 201 of the ASIC die 20 ′. There may be a plurality of types of second IO cells having different distances from one side 201 of the bonding pad. That is, in the arrangement of FIG. 2, except for the third IO cell 213, the first IO cells 211 and the second IO cells 212 are arranged alternately, and the bonding pads 221 and 222 are arranged in two rows. However, when a plurality of types of second IO cells are provided, the first IO cell, one type of the second IO cell, another type of the second IO cell, etc. are arranged cyclically. In addition, one of the first IO cells among the IO cells may be replaced with the third IO cell. In that case, the second bonding pad of the third IO cell is at least one of the plurality of types of second IO cells, of the second IO cell of the type arranged adjacent to the third IO cell, Specifically, for example, one side 201 than the bonding pad of the second IO cell having a bonding pad closest to one side 201 of the ASIC die 20 ′ among the plurality of types of second IO cells. It is arrange | positioned in the position further away from.

10, 10 'Semiconductor device 20, 20' ASIC die 21, 31 IO region 23 Power supply ring 30 Memory die 40 Finger 51, 52, 53 Bonding wire 60 CAD system 201, 301 Side 211, 212, 213, 311 IO cell 221, 221a , 222, 222a, 224a, 224b, 321 Bonding pad 223 Metal 251, 251a, 261 Wiring 271 Via 311a Power supply IO cell M2, M3 Wiring layer

Claims (5)

A plurality of first IO cells and at least one type of second IO cells are arranged along the first side of the surface of the first semiconductor substrate so that different types of IO cells are adjacent to each other. A semiconductor device comprising a first semiconductor integrated circuit having a first IO region,
Each of the first IO cells disposed in the first IO region has a first bonding pad disposed at a predetermined distance from the first side,
Each of the second IO cells arranged in the first IO region is located at a position farther from the first side than the first bonding pad of the first IO cell . a third bonding pads spaced apart in a direction perpendicular from the first bonding pad to the first side, and,
At least one of the first IO cells includes a third bonding pad disposed adjacent to the third bonding pad in addition to the first bonding pad disposed at a predetermined distance from the first side . The second bonding pad of the second IO cell arranged adjacent to the first bonding pad is located farther from the first side than the first bonding pad and away from the third bonding pad in a direction perpendicular to the first side. A third IO cell having a second bonding pad connected to one bonding pad by wiring ;
The second bonding pad is connected to the first bonding pad via an IO cell and is connected to a wiring connected to supply power to a part of the first semiconductor integrated circuit. Is also connected to the semiconductor device. In addition to the first semiconductor integrated circuit, the second semiconductor substrate has a second IO region in which a plurality of fourth IO cells are arranged on the surface of the second semiconductor substrate, and the semiconductor substrate of the first semiconductor integrated circuit A second semiconductor integrated circuit laminated on the surface so as to expose the first IO region;
The fourth IO cell includes a power supply IO cell having a power supply bonding pad connected to a second bonding pad of the third IO cell by a power supply bonding wire, and the second semiconductor integrated circuit includes: A first bonding pad of the third IO cell, a wiring connected to supply power to a part of the first semiconductor integrated circuit, a second bonding pad, and the bonding wire for power supply 2. The semiconductor device according to claim 1, wherein the semiconductor device operates with power supplied through the power supply bonding pad. The fourth IO cell has a signal bonding pad having a signal bonding pad connected to a third bonding pad of a second IO cell arranged adjacent to the third IO cell by a signal bonding wire. A cell is included and operates by performing at least one of transmission and reception of signals between the first semiconductor integrated circuit and the second semiconductor integrated circuit via the signal bonding wire. The semiconductor device according to claim 2. A second bonding pad of a third IO cell disposed in the first IO region and a third bonding pad of a second IO cell disposed adjacent to the third IO cell; 4. The semiconductor device according to claim 1 , wherein the semiconductor device is disposed so as to overlap in a direction parallel to the first side . A method of designing a layout of a semiconductor integrated circuit using a CAD system having a cell library,
A first IO cell having a first bonding pad arranged at a first distance from a first short side of a rectangular arrangement region;
The first IO cell and the first short are positioned at a second distance greater than the first distance from the first short side of the arrangement region having the same dimensions as the arrangement region of the first IO cell. When arranged side by side, at least one type of first bonding pad having a first bonding pad of the first IO cell and a third bonding pad arranged away from each other in a direction perpendicular to the first short side. Two IO cells,
The first short side is disposed at the first distance from the first short side in the rectangular arrangement region whose short side is the same as the short side length of the first and second IO cell arrangement regions. A first bonding pad, and the second distance of the at least one type of second IO cells from the first short side is larger than the second distance of the shortest second IO cell. When the second IO cell with the shortest second distance is aligned with the first short side at the position of the distance 3, the third bonding pad of the second IO cell and the first A part of the first semiconductor integrated circuit through the IO cell through the second bonding pad arranged away from the short side of the first bonding pad and the first bonding pad and the second bonding pad. And a wiring for connecting to supply power to the circuit Of the IO cell registered in the cell library,
Each of the plurality of first and second IO cells and at least one third IO cell is a straight line in which the first short side of each arrangement region is parallel to one side of the die of the semiconductor integrated circuit. And the different types of IO cells are adjacent to each other in a direction parallel to one side of the die, and the long side of each of the arrangement regions is in contact with the long side of the adjacent IO cell arrangement region. In one third IO cell, the second IO cell having the third bonding pad is disposed adjacent to the second distance that is shorter than the third distance. Forming a semiconductor integrated circuit .

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