JP5744971B2 - Game machine - Google Patents

Description

The present invention is a game when a specific display resulting display result of the variable display is derived displayed in rows cormorants variable display means variable display based on the establishment of the start condition after a game medium has passed through the starting area controls advantageously specific gaming state, the probability that the particular display result is derived displayed as a display result of the variable display than when predetermined shift condition is normal gaming state based on the established improved for users The present invention relates to a gaming machine such as a pachinko gaming machine that controls to a high probability state.

  As a gaming machine, a game ball, which is a game medium, is launched into a game area by a launching device, and when a game ball wins a prize area such as a prize opening provided in the game area, a predetermined value is given to the player. There is something. Further, a variable display unit capable of variably displaying the identification information (also referred to as “fluctuation”) is provided, and a predetermined game value is obtained when the display result of the variable display of the identification information in the variable display unit becomes a specific display result. Are configured to give the player.

  The game value is the right that the state of the variable winning ball apparatus provided in the gaming area of the gaming machine becomes advantageous for a player who is easy to win, and the right for becoming advantageous for a player. In other words, or a condition for winning a prize ball is easily established.

  As a pachinko machine, either a normal gaming state (normal state: low probability state) or a high probability state (probability variation state) with a higher probability of being controlled to a specific gaming state (big hit gaming state) than the normal state There are controllable gaming machines (see, for example, Patent Document 1).

  In addition, the gaming machine described in Patent Literature 1 performs an effect that makes it difficult for the player to grasp whether the gaming state is the normal state or the probability variation state. Hereinafter, a state in which it is difficult for the player to grasp whether the state is the normal state or the probability variation state is referred to as a probability variation latent state (or a latent state). In the probability variation latent state, the actual gaming state is the normal state or the probability variation state.

  Furthermore, the gaming machine described in Patent Document 1 has a plurality of effect modes regarding effects. The difference in the effect mode is realized by the difference in the situation expressed by the image (background image or character image) displayed on the display device. When the predetermined condition is satisfied, the production mode is changed. However, when the actual gaming state is the probability variation state, the representation corresponding to the high probability variation expectation (the possibility that the actual gaming state is the probability variation state). It is easy to shift to the mode, and when the actual gaming state is the normal state, it is easy to shift to the effect mode corresponding to the low probability change expectation.

JP 2010-142503 A

  In the gaming machine described in Patent Document 1, it is possible to prevent the same production mode from continuing by changing the production mode and to prevent the production from being monotonous. However, even if the effect mode is changed, when the actual game state is the normal state (low probability state), the change is often made between the plurality of effect modes corresponding to the low probability change expectation. Then, by continuing the production based on the production mode corresponding to the low probability change expectation, the player may lose the expectation for the probability change state and stop the game.

  In view of this, the present invention, when performing an effect that makes it difficult to grasp whether the game state is a high probability state or a normal game state, can be applied to the player's high probability state even when the actual game state is the normal game state. It is an object of the present invention to provide a gaming machine that can prevent a decrease in expectation.

(1) a gaming machine according to the present invention, the starting region (e.g., the first starting winning opening 13 and second start winning hole 14) of the game media (e.g., game balls) establishment of start conditions after has passed (e.g. , Based on the fact that the total number of reserved storage is not 0, the variable display of the first special symbol and the second special symbol is not executed, and the jackpot game is not executed) line cormorant variable display means variable display Te (e.g., first special symbol display device 8a, the second special symbol display device 8b, effect display device 9) specific display resulting display result of the variable display (eg, big hit symbol ) preferred specific gaming state (e.g. for the player when the derived display controls to the jackpot gaming state), variable display than when predetermined shift condition is normal gaming state based on the established as the display result High-probability state probability is improved by the constant display result is derived displayed (e.g., probability variation state) a gaming machine to control the, whether transient control of whether to control the specific game state to the high probability state, Predetermining means for deciding before the display result of the variable display is derived and displayed (for example, in the game control microcomputer 560, the part that executes the processing of steps S61, S66, and S67) and the specific gaming state is completed. After that, the gaming state is set to a high-frequency state (for example, a short-time state) with a high frequency of entering the start-up region as compared to a low-frequency state (for example, a state that is not a short-time state) in which the game medium enters the starting region. Game state control means (for example, a part for executing the processing of step S171 in the game control microcomputer 560), and variable in the high-frequency state Continued number determination means for determining the number of executions shown to be one of a plurality of times (for example, in the game control microcomputer 560, the part that executes the processing of steps S66 and S67: the time reduction number is determined by determining the jackpot type) When determined (see FIG. 14)), in the high-frequency state and the low-frequency state shifted from the high-frequency state, the common effects (for example, the case where the gaming state is the high-probability state and the normal gaming state) Common effect executing means (for example, a portion for executing the processing of steps S887 and S8339 in the effect control microcomputer 100) for executing the probability variation latent effect and the chance mode effect), and the continuation number determining means is the gaming state. When the number of executions is controlled to a high probability state, the number of executions is reduced as compared to the case where it is not controlled to a high probability state. When the game state is a high-probability state, the common effect execution means can determine the specific game state in the low-frequency state. The common effect is executed until it is controlled (for example, in the process of step S8338 shown in FIG. 58, in the case of a probable big hit, a virtually infinite value is set in the chance mode continuation counter), and the gaming state is when the normal gaming state, in a low frequency state, perform the common effect over a long period as compared with the case of determining the smaller number of times if the remain times determining means to determine the number of executions in number of times (Fig. (Refer to 60: If the number of time reductions is a big hit, the chance mode continuation count increases overall.) , There are multiple types of common effects, and the common effect execution means is a combination of multiple types. One of the effects is performed .
Since it is configured in such a way, when performing an effect that makes it difficult to grasp whether the state is a high probability state or a normal gaming state, the player's high level is also obtained when the actual gaming state is the normal gaming state. The expectation for the probability state can be prevented from being lowered.

(2) In the gaming machine of (1), the common effect execution means executes any one of a plurality of types of common effects (for example, chance modes A, B, and C) when in a low frequency state. The common effect selection means includes a common effect selection means (for example, a part that executes the processing of steps S8333 and S8334 in the effect control microcomputer 100), and the common effect selection means includes: When the number of execution times is determined to be a large number of times (for example, 50 times), the continuation number selection means is selected at a higher rate when the gaming state is controlled to a high probability state than when it is determined to be a small number of times. Common presentations (for example, chance mode A: see FIG. 59A) may be selected at a high rate (see FIGS. 59B and 59C).
In the case of such a configuration, it is possible to maintain the player's expectation that is increased by the number of times that variable display can be performed in the high-frequency state.

(3) In the gaming machine of the above (1) or (2), the common effect execution means determines the number of variable displays that can execute the common effect in the low frequency state (for example, the effect) The control microcomputer 100 includes a portion for executing the processing of steps S8336 and S8337, and the variable display number determination means is a predetermined upper limit number of times (for example, 20) when not controlled to a high probability state. The common effect executing means ends the common effect when the variable display is executed for the number of times determined by the variable display frequency determining means (step in FIG. 57). S8309 to S8312).
In the case of such a configuration, it is possible to reduce the possibility of discouraging the player when the predetermined effect is executed for a long period of time despite the low frequency state and the predetermined effect ends. it can.

(4) In the above gaming machines (1) to (3), as the fluctuation data generated when the control is performed, information in the high probability state (for example, high probability state) indicating that the control is at least in the high probability state. Fluctuating data storage means (for example, a backup RAM) for storing data including a medium signal) and a memory capable of holding the storage contents of the fluctuation data storage means for a predetermined period even when power supply to the gaming machine is stopped The content holding means (for example, a capacitor as a backup power supply) and when the power supply is started, the high-probability state is controlled based on the fact that the information in the high-probability state is stored in the fluctuation data storage means. A high probability state signal external output means for outputting a high probability state signal indicating the presence of the signal to the outside of the gaming machine (for example, a step in the gaming control microcomputer 560). The high-probability state signal external output means outputs a high-probability state signal until a predetermined condition is satisfied after the power supply is started (for example, the first jackpot is generated). The output may be continued, and if a predetermined condition is satisfied, the output of the signal in the high probability state may be prohibited (for example, the process of step S131 shown in FIG. 31 is executed).
In such a configuration, in the gaming machine configured not to notify the high probability state, the gaming state of the gaming machine when the power supply is started can be easily grasped.
(5) In the above gaming machines (1) to (4), a player can play a predetermined game using a game medium, and a predetermined payout condition (for example, the first start winning award 13, A gaming machine that pays out game media based on the establishment of the second start winning port 14, the big winning port, and the normal winning ports 29, 30), and when a predetermined payout condition is satisfied, A payout condition establishment signal external output means (for example, a payout condition establishment signal) that externally outputs a payout condition establishment signal (for example, a winning signal) indicating that a predetermined payout condition for paying out several minutes (for example, 10 pieces) of game media is established. , The game control microcomputer 560 may include steps S1021 to S1023, S1102, and S1103.
In such a configuration, it becomes possible to accurately grasp the time when a predetermined payout condition is satisfied outside the gaming machine without increasing the control burden.

It is the front view which looked at the pachinko game machine from the front. It is the rear view which looked at the gaming machine from the back. It is a block diagram which shows the structural example of a game control board (main board). It is a block diagram which shows the circuit structural example of a payout control board. It is a block diagram which shows the circuit structural example of a relay board | substrate, an effect control board | substrate, a lamp driver board | substrate, and an audio | voice output board | substrate. It is explanatory drawing which shows the example of bit allocation of the output port in a game control means. It is explanatory drawing which shows the bit allocation example of the input port in a game control means. It is a circuit diagram which shows the internal structure of a terminal board | substrate. It is a flowchart which shows the main process which the microcomputer for game control performs. It is a flowchart which shows the process example of a hot start process. It is a flowchart which shows a 4 ms timer interruption process. It is explanatory drawing which shows each random number. It is explanatory drawing which shows a jackpot determination table. It is explanatory drawing which shows the big hit classification determination table. It is explanatory drawing which shows a fluctuation pattern table. It is explanatory drawing which shows an example of the content of an effect control command. It is a flowchart which shows an example of a prize ball process. It is explanatory drawing which shows the example of a prize ball number table. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball command output counter addition process. It is a flowchart which shows a prize ball control process. It is a flowchart which shows a prize ball counter subtraction process. It is a flowchart which shows an example of the program of a special symbol process process. It is a flowchart which shows a starting port switch passage process. It is explanatory drawing which shows the structural example of a pending | holding buffer. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a special symbol normal process. It is a flowchart which shows a fluctuation pattern setting process. It is a flowchart which shows a display result designation | designated command transmission process. It is a flowchart which shows the special symbol change process. It is a flowchart which shows a special symbol stop process. It is a flowchart which shows a big hit end process. It is explanatory drawing which shows each 2 byte buffer formed in RAM used by switch processing. It is a flowchart which shows the process example of a switch process. It is a flowchart which shows a switch normal / abnormality check process. It is a block diagram which shows the various signals output to a terminal board. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows an information output process. It is a flowchart which shows a winning timer set process. It is explanatory drawing which shows the output timing of a highly accurate middle signal. It is explanatory drawing which shows the output timing of a security signal. It is explanatory drawing which shows an example of a probability change alerting | reporting effect, an uncertain change alerting effect, and a common effect. It is a flowchart which shows the main process which CPU for production control performs. It is a flowchart which shows command analysis processing. It is a flowchart which shows command analysis processing. It is a flowchart which shows command analysis processing. It is a flowchart which shows command analysis processing. It is explanatory drawing which shows the random number which the microcomputer for production control uses. It is a flowchart which shows production control process processing. It is a flowchart which shows a fluctuation pattern command reception waiting process. It is a flowchart which shows a decoration design change start process. It is a flowchart which shows an effect determination process. It is explanatory drawing which shows a notice determination table. It is a flowchart which shows a process during decoration design change. It is a flowchart which shows a decoration design change stop process. It is a flowchart which shows a chance mode setting process. It is explanatory drawing which shows a chance mode determination table. It is explanatory drawing which shows a chance mode continuation frequency determination table. It is a flowchart which shows a big hit end effect process.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
First, the overall configuration of a pachinko gaming machine 1 that is an example of a gaming machine will be described. FIG. 1 is a front view of the pachinko gaming machine 1 as seen from the front. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to other gaming machines such as a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) that can be opened and closed with respect to the outer frame, a mechanism plate (not shown) to which mechanism parts and the like are attached, and various parts (games to be described later) attached to them. A structure including the board 6).

  On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, there are provided a surplus ball receiving tray 4 for storing game balls that cannot be accommodated in the hitting ball supply tray 3, and a hitting operation handle (operation knob) 5 for firing the hitting ball. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. In addition, a game area 7 is formed on the front surface of the game board 6 in which a game ball that has been struck can flow down.

  An effect display device 9 composed of a liquid crystal display device (LCD) is provided near the center of the game area 7. The display screen of the effect display device 9 includes an effect symbol display area for performing variable display of the effect symbol in synchronization with the variable display of the first special symbol or the second special symbol. Therefore, the effect display device 9 corresponds to a variable display device that performs variable display of effect symbols. The effect symbol display area includes a symbol display area for variably displaying, for example, three decorative (effect) effect symbols of “left”, “middle”, and “right”. The symbol display area includes “left”, “middle”, and “right” symbol display areas, but the position of the symbol display area does not have to be fixed on the display screen of the effect display device 9. Three areas of the display area may be separated. The effect display device 9 is controlled by an effect control microcomputer mounted on the effect control board. When the first special symbol display 8a is executing variable display of the first special symbol, the effect control microcomputer causes the effect display device 9 to execute the effect display along with the variable display, and the second special symbol display 8a executes the second special display. When the variable display of the second special symbol is executed on the symbol display 8b, the effect display is executed by the effect display device 9 along with the variable display, so that the progress of the game can be easily grasped. .

  Further, in the effect display device 9, symbols other than the symbol that will be the final stop symbol (for example, the middle symbol of the left and right middle symbols) have continued for a predetermined time, and the jackpot symbol (for example, the left middle right symbol is aligned with the same symbol) Stops, swings, scales, or deforms in a state that matches the symbol combination), or multiple symbols fluctuate synchronously in the same symbol, or the position of the display symbol is switched Thus, an effect performed in a state where the possibility of occurrence of a big hit (hereinafter, these states are referred to as reach states) before the final result is displayed is referred to as reach effect. Further, the reach state and its state are referred to as a reach mode. Furthermore, variable display including reach production is called reach variable display. And when the display result of the symbol variably displayed on the effect display device 9 is not a big hit symbol, it becomes “out” and the variation display state ends. A player plays a game while enjoying how to generate a big hit.

  In the upper right part of the display screen of the effect display device 9, there are provided fourth symbol display areas 9c and 9d for displaying a fourth symbol after the effect symbol, a special symbol described later, and a normal symbol. In this embodiment, a fourth symbol display area 9c for the first special symbol in which the variation display of the fourth symbol for the first special symbol is performed in synchronization with the variation display of the first special symbol described later, There is provided a fourth symbol display area 9d for the second special symbol in which the variation display of the fourth symbol for the second special symbol is performed in synchronization with the variation display of the special symbol.

  The 4th symbol for the first special symbol and the 4th symbol for the 2nd special symbol may be collectively referred to as the 4th symbol, and the 4th symbol display area 9c for the 1st special symbol and the 2nd special symbol The 4th symbol display area 9d for symbols may be collectively referred to as a 4th symbol display area.

  The variation (variable display) of the fourth symbol is realized by continuing the state where the fourth symbol display areas 9c and 9d are repeatedly turned on and off at a predetermined time interval in a predetermined display color (for example, blue). . The variable display of the first special symbol on the first special symbol display unit 8a is synchronized with the variable display of the fourth symbol for the first special symbol in the fourth symbol display area 9c for the first special symbol. The variable display of the second special symbol on the second special symbol display 8b is synchronized with the variable display of the fourth symbol for the second special symbol in the fourth symbol display area 9d for the second special symbol. Synchronous means that the variable display start time and end time are the same, and the variable display period is the same. When the big win symbol is stopped and displayed on the first special symbol display 8a, the fourth special symbol display area 9c for the first special symbol is kept lit in a display color (for example, red) reminiscent of the big hit. . When the big win symbol is stopped and displayed on the second special symbol display 8b, the fourth special symbol display area 9d for the second special symbol is kept lit in a display color reminiscent of the big hit (for example, red).

  On the left side of the lower part of the game board 6, a first special symbol display (first variable display portion) 8a for variably displaying the first special symbol as identification information is provided. In this embodiment, the first special symbol display 8a is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. In other words, the first special symbol display 8a is configured to variably display numbers (or symbols) from 0 to 9. On the lower right side of the game board 6, a second special symbol display (second variable display portion) 8b for variably displaying the second special symbol as identification information is provided. The second special symbol display 8b is realized by a simple and small display (for example, 7 segment LED) capable of variably displaying numbers 0 to 9. That is, the second special symbol display 8b is configured to variably display numbers (or symbols) from 0 to 9.

  The small display is formed in a square shape, for example. In this embodiment, the type of the first special symbol and the type of the second special symbol are the same (for example, both 0 to 9), but the types may be different. Further, the first special symbol display 8a and the second special symbol display 8b may be configured to variably display numbers (or two-digit symbols) of, for example, 00 to 99, for example.

  Hereinafter, the first special symbol and the second special symbol may be collectively referred to as a special symbol, and the first special symbol indicator 8a and the second special symbol indicator 8b are collectively referred to as a special symbol indicator (variable display unit). There are things to do.

  Although this embodiment shows a case where two special symbol indicators 8a and 8b are provided, the gaming machine may be provided with only one special symbol indicator.

  For the variable display of the first special symbol or the second special symbol, the first start condition or the second start condition, which is the variable display execution condition, is satisfied (for example, the game ball has the first start winning opening 13 or the second start winning opening) 14 after passing (including winning)), the variable display start condition (for example, when the number of reserved memories is not 0 and the variable display of the first special symbol and the second special symbol is not executed) The state is started and the big hit game is not executed), and when the variable display time (fluctuation time) elapses, the display result (stop symbol) is derived and displayed. Note that the passing of a game ball means that the game ball has passed through a predetermined area such as a prize opening or a gate, and that includes a game ball entering (winning) a prize opening. It is. Deriving and displaying the display result is to finally stop and display a symbol (an example of identification information).

  A winning device having a first start winning port 13 is provided below the effect display device 9. The game ball won in the first start winning opening 13 is guided to the back of the game board 6 and detected by the first start opening switch 13a.

  A variable winning ball device 15 having a second starting winning port 14 through which a game ball can be won is provided below a winning device having a first starting winning port (first starting port) 13. The variable winning ball device 15 is configured to be able to open and close the wings, and when the wings are open, the game ball is likely to win a prize (open state), and when the wings are not open (closed). The game ball becomes difficult to win (closed state). The game ball won in the second start winning opening (second start opening) 14 is guided to the back of the game board 6 and detected by a second start opening switch 14a (for example, a proximity switch), and a winning confirmation switch 14b. (For example, a photo sensor). In this embodiment, based on the fact that a game ball has been detected by the second start port switch 14a, the variation display of the second special symbol is started, and a prize ball payout is executed. Further, as will be described later, the presence or absence of occurrence of an abnormal winning is determined based on the detection result of the winning confirmation switch 14b in addition to the detection result of the second start opening switch 14a, and the occurrence of the abnormal winning is detected. A security signal is output externally. The variable winning ball device 15 is opened by a solenoid 16.

  For each of the first start winning opening 13 and the second starting winning opening 14, a start opening switch (for example, a proximity switch) may be provided and a winning confirmation switch (for example, a photo sensor) may be provided. Then, for each of the first start winning opening and the second starting winning opening, the variation display of the special symbol is started based on the detection of the game ball by the start opening switch as in this embodiment. A ball payout may be executed. Further, for each of the first start winning opening and the second starting winning opening, whether or not an abnormal winning has occurred is determined based on the detection result of the winning confirmation switch in addition to the detection result by the start opening switch, as in this embodiment. A security signal may be output to the outside based on the determination and the occurrence of an abnormal winning.

  Further, in this embodiment, when the variable winning ball device 15 is in the open state, the game ball can be won in the second starting winning opening 14 (easier to start winning), and is in an advantageous state for the player. Become. In the state where the variable winning ball apparatus 15 is in the open state, it is easier for the game ball to win the second start winning opening 14 than the first starting winning opening 13. In addition, in a state where the variable winning ball device 15 is in the closed state, the game ball does not win the second start winning opening 14. Therefore, in a state where the variable winning ball device 15 is in the closed state, it is easier for the game ball to win the first starting winning port 13 than the second starting winning port 14. In the state where the variable winning ball apparatus 15 is in the closed state, it may be configured that the winning is possible (that is, it is difficult for the gaming ball to win) although it is difficult to win a prize.

  Hereinafter, the first start winning opening 13 and the second start winning opening 14 may be collectively referred to as a start winning opening or a starting opening.

  When the variable winning ball device 15 is controlled to be in the open state, the game ball heading for the variable winning ball device 15 is very likely to win the second start winning port 14. The first start winning opening 13 is provided directly under the effect display device 9, but the interval between the lower end of the effect display device 9 and the first start winning opening 13 is further reduced, or the first start winning opening is set. The nail arrangement around the first start winning opening 13 is made difficult to guide the game balls to the first starting winning opening 13 so that the winning rate of the second starting winning opening 14 is increased. It is also possible to make the direction higher than the winning rate of the first start winning opening 13.

  In this embodiment, as shown in FIG. 1, the variable winning ball apparatus 15 that opens and closes only the second start winning opening 14 is provided. Any of the start winning ports 14 may be provided with a variable winning ball device that performs an opening / closing operation.

  On the side of the first special symbol display 8a, the number of effective winning balls that have entered the first start winning opening 13, that is, the first reserved memory number (the reserved memory is also referred to as the start memory or the start prize memory) is displayed. A first special symbol storage memory display 18a comprising four displays is provided. The first special symbol storage memory indicator 18a increases the number of indicators to be lit by 1 each time there is an effective start winning. Then, each time the variable display on the first special symbol display 8a is started, the number of indicators to be turned on is reduced by one.

  On the side of the second special symbol display 8b, a second special symbol hold memory display 18b comprising four displays for displaying the number of effective winning balls that have entered the second start winning opening 14, that is, the second reserved memory number. Is provided. The second special symbol storage memory display 18b increases the number of indicators to be lit by 1 every time there is an effective start winning. Then, each time the variable display on the second special symbol display 8b is started, the number of indicators to be turned on is reduced by one.

  In addition, in the lower part of the display screen of the effect display device 9, there is provided a total pending storage display unit 18c for displaying the total number (total number of total pending storage) that is the sum of the first reserved memory count and the second reserved memory count. ing. As described above, if the summation pending storage display section for displaying the total number is provided, it is possible to easily grasp the total number of execution conditions that are not satisfied with the variable display start condition.

  The effect display device 9 is for decoration (for effects) during the variable display time of the first special symbol by the first special symbol display 8a and during the variable display time of the second special symbol by the second special symbol display 8b. A variable display of the effect symbol as the symbol is performed. The variable display of the first special symbol on the first special symbol display 8a and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, the variable display of the second special symbol on the second special symbol display 8b and the variable display of the effect symbol on the effect display device 9 are synchronized. Further, when the jackpot symbol is stopped and displayed on the first special symbol display 8a and when the jackpot symbol is stopped and displayed on the second special symbol display 8b, the effect display device 9 reminds the jackpot The combination of is stopped and displayed.

  Further, as shown in FIG. 1, a special variable winning ball device 20 is provided below the variable winning ball device 15. The special variable winning ball apparatus 20 includes an opening / closing plate, and when the specific display result (big hit symbol) is derived and displayed on the first special symbol display 8a, and the specific display result (big hit symbol) on the second special symbol display 8b. When the open / close plate is controlled to be open by the solenoid 21 in the specific game state (big hit game state) that occurs when the symbol is derived and displayed, the big winning opening serving as the winning area is opened. The game ball that has won the big winning opening is detected by the count switch 23.

  In this embodiment, only the second start winning opening 14 is provided with a winning confirmation switch 14b in addition to the second start opening switch 14a. However, in addition to the count switch 23, the big winning opening is also provided. A winning confirmation switch may be provided. In this case, for example, the count switch 13 may be configured by using a proximity switch and the winning confirmation switch may be configured by using a photosensor as in the case of the second start winning opening 14 (inversely, counting The switch 13 may be configured using a photo sensor, and the winning confirmation switch may be configured using a proximity switch, or a mechanical switch such as a micro switch may be used instead of the proximity switch or the photo sensor). Further, the game control microcomputer may perform the payout of the winning ball based only on the detection result of the count switch 23 in the winning ball payout process based on the winning of the game ball to the big winning opening (step). (See S32). On the other hand, the game control microcomputer, when performing an abnormal winning to the big winning opening, may make a determination based on both the detection result of the count switch 23 and the detection result of the winning confirmation switch. . In this case, for example, in the game control microcomputer, the difference between the detected number of the count switch 23 and the detected number of the winning confirmation switch is a predetermined value (for example, 10) according to the same process as the switch normal / abnormal check process described later. Based on what has been described above, it may be determined that an abnormal winning in the special winning opening has occurred (see steps S251 to S257).

  The game area 6 is also provided with winning ports (ordinary winning ports) 29 and 30 for paying out a predetermined number of premium game balls determined in advance based on winning of game balls. The game balls that have won the winning ports 29 and 30 are detected by the winning port switches 29a and 30a.

  A normal symbol display 10 is provided on the right side of the game board 6. The normal symbol display 10 variably displays a plurality of types of identification information (for example, “◯” and “x”) called normal symbols.

  When the game ball passes through the gate 32 and is detected by the gate switch 32a, variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the upper and lower lamps (the symbols can be visually recognized when turned on). For example, if the lower lamp is turned on at the end of the variable display, it is a hit. . When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In other words, the state of the variable winning ball apparatus 15 is a state that is advantageous from a disadvantageous state for the player when the normal symbol is a stop symbol (a state in which a game ball can be awarded at the second start winning port 14). To change. In the vicinity of the normal symbol display 10, a normal symbol holding storage display 41 having a display unit with four LEDs for displaying the number of winning balls that have passed through the gate 32 is provided. Each time there is a game ball passing through the gate 32, that is, every time a game ball is detected by the gate switch 32a, the normal symbol storage memory display 41 increases the number of LEDs to be turned on by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one. In addition, a probability variation state in which the probability of being determined to be a big hit compared to the normal state is high (a state in which the probability of being determined to be a big hit as a result of fluctuation display of special symbols is increased compared to the normal state). Then, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. Even in the short state (the game state in which the variable display time of the special symbol is shortened) when the symbol variation time is shortened although it is not the probability variation state, the opening time and the number of times of opening of the variable winning ball device 15 are increased.

  On the left and right sides of the game area 7 of the game board 6, there are provided decorative LEDs 25 that are displayed blinking during the game, and at the lower part there is an outlet 26 for taking in a hit ball that has not won. In addition, two speakers 27 that utter sound effects and sounds as predetermined sound outputs are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a frame LED 28 provided on the front frame is provided.

  The members constituting the hitting ball supply tray 3 are provided with operation buttons 120 as operation means that can be operated by the player. The operation button 120 is provided with a push button switch that can be pressed by the player. The operation button 120 is provided not only with a push button switch that can be pressed by the player, but also with a dial that can be rotated by the player. The player can perform a predetermined selection (for example, selection of effects) by rotating the dial.

  In the gaming machine, a ball striking device (not shown) that drives a driving motor in response to a player operating the batting operation handle 5 and uses the rotational force of the driving motor to launch a gaming ball to the gaming area 7. ) Is provided. A game ball launched from the ball striking device enters the game area 7 through a ball striking rail formed in a circular shape so as to surround the game area 7, and then descends the game area 7. When the game ball enters the first start winning opening 13 and is detected by the first start opening switch 13a, if the variable display of the first special symbol can be started (for example, the variable display of the special symbol ends, 1), the variable display (variation) of the first special symbol is started on the first special symbol display 8a, and the variable display of the effect symbol is started on the effect display device 9. That is, the variable display of the first special symbol and the effect symbol corresponds to winning in the first start winning opening 13. If the variable display of the first special symbol cannot be started, the first reserved memory number is increased by 1 on the condition that the first reserved memory number has not reached the upper limit value.

  When the game ball enters the second start winning opening 14 and is detected by the second start opening switch 14a, if the variable display of the second special symbol can be started (for example, the special symbol variable display ends, 2), the second special symbol display 8b starts variable display (variation) of the second special symbol, and the effect display device 9 starts variable display of the effect symbol. That is, the variable display of the second special symbol and the effect symbol corresponds to winning in the second start winning opening 14. If the variable display of the second special symbol cannot be started, the second reserved memory number is increased by 1 on condition that the second reserved memory number has not reached the upper limit value.

  In this embodiment, when the probability variation is a big hit, the game state is shifted to a high probability state, and the game ball is easily started and won (that is, in the special symbol indicators 8a and 8b and the effect display device 9). It shifts to a high base state, which is a gaming state controlled so that a variable display execution condition is easily established. In addition, when the gaming state is shifted to the short time state, the state is shifted to the high base state. In the high base state, for example, the frequency at which the variable winning ball device 15 is in the open state is increased or the time in which the variable winning ball device 15 is in the open state is extended compared to the case in which the high base state is not in the high base state. It becomes easier to win a start.

  Instead of extending the time during which the variable winning ball apparatus 15 is in the open state (also referred to as the open extended state), the normal symbol display unit 10 shifts to a normal symbol probability changing state in which the probability that the stop symbol in the normal symbol display unit 10 is a hit symbol is increased. Depending on the situation, the high base state may be entered. When the stop symbol in the normal symbol display 10 becomes a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In this case, by performing the transition control to the normal symbol probability changing state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the frequency at which the variable winning ball apparatus 15 is opened is increased. Therefore, if the normal symbol probability changing state is entered, the opening time and the number of opening times of the variable winning ball device 15 are increased, and a state where it is easy to start a winning (high base state) is achieved. That is, the opening time and the number of times of opening of the variable winning ball device 15 can be increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol. It changes to an advantageous state (a state where it is easy to win a start). It should be noted that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Moreover, you may transfer to a high base state by shifting to the normal symbol time short state where the fluctuation time (variable display period) of the normal symbol in the normal symbol display 10 is shortened. In the normal symbol short-time state, the variation time of the normal symbol is shortened, so that the frequency of starting the variation of the normal symbol increases, and as a result, the frequency of hitting the normal symbol increases. Therefore, when the frequency that the normal symbol is hit increases, the frequency that the variable winning ball apparatus 15 is opened is increased, and the start winning state is easily set (high base state).

  In addition, the change time of special symbols and production symbols will be shortened by shifting to the short time state when the variation time (variable display period) of special symbols and production symbols is shortened. The frequency of being played (in other words, the digestion of the reserved memory becomes faster), and the situation where an invalid start prize is generated can be reduced. Therefore, an effective start winning is likely to occur, and as a result, the possibility of a big hit game being increased.

  Furthermore, by making transitions to all the states shown above (open extended state, normal symbol probability change state, normal symbol short time state, and special symbol short time state), it will be easier to win a start (shift to a high base state). May be. In addition, it is easier to win a start (high base) by shifting to any one of the above states (open extended state, normal symbol probability changing state, normal symbol short time state, and special symbol short time state). Transition to a state). In addition, it is easier to win a start by shifting to any one of the above states (open extended state, normal symbol probability changing state, normal symbol short time state, and special symbol short time state). You may make it move to a base state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine as seen from the back side. As shown in FIG. 2, on the back side of the pachinko gaming machine 1, there are a variable display control unit including an effect control board 80 on which an effect control microcomputer 100 for controlling the effect display device 9 is mounted, a game control microcomputer, and the like. Various boards such as a mounted game control board (main board) 31, an audio output board 70, a lamp driver board 35, and a payout control board 37 mounted with a payout control microcomputer for performing ball payout control are installed. Yes. The game control board 31 is stored in the board storage case 200.

  Further, on the back side of the pachinko gaming machine 1, a power supply substrate 910 and a touch sensor substrate 91 on which power supply circuits for generating various power supply voltages such as DC30V, DC21V, DC12V, and DC5V are mounted. The power supply board 910 is supplied with the game control board 31 and each electrical component control board (the effect control board 80 and the payout control board 37) in the pachinko gaming machine 1 and each electrical component (power is supplied) provided in the pachinko gaming machine 1. A power switch as a power supply permission means for executing or shutting off the power supply to the component), and a clear switch for clearing the RAM 55 of the game control microcomputer 560 of the game control board 31 are provided. ing. Further, a replaceable fuse is provided inside the power switch (inside the substrate).

  In this embodiment, the main board 31 is provided on the game board side, and the payout control board 37 is provided on the game frame side. Even in such a configuration, as will be described later, the communication between the main board 31 and the payout control board 37 is performed by serial communication, thereby facilitating the routing of the wiring when replacing the game board. .

  Each control board is equipped with control means including a control microcomputer. The control means is an electrical component (game device: ball payout device 97, effect display device 9, light emission from a lamp, LED, etc.) provided in the gaming machine according to a command signal (control signal) as a command from the game control means or the like. Body, speaker 27, etc.). Hereinafter, the main board 31 may be included in the control board for explanation. In that case, the control means mounted on the control board refers to each of the game control means and the means for controlling the electrical components provided in the gaming machine in accordance with a command signal from the game control means or the like. A substrate on which a microcomputer other than the main substrate 31 is mounted may be referred to as a sub-substrate. The ball payout device 97 is a device for paying out a game ball guided by a passage for guiding the game ball and a sprocket driven by a stepping motor or the like to an upper plate or a lower plate. A payout number counting switch for counting prize balls and rental balls is also configured as part of the unit. In this embodiment, the payout detection means is realized by the payout number count switch 301 and has a function of detecting that a winning ball or a lending ball is actually paid out from the ball payout device 97. In this case, the payout number count switch 301 outputs a detection signal every time one payout of prize balls or rental balls is detected.

  On the back side of the pachinko gaming machine 1, a terminal board 160 having terminals for outputting various information to the outside of the pachinko gaming machine 1 is installed above. The terminal board 160 has, for example, information output signals such as jackpot information indicating the occurrence of a jackpot gaming state (symbol determination number of times 1 signal shown in FIG. 8, start port signal, jackpot 1 signal, jackpot 2 signal, jackpot 3 signal, hour An information output terminal for externally outputting a short signal, a winning signal, a security signal, a high-accuracy signal, and winning ball information) is provided.

  The game ball stored in the storage tank 38 passes through a guide rail (not shown), and reaches a ball payout device 97 covered with a payout case 40A through a curve rod. Above the ball payout device 97, a ball break switch 187 is provided as a game medium break detection means. When the ball break switch 187 detects a ball break, the payout operation of the ball payout device 97 stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail (in the storage tank 38). (Proximate part). When the ball break detection switch 167 detects a shortage of game balls, the game balls are replenished to the pachinko gaming machine 1 from the replenishment mechanism provided on the gaming machine installation island.

  When a large number of game balls as prizes based on winning a prize or a game ball based on a ball lending request are paid out and the hitting ball supply tray 3 is full, the game balls are guided to the surplus ball receiving tray 4 through the surplus ball guiding path. Further, when the game ball is paid out, a sensing lever (not shown) presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device is stopped, the operation of the ball payout device is stopped, and the driving of the ball hitting device is also stopped.

  FIG. 3 is a block diagram showing an example of the circuit configuration of the main board (game control board) 31. FIG. 3 also shows a payout control board 37, an effect control board 80, and the like. A game control microcomputer (corresponding to game control means) 560 for controlling the pachinko gaming machine 1 according to a program is mounted on the main board 31. The game control microcomputer 560 includes a ROM 54 for storing a game control (game progress control) program and the like, a RAM 55 as storage means used as a work memory, a CPU 56 for performing control operations in accordance with the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and the RAM 55 are built in the game control microcomputer 560. That is, the game control microcomputer 560 is a one-chip microcomputer. The one-chip microcomputer only needs to include at least the RAM 55, and the ROM 54 may be external or internal. The I / O port unit 57 may be externally attached.

  In the game control microcomputer 560, the CPU 56 executes control in accordance with the program stored in the ROM 54, so that the game control microcomputer 560 (or CPU 56) executes (or performs processing) hereinafter. Specifically, the CPU 56 executes control according to a program. The same applies to microcomputers mounted on substrates other than the main substrate 31.

  The game control microcomputer 560 includes a random number circuit 503. The random number circuit 503 is a hardware circuit that is used to generate a random number for determination to determine whether or not to win a jackpot based on a display result of variable symbol special display. The random number circuit 503 updates numerical data in accordance with a set update rule within a numerical range in which an initial value (for example, 0) and an upper limit value (for example, 65535) are set, and starts at a random timing Based on the fact that the winning time is the reading (extraction) of the numerical data, it has a random number generation function in which the numerical data to be read becomes a random value.

  The random number circuit 503 includes a numeric data update range selection setting function (initial value selection setting function and upper limit value selection setting function), numeric data update rule selection setting function, and numeric data update rule selection. It has various functions such as a switching function. With such a function, the randomness of the generated random numbers can be improved.

  Further, the game control microcomputer 560 has a function of setting an initial value of numerical data updated by the random number circuit 503. For example, a predetermined calculation is performed using the ID number of the game control microcomputer 560 stored in a predetermined storage area such as the ROM 54 (an ID number assigned with a different value for each product of the game control microcomputer 560). The numerical data obtained by the execution is set as the initial value of the numerical data updated by the random number circuit 503. By performing such processing, the randomness of the random number generated by the random number circuit 503 can be further improved.

  The game control microcomputer 560 reads the numerical data as random R from the random number circuit 503 when a start winning to the first start port switch 13a or the second start port switch 14a occurs, and starts to change the special symbol and the production symbol. Sometimes it is determined whether or not to make a big hit display result as a specific display result based on the random R, that is, whether or not to make a big hit. Then, when it is determined to be a big hit, the gaming state is shifted to a big hit gaming state as a specific gaming state advantageous to the player.

  In addition, the game control microcomputer 560 has a built-in serial communication circuit 505 for inputting / outputting (transmitting / receiving) signals to / from the payout control board 37 (the payout control microcomputer 370) by serial communication. The payout control microcomputer 370 also includes a serial communication circuit for inputting / outputting signals via the serial communication with the game control microcomputer 560 (a serial communication circuit built in the payout control microcomputer 370). (See FIG. 4).

  The RAM 55 is a backup RAM as a non-volatile storage means, part or all of which is backed up by a backup power supply created on the power supply board. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is stored for a predetermined period (until the capacitor as the backup power supply is discharged and the backup power supply cannot be supplied). In particular, at least data corresponding to the game state, that is, the control state of the game control means (a special symbol process flag, a value of a reserved memory number counter for counting the number of reserved memories) and data indicating the number of unpaid winning balls ( Specifically, a value of a prize ball command output counter (to be described later) is stored in the backup RAM. The data corresponding to the control state of the game control means is data necessary for resuming the game based on the data when the power is restored after a power failure or the like occurs. Further, data corresponding to the control state and data indicating the number of unpaid winning balls are defined as data indicating the progress state of the game. In this embodiment, it is assumed that the entire RAM 55 is backed up.

  A reset signal from the power supply board is input to the reset terminal of the game control microcomputer 560. A reset circuit for generating a reset signal supplied to the game control microcomputer 560 and the like is mounted on the power supply board. When the reset signal becomes high level, the game control microcomputer 560 and the like are in an operable state, and when the reset signal becomes low level, the game control microcomputer 560 and the like are in an operation stop state. Therefore, an allowable signal that allows the operation of the game control microcomputer 560 or the like is output during a period when the reset signal is at a high level, and a game control microcomputer is output when the reset signal is at a low level. An operation stop signal for stopping the operation of 560 or the like is output. Note that the reset circuit may be mounted on each electric component control board (a board on which a microcomputer for controlling the electric parts is mounted).

  Further, a power-off signal indicating that the power supply voltage from the power supply board has dropped below a predetermined value is input to the input port of the game control microcomputer 560. That is, the power supply board monitors the voltage value of a predetermined voltage (for example, DC30V or DC5V) used in the gaming machine, and when the voltage value decreases to a predetermined value (the power supply voltage is reduced). A power supply monitoring circuit that outputs a power-off signal indicating that). Instead of mounting the power monitoring circuit on the power supply board, it may be mounted on a board that is backed up by a backup power supply (for example, the main board 31). A clear signal (not shown) indicating that the clear switch for instructing to clear the contents of the RAM is operated is input to the input port of the game control microcomputer 560.

  Also, an input driver circuit for supplying the basic circuit 53 with detection signals from the gate switch 32a, the first start port switch 13a, the second start port switch 14a, the winning confirmation switch 14b, the count switch 23, and the winning port switches 29a and 30a. 58 is also mounted on the main board 31, and an output circuit 59 for driving the solenoid 16 for opening / closing the variable winning ball apparatus 15 and the solenoid 21 for opening / closing the special variable winning ball apparatus according to a command from the basic circuit 53 is also mounted on the main board 31. A system reset circuit (not shown) for resetting the game control microcomputer 560 when the power is turned on, and an information output signal such as jackpot information indicating the occurrence of a jackpot gaming state are sent to the hall via the terminal board 160. An information output circuit 64 that outputs to an external device such as a computer is also main. It is mounted to the plate 31.

  In this embodiment, the effect control means (configured by the effect control microcomputer) mounted on the effect control board 80 receives the effect control command from the game control microcomputer 560 via the relay board 77. The display control of the effect display device 9 that receives and displays the effect symbol variably is performed.

  FIG. 4 is a block diagram showing components related to payout, such as the payout control board 37 and the ball payout device 97. As shown in FIG. 4, the payout control board 37 includes a payout control microcomputer 370 including a payout control CPU 371. In this embodiment, the payout control microcomputer 370 is a one-chip microcomputer and incorporates at least a RAM. The payout control microcomputer 370, the RAM (not shown), the ROM (not shown) storing the payout control program, the I / O port, and the like constitute the payout control means. That is, the payout control means is realized by a payout control CPU 371, a payout control microcomputer 370 having a RAM and a ROM, and an I / O port. The I / O port may be built in the payout control microcomputer 370. Note that, unlike the game control microcomputer 560, the RAM built in the payout control microcomputer 370 has not been backed up by a backup power source. Therefore, if the power supply to the gaming machine is stopped, the stored contents of the RAM built in the payout control microcomputer 370 are lost.

  The payout control microcomputer 370 performs control to pay out the game ball based on a predetermined payout condition being satisfied. The predetermined payout condition is that a game ball has won in a winning area (ordinary winning holes 29, 30, large winning opening, first starting winning opening 13, second starting winning opening 14) provided in the game area. It is established when a rental ball request is made. In addition, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also satisfied when a game ball or medal return request is made. Further, for example, when applied to a gaming machine such as a parrot machine or a slot machine, the predetermined payout condition is also established when the symbol stop symbol becomes a predetermined winning symbol.

  Detection signals from the ball break switch 187, the full switch 48, and the payout count switch 301 are input to the I / O port 372 f of the payout control board 37 via the relay board 72. In this embodiment, the detection signal from the payout number count switch 301 is input to the payout control microcomputer 370 and then output to the main board 31 via the I / O port 372a and the output circuit 373B. .

  A detection signal from the payout motor position sensor 295 is input to the I / O port 372e of the payout control board 37 via the relay board 72. The payout motor position sensor 295 is a sensor composed of a light emitting element (LED) and a light receiving element for detecting the rotational position of the payout motor 289, and is used for detecting that the game ball is clogged, that is, so-called ball biting. . In the payout control microcomputer 370 mounted on the payout control board 37, the detection signal from the ball break switch 187 indicates that the ball is out of ball, or the detection signal from the full tank switch 48 indicates that the ball is full. Then, the ball payout process is stopped.

  Further, when the detection signal from the full tank switch 48 indicates a full state, the payout control microcomputer 370 has a low level with respect to the launch board 90 in order to stop the ball launch from the hitting ball launcher. A full tank signal is output. A launch motor signal output from the AND circuit 91 of the launch board 90 to the launch motor 94 is transmitted from the launch board 90 to the launch motor 94. A full tank signal from the payout control microcomputer 370 is input to one of the input sides of the AND circuit 91 mounted on the launch board 90, and a drive signal from the drive signal generation circuit 92 (for driving the launch motor 94). Is a signal that serves to supply power from the power supply board.) Is input to the other input side of the AND circuit 91. Then, the firing motor signal of the AND circuit 91 is input to the firing motor 94. That is, while the payout control microcomputer 370 is outputting the full tank signal, the output of the firing motor signal to the firing motor 94 is stopped. Even when the payout control microcomputer 370 is outputting a full tank signal, the output of the launch motor signal to the launch motor 94 is not stopped, and the ball launch from the hitting ball launcher is not stopped. May be.

  The payout control microcomputer 370 incorporates a serial communication circuit 380 for inputting / outputting (transmitting / receiving) signals with the game control microcomputer 560 through serial communication. In this embodiment, the game control microcomputer 560 and the payout control microcomputer 370 are connected between the game control microcomputer 560 and the payout control microcomputer 370 via serial communication circuits 505 and 380. In order to confirm, payout control commands (connection confirmation command, connection OK command) are exchanged (transmitted / received) at regular intervals (for example, 1 second). For example, the game control microcomputer 560 transmits a connection confirmation command for performing connection confirmation at regular intervals via the serial communication circuit 505, and the payout control microcomputer 370 receives the game control microcomputer 560 from the game control microcomputer 560. When the connection confirmation command is received, a connection OK command notifying that is transmitted to the game control microcomputer 560. Also, for example, when a winning occurs, the game control microcomputer 560 sets data indicating the number of winning balls to be paid out in the lower 4 bits of the winning ball number command, and the number of winning balls set in the setting. The command is transmitted to the payout control microcomputer 370. Then, the payout control microcomputer 370 transmits a prize ball number reception command indicating that the prize ball number has been received to the game control microcomputer 560. Furthermore, when the payout control microcomputer 370 finishes the prize ball payout operation, it transmits a prize ball end command indicating the completion of the prize ball to the game control microcomputer 560. The payout control microcomputer 370 transmits a prize ball preparing command to the game control microcomputer 560 at regular intervals until the prize ball payout operation is completed. In addition, when a predetermined error (an error such as ball lending, full tank, or out of ball) has occurred, the lower 4 bits of the connection OK command or the winning ball preparation command should be made different from the data indicating the error content. The connection OK command and the winning ball preparation command in which the setting is made are transmitted to the game control microcomputer 560.

  Also, the payout control microcomputer 370 outputs an error signal to the error display LED 374 using a 7-segment LED via the output port 372c. A detection signal from an error release switch 375 for releasing the error state is input to the input port 372f of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a drive signal from the payout control microcomputer 370 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372a and the relay board 72. A driver circuit (motor drive circuit) is installed outside the output port 372a, but is not shown in FIG.

  A card unit control microcomputer is mounted on the card unit 50 installed adjacent to the gaming machine. In addition, the card unit 50 is provided with a usable display lamp, a connecting table direction indicator, a card insertion display lamp, and a card insertion slot. A frequency display LED 60, a ball lending LED 61, a ball lending switch 62, and a return switch 63 provided in the vicinity of the hitting ball supply tray 3 are connected to the interface board (relay board) 66.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are provided to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is transmitted / received via the input port 372f and the output port 372d. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is transmitted and received between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control microcomputer 370 mounted on the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal when the power is turned on. The payout control microcomputer 370 determines the connected / unconnected state of the card unit 50 according to the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control microcomputer 370 raises the EXS signal to the card unit 50 and, when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to give a predetermined number of rental balls to the player. Pay out. When the payout is completed, the payout control microcomputer 370 causes the EXS signal to the card unit 50 to fall. Thereafter, on the condition that the BRDY signal from the card unit 50 is not in the ON state, the winning ball payout control is executed when a payout command signal is received from the game control means.

  The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37. That is, power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in a 24 V AC power supply line for the card unit 50 arranged in the interface board 66, and a voltage higher than a predetermined voltage is supplied to the card unit 50. It is prevented.

  Further, in this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 5 is a block diagram illustrating a circuit configuration example of the relay board 77, the effect control board 80, the lamp driver board 35, and the audio output board 70. In the example shown in FIG. 5, the lamp driver board 35 and the audio output board 70 are not equipped with a microcomputer, but may be equipped with a microcomputer. Further, without providing the lamp driver board 35 and the audio output board 70, only the effect control board 80 may be provided for effect control.

  The effect control board 80 includes an effect control CPU 101 and an effect control microcomputer 100 including a RAM for storing information related to effects such as effect symbol process flags. The RAM may be externally attached. In this embodiment, the RAM in the production control microcomputer 100 is not backed up. In the effect control board 80, the effect control CPU 101 operates in accordance with a program stored in a built-in or external ROM (not shown), and receives a capture signal from the main board 31 input via the relay board 77 ( In response to the (effect control INT signal), an effect control command is received via the input driver 102 and the input port 103. Further, the effect control CPU 101 causes the VDP (video display processor) 109 to perform display control of the effect display device 9 based on the effect control command.

  In this embodiment, a VDP 109 that performs display control of the effect display device 9 in cooperation with the effect control microcomputer 100 is mounted on the effect control board 80. The VDP 109 has an address space independent of the production control microcomputer 100, and maps a VRAM therein. VRAM is a buffer memory for developing image data. Then, the VDP 109 outputs the image data in the VRAM to the effect display device 9 via the frame memory.

  The effect control CPU 101 outputs to the VDP 109 a command for reading out necessary data from a CGROM (not shown) in accordance with the received effect control command. The CGROM stores character image data and moving image data displayed on the effect display device 9, specifically, a person, characters, figures, symbols (including effect symbols), and background image data in advance. ROM. The VDP 109 reads image data from the CGROM in response to the instruction from the effect control CPU 101. The VDP 109 executes display control based on the read image data.

  Further, the effect control CPU 101 outputs a signal for driving the LED to the lamp driver board 35 via the output port 105. Further, the production control CPU 101 outputs sound number data to the audio output board 70 via the output port 104.

  In the lamp driver board 35, a signal for driving the LED is input to the LED driver 352 via the input driver 351. The LED driver 352 supplies a current to a light emitter provided on the frame side such as the frame LED 28 based on a signal for driving the LED. Further, an electric current is supplied to the decoration LED 25 provided on the game board side.

  In the voice output board 70, the sound number data is input to the voice synthesis IC 703 via the input driver 702. The voice synthesizing IC 703 generates voice or sound effect according to the sound number data, and outputs it to the amplifier circuit 705. The amplification circuit 705 outputs an audio signal obtained by amplifying the output level of the speech synthesis IC 703 to a level corresponding to the volume set by the volume 706 to the speaker 27. The voice data ROM 704 stores control data corresponding to the sound number data. The control data corresponding to the sound number data is a collection of data showing the output form of the sound effect or sound in a time series in a predetermined period (for example, the changing period of the effect design).

  FIG. 6 is an explanatory diagram showing an example of output port assignment in the game control means. As shown in FIG. 6, a payout control signal (in this example, a connection signal) transmitted to the payout control board 37 is output from the output port 0. Further, a solenoid (large winning port door solenoid) 21 for opening and closing a variable winning ball device 20 for opening and closing the big winning port, and a solenoid (ordinary electric accessory solenoid) 16 for opening and closing the variable winning ball device 15 are driven. The signal is also output from output port 0. Further, a high-accuracy signal is also output from signals output from the output port 0 to an external device (for example, a hall computer) via the terminal board 160.

  Note that the logic (for example, 0 is on) opposite to the “logic” (for example, 1 is on) shown in FIG. 6 may be used. In particular, for the connection signal, the main board 31 and the payout control board. The “logic” is determined so that the payout control microcomputer 370 always detects the off state when the signal line to the terminal 37 is disconnected or when the cable is disconnected (including no cable connection). . Specifically, generally, when disconnection or cable disconnection occurs, a high level is detected on the signal receiving side, so the high level on the signal line between the main board 31 and the payout control board 37 is the game control means. The “logic” is determined to be in the off state at the output port at. Therefore, if necessary, an output buffer circuit for logically inverting the signal is provided outside the output port on the main board 31.

  From the output port 1 to the external device (for example, hall computer) via the terminal board 160, various information output signals, that is, information related to the control (for example, symbol determination frequency 1 signal, start port signal, jackpot 1 signal, 2 jackpots, 3 jackpots, time-short signal, winning signal, security signal) are output. However, as already described, the high-accuracy intermediate signal among the signals output externally is output from the output port 0. In this embodiment, prize ball information (a signal outputted every time ten prize ball payouts are detected) is also outputted to an external device via the terminal board 160. In this case, on the payout control board 37 side, a prize ball payout is detected, and prize ball information is input to the main board 31. The prize ball information input to the main board 31 is output to the outside via the terminal board 160 via the main board 31 as it is without passing through the game control microcomputer 560. The prize ball information input to the main board 31 may be output to the outside via the terminal board 160 after temporarily passing through the game control microcomputer 560.

  Note that signals output to the outside via the terminal board 160 are not limited to those shown in this embodiment. For example, a door opening signal indicating that the gaming frame is in an open state, a prize ball signal 1 (a signal output every time one prize ball payout is detected), a gaming machine error status signal (a gaming machine has an error) The state (in this example, a signal indicating that the ball is out of error state or full tank error state) may also be output to the external device via the terminal board 160. In this case, on the payout control board 37 side, it is also detected that the gaming frame is in an open state, a prize ball payout, and an error state of the gaming machine, and the door opening signal, the prize ball signal 1, and the gaming machine error status signal are the main board. 31. The door opening signal, the prize ball signal 1, and the gaming machine error state signal input to the main board 31 are not transmitted through the game control microcomputer 560 but directly passed through the main board 31 to the terminal board 160. Output externally. Also in this case, the door opening signal, the prize ball signal 1 and the gaming machine error state signal input to the main board 31 pass through the gaming control microcomputer 560 once and then externally output via the terminal board 160. You may be made to do.

  Further, for example, in addition to the symbol determination frequency 1 signal as a symbol determination frequency signal for notifying the number of fluctuations of the special symbol, the symbol determination frequency 2 signal may be externally output via the terminal board 160. In this case, for example, in order to notify the number of fluctuations of both the first special symbol and the second special symbol by externally outputting the symbol determination number 2 signal as a signal for notifying only the number of fluctuations of the first special symbol. The signal may be configured to be externally output as a signal of the number of symbol determinations. With such a configuration, on the external device side such as a hall computer, in addition to the number of fluctuations of only the first special symbol, the number of fluctuations of the first special symbol and the second special symbol, or the fluctuation of only the second special symbol The number of times can also be grasped.

  FIG. 7 is an explanatory diagram showing an example of bit assignment of input ports in the game control means. As shown in FIG. 7, the detection signal of the count switch 23, the detection signals of the winning opening switches 29a and 30a, and the detection signal of the winning confirmation switch 14b are input to bits 0 and 2 to 4 of the input port 0, respectively. . In addition, a radio wave sensor signal, a magnet sensor signal, a door opening signal, and prize ball information are input to the bits 4 to 7 of the input port 1, respectively. In addition, bits 0 to 4 of the input port 2 respectively include a detection signal of the first start port switch 13a, a detection signal of the second start port switch 14a, a detection signal of the gate switch 32a, and a clear switch from the power supply board 910. A detection signal and a power-off signal are input.

  FIG. 8 is a circuit diagram showing an internal configuration of the terminal board 160. In the terminal board 160 shown in FIG. 8, the connectors CN-1 and CN-2 on the upper left side are connectors for connecting cables that transmit signals from the main board 31, and the connector CN-3 on the lower left side is This is a connector for connecting a cable for transmitting a signal from the payout control board 37 via the main board 31. The right connectors CN1 to CN10 are connectors for connecting cables that transmit signals to an external device such as a hall computer. The terminal board 160 is mounted with semiconductor relays (PhotoMOS relays) PC1 to PC10 as driver circuits.

  When the cable from the main board 31 is connected to the connectors CN-1 and CN-2, various signals are input to the terminal board 160 from the main board 31 (game control microcomputer 560). Specifically, the symbol determination number 1 signal is input to the terminal “2” of the connector CN-1, the start port signal is input to the terminal “3” of the connector CN-1, and the terminal “4” of the connector CN-1 is input. 1 signal is input to the terminal “5” of the connector CN-1, 2 signals are input to the terminal “6” of the connector CN-1, and 3 signals of the jackpot are input to the terminal “7” of the connector CN-1. To the terminal “8” of the connector CN-1, a winning signal is input to the terminal “9” of the connector CN-1, and a terminal “9” of the connector CN-2 is input. A high-accuracy signal is input.

  Further, when the cable from the payout control board 37 is connected to the connector CN-3 via the main board 31, a signal from the payout control board 37 (the payout control microcomputer 370) is input to the terminal board 160. The Specifically, the prize ball information is input to the terminal “9” of the connector CN-3.

  As shown in FIG. 8, in the terminal board 160, the signal line of the reference potential is connected to the terminal “1” of the connector CN-1, the connector CN-2, and the connector CN-3, the signal lines are branched, Are connected to the input terminal “1” of the semiconductor relays PC1 to PC10. The signal lines connected to the terminals “2” to “9” of the connector CN-1, the connector “9” of the connector CN-2, and the connector “9” of the connector CN-3 are each 1KΩ resistance R1. Are connected to the input terminal “2” of the semiconductor relays PC1 to PC10 via R10. The signal lines connected to the output terminals “4” of the semiconductor relays PC1 to PC10 are connected to the terminals “1” of the connectors CN1 to CN10, respectively. The signal lines connected to the output terminals “3” of the semiconductor relays PC1 to PC10 are connected to the terminals “2” of the connectors CN1 to CN10, respectively.

  In the semiconductor relays PC1 to PC10, when a signal current flows through the input terminal, the light emitting element (LED) on the input side emits light. The emitted light is applied to the photoelectric element (solar cell) provided opposite to the LED through the transparent silicon. The photoelectric element that has received the light is exchanged for voltage according to the amount of light, and this voltage passes through the control circuit to charge the MOSFET gate of the output section. When the MOSFET gate voltage supplied from the photoelectric element reaches the set voltage value, the MOSFET becomes conductive and turns on the load. When the signal current at the input terminal is cut off, the light emitting element (LED) stops emitting light. When the light emission of the LED stops, the voltage of the photoelectric element decreases, and when the voltage supplied from the photoelectric element decreases, the gate load of the MOSFET is rapidly discharged by the control circuit. With this control circuit, the MOSFET is turned off and the load is turned off.

  By the operation of the semiconductor relays PC1 to PC10 as described above, signals input from the input side connector CN-1, connector CN-2, and connector CN-3 are transmitted to the output side connectors CN1 to CN10, and a hall computer or the like. Output to an external device. Specifically, the design CN count 1 signal is output from the connector CN1, the start signal is output from the connector CN2, the jackpot signal is output from the connector CN3, the jackpot signal is output from the connector CN4, and the connector CN5 is output. Three jackpot signals are output, a time signal is output from the connector CN6, a winning signal is output from the connector CN7, a security signal is output from the connector CN8, a high-probability medium signal is output from the connector CN9, and a prize is output from the connector CN10. Sphere information is output. The assignment of connectors to each external output signal on terminal board 160 is not limited to that shown in this embodiment. For example, the security signal may be output from the end connector (for example, connector CN10) provided on the terminal board 160.

  Note that the winning signal output from the connector CN7 indicates that a predetermined payout condition for paying out a predetermined number (in this embodiment, 10 balls) of winning balls is satisfied (the first start winning port 13, This is a signal indicating that a winning has occurred in the second start winning port 14, the big winning port, and the normal winning ports 29, 30. The award ball has not been paid out. By confirming the winning signal, the expected number of prize balls to be paid out can be recognized by an external device such as a hall computer.

  Also, the prize ball information output from the connector CN10 is that a specific number (10 balls in this embodiment) of prize balls has been paid out (the ball payout device 97 is driven and the prize balls are actually paid out). This is a signal indicating that By confirming the prize ball information, the number of prize balls actually paid out can be recognized by an external device such as a hall computer. Also, by confirming the planned number of prize balls indicated by the winning signal and the number of prize balls already paid out indicated by the prize ball information, whether or not the prize balls have been paid out normally and the number of excess or insufficient prize balls are determined. It can be recognized by an external device such as a hall computer.

  The security signal output from the connector CN8 is a signal indicating the security state of the gaming machine. Specifically, as will be described later, when it is determined that an abnormal winning to the second starting winning opening 14 has occurred based on the detection result of the second starting opening switch 14a and the detection result of the winning confirmation switch 14b. In addition, a security signal is output to an external device such as a hall computer for a predetermined period (for example, 4 minutes). With such a configuration, a fraudulent act such as recognizing that the number of winnings to the second start winning opening 14 is larger than the actual winning number using radio waves or the like has been performed. Can be recognized on the external device side.

  In this embodiment, even when the gaming machine is turned on and the initialization process is executed, the security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds). . By configuring as such, it is recognized that the initialization process has been executed at an unnatural timing (for example, even after all the gaming machine power reset operations have been completed when the amusement store is opened). By making it possible, the external device such as a hall computer can recognize the possibility that an unauthorized act of illegally resetting the power of the gaming machine and aiming for a big hit at the power reset timing is performed. it can.

  In this embodiment, as described above, when the abnormal winning is detected and the initialization process (for example, the operation of the clear switch is performed when the power to the gaming machine is turned on) A common security signal is output from the common connector CN8 of the terminal board 160 to the outside when the process (such as clearing the stored contents) is executed. This is because the initialization process is usually performed only when the game machine power is reset when the amusement store is opened, so the terminal is used for a signal that is output only once a day. Providing a dedicated connector or semiconductor relay on the substrate 160 is not efficient and wasteful. Therefore, in this embodiment, an external output signal is configured by outputting a security signal from the common connector CN8 when an abnormal winning is detected and when an initialization process is executed. The waste of lines and circuit elements is reduced. That is, it is possible to prevent an increase in the number of parts of a mechanism for outputting information to an external device such as a hall computer and complication of wiring work.

  The signal output from the common connector as a security signal is not limited to that shown in this embodiment. For example, not only abnormal winning at the second starting winning opening 14, but abnormal winning at the first starting winning opening 13, the large winning opening, and the normal winning openings 29, 30 is detected, and a common connector of the terminal board 160 is detected. You may comprise so that external output is possible as a security signal from CN8. In this case, for example, the first start winning opening 13, the big winning opening, and the normal winning openings 29 and 30 are also used as a switch for detecting the winning of the game ball, similarly to the second starting winning opening 14. Two different types of switches (proximity switch and photo sensor) may be provided, and the presence / absence of an abnormal prize may be determined according to the same determination method as that for the second start winning opening 14.

  Further, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, a security signal is output from the common connector CN8 of the terminal board 160. You may comprise so that external output is possible. In addition, for example, when an abnormality of various switches provided in the gaming machine is detected (for example, when occurrence of a short circuit is detected by determining that the input value has exceeded the threshold value), a common terminal board 160 is used. The connector CN8 may be configured so that it can be externally output as a security signal.

  As described above, even if there is an abnormal winning at the grand prize opening, an abnormal magnetic error, or an abnormal radio wave error, it is possible to output only one signal line as a security signal from the common connector CN8 of the terminal board 160. If connected, an error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  In the case of detecting an abnormal winning at the big winning opening, when determining based on the number of detections by the count switch 23 and the number of detections by the winning confirmation switch being a predetermined value (for example, 10) or more. In addition, the count switch 23 when the value of the special symbol process flag is not a value indicating that the game is a big hit game (for example, when the value of the special symbol process flag is not 5 or more, see FIG. 23). Even when a game ball is detected by the above, it may be determined that an abnormal winning to the big winning opening has occurred. In addition, in this way, when it is determined that an abnormal winning to the big winning opening has occurred based on the detection result of the count switch 23 and the winning confirmation switch, or an abnormal to the big winning opening based on the value of the special symbol process flag. Even when it is determined that a winning has occurred, the security signal is externally output by setting a predetermined time (for example, 4 minutes) in the security signal information timer, as in step S128 in the switch normality / abnormality check process. You can do it.

  Further, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, it can be externally output as a security signal from the common connector CN8 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN8 of the board 160. Further, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any error bit in the status register (not shown) of the serial communication circuit 505 being set, The security signal may be externally output from the common connector CN8 of the terminal board 160.

  In addition to the signal line and connector CN8 for security signals, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  In addition to the signal line for security signal output, detection of initialization processing, detection of abnormal winning at the first start winning opening 13, detection of abnormal winning at the second starting winning opening 14, and big winning opening A separate signal line is provided for detection of abnormal prize winning, detection of abnormal magnetic error, detection of abnormal radio wave error, and detection of communication error. From the terminal board 160, corresponding to each error together with the security signal. An external output signal may also be output to an external device such as a hall computer. With such a configuration, it is possible to recognize that an error has occurred by checking the security signal, and further, by checking the signal output for each type of error, the type of error can be determined on the amusement store side. Can be confirmed. Therefore, when an amusement store requires a confirmation of the type of error, an external output signal for each error type is provided separately from the security signal, so that an external output that better meets the needs of the amusement store can be provided. Can be done. On the other hand, in the case of a game shop that only requests confirmation that some kind of error has occurred, only the security signal out of the externally output signals is connected to an external device such as a hall computer. Check it.

  As described above, by providing the semiconductor relays PC1 to PC10 on the terminal board 160, signal input from the outside to the inside of the gaming machine can be prevented, and as a result, illegal acts can be reliably prevented. In the above example, the semiconductor relays PC1 to PC10 are provided on the terminal board 160. However, other relay elements such as a mechanical relay may be used instead of the semiconductor relays PC1 to PC10.

  Next, the operation of the gaming machine will be described. FIG. 9 is a flowchart showing the main processing executed by the CPU 56 of the game control microcomputer 560 in response to the start of power supply to the game machine and the reset signal to the game control microcomputer 560 becoming high level. It is. When the input level of the reset terminal to which the reset signal is input becomes high level, the CPU 56 of the game control microcomputer 560 executes a security check process that is a process for confirming whether the contents of the program are valid. The main processing after step S1 is started. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, an interrupt mode for maskable interrupts is set (step S2), and a stack pointer designation address is set for the stack pointer (step S3). In step S2, the address synthesized from the value (1 byte) of the specific register (I register) of the game control microcomputer 560 and the interrupt vector (1 byte: least significant bit 0) output from the built-in device is Set to the mode indicating the interrupt address. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Next, the CPU 56 starts outputting a connection signal to the payout control microcomputer 370 (step S4). When the CPU 56 starts outputting the connection signal in step S4, the CPU 56 sends a connection signal to the payout control microcomputer 370 unless the power supply of the gaming machine is stopped or output is impossible due to some communication error. Output continuously.

  Next, the built-in device register is set (initialized) (step S5). By the processing in step S5, the CTC (counter / timer) and PIO (parallel input / output port) which are built-in devices (built-in peripheral circuits) are set (initialized).

  The game control microcomputer 560 used in this embodiment also includes an I / O port (PIO) and a timer / counter circuit (CTC) 504.

  Next, the CPU 56 sets the RAM 55 in an accessible state (step S6), and proceeds to a clear signal check process.

  Note that a software delay process for delaying the start timing of the game device control process (game control process) for controlling the progress of the game by software may be executed. By such software delay processing, the start timing of the game control processing can be delayed as compared with the case where the software delay processing is not executed. When the delay process is executed, a situation occurs in which the microcomputer of the other control board cannot receive the command transmitted from the game control board (main board 31) to the other control board (for example, the payout control board 37). Can be prevented.

  Next, the CPU 56 checks whether or not the clear switch is turned on (step S7). Note that the CPU 56 may confirm the state of the clear signal only once via the input port 0, but may confirm the state of the clear signal a plurality of times. For example, if it is confirmed that the state of the clear signal is an off state, after a delay time of a predetermined time (for example, 0.1 seconds), the state of the clear signal is reconfirmed. If it is confirmed that the clear signal is in the on state at that time, it is determined that the clear signal is in the on state. Further, at this time, if it is confirmed that the state of the clear signal is the off state, after a delay time of a predetermined time, the state of the clear signal may be confirmed again. Here, the number of reconfirmations is not limited to once or twice, but may be three or more times. It is also possible to check twice and check again when the check results do not match.

  If the clear switch is not turned on in step S7, whether or not data protection processing of the backup RAM area (for example, power supply stop processing such as addition of parity data) has been performed when power supply to the gaming machine is stopped Confirm (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When it is confirmed that such power supply stop processing has been performed, the CPU 56 determines that the power supply stop processing has been performed, that is, the control state at the time of power supply stop is stored. . When it is confirmed that the power supply stop process is not performed, the CPU 56 executes an initialization process.

  Whether or not the power supply stop process has been performed is determined by the value of the backup monitoring timer stored in the backup RAM area in the power supply stop process corresponding to the execution of the power supply stop process (for example, 2). ) Is confirmed by whether or not. Note that such a confirmation method is an example. For example, a flag indicating that the power supply stop process has been executed is set in the backup flag area in the power supply stop process, and the flag is set in step S8. If it is confirmed that the power supply is stopped, it may be determined that the power supply stop process has been performed.

  If it is determined that the control state at the time of stopping power supply is stored, the CPU 56 performs data check (parity check in this example) in the backup RAM area (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count becomes 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area may be different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, the initialization process (the process of steps S10 to S14) executed when the power is turned on, not when the power supply is stopped is stopped. Run.

  If the check result is normal, the CPU 56 performs a hot start process for resuming the game using the data stored in the RAM 55 that has been backed up (step S91). Further, the CPU 56 sets the head address of the backup command transmission table stored in the ROM 54 as a pointer (step S92), and proceeds to step S15. In addition, after setting in step S92, a backup command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  In the initialization process, the CPU 56 first performs a RAM clear process (step S10). Note that the predetermined data may be left as it is without initializing the entire area of the RAM 55. Further, the start address of the initialization setting table stored in the ROM 54 is set as a pointer (step S11), and the contents of the initialization setting table are sequentially set in the work area (step S12).

  By the processing of steps S11 and S12, for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol buffer, a special symbol process flag, a winning ball flag, a ball-out flag, and the like are selectively processed according to the control state. An initial value is set in a flag for performing the above. An initial value (clear data) is also set in each timer (start port information storage timer, winning information storage timer, security signal information timer, etc.) used to output each external output signal described later.

  Further, the CPU 56 sets the head address of the initialization command transmission table stored in the ROM 54 as a pointer (step S13), and transmits an initialization command for initializing the sub board according to the contents to the sub board. Processing is executed (step S14). As an initialization command, a command indicating an initial symbol displayed on the effect display device 9, an initialization command to the payout control board 37, or the like can be used. After setting in step S13, an initialization command is transmitted after serial communication circuit setting processing in step S15a described later is performed.

  The CPU 56 sets a predetermined time (in this example, 30 seconds) in the security signal information timer (step S14a). The security signal information timer is a timer for measuring the ON time of the security signal output from the terminal board 160. In this embodiment, an initialization process is performed when the gaming machine is turned on by executing an information output process (see S31), which will be described later, based on the fact that a predetermined time is set in the security signal information timer in step S14a. Is executed, a security signal is externally output for a predetermined time (in this example, 30 seconds).

  Further, the CPU 56 executes a random number circuit setting process for initially setting the random number circuit 503 (step S15). In this case, the CPU 56 performs settings according to the random number circuit setting program stored in the ROM 54 in advance, thereby setting the random number circuit 503 to update the random R value.

  Further, the CPU 56 executes a serial communication circuit setting process for initial setting of the serial communication circuit 505 (step S15a). In this case, the CPU 56 sets the data stored in the predetermined area of the ROM 54 in the serial communication circuit 505 according to the serial communication circuit setting program, so that the serial communication circuit 505 performs serial communication with the payout control microcomputer. I do.

  When the serial communication circuit 505 is initialized, the CPU 56 initializes the priority of interrupt processing executed in response to the interrupt request from the serial communication circuit 505 (step S15b). In this case, the CPU 56 initializes the priority of interrupt processing by executing processing according to the interrupt priority setting program 557.

  For example, the CPU 56 initializes the priority of each interrupt process according to a predetermined interrupt process priority table including the default priority of each interrupt process. In this embodiment, the CPU 56 performs an initial setting so as to preferentially execute an interrupt process that causes the occurrence of a communication error in the serial communication circuit 505 according to the interrupt process priority order table. In this case, for example, the CPU 56 sets an interrupt priority execution flag at the time of communication error indicating that priority is given to an interrupt process whose cause is an interrupt.

  In this embodiment, when a timer interrupt and an interrupt request from the serial communication circuit 505 are generated at the same time, the CPU 56 preferentially performs an interrupt process by the timer interrupt.

  In addition, the default priority of each interrupt process can be changed by the user. For example, the game control microcomputer 560 stores specification information for specifying an interrupt process set by a user (for example, a game machine manufacturer) in a predetermined storage area of the ROM 54 in advance. Then, the CPU 56 sets the priority of interrupt processing according to the designation information stored in a predetermined storage area of the ROM 54.

  In addition to steps S15 to S15b, a part of the setting process of the random number circuit 503 and the serial communication circuit 505 is also executed in the process of step S5. For example, in step S5, an initial value is set in the baud rate register, communication setting register, interrupt control register, and status register of the serial communication circuit 505 as the built-in device register.

  In the initialization process of the main process, a process of setting “250” as an initial value to a prize ball number counter used for detecting a prize ball shortage error or a prize ball excess error, which will be described later, is also executed. Note that the process of setting the initial value in the prize ball number counter may be executed, for example, in the hot start process in step S91 or in the process of sequentially setting each initial value in the work area in step S12, and in steps S15 to S17. It suffices if it is executed before the process is shifted.

  Then, the CPU 56 executes a timer interrupt setting process for setting a CTC register built in the game control microcomputer 560 so that a timer interrupt is periodically taken every predetermined time (for example, 4 ms) ( Step S16). That is, a value corresponding to, for example, 4 ms is set in a predetermined register (time constant register) as an initial value. In this embodiment, it is assumed that a timer interrupt is periodically taken every 4 ms.

  When the timer interrupt setting is completed, the CPU 56 first disables the interrupt (step S17), executes the initial value random number update process (step S18a) and the display random number update process (step S18b), The interrupt is permitted again (step S19). That is, the CPU 56 sets the interrupt disabled state when the initial value random number update process and the display random number update process are executed, and interrupts enable state when the initial value random number update process and the display random number update process are finished. To.

  The initial value random number update process is a process of updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining the type of jackpot (for example, a jackpot symbol determining random number for determining a special symbol for generating a jackpot or whether to shift the gaming state to a probable state) Initial value of the count value such as a counter (determination random number generation counter) for generating a probability variation determining random number for generating, a normal random number for determining whether or not to generate a hit based on a normal symbol It is a random number for determining the value. A game control process described later (a process in which a game control microcomputer controls itself a game device such as an effect display device 9, a variable winning ball device 15, a ball payout device 97 provided in the gaming machine, or When the count value of the determination random number generation counter makes one round in a process of transmitting a command signal to cause another microcomputer to control, or a gaming apparatus control process), an initial value is set in the counter.

  The display random number is a random number for determining the display of the first special symbol display 8a and the second special symbol display 8b. In this embodiment, as a display random number, a random number for determining a variation pattern for determining a variation pattern of a special symbol, or a random number for determining a reach for determining whether or not to reach when a big hit is not generated, is used. Used. The display random number update process is a process for updating the count value of the counter for generating the display random number.

  In addition, when the display random number update process is executed, the interrupt disabled state is executed by the display random number update process and the initial value random number update process also in the timer interrupt process described later (that is, the timer This is because the same process is executed in steps S26 and S27 of the interrupt process), so as to avoid conflict with the process in the timer interrupt process. That is, if a timer interrupt is generated during the processing of steps S18a and S18b and the count value of the counter for generating the initial value random number and the display random number is updated during the timer interrupt processing, The continuity of values may be impaired. However, such an inconvenience does not occur if the interrupt is prohibited during the processing of steps S18a and S18b.

  When the interrupt-permitted state is set in step S19, the timer interrupt or interrupt request from the serial communication circuit 505 is permitted until the next processing in step S17 is executed and the interrupt-prohibited state is set. . When a timer interrupt occurs while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 executes a timer interrupt process to be described later. If an interrupt request is generated from the serial communication circuit 505 while the interrupt permission state is set, the CPU 56 of the game control microcomputer 560 causes each interrupt process (communication error interrupt process, reception time interrupt, Load processing, transmission completion interrupt processing). In this embodiment, priority is given to the interrupt process before the timer interrupt or the interrupt request is set to be permitted by executing step S15b before the loop process from step S17 to step S19. Processing for setting or changing the order is performed.

  Next, the hot start process in step S91 will be described. FIG. 10 is a flowchart illustrating an example of the hot start process. In the hot start process, the CPU 56 first sets the start address of the backup setting table stored in the ROM 54 as a pointer (step S9101), and sequentially stores the contents of the backup setting table in the work area (area in the RAM 55). Setting is performed (step S9102). The work area is backed up by a backup power source. Initialization data (for example, a prize ball process code, a prize ball process timer, a frame status display buffer, and a previous frame status display buffer) for an area that may be initialized in the work area is set in the backup setting table. Yes. As a result of the processing in steps S9101 and S9102, the saved contents of the work area that should not be initialized remain as they are. The parts that should not be initialized include, for example, data indicating the gaming state before the power supply is stopped (special symbol process flag, etc.), the area where the output state of the output port is saved (output port buffer), unpaid prize balls This is the part where data indicating the number is set.

  The CPU 56 also outputs a high-probability output permission flag for permitting external output via the terminal board 160 of a high-probability signal indicating that the gaming state is controlled to a high probability state (probability change state). Is set (step S9103). Instead of unconditionally setting the high-accuracy output permission flag, first, it is confirmed whether or not it is in a high-probability state (probability variation state) (specifically, the probability variation flag stored in the backup RAM). It is also possible to set the high-accuracy output permission flag on the condition that it is in a high-probability state (probability variation state). As such, at the start of power supply, the high-accuracy output permission flag may be set unconditionally, or the high-accuracy output flag may be set on the condition that it is in a high probability state (probability variation state). .

  In addition, the CPU 56 clears a prize information storage timer for measuring a prize signal output time, which will be described later (step S9104). In other words, in this embodiment, the value of the winning information storage timer is stored in the power-backed RAM 55 and is maintained for a predetermined time even when the power supply is stopped, but the process of step S9104 is executed. Cleared when power is restored. As described above, in this embodiment, in the common hot start process, the setting process of the high-accuracy output permission flag and the clearing process of the winning information storage timer can be executed, and the process routine is shared. The control burden on the game control microcomputer 560 is reduced.

  For example, in the backup setting table, a value for setting the high-accuracy output permission flag (for example, logical value “1”) or a value for clearing the winning information storage timer (for example, clear data “ 0 ") may also be set and step S9102 may be executed to turn on the high-accuracy output permission flag and clear the winning information storage timer. In this case, for example, based on the backup time setting table, the value of the high-accuracy medium output permission flag in the work area is set to the on state (for example, a logical value “1” is written), or a prize is awarded in the work area. Clear data may be written to the value of the information storage timer. By doing so, it is possible to use a single data table (setting table at the time of backup) to share the setting processing of the high-accuracy output permission flag and the clearing processing of the winning information storage timer, and the game control micro The control burden on the computer 560 can be further reduced.

  Next, the timer interrupt process will be described. FIG. 11 is a flowchart showing the timer interrupt process. When a timer interrupt occurs during execution of the main process, specifically, in a period during which interruption is permitted during execution of the loop process of steps S17 to S19, the CPU 56 of the game control microcomputer 560 A timer interrupt process that is activated in response to the occurrence of a timer interrupt is executed. In the timer interrupt process, the CPU 56 first executes a power-off process (power-off detection process) for detecting whether or not a power-off signal is output (whether the power-on signal is turned on) (step S20). Then, the CPU 56 detects switches such as the gate switch 32a, the first start port switch 13a, the second start port switch 14a, the winning confirmation switch 14b, the count switch 23, and the winning port switches 29a and 30a through the switch circuit 58. A signal is input and the input of each switch is detected (switch processing: step S21). Specifically, if the state of the input port for inputting the detection signal of each switch is ON, the value of the switch timer provided corresponding to each switch is incremented by one.

  Next, the CPU 56 has a first special symbol display 8a, a second special symbol display 8b, a normal symbol display 10, a first special symbol hold storage display 18a, a second special symbol hold storage display 18b, a normal symbol. A display control process for controlling the display of the on-hold storage display 41 is executed (step S22). For the first special symbol display 8a, the second special symbol display 8b, and the normal symbol display 10, a drive signal is output to each display according to the contents of the output buffer set in steps S36 and S37. Execute control to

  Next, the CPU 56 executes magnet sensor error notification processing for performing magnet sensor error notification based on the detection signal input from the magnet sensor (step S24).

  Next, the CPU 56 performs a process of updating the count value of each counter for generating each determination random number such as a random number for determination per ordinary symbol used for game control (determination random number update process: step S25). Further, the CPU 56 performs a process of updating the count value of the counter for generating the initial value random number (initial value random number update process: step S26). Further, the CPU 56 performs a process of updating the count value of the counter for generating the display random number (display random number update process: step S27).

  Next, the CPU 56 performs special symbol process processing (step S28). In the special symbol process, the corresponding process is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S29). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the effect symbol synchronized with the variation of the special symbol in the transmission data register of the serial communication circuit 505 and sending the effect control command (effect control command control process: step S30). . It should be noted that the fact that the variation of the effect symbol is synchronized with the variation of the special symbol means that the variation time (variable display period) is the same.

  Next, the CPU 56 outputs, for example, data such as a symbol determination number 1 signal, a start opening signal, a jackpot signal 1-3, a time reduction signal, a winning signal, a security signal, and a high accuracy signal supplied to the hall management computer. Information output processing is performed (step S31).

  Next, the CPU 56 executes processing for transmitting / receiving (input / output) signals to / from the payout control microcomputer 370 via the serial communication circuit 505, and when a winning occurs, detection of the winning opening switches 29a, 30a, etc. Prize ball processing is performed for setting the number of prize balls based on the signal (step S32). In this embodiment, data indicating the number of winning balls is obtained by changing the lower 4 bits of the winning ball number command in response to detection of winning based on the winning opening switch 29a, 30a being turned on. The set prize ball number command is output to the payout control microcomputer 370 via the serial communication circuit 505. The payout control microcomputer 370 mounted on the payout control board 37 drives the ball payout device 97 in response to receiving a prize ball number command in which data indicating the number of prize balls is set.

  In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S33).

  Further, in this embodiment, a RAM area (output port buffer) corresponding to the output state of the output port is provided. Is output to the output port (step S34: output processing). And CPU56 performs the memory | storage process which checks the increase / decrease in a pending | holding memory | storage number (step S35).

  Further, the CPU 56 performs special symbol display control processing for setting special symbol display control data for effect display of the special symbol in the output buffer for setting the special symbol display control data according to the value of the special symbol process flag ( Step S36). Further, the CPU 56 performs a normal symbol display control process for setting normal symbol display control data for effect display of the normal symbol in an output buffer for setting the normal symbol display control data according to the value of the normal symbol process flag ( Step S37).

  Next, the CPU 56 performs a status display lamp display process for setting status display control data for displaying each status display lamp in an output buffer for setting the status display control data (step S38). In this case, when the gaming state is the short time state, the state display control data for displaying the state indicator lamp indicating the short time state is set in the output buffer. When the gaming state is also controlled to a high probability state (for example, a probability variation state), state display control data for displaying a state indicator lamp indicating the high probability state is set in the output buffer. You may do it.

  Next, the CPU 56 performs a frame state output process for transmitting a frame state display command in which information indicating the error state of the gaming machine is set to the effect control microcomputer 100 in order to display the error state of the gaming machine. Execute (Step S39).

  Thereafter, the interrupt permission state is set (step S40), and the process ends.

FIG. 12 is an explanatory diagram showing each random number. Each random number is used as follows.
(1) Random 1 (MR1): Determine the type of jackpot (for jackpot type determination)
(2) Random 2 (MR2): A variation pattern (variation time) is determined (for variation pattern determination)
(3) Random 4 (MR3): Determines whether or not to generate a hit based on the normal symbol (for normal symbol hit determination)
(4) Random 5 (MR3): Determine the initial value of random 3 (for determining the random 4 initial value)

  In step S25 in the game control process shown in FIG. 11, the game control microcomputer 560 uses a counter for generating (1) a big hit type determination random number and (3) a normal symbol determination random number. Count up (add 1). That is, they are determination random numbers, and other random numbers are display random numbers (random 2) or initial value random numbers (random 4). In addition, in order to improve a game effect, you may use random numbers other than said random number. In this embodiment, a random number generated by hardware incorporated in the game control microcomputer 560 (or hardware external to the game control microcomputer 560) is used as the jackpot determination random number.

  FIG. 13 is an explanatory diagram showing a jackpot determination table. The jackpot determination table is a collection of data stored in the ROM 54 and is a table in which a jackpot determination value to be compared with the random R is set. The jackpot determination table includes a normal-time jackpot determination table used in a normal state (a gaming state that is not a probability change state) and a probability change jackpot determination table used in a probability change state. Each numerical value described in the left column of FIG. 13 is set in the normal jackpot determination table, and each numerical value described in the right column of FIG. 13 is set in the probability changing big hit determination table. The numerical values described in FIG. 13 are jackpot determination values.

  The CPU 56 extracts the count value of the random number circuit 503 at a predetermined time and sets the extracted value as the value of the jackpot determination random number (random R). If it matches the big hit judgment value, it is decided to make a big hit (normal big hit (non-probable big hit), probable big hit) for the special symbol. Note that the “probability” shown in FIG. 13 indicates the probability (ratio) of a big hit. Further, deciding whether or not to win a jackpot means deciding whether or not to shift to the jackpot gaming state, but the stop symbol in the first special symbol display 8a or the second special symbol display 8b is determined. It also means deciding whether or not to make a jackpot symbol.

  FIG. 14 is an explanatory diagram showing a jackpot type determination table stored in the ROM 54. In the jackpot type determination table shown in FIG. 14, when it is determined that the variable display result is a jackpot symbol, the jackpot type is determined based on a random number (random 1) for determining the jackpot type. ”,“ 10R probability big hit ”,“ 15R normal big hit ”, and“ 10R normal big hit ”.

  There are a plurality of types in each of “15R probable big hit”, “10R probable big hit”, “15R normal big hit”, and “10R normal big hit”. In the example shown in FIG. 14, there are nine types of jackpot types.

  The 15R probability variable big hit and the 15R normal big hit are big hits that are allowed up to a large number of times (for example, 15 rounds (15 rounds)) of the big winning opening in the big hit gaming state. In the case of 15R probability change big hit, when the big hit gaming state ends, the gaming state is changed to the probability changing state. The 10R probability variable big hit and the 10R normal big hit are big hits that are permitted up to a relatively small number of times (for example, 10 rounds (10 rounds)) in the big hit gaming state. In the case of 10R probability variation big hit, when the big hit gaming state ends, the gaming state is changed to the probability varying state.

  Further, as shown in FIG. 14, when any type of big hit occurs, after the big hit game is finished, the gaming state shifts to a short time state (also referred to as a high base state). In the high base state, the opening time of the variable winning ball device 15 becomes longer and the number of times of opening is increased. That is, it becomes easy for the game ball to start and win (that is, the condition for executing variable display in the special symbol indicators 8a and 8b and the effect display device 9 is easily established).

  Instead of extending the time during which the variable winning ball apparatus 15 is in the open state (also referred to as the open extended state), the normal symbol display unit 10 shifts to a normal symbol probability changing state in which the probability that the stop symbol in the normal symbol display unit 10 is a hit symbol is increased. Depending on the situation, the high base state may be entered. When the stop symbol in the normal symbol display 10 becomes a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In this case, by performing the transition control to the normal symbol probability changing state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the frequency at which the variable winning ball apparatus 15 is opened is increased. Therefore, if the normal symbol probability changing state is entered, the opening time and the number of opening times of the variable winning ball device 15 are increased, and a state where it is easy to start a winning (high base state) is achieved. That is, the opening time and the number of times of opening of the variable winning ball device 15 can be increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol. It changes to an advantageous state (a state where it is easy to win a start). It should be noted that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Moreover, you may transfer to a high base state by shifting to the normal symbol time short state where the fluctuation time (variable display period) of the normal symbol in the normal symbol display 10 is shortened. In the normal symbol short-time state, the variation time of the normal symbol is shortened, so that the frequency of starting the variation of the normal symbol increases, and as a result, the frequency of hitting the normal symbol increases. Therefore, when the frequency that the normal symbol is won increases, the frequency that the variable winning ball apparatus 15 is opened is increased, and the start winning state is easily set (high base state).

  Therefore, the short time state (high base state) corresponds to a high frequency state in which a game ball enters the start area at a high frequency.

  Further, as shown in FIG. 14, the high base state continues until a predetermined number of variable displays (variable display) is executed or until the next big hit occurs, but the number of continuous times (executes in the high base state). The number of possible variable displays) depends on the type of jackpot.

  The type of jackpot and the type of stop symbol of the special symbol uniquely correspond to each other.

  In this embodiment, the jackpot type is determined using a predetermined random number, but the stop pattern of the special symbol is determined using the predetermined random number, and the jackpot type is determined according to the determined special symbol type. It may be determined.

  FIG. 14 (A) shows a case where the jackpot type is determined by using the stored memory based on the fact that the game ball has won the first start winning opening 13 (that is, when the first special symbol variation display is performed). A big hit type determination table (for the first special symbol) is shown. FIG. 14B shows a case in which the jackpot type is determined using the holding memory based on the fact that the game ball has won the second start winning opening 14 (that is, when the second special symbol is displayed in a variable manner). A big hit type determination table (for the second special symbol) is shown.

  In the high base state, there are more opportunities for the game ball to win the second start winning opening 14 than for the game ball to win the first start winning opening 13, so the second special symbol shown in FIG. There are many occasions where the big hit type determination table for use is used. Also, in the low base state (the state that is not the short-time state), there is no opportunity for the game ball to win the second start winning opening 14, so the jackpot type determination table for the first special symbol shown in FIG. 14 (A) is used. Is done.

  FIG. 15 is an explanatory diagram showing a variation pattern table stored in the ROM 54. In this embodiment, as shown in FIG. 15, there are three variation pattern tables, tables A to C, as the variation pattern tables. Each variation pattern table stores determination values corresponding to the variation patterns. FIG. 15 shows the number of determination values, not the determination value itself.

  Table A is a variation pattern table used when the gaming state is the high base state and the game state is shifted. Table B is a variation pattern table used when the gaming state is the low base state and the game state is shifted. Table C is a variation pattern table used in the case of a big hit.

  In FIG. 15, “no reach” is a change mode (effect mode) in which the reach effect is not executed during the change of the decorative symbol. “Reach α” is a variation mode in which reach production of reach α is executed during the variation of the decorative design, and “reach β” is a reach β that is different from the reach α during the variation of the decorative design. This is a variation mode in which the reach effect is executed. “Reach γ” is a variation mode in which a reach effect of reach γ, which is different from reach α and reach β, is executed during the variation of the decorative design.

  FIG. 16 is an explanatory diagram showing an example of the contents of the effect control command transmitted by the game control microcomputer 560. In the example shown in FIG. 16, the command 80XX (H) is an effect control command (variation pattern command) for designating a variation pattern of a decorative symbol that is variably displayed on the effect display device 9 in response to variable display of a special symbol. (Corresponding to the variation pattern XX, respectively). That is, when a unique number is assigned to each of the usable variation patterns shown in FIG. 15, there is a variation pattern command corresponding to each variation pattern specified by the number. “(H)” indicates a hexadecimal number. The effect control command for designating the variation pattern is also a command for designating the start of variation. Therefore, when the effect control microcomputer 100 receives the command 80XX (H), the effect display device 9 controls the effect display device 9 to start variable display of decorative symbols.

  Further, in this embodiment, if the variation pattern is the same, a common variation pattern command is used for the case where the big hit and the case where the big pattern is lost. However, the variation pattern command that specifies the variation pattern that is used when the variation pattern command that is used in the case of the big hit is different from the variation pattern command that is used when the variation pattern command is different. That is, the variation pattern command used in the case of a big hit may not be used in the case of a loss.

  Commands 8C01 (H) to 8C0A (H) are effect control commands (display result designation commands) indicating whether or not to make a big hit and the type of big hit. The effect control microcomputer 100 determines the display result of the decorative symbols in response to the reception of the commands 8C01 (H) to 8C0A (H). Therefore, the commands 8C01 (H) to 8C0A (H) are also referred to as display result specifying commands. .

  Command 8D01 (H) is an effect control command (first symbol variation designation command) indicating that variable display (variation) of the first special symbol is started. Command 8D02 (H) is an effect control command (second symbol variation designation command) indicating that variable display (variation) of the second special symbol is started. The first symbol variation designation command and the second symbol variation designation command may be collectively referred to as a special symbol specifying command (or symbol variation designation command). Note that information indicating whether to start variable display of the first special symbol or variable display of the second special symbol may be included in the variation pattern command.

  Command 8F00 (H) is an effect control command (symbol confirmation designation command) indicating that the variable display (fluctuation) of the decorative symbols is terminated and the display result (stop symbol) is derived and displayed.

  Command 9000 (H) is an effect control command (initialization designation command: power-on designation command) transmitted when power supply to the gaming machine is started. Command 9200 (H) is an effect control command (power failure recovery designation command) transmitted when power supply to the gaming machine is resumed. When the power supply to the gaming machine is started, the gaming control microcomputer 560 transmits a power failure recovery designation command if data is stored in the backup RAM, and if not, initialization designation is performed. Send a command.

  Command 9F00 (H) is an effect control command (customer waiting demonstration designation command) for designating a customer waiting demonstration.

  Command A001 (H) is an effect control command for displaying a fanfare screen, that is, designating the start of a big hit game (hereinafter also referred to as a big hit start designation command or a fanfare designation command).

  The command A1XX (H) is an effect control command (special command during opening of a big winning opening) indicating a display during the opening of the big winning opening for the number of times (round) indicated by XX. A2XX (H) is an effect control command (designation command after opening the big winning opening) indicating the closing of the big winning opening for the number of times (round) indicated by XX.

  The command A301 (H) is an effect control command (hereinafter also referred to as a jackpot end designation command or an ending designation command) for displaying a jackpot end screen (ending screen), that is, for ending the jackpot game.

  The command A4XX (H) is an effect control command (short time duration count command) that designates the short duration duration indicated by XX. The number of time-continuations is the number of variable displays that can be executed in the high base state, but when the high base state continues until a predetermined number of variable displays (variable display) is executed, “XX” FF "is set.

  Command B001 (H) is an effect control command (high base state designation command) for designating that the gaming state is the high base state. Command B002 (H) is an effect control command (low base state designation command) that designates that the gaming state is in the low base state. The high base state designation command and the low base state designation command may be collectively referred to as a base state designation command.

  Command B101 (H) is an effect control command (high probability state designation command) that designates that the gaming state is a probability variation state (high probability state). Command B102 (H) is an effect control command (low probability state designation command) that designates the normal state. The high probability state designation command and the low probability state designation command may be collectively referred to as a probability state designation command.

  Command C000 (H) is an effect control command (first reserved memory number addition designation command) that specifies that the first reserved memory number has increased by one. Command C100 (H) is an effect control command (second reserved memory number addition designation command) that specifies that the second reserved memory number has increased by one.

  Command C200 (H) is an effect control command (first reserved memory number subtraction designation command) that specifies that the first reserved memory number has decreased by one. Command C300 (H) is an effect control command (second reserved memory number subtraction designation command) that specifies that the second reserved memory number has decreased by one.

  In this embodiment, an effect control command indicating that the reserved memory number has increased or decreased is transmitted for the total reserved memory number, but an effect control command for designating the reserved memory number itself is transmitted. Also good.

  Next, the prize ball process (step S32 in the timer interrupt process) will be described. FIG. 17 is a flowchart illustrating an example of the prize ball processing in step S32. In the prize ball process, the game control microcomputer 560 (specifically, the CPU 56), the prize ball command output counter addition process (step S501), the prize ball control process (step S502), and the prize ball counter subtraction process (step S503). ).

  In the prize ball command output counter addition process, a prize ball number table shown in FIG. 18 is used. The prize ball number table is set in the ROM 54. The number of processes (in this example, “5”) is set to the start address of the prize ball number table, and then the lower address of the switch-on buffer, the lower address of the prize ball command output counter, the switch input bit designation value, The prize ball number data for designating the number of prize balls is sequentially set. The prize ball command output counter is a counter that counts the number of prizes received in the prize opening, and is set in the ROM 54, for example. The game control microcomputer 560 includes a corresponding prize ball command output counter for each number of prize balls (0 to 15). In this embodiment, the game control microcomputer 560 includes a prize ball command output counter 1 corresponding to the prize ball number “15” and prize ball command output counters 2 and 3 (2) corresponding to the prize ball number “10”. Corresponding to the normal winning ports 29 and 30), and prize ball command output counters 4 and 5 corresponding to the number of prize balls “3”. Each prize ball command output counter is counted up by prize ball command output counter addition processing, as will be described later. If the prize ball command output counter 1 set in the prize ball number table is not 0, the CPU 56 indicates the prize ball number (15) based on the prize ball number data designating the prize ball number (15). The data is set in the lower 4 bits of the prize ball number command, and the set prize ball number command is transmitted to the payout control microcomputer 370. The CPU 56 determines the number of prize balls (10) if the value of the prize ball command output counter 1 set in the prize ball number table is 0 and the value of the prize ball command output counters 2 and 3 is not 0. Data indicating the number of winning balls (10) is set in the lower 4 bits of the winning ball number command, and the set winning ball number command is transmitted to the payout control microcomputer 370. To do. Further, the CPU 56 must set the value of the prize ball command output counter 1 and the prize ball command output counters 2 and 3 set in the prize ball number table to 0, and the value of the prize ball command output counters 4 and 5 must be 0. For example, data indicating the number of winning balls (3) is set in the lower 4 bits of the winning ball number command based on the winning ball number data designating the number of winning balls (3), and the set winning ball number command is set. Is sent to the payout control microcomputer 370. In FIG. 18, the switch-on buffer 1 corresponds to the input port 0 and the switch-on buffer 2 corresponds to the input port 2.

  19 and 20 are flowcharts showing the prize ball command output counter addition processing in step S501. In the prize ball command output counter addition process, the game control microcomputer 560 (specifically, the CPU 56) sets the start address of the prize ball number table as a pointer (step S5101). Then, the data at the address pointed to by the pointer (in this case, the number of processes) is loaded (step S5102).

  Next, the CPU 56 increments the pointer value by 1 (step S5103), loads the lower address of the switch-on buffer pointed to by the pointer into the lower byte of the pointer buffer (step S5104), and loads the switch-on buffer pointed by the pointer buffer into the register. (Step S5105). Next, the CPU 56 increments the value of the pointer by 1 (step S5106), and loads the lower address of the prize ball command output counter pointed to by the pointer into the lower byte of the pointer buffer (step S5107). Next, the CPU 56 increments the value of the pointer by 1 (step S5108), and calculates the logical product of the contents of the switch-on buffer loaded into the register and the switch winning bit designation value pointed to by the pointer (step S5109). Then, the CPU 56 increases the value of the pointer by 1 (step S5110). When the pointer value is incremented by 1 in step S5110, the pointer value indicates the address where the prize ball number data in the prize ball number table is stored.

  Next, if the calculation result in step S5109 is 0 (Y in step S5111), that is, if the detection signal of the switch to be inspected is not in the on state, the CPU 56 decreases the number of processes by 1 (step S5128). If NO is 0, the process is terminated. If the number of processes is not 0, the process returns to step S5103 (step S5129).

  If the calculation result in step S5109 is not 0 (N in step S5111), that is, if the detection signal of the switch to be inspected is on, the CPU 56 performs processing for exchanging the pointer buffer value and the pointer value. This is performed (step S5112). In this case, the value of the pointer indicates the address where the prize ball number data in the prize ball number table is stored by executing the process of step S5110, and the value of the pointer buffer is the value of step S5107. As a result, the lower address of the prize ball command output counter has been loaded, so that the value of the pointer buffer becomes the number of prize balls by executing the exchange process in step S5112. The table indicates the address where the prize ball number data is stored, and the value of the pointer indicates the lower address of the prize ball command output counter.

  Next, the CPU 56 adds 1 to the value of the prize ball command output counter pointed to by the pointer (step S5113). However, when a carry occurs in the value of the prize ball command output counter as a result of the addition, the CPU 56 subtracts 1 from the value of the prize ball command output counter and restores the original value (steps S5114 and S5115). Then, the process proceeds to step S5116. In steps S5113 to S5115, the CPU 56 first loads the value of the prize ball command output counter into the register, adds 1 to the value of the register, and that no carry has occurred in the value of the register after the addition. After confirming, the value after addition may be stored in the prize ball command output counter. By doing so, it is possible to prevent the waste of subtracting again after adding the value of the prize ball command output counter.

  Next, the CPU 56 counts the cumulative value of the expected number of winning balls based on the detection of winning in any one of the winning winning openings (start winning winning openings 13, 14, large winning opening, ordinary winning openings 29, 30). The lower address of the winning counter is loaded into the lower byte of the pointer (step S5116). Next, the CPU 56 loads prize ball number data pointed to by the pointer buffer (step S5117). Next, the CPU 56 reads the value of the winning counter pointed by the pointer, and adds the read value to the number of winning balls indicated by the winning ball number data loaded in step S5117 (step S5118). By executing the calculation in step S5118, the cumulative value of the expected number of winning balls obtained by adding the number of winning balls for the newly generated winning ball is obtained. Then, the CPU 56 subtracts 1 from the value of the pointer (step S5119).

  In this embodiment, in the ROM 54, the winning information storage counter is set in the area of the address immediately before the area where the winning counter is set. The winning information storage counter is a counter for counting the number of possible output of winning signals. For example, if the value of the winning information storage counter is 1, a winning signal is output once in an information output process described later. If the value of the winning information storage counter is 2, control for outputting the winning signal twice is performed in the information output process described later. In this embodiment, the pointer value is decremented by 1 in step S5119, so that the pointer value indicates the lower address of the prize ball information output counter.

  Next, the CPU 56 checks whether or not the cumulative value of the expected number of winning balls calculated in step S5118 is equal to or greater than a predetermined winning output determination value (10 in this example) (step S5120). If the cumulative value of the planned number of winning balls is equal to or greater than a predetermined winning output determination value (10 in this example), the CPU 56 determines a predetermined winning output determination value from the cumulative value of the planned number of winning balls calculated in step S5118. (10 in this example) corresponding to is subtracted (step S5121). Then, the CPU 56 adds 1 to the value of the winning information storage counter pointed to by the pointer (step S5122). However, when a carry occurs in the value of the winning information storage counter as a result of the addition, the CPU 56 subtracts 1 from the value of the winning information storage counter and restores the original value (steps S5123 and S5124). Then, the process returns to step S5120. In steps S5122 to S5124, the CPU 56 first loads the value of the winning information storage counter into the register, adds 1 to the register value, and confirms that no carry has occurred in the register value after the addition. After confirmation, the value after addition may be stored in the winning information storage counter. By doing so, it is possible to prevent wasteful re-subtraction after adding the value of the winning information storage counter.

  On the other hand, if the cumulative value of the estimated number of winning balls calculated in step S5118 is not equal to or greater than a predetermined winning output determination value (10 in this example) (that is, less than 9), the process proceeds to step S5125.

  By executing the processing of steps S5120 to S5124, in this embodiment, every time a predetermined number of payout conditions are satisfied (every time 10 winning balls are won), the winning information storage counter The value is incremented by 1, and a winning signal is output to the outside by an information output process described later.

  In addition, the cumulative value of the planned number of prize balls calculated in step S5118 may be 20 or more. For example, if the count value of the winning counter is 9, and a winning to the big winning opening occurs and 15 new winning balls are generated, the cumulative value of the expected number of winning balls in step S5118. Will be required as 24. In this case, it is determined as Y in step S5120, and the value of the winning information storage counter is incremented by 1 in step S5122 (in this case, the cumulative value of the expected number of winning balls is subtracted by 10 in the process of step S5121 to become 14). ) Once again, it is determined as Y in step S5120, the value of the prize information storage counter is incremented by 1 in step S5122, and the value of the prize information storage counter is incremented by 2 while one prize ball command output counter addition process is executed. Will be.

  In this embodiment, in the prize ball command output counter addition process during the prize ball process, whether or not the cumulative value of the planned number of prize balls is 10 or more by executing the processes of steps S5120 to S5124. It is shown that the control is performed so that the winning information storage counter is added and the winning signal is output, but the winning signal output processing method is limited to that shown in this embodiment. I can't. For example, in the prize ball command output counter addition process, only the prize counter addition process is performed. In the information output process in step S31, it is determined whether the value of the prize counter is 10 or more. If there is, it may be controlled to output a winning signal. In this case, similarly to the above, if the value of the winning counter is 20 or more, in the information output process, the process of determining whether the value of the winning counter is 10 or more is repeatedly executed, and the value of the winning information storage counter May be processed so that the winning signal can be output twice.

  In addition, for example, in this embodiment, after the winning information storage counter is updated, a winning signal is externally output based on the value of the winning information storage counter in the information output processing described later. Instead of using the winning information storage counter, if it is determined in step S5120 that the accumulated value is 10 or more, the winning signal external output processing may be immediately performed within the winning ball command output counter addition processing. . In this case, in this embodiment, the result accumulated value of the calculation in step S5118 is 10 or more and less than 20, and it is necessary to output the winning signal once, and the result accumulated value of the calculation in step S5118 is 20 or more (this In the embodiment, there are two cases where it is necessary to output the winning signal twice, never exceeding 30). Therefore, for example, as a table for outputting a winning signal, a table for outputting a winning signal once (a table in which the ON time and OFF time of one winning signal are set) and a winning signal are continuously provided. A table for outputting twice (a table in which the on time and off time of the winning signal for two times are set) may be prepared. Then, if the calculated accumulated value is 10 or more and less than 20, a control for outputting the winning signal once outside is performed in the winning ball command output counter addition process using the table for outputting the winning signal once. If the calculated cumulative value is 20 or more, a table for outputting the winning signal twice is used, and the control for outputting the winning signal twice continuously in the winning ball command output counter addition process is performed. May be.

  If the cumulative value calculated in step S5118 exceeds 20, as described above, the winning signal is continuously generated in the winning ball command output counter adding process using the table for outputting the winning signal twice. In the prize ball command output counter addition process, the determination process in step S5120 is repeatedly performed until the calculation result is less than 10, and the winning signal is externally output twice in succession. You may do it. Also, for example, when the winning ball command output counter addition process executed within one timer interrupt is performed so that a winning signal is output only once, and when the next timer interrupt is executed, the winning ball command output counter addition process is executed. The next winning signal may be externally output based on the accumulated value being 10 or more.

  Next, in step S5125, the CPU 56 adds 1 to the pointer value (therefore, the pointer value returns to the state indicating the lower address of the winning counter). Next, the CPU 56 stores the calculation result of the cumulative value of the expected number of winning balls in the winning counter indicated by the pointer (step S5126). In this case, if the process proceeds to step S5125 and subsequent steps without being determined as Y once in step S5120, the cumulative value of the expected number of winning balls obtained in step S5118 is stored as it is in the winning counter. become. If it is determined as Y in step S5120 and the processing from step S5121 is executed, the cumulative value of the planned number of winning balls after subtraction is stored in the winning counter in step S5121. As a result of the determination process in step S5120 and the subtraction process in step S5121, the value less than 10 is always stored in the winning counter in step S5126.

  Next, the CPU 56 performs a process of exchanging the pointer buffer value and the pointer value (step S5127). In this case, since the address at which the winning ball number data in the winning ball number table is stored is saved in the pointer buffer by executing the process of step S5112, the processing of step S5127 is executed. The pointer value is returned to the state indicating the address where the prize ball number data in the prize ball number table is stored again.

  Then, the CPU 56 reduces the number of processes by 1 (step S5128), ends the process if the number of processes is 0, and returns to step S5103 if the number of processes is not 0 (step S5129).

  FIG. 21 is a flowchart showing the prize ball control process in step S502. In the prize ball control process, the game control microcomputer 560 (specifically, the CPU 56) executes any one of steps S521 to S525 in accordance with the value of the prize ball process code.

  In the prize ball transmission process 1 (step S521), the CPU 56 performs a process of transmitting a connection confirmation command to the payout control microcomputer 370. In the winning ball connection confirmation process (step S522), when the connection OK command corresponding to the connection confirmation command is received from the payout control microcomputer 370 from the payout control microcomputer 370, the CPU 56 is indicated by the connection OK command. Processing for transmitting error information indicating an error related to payout control to the effect control microcomputer 100 is performed. In the prize ball transmission process 2 (step S523), when an error has not occurred in the payout control, the CPU 56 performs control to send a prize ball number command indicating the number of prize balls to be paid out to the payout control microcomputer 370. Do. In the prize ball reception confirmation process (step S524), the CPU 56 performs a process according to the command transmitted from the payout control microcomputer 370 in accordance with the transmitted prize ball number command. In the winning ball end confirmation process (step S525), the CPU 56 performs processing according to whether or not the paying out of the winning ball has ended.

  FIG. 22 is a flowchart showing the prize ball counter subtraction process in step S503. In the prize ball counter subtraction process, the CPU 56 first checks whether or not the prize ball information input invalid timer has timed out (step S5301). The prize ball information input invalid timer is a timer that is measured in order to provide an interval period after confirming the input of prize ball information until confirming the next prize ball information. If not timed out, the CPU 56 subtracts 1 from the value of the prize ball information input invalid timer (step S5302) and ends the process.

  If the prize ball information input invalid timer has timed out, the CPU 56 inputs the contents of the input port 0 (step S5303), and checks whether or not the bit of the prize ball information is on (step S5304). If the bit of the prize ball information is on, the process proceeds to step S5305.

  In step S5305, the CPU 56 sets a predetermined prize ball information confirmation count (for example, 8) as the number of processes (step S5305). Then, the CPU 56 confirms whether or not the prize ball information is input, and if the input of the prize ball information can be confirmed, the CPU 56 adds the value of the prize ball information on counter to 1 and the number of processes (8 in this example). The process is repeated until the process is completed (steps S5306 to S5308).

  Next, the CPU 56 checks whether or not the value of the prize ball information on counter is 6 or more (step S5309). If the value of the prize ball information on counter is 6 or more, the CPU 56 sets a predetermined time (for example, 0.8 seconds) in the prize ball information input invalid timer (step S5310) and sets the value of the prize ball number counter to 10 Subtraction is performed (step S5311).

  By executing the above processing, in this embodiment, it is determined that the prize ball information has been inputted on the condition that the prize ball information has been inputted 6 times or more out of the 8 confirmation processes, and 10 pieces of prize ball information are entered. The value of the prize ball number counter is decremented by 10 assuming that the prize ball has been paid out. By such processing, in this embodiment, the situation where it is determined that the prize ball information is erroneously input is reduced, and the game control microcomputer 560 side cannot properly grasp the number of prize balls that have not been paid out. It is preventing.

  Next, the CPU 56 checks whether or not the count value after subtraction is less than a predetermined prize ball excess determination value (for example, 0) (step S5312). When the count value of the prize ball number counter is less than a predetermined prize ball excess determination value (for example, 0), the CPU 56 checks whether or not the prize ball error flag is already set (step S5313). If the prize ball error flag has already been set, the process is terminated. If the prize ball error flag is not set, the CPU 56 sets a prize ball error flag (step S5314) and controls to send a prize ball excess error command to the effect control microcomputer 100 (step S5315). Specifically, the CPU 56 performs a process of setting the address of the winning ball excessive error command transmission table as a pointer. Then, based on the fact that the address of the prize ball excessive error command transmission table is set in the pointer in step S5315, the effect control command control process in step S30 is executed, whereby the prize ball excessive error command is effect controlled. To the microcomputer 100 for use.

  FIG. 23 is a flowchart showing an example of a special symbol process (step S26) program executed by the game control microcomputer 560 (specifically, the CPU 56) mounted on the main board 31. In the special symbol process, a process for controlling the first special symbol display 8a or the second special symbol display 8b and the special winning opening is executed. In the special symbol process, the CPU 56 executes a start port switch passing process (step S321). Further, any one of steps S300 to S307 is performed.

  The processes in steps S300 to S307 are as follows.

  Special symbol normal processing (step S300): Executed when the value of the special symbol process flag is zero. When the game control microcomputer 560 is in a state where the variable symbol special display can be started, the game control microcomputer 560 confirms the number of numerical data stored in the reserved storage buffer (total number of reserved storage). The stored number of numerical data stored in the hold storage buffer can be confirmed by the count value of the combined hold storage number counter. If the count value of the total pending storage number counter is not 0, it is determined whether or not the display result of the variable display of the first special symbol or the second special symbol is a big hit. In case of big hit, set big hit flag. Then, the internal state (special symbol process flag) is updated to a value (1 in this example) according to step S301. The jackpot flag is reset when the jackpot game ends.

  Fluctuation pattern setting process (step S301): This process is executed when the value of the special symbol process flag is 1. Also, the variation pattern is determined, and the variation time in the variation pattern (variable display time: the time from the start of variable display until the display result is derived and displayed (stop display)) is defined as the variation display variation time of the special symbol. Decide to do. Also, a variable time timer for measuring the special symbol variable time is started. Then, the internal state (special symbol process flag) is updated to a value (2 in this example) corresponding to step S302.

  Display result designation command transmission process (step S302): This process is executed when the value of the special symbol process flag is 2. Control for transmitting a display result designation command to the production control microcomputer 100 is performed. Then, the internal state (special symbol process flag) is updated to a value (3 in this example) corresponding to step S303.

  Special symbol changing process (step S303): This process is executed when the value of the special symbol process flag is 3. When the variation time of the variation pattern selected in the variation pattern setting process elapses (the variation time timer set in step S301 times out, that is, the variation time timer value becomes 0), the design control microcomputer 100 determines the symbol. Control to transmit the specified command is performed, and the internal state (special symbol process flag) is updated to a value (4 in this example) corresponding to step S304. The effect control microcomputer 100 controls the effect display device 9 to stop the decorative symbols when receiving the symbol confirmation designation command transmitted by the game control microcomputer 560.

  Special symbol stop process (step S304): executed when the value of the special symbol process flag is 4. After the display result of the special symbol is derived and displayed, the internal state (special symbol process flag) is updated to a value corresponding to step S305 (5 in this example) when the big hit flag is set.

  Preliminary winning opening opening process (step S305): This is executed when the value of the special symbol process flag is 5. In the pre-opening process for the big prize opening, control for opening the big prize opening is performed. Specifically, a counter (for example, a counter that counts the number of game balls that have entered the big prize opening) is initialized and the solenoid 21 is driven to open the big prize opening. Also, the execution time of the special prize opening opening process is set by the timer, and the internal state (special symbol process flag) is updated to a value corresponding to step S306 (6 in this example). The pre-opening process for the big winning opening is executed for each round, but when the first round is started, the pre-opening process for the big winning opening is also a process for starting the big hit game.

  Large winning opening opening process (step S306): This process is executed when the value of the special symbol process flag is 6. A control for transmitting a presentation control command for round display during the big hit gaming state to the microcomputer 100 for the presentation control, a process for confirming that the closing condition for the big prize opening is satisfied, and the like are performed. If the closing condition for the special prize opening is satisfied and there are still remaining rounds, the internal state (special symbol process flag) is updated to a value (5 in this example) corresponding to step S305. When all the rounds are completed, the internal state (special symbol process flag) is updated to a value corresponding to step S307 (7 in this example).

  Big hit end process (step S307): executed when the value of the special symbol process flag is 7. Control is performed to cause the microcomputer 100 for effect control to perform display control for notifying the player that the big hit gaming state has ended. In addition, a process for setting a flag indicating a gaming state (for example, a probability change flag or a time reduction flag) is performed. Then, the internal state (special symbol process flag) is updated to a value (0 in this example) corresponding to step S300.

  FIG. 24 is a flowchart showing the start-port switch passing process in step S321. In the start port switch passing process, the CPU 56 checks whether or not the first start port switch 13a is turned on (step S210A). If the first start port switch 13a is on, the CPU 56 checks whether or not the value of the first reserved memory number counter for counting the first reserved memory number is 4 which is the upper limit value (step). S211A). If the value of the first reserved memory number counter is 4, the process proceeds to step S210B.

  If the value of the first reserved memory number counter is not 4, the CPU 56 increases the value of the first reserved memory number counter by 1 (step S212A) and increases the value of the total reserved memory number counter by 1 (step S213A). Further, the CPU 56 sets “first” in the area corresponding to the value of the total reserved memory number counter in the reserved specific area for storing the winning order to the first start winning opening 13 and the second starting winning opening 14. The indicated data is set (step S214A).

  In this embodiment, when the first start opening switch 13a is turned on (that is, when a game ball starts and wins the first start winning opening 13), data indicating “first” is stored in the reserved specific area. When the second start port switch 14a is turned on (that is, when a game ball starts and wins the second start winning port 14), data indicating “second” is set in the reserved specific area. To do. For example, the CPU 56 sets 01 (H) as data indicating “first” when the first start port switch 13a is turned on in the hold specific area, and the second start port switch 14a is turned on. In this case, 02 (H) is set as data indicating “second”. When there is no hold storage, 00 (H) is set in the hold specific area.

  FIG. 25A is an explanatory diagram illustrating a configuration example of the reserved specific area. As shown in FIG. 25A, an area corresponding to the maximum value (8 in this example) of the total reserved memory number counter is secured in the reserved specific area, and the first start winning opening 13 or the second start Data indicating “first” or “second” is set in order of winning based on winning in the winning opening 14. Accordingly, in the reserved specific area, the winning order to the first start winning opening 13 and the second starting winning opening 14 is stored. The reserved specific area is formed in the RAM 55. Being formed in the RAM means an area in the RAM. FIG. 25A shows an example in which the value of the total pending storage number counter is 5. The first reserved storage buffer and the second reserved storage buffer are formed in the RAM 55.

  Next, the CPU 56 extracts values from the random number circuit 503 and a counter for generating software random numbers, and executes a process of storing them in the storage area in the first reserved storage buffer (step S215A). In the process of step S215A, a random R (big hit determination random number) that is a hardware random number, a big hit type determination random number (random 1) and a variation pattern determination random number (random 2) that are software random numbers are extracted, Stored in the save area. Note that the variation pattern determination random number (random 2) is not extracted in the first start port switch passing process (at the time of start winning) and stored in the storage area in advance, but is extracted at the start of variation of the first special symbol. You may do it. For example, the game control microcomputer 560 may directly extract a value from a variation pattern determination random number counter for generating a variation pattern determination random number (random 2) in the variation pattern setting process.

  FIG. 25B is an explanatory diagram showing a configuration example of an area (holding storage buffer) for storing random numbers and the like corresponding to holding storage. As shown in FIG. 25 (B), a storage area corresponding to the upper limit value (4 in this example) of the first reserved storage number is secured in the first reserved storage buffer. In addition, a storage area corresponding to the upper limit value of the second reserved storage number (4 in this example) is secured in the second reserved storage buffer. The first reserved storage buffer and the second reserved storage buffer are formed in the RAM 55. Further, a counter for generating a software random number and a reserved storage number counter are also formed in the RAM 55.

  Further, the CPU 56 increases the number of lighting of the first special symbol reservation storage display 18a by 1 (step S219A). Moreover, control which transmits the 1st pending | holding memory number addition designation | designated command is performed (step S220A).

  When transmitting an effect control command to the effect control microcomputer 100, the CPU 56 sets the address of a command transmission table (preliminarily set for each command in the ROM) corresponding to the effect control command as a pointer. . Then, the address of the command transmission table corresponding to the effect control command is set in the pointer, and the effect control command is transmitted in the effect control command control process (step S30).

  Next, the CPU 56 checks whether or not the second start port switch 14a is turned on (step S210B). If the second start port switch 14a is on, the CPU 56 checks whether or not the value of the second reserved memory number counter for counting the second reserved memory number is 4 which is the upper limit value (step). S211B). If the value of the second reserved memory number counter is 4, the process is terminated.

  If the value of the second reserved memory number counter is not 4, the CPU 56 increases the value of the second reserved memory number counter by 1 (step S212B) and increases the value of the total reserved memory number counter by 1 (step S213B). Further, the CPU 56 sets data indicating “second” in an area corresponding to the value of the total reserved storage number counter in the reserved storage specific information storage area (hold specific area) (step S214B).

  In addition, the CPU 56 extracts values from the random number circuit 503 and a counter for generating software random numbers, and executes a process of storing them in a storage area in the second reserved storage buffer (step S215B). As shown in FIG. 25B, the same number of storage areas as the upper limit value of the second reserved memory number are secured in the second reserved memory buffer. In the process of step S215B, the CPU 56 stores a value in a storage area corresponding to the value of the second reserved storage number counter in the second reserved storage buffer.

  Next, the CPU 56 increases the number of lighting of the second special symbol hold storage display 18b by 1 (step S219B). Further, control is performed to transmit the second reserved memory number addition designation command (step S220B).

  26 and 27 are flowcharts showing the special symbol normal process (step S300) in the special symbol process. In the special symbol normal process, the CPU 56 confirms the value of the total pending storage number (step S51). Specifically, the count value of the total pending storage number counter is confirmed. If the total pending storage number is 0, the process is terminated.

  If the total pending storage number is not 0, the CPU 56 checks whether or not the first data among the data set in the pending specific area (see FIG. 25A) is data indicating “first”. (Step S52). If it is data indicating “first”, a special symbol pointer (a flag indicating whether special symbol process processing is being performed for the first special symbol or special symbol process processing is being performed for the second special symbol) is set to “first 1 "is set (step S53). If it is not data indicating “first”, that is, if it is data indicating “second”, data indicating “second” is set in the special symbol pointer (step S54).

  Next, the CPU 56 reads out each random number value stored in the storage area corresponding to the reserved storage number = 1 indicated by the special symbol pointer in the RAM 55 and stores it in the random number buffer area of the RAM 55 (step S55). Specifically, when the special symbol pointer indicates “first”, the CPU 56 determines each random number value stored in the storage area corresponding to the first reserved memory number = 1 in the first reserved memory buffer. Is stored in the random number buffer area of the RAM 55. In addition, when the special symbol pointer indicates “second”, the CPU 56 reads out each random number value stored in the storage area corresponding to the second reserved memory number = 1 in the second reserved memory buffer. Store in the random number buffer area of the RAM 55.

  Then, the CPU 56 decrements the count value of the reserved storage number counter indicated by the special symbol pointer, and shifts the contents of each storage area (step S56). Specifically, when the special symbol pointer indicates “first”, the CPU 56 decrements the count value of the first reserved memory number counter by 1 and stores each storage area in the first reserved memory buffer. Shift content. When the special symbol pointer indicates “second”, the count value of the second reserved memory number counter is decremented by 1, and the contents of each storage area in the second reserved memory buffer are shifted.

  That is, when the special symbol pointer indicates “first”, the CPU 56 stores the first reserved memory number = n (n = 2, 3, 4) in the first reserved memory buffer of the RAM 55. Each stored random number value is stored in a storage area corresponding to the first reserved storage number = n−1. Further, when the special symbol pointer indicates “second”, each stored in the storage area corresponding to the second reserved memory number = n (n = 2, 3, 4) in the second reserved memory buffer of the RAM 55. The random value is stored in the storage area corresponding to the second reserved memory number = n−1.

  Therefore, the order in which each random value stored in each storage area corresponding to each first reserved memory number (or each second reserved memory number) is extracted is always the first reserved memory number (or (Second reserved storage number) = 1, 2, 3, 4 in order.

  Then, the CPU 56 decreases the value of the total pending storage number by one. That is, 1 is subtracted from the count value of the total pending storage number counter (step S57).

  In the special symbol normal process, first, data indicating “first” indicating that the process is executed for the first start winning opening 13, that is, “first” indicating that the process is executed for the first special symbol. ”Or“ second ”indicating that the process is performed on the second special symbol, that is,“ second ”indicating that the process is performed on the second start winning opening 14. Data is set in the special symbol pointer. In the subsequent processing in the special symbol process, processing corresponding to the data set in the special symbol pointer is executed. Therefore, the process of steps S300 to S307 can be shared between the case where the first special symbol is the target and the case where the second special symbol is the target.

  Next, the CPU 56 reads a random R (a jackpot determining random number) from the random number buffer area and determines whether or not to make a jackpot. That is, it is determined whether or not the value of the jackpot determination random number matches one of the jackpot determination values (see FIG. 7) set in the jackpot determination table (step S61). The CPU 56 reads out the big hit determination random number extracted in step S215A of the first start port switch passing process or step S215B of the second start port switch passing process and stored in advance in the first hold memory buffer or the second hold memory buffer. The jackpot is determined (a process of comparing the jackpot determination random number value with the jackpot determination value).

  When the gaming state is a probabilistic change state (high probability state), the probability that a big hit will be higher than when the gaming state is a non-probability changing state (normal game state and short-time state). More specifically, a probability change jackpot determination table (a table in which the numerical values on the right side of FIG. 7 in the ROM 54 are set) in which a large number of jackpot determination values are set in advance, and a probability change jackpot determination table in which the number of jackpot determination values is set. And a normal big hit determination table (a table in which the numerical values on the left side of FIG. 7 in the ROM 54 are set) are set. Then, the CPU 56 checks whether or not the gaming state is a probability variation state. If the gaming state is a probability variation state, the jackpot determination process is performed using the probability variation jackpot determination table, and the gaming state is normal. When in the gaming state or the short-time state, the big hit determination process is performed using the normal big hit determination table. That is, when the value of the big hit determination random number (random R) matches one of the big hit determination values shown in FIG. 7, the CPU 56 determines that the special symbol is a big hit.

  Note that whether or not the current gaming state is the probability variation state is determined by whether or not the probability variation flag is set. The probability variation flag is set when the gaming state is shifted to the probability variation state, and is reset when the probability variation state is terminated. Specifically, it is determined to be 15R probability variation jackpot or 10R probability variation jackpot, and is set in the process of ending the jackpot game. When it is determined that the jackpot game, the special symbol variation display is terminated and the stop symbol is halted. It is reset at the timing.

  If it is decided to win, the process proceeds to step S65. Note that deciding whether to win or not is to decide whether or not to shift to the big hit gaming state, but to decide whether or not to stop the special symbol display as a big hit symbol. But there is.

  If it is confirmed in step S61 that the value of the random R (random number for jackpot determination) does not match any jackpot determination value, the process proceeds to step S71.

  In step S65, the CPU 56 sets a big hit flag indicating that it is a big hit. Then, the jackpot type determination table indicated by the special symbol pointer is selected as a table used to determine the jackpot type as one of a plurality of types (step S66). Specifically, when the special symbol pointer indicates “first”, the CPU 56 selects the jackpot type determination table for the first special symbol shown in FIG. When the special symbol pointer indicates “second”, the CPU 56 selects the big hit type determination table for the second special symbol shown in FIG.

  Next, the CPU 56 uses the selected jackpot type determination table to determine the type (see FIG. 14) corresponding to the value corresponding to the value of the random number for random determination (random 1) stored in the random number buffer area. The type is determined (step S67). In this case, the CPU 56 determines the jackpot type that is extracted in step S215A of the first start port switch passing process or step S215B of the second start port switch pass process and stored in advance in the first hold memory buffer or the second hold memory buffer. The random number is read and the jackpot type is determined.

  Further, the CPU 56 sets data indicating the determined jackpot type in the jackpot type buffer in the RAM 55 (step S68). For example, when the big hit type is “15R probability variable big hit 1”, “02” is set as the data indicating the big hit type, and when “15R probability variable big hit 2”, “03” is set as the data indicating the big hit type. In the case of “15R probability variation big hit 3”, “04” is set as data indicating the big hit type. In the case of “10R probability variation big hit 1”, “05” is set as data indicating the big hit type, and in the case of “10R probability variable big hit 2”, “06” is set as the data indicating the big hit type. In the case of “15R normal big hit 1”, “07” is set as data indicating the big hit type, and in the case of “15R normal big hit 2”, “08” is set as the data indicating the big hit type. In the case of “10R normal big hit 1”, “09” is set as data indicating the big hit type, and in the case of “10R normal big hit 2”, “0A” is set as the data indicating the big hit type.

  Next, the CPU 56 determines a special symbol stop symbol (step S71). Specifically, when the big hit flag is not set, “−”, which is a missing symbol, is determined as a special symbol stop symbol. When the big hit flag is set, one of the big hit symbols “1” to “9” is determined as the special symbol stop symbol according to the determination result of the big hit type.

  In this embodiment, the case where the jackpot type is first determined and the stop symbol of the special symbol corresponding to the determined jackpot type is shown, but the method for determining the jackpot type and the stop symbol of the special symbol is as follows. It is not restricted to what was shown in embodiment. For example, a table in which a special symbol stop symbol and a jackpot type are associated in advance is prepared, and when a special symbol stop symbol is first determined based on the random number for determining the big hit type, the corresponding jackpot is determined based on the determination result. You may comprise so that a classification may also be determined.

  Then, the value of the special symbol process flag is updated to a value corresponding to the variation pattern setting process (step S301) (step S72).

  FIG. 28 is a flowchart showing the variation pattern setting process (step S301) in the special symbol process. In the variation pattern setting process, the CPU 56 selects a variation pattern table (see FIG. 15C) at the time of the big hit if it is a big hit (steps S91 and S92).

  If it is not a big hit and the gaming state is the high base state (short time state), the variation pattern table (see FIG. 15A) in the case of a shift in the high base state is selected (steps S93 and S94). When the gaming state is the low base state, a variation pattern table (see FIG. 15B) in the case of a shift in the low base state is selected (step S95). Note that whether or not the gaming state is the high base state is determined by whether or not the hourly flag is set.

  Next, the CPU 56 reads random 2 (random number for variation pattern determination) from the random number buffer area (first reserved storage buffer or second reserved storage buffer) (step S101), and the table selected in step S92, S94 or S95. The variation pattern is determined as one of a plurality of types by referring to (Step S102). That is, the random 2 is compared with the determination value set in the selected table, and the variation pattern corresponding to the determination value that matches the random 2 value is used as the variation pattern to be used.

  Further, the CPU 56 performs control to transmit the symbol variation designation command indicated by the special symbol pointer to the effect control microcomputer 100 (step S103). Specifically, when the special symbol pointer indicates “first”, the CPU 56 performs control to transmit a first symbol variation designation command. In addition, when the special symbol pointer indicates “second”, the CPU 56 performs control to transmit a second symbol variation designation command. Further, the CPU 56 performs control to transmit an effect control command (variation pattern command) corresponding to the determined change pattern to the effect control microcomputer 100 (step S104).

  Next, the CPU 56 starts changing the special symbol (step S105). Further, a value corresponding to the variation time corresponding to the selected variation pattern is set in the variation time timer formed in the RAM 55 (step S106). Then, the value of the special symbol process flag is updated to a value corresponding to the display result designation command transmission process (step S302) (step S107).

  In the case where it is determined to be out of place, instead of determining the variation pattern regardless of the reach, it may be determined first whether or not to reach by a lottery process using a random number for reach determination. . Then, the variation pattern may be determined based on the determination result of whether or not to reach.

  FIG. 29 is a flowchart showing the display result designation command transmission process (step S302). In the display result designation command transmission process, the CPU 56 performs control to transmit an effect control command (see FIG. 16) of any one of the display result 1 designation to the display result 10 designation in accordance with the determined jackpot type or loss. Do. Specifically, the CPU 56 first checks whether or not the big hit flag is set (step S111). If not set, the process proceeds to step S113. When the big hit flag is set, it is confirmed whether or not the big hit type is 15R big hit (step S112). Control is performed to transmit any one of the display result 2 designation command to the display result 10 designation command shown in FIG. 16 according to the type of jackpot (step S112).

  In step S113, the CPU 56 performs control to transmit a display result 1 designation command.

  Then, the CPU 56 decreases the number of lighting of the special symbol reservation storage display by 1 (step S114). In the process of step S116, when the special symbol pointer indicates “first”, the CPU 56 decreases the number of lighting of the first special symbol hold storage display 18a by 1, and the special symbol pointer becomes “second”. ", The number of lighting of the second special symbol reservation storage display 18b is decreased by one. Further, control is performed to transmit the reserved memory number subtraction designation command indicated by the special symbol pointer to the production control microcomputer 100 (step S115). In step S115, when a value indicating "first" is set in the special symbol pointer, the CPU 56 performs control to transmit a first reserved storage number subtraction designation command. Further, when a value indicating “second” is set in the special symbol pointer, control for transmitting the second reserved memory number subtraction designation command is performed. Then, the value of the special symbol process flag is updated to a value corresponding to the special symbol changing process (step S303) (step S116).

  FIG. 30 is a flowchart showing the special symbol changing process (step S303) in the special symbol process. In the special symbol changing process, the CPU 56 decrements the variable time timer by 1 (step S125). When the variable time timer times out (step S126), the special symbol stop time symbol is derived and displayed (step S127), and the effect control is performed. Control is performed to transmit a symbol confirmation designation command to the microcomputer 100 (step S128). Then, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol stop process (step S304) (step S129). If the variable time timer has not timed out, the process ends.

  FIG. 31 is a flowchart showing the special symbol stop process (step S304) in the special symbol process. In the special symbol stop process, the CPU 56 checks whether or not the big hit flag is set (step S130). When the big hit flag is set, the CPU 56 resets the high-accuracy output permission flag indicating that the signal indicating that the high probability state is output to the outside of the gaming machine is permitted (step S131). ). Further, the probability variation flag indicating the probability variation state and the time reduction flag indicating the time reduction state are reset (step S132), and the low probability state designation command and the low base state designation command are transmitted to the effect control microcomputer 100. Control is performed (steps S133 and S134). In addition, control for transmitting a big hit start designation command to the production control microcomputer 100 is performed (step S135).

  Further, a value corresponding to the big hit display time (for example, the time for notifying that the big hit has occurred in the effect display device 9) is set in the big prize opening control timer (step S136). Further, the number of times of opening is set in the number of times of opening counter (step S137). Then, the value of the special symbol process flag is updated to a value corresponding to the pre-winner opening pre-processing (step S305) (step S138). In the process of step S135, the CPU 56 sets 15 times if the big hit type is 15R probability variation big hit or 15R normal big hit, and sets 10 times if it is 10R positive variation big hit or 10R normal big hit. .

  When the big hit flag is not set, the CPU 56 checks whether or not the time reduction flag indicating that the time reduction state is set (step S141). If not set, the process proceeds to step S148. If the time reduction flag is set, the value of the time reduction counter indicating the number of times the special symbol can be changed in the time reduction state (high base state) is decremented by 1 (step S142). When the value of the time reduction counter after subtraction becomes 0 (step S143), the CPU 56 resets the time reduction flag (step S144). Further, the CPU 56 performs control to transmit a low base state designation command to the effect control microcomputer 100 (step S145). It should be noted that when the time reduction flag is set in the big hit end process (see FIG. 32), a value corresponding to the type of the big hit is set in the time reduction number counter.

  Thereafter, the CPU 56 updates the value of the special symbol process flag to a value corresponding to the special symbol normal process (step S300) (step S146).

  FIG. 32 is a flowchart showing the jackpot end process (step S307) in the special symbol process. In the jackpot end process, the CPU 56 checks whether or not the jackpot end display timer is operating (step S160). If the jackpot end display timer is operating, the process proceeds to step S164. If the jackpot end display timer is not in operation, the jackpot flag is reset (step S161), and control for transmitting a jackpot end designation command is performed (step S162). And the value corresponding to the display time corresponding to the time (big hit end display time) that the big hit end display is performed in the effect display device 9 is set in the big hit end display timer, and the big hit end display timer is operating. (Step S163), and the process is terminated.

  In step S164, 1 is subtracted from the value of the jackpot end display timer. Then, the CPU 56 checks whether or not the value of the jackpot end display timer is 0, that is, whether or not the jackpot end display time has elapsed (step S165). If not, the process ends.

  When the big hit end display time has elapsed, the CPU 56 sets a probability change flag to change the gaming state to the probability change state when the probability change big hit (15R probability change big hit or 10R probability change big hit) is reached (step S166). Set (step S167). Moreover, control which transmits the high probability state designation | designated command to the microcomputer 100 for production control is performed (step S168).

  Further, the CPU 56 sets a time reduction flag indicating the time reduction state (high base state) in order to change the gaming state to the time reduction state (high base state) (step S171). Then, the number of time reductions (see FIG. 14) corresponding to the type of jackpot is set in the time reduction number counter (2-byte configuration) (step S172). Further, control for transmitting a high base state designation command to the production control microcomputer 100 is performed (step S173). In addition, control is performed to transmit the time duration number command to the production control microcomputer 100 (step S174).

  Thereafter, the value of the special symbol process flag is updated to a value corresponding to the special symbol normal process (step S300) (step S175).

  In the process of step S172, when the big hit type is 1 to 15 big change big hits (short time until the next big hit), the CPU 56 sets 65536 (substantially infinite) to the short time counter. Instead of setting 65536 to the hourly counter, set a flag indicating that it is a 15-variable big hit, and reset the flag if it is another type of big hit. May be. In that case, in the special symbol stop process shown in FIG. 31, when the flag is not set, the processes of steps S142 to S145 are not executed. When the flag is used, even if variable display exceeding 65536 is executed during the period when the power is continuously turned on (no big hit occurs during that time), the big hit type is 15 probability change big hit. If there is, the time is continuously controlled.

  Further, the CPU 56 can confirm the jackpot type by the value stored in the jackpot type buffer.

  Next, the switch process (step S21) in the timer interrupt process will be described. In this embodiment, when the ON state of the detection signal of each switch related to winning detection or gate passage continues for a predetermined time, it is determined that the switch is surely turned on, and processing corresponding to the switch on is started. FIG. 33 is an explanatory diagram showing each 2-byte buffer formed in the RAM 55 used in the switching process. The previous port buffer is a buffer in which the previous switch-on / off determination result (for example, 4 ms before) is stored. The port buffer is a buffer in which the contents of ports 0 and 2 input this time are stored. The switch-on buffer is a buffer in which the corresponding bit is set to 1 when switch on is detected and the corresponding bit is set to 0 when switch off is detected. Note that the previous port buffer, port buffer, and switch-on buffer shown in FIG. 33 are prepared for each of the input ports 0 and 2. For example, in this embodiment, two switch-on buffers 1 and 2 are prepared, the switch state of the input port 0 is set to the switch-on buffer 1, and the switch state of the input port 2 is the switch-on buffer 2. Set to

  FIG. 34 is a flowchart showing a processing example of the switch processing in step S21 in the game control processing. In the switch process, the game control microcomputer 560 first inputs data input to the input ports 0 and 2 (see FIG. 7) (step S2101), and sets the input data in the port buffer (step S2102). ).

  Next, the initial value of the weight counter formed in the RAM 55 is set (step S2103), and the value of the weight counter is decremented by 1 until the value of the weight counter becomes 0 (steps S2104 and S2105).

  When the value of the wait counter reaches 0, the data of the input ports 0 and 2 are input again (step S2106), and a logical product is obtained for each bit between the input data and the data set in the port buffer. (Step S2107). Then, the operation result of the logical product is set in the port buffer (step S2108). Of the two input data input from the input ports 0 and 2 with a time interval of approximately [initial value of wait counter × (processing time of steps S2104 and S2105)], two times of the input data input by the processing of steps S2103 to S2108 Only the bits that are both “1” become “1” in the port buffer. That is, if the switch detection signal is kept on for a predetermined period [initial value of wait counter × (processing time in steps S2104 and S2105)], the corresponding bit in the port buffer becomes “1”.

  Further, the game control microcomputer 560 performs exclusive OR for each bit between the data previously set in the port buffer and the data set in the port buffer (step S2109). In the result of the exclusive OR operation, the bit corresponding to the switch for which the previous switch-on / off determination result (for example, 4 ms before) differs from the switch-on / off determination result determined to be on this time is “ 1 ”. The game control microcomputer 560 further performs a logical product for each bit between the result of the exclusive OR operation and the data set in the port buffer (step S2110). As a result, of the bits corresponding to the switches for which the previous switch on / off determination result and the switch on / off determination result determined to be on this time are different (according to the exclusive OR operation result), the current on Only the bit corresponding to the switch determined to be (by AND operation) remains as “1”.

  Then, the game control microcomputer 560 sets the logical product calculation result in step S110 in the switch-on buffer (step S2111), and sets the contents of the port buffer in which the calculation result in step S2108 is set in the previous port buffer. (Step S2112).

  By the above processing, among the switches that have been on for a predetermined period of time, the switch on / off determination result of the previous time (for example, 4 ms ago) was off, that is, the switch changed from the off state to the on state. The bit corresponding to the switch is “1” in the switch-on buffer.

  Further, the game control microcomputer 560 (specifically, the CPU 56) performs a switch normality / abnormality check process (step S2113).

  FIG. 35 is a flowchart showing a switch normal / abnormal check process. In the switch normality / abnormality check process shown in FIG. 35, the CPU 56 reads the contents of the switch-on buffer corresponding to the input port 2 (step S251). Then, it is confirmed whether or not the value of bit 1 corresponding to the second start port switch 14a in the switch-on buffer corresponding to the input port 2 is 0 (step S252). That is, it is confirmed whether or not the second start port switch 14a (proximity switch) provided in the upper part of the second start winning port 14 is turned on (a game ball is detected).

  When the value of bit 1 corresponding to the second start port switch 14a in the switch-on buffer corresponding to the input port 2 is 0 (that is, when the second start port switch 14a is in the on state), it is formed in the RAM 55. The value of the switch counter being incremented is incremented by 1 (step S253).

  Further, the CPU 56 reads the contents of the switch-on buffer corresponding to the input port 0 (step S254). Then, the CPU 56 confirms whether or not the value of the bit 4 corresponding to the winning confirmation switch 14b in the switch-on buffer corresponding to the input port 0 is 1 (step S255). That is, it is confirmed whether or not a winning confirmation switch 14b (photo sensor) provided at the lower part of the second start winning opening 14 is turned on (a game ball is detected).

  When the value of bit 4 corresponding to the winning confirmation switch 14b in the switch-on buffer corresponding to the input port 0 is 1 (that is, when the winning confirmation switch 14b is in the ON state), the switch formed in the RAM 55 The counter value is decreased by 1 (step S256).

  Then, the CPU 56 checks whether or not the value of the switch counter is equal to or greater than a predetermined value (step S257). When the value of the switch counter is equal to or greater than a predetermined value, the CPU 56 determines that an abnormal winning to the second start winning port 14 has occurred, and the security signal information timer has a predetermined time (in this example, 4). Minute) is set (step S258). In this embodiment, the CPU 56 sets a predetermined time (4 minutes in this example) to the security signal information timer based on the fact that the value of the switch counter is 10 or more as a predetermined value. To do. In this embodiment, the abnormal output of the second start winning opening 14 is detected by executing the information output process (see S31) based on the fact that the predetermined time is set in the security signal information timer in step S258. When this is done, the security signal is externally output for a predetermined time (in this example, 4 minutes).

  In addition, in the process of step S257, in addition to determining that the abnormal winning to the second start winning opening 14 has occurred, for example, the CPU 56 based on the value of the switch counter being 10 or more, On the contrary, even if the value of the switch counter becomes −10 or less, it may be determined that an abnormal winning to the second start winning opening 14 has occurred. In this case, if the switch counter value is configured so that it cannot be recognized that the value is negative, for example, 10 is set as the default value of the switch counter value. Based on the fact that the counter value becomes 0 or 20 or more, it may be determined that an abnormal winning to the second start winning opening 14 has occurred.

  In this embodiment, even when a value is already set in the security signal information timer and the security signal is being output to the outside, when a new abnormal winning is detected, the process of step S258 is executed again. The security signal information timer is overwritten with a predetermined time (in this example, 4 minutes). Therefore, when a new abnormal winning is detected during the external output of the security signal, the external output period of the security signal is substantially extended, and a predetermined time (in this example) from the time when the new abnormal winning is detected. 4 minutes) The output of the security signal is continued.

  In this embodiment, the case where the abnormal winning to the second start winning opening 14 is detected using only one switch counter is shown. However, the number of detections of the second start opening switch 14a and the winning confirmation switch 14b are shown. Different switch counters may be used depending on the number of times detected. In this case, for example, the value of the counter for the first switch is incremented by 1 each time the on state of the second start port switch 14a is detected, and the second switch is detected every time the on state of the winning confirmation switch 14b is detected. The counter value may be incremented by one. In step S257, based on the determination that the difference between the value of the first switch counter and the value of the second switch counter is equal to or greater than a predetermined value (for example, 10), the second start winning award 14 is entered. It may be determined that an abnormal prize has occurred and the process of step S258 is executed to output the security signal to the outside.

  If it is detected that an abnormal winning at the second start winning opening 14 has occurred, the process of step S258 is executed to output a security signal to the outside, and a predetermined error notification command is sent to the effect control microcomputer. It is desirable that error notification can be performed by displaying a predetermined error screen on the effect display device 9 on the effect control microcomputer 100 side.

  Further, for example, in addition to the abnormal winning at the second starting winning opening 14, an abnormal winning at the first starting winning opening 13, an abnormal winning at the large winning opening, an abnormal magnetic error, an abnormal radio wave error, and a communication error are detected. In such a case, when the security signal is output, a different error notification command may be transmitted to the effect control microcomputer 100 for each error type. Then, on the effect control microcomputer 100 side, error notification may be performed by causing the effect display device 9 to display different error screens for each type of error.

  In the above configuration, when power supply is resumed after the power supply to the gaming machine is stopped, an error notification is being issued before the power supply is stopped. The error notification command may be transmitted again to the effect control microcomputer 100. In other words, since the storage content such as RAM is not backed up by the backup power source on the production control microcomputer 100 side, if a power failure occurs, it is not possible to execute the production such as error notification that has been executed until then. However, the error notification can be resumed when the power failure is recovered by configuring the predetermined error notification command to be transmitted again when the power failure is recovered. The game control microcomputer 560 also backs up the value of the security signal information timer in the backup RAM. If the security signal is being output before the power supply is stopped, it is backed up when the power failure is restored. The output of the security signal may be resumed based on the value of the security signal information timer. By providing these configurations, it is possible to prevent an illegal act such as turning off the error notification or stopping the output of the security signal by intentionally turning off the power to the gaming machine.

  FIG. 36 is a block diagram showing various signals output to the terminal board 160. As shown in FIG. 36, in this embodiment, the game control microcomputer 560 mounted on the main board 31 is connected to the terminal board 160 with a symbol determination number of times 1 signal, a start port signal, a jackpot signal, a jackpot. Two signals, three jackpot signals, a time reduction signal, a winning signal, a security signal, and a high probability signal are output by the information output process (see step S31) on the game control microcomputer 560 side. In this embodiment, the prize ball information is sent from the payout control microcomputer 370 mounted on the payout control board 37 to the terminal board 160 via the main board 31. It is output by the information output process on the 370 side (see step S759).

  The symbol determination number 1 signal is a signal for notifying the number of fluctuations of the first special symbol and the second special symbol. The starting port signal is a signal for notifying the number of winnings to the first starting winning port 13 and the second starting winning port 14. The jackpot 1 signal is a signal for notifying that the jackpot game (during the operation of the special variable winning ball apparatus) is in progress. The jackpot 2 signal is a signal for notifying that the jackpot game is in progress (during the operation of the special variable winning ball apparatus) or that the special symbol variation time reduction function is in operation (during the high base state). The jackpot 3 signal is a signal for notifying that during the jackpot game, a transition to the high base state is made after the jackpot game is over. The time-short signal is a signal for notifying that the special symbol variation time reduction function is in operation (during the high base state).

  In addition, as described above, the winning signal indicates that a predetermined payout condition for paying out a predetermined number (in this embodiment, 10 balls) of winning balls is satisfied (the first start winning port 13, This is a signal indicating that a winning has occurred in the second start winning port 14, the big winning port, and the normal winning ports 29, 30. The award ball has not been paid out.

  The security signal is a signal indicating the security state of the gaming machine. Specifically, when it is determined that an abnormal winning to the second starting winning opening 14 has occurred based on the detection result of the second starting opening switch 14a and the detection result of the winning confirmation switch 14b, the security signal is It is output to an external device such as a hall computer for a predetermined period (for example, 4 minutes). Also, when the gaming machine is turned on and the initialization process is executed, a security signal is output to an external device such as a hall computer for a predetermined period (for example, 30 seconds).

  It should be noted that the signal output externally as the security signal is not limited to that shown in this embodiment. For example, not only abnormal winning at the second starting winning port 14, but abnormal winning at the first starting winning port 13, the large winning port, or the normal winning ports 29, 30 can be detected and output as a security signal to the outside. You may comprise as follows. In addition, for example, when abnormal magnetism is detected by a magnet sensor provided in a gaming machine or when abnormal radio waves are detected by a radio wave sensor provided in a gaming machine, it is configured so that it can be output externally as a security signal. Also good. In addition, for example, when an abnormality of various switches provided in a gaming machine is detected (for example, when an occurrence of a short circuit is detected by determining that an input value exceeds a threshold value), it can be externally output as a security signal. You may comprise as follows. In this way, even if an abnormal winning at the big prize opening, abnormal magnetic error, or abnormal radio wave error is configured to be output as a security signal from the common connector CN8 of the terminal board 160, even one signal line can be connected. In this case, error detection can be performed by an external device such as a hall computer, and the work load related to error detection can be reduced.

  Further, for example, even when a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, it can be externally output as a security signal from the common connector CN8 of the terminal board 160. May be. In this case, for example, the game control microcomputer 560 determines that a communication error has occurred based on failure to receive a connection OK command or a prize ball number reception command (to be described later) from the payout control microcomputer 370, and the terminal The security signal may be externally output from the common connector CN8 of the board 160. Also, for example, the game control microcomputer 560 determines that a communication error has occurred based on the value of any error bit in the status register of the serial communication circuit 505 being set, and the terminal board 160 has The connector CN8 may be externally output as a security signal.

  In addition to the signal line and connector CN8 for security signals, a signal line and connector dedicated to communication errors between the game control microcomputer 560 and the payout control microcomputer 370 may be provided on the terminal board 160. When a communication error between the game control microcomputer 560 and the payout control microcomputer 370 is detected, an external device such as a hall computer is transmitted via the terminal board 160 as a signal different from the security signal. May be output.

  The high probability signal is a signal indicating that the gaming state is controlled to a high probability state (probability change state). In this embodiment, the high-accuracy signal is externally output via the terminal board 160 until a predetermined condition is satisfied after the power failure is restored (specifically, until the first big hit occurs).

  The prize ball information is a signal that is output every time a specific number (10 in this example) of prize ball payouts is detected. In this embodiment, a predetermined payout condition for paying out a predetermined number of prize balls (10 balls in this embodiment) is satisfied (first start winning opening 13, second start winning prize). The winning signal is output to the outside based on the fact that the winning to the mouth 14, the large winning opening, the normal winning openings 29, 30 has occurred), and the number of winning balls can be grasped on the hall side based on the winning signal. Therefore, the prize ball information may be configured not to be output externally. In this example, a winning signal is output to the outside based on a predetermined payout condition for paying out a predetermined number of prize balls. On the other hand, it is conceivable that a winning signal is output externally after the winning ball is paid out. However, if the winning signal is output after the winning ball is paid out, it is considered that the gaming state has changed between winning and outputting the winning signal. It is not possible to accurately manage the game for each game state outside. Therefore, in this example, a winning signal is output to the outside based on a predetermined payout condition for paying out a predetermined number of prize balls.

  37 to 40 are flowcharts showing the information output processing in step S31. Of the processes shown in FIGS. 37 to 40, steps S1002 to S1020 are processes for outputting a start port signal, steps S1021 to S1023 are processes for outputting a winning signal, and steps S1031 to S1036. Is a process for outputting one signal for the number of symbol determinations, and steps S1037 to S1051 are processes for outputting one signal for big hit, two signals for big hit, three signals for big hit, and a short time signal. Steps S1069 to S1074 are processes for outputting a security signal, and steps S1075 to S1077 are processes for outputting a high-accuracy signal.

  In the information output process, the CPU 56 first sets the address of the start port information setting table in the pointer (step S1002) and loads the number of processes pointed to by the pointer (step S1003). The start port information setting table includes the number of processes (= 2), two start port switch input bits (first start port switch input bit determination value (01 (H))) and second start port switch input bit determination value ( 02 (H))) is set. The first start port switch input bit determination value is a determination value for determining whether or not there is a start winning in the first start winning port 13, and the second start port switch input bit determination value is a second value. This is a determination value for determining whether or not there is a start winning in the start winning opening 14. In step S1003, since the pointer points to the address of the number of processes in the start port information setting table, the data of the number of processes (= 2) in the start port information setting table is loaded.

  Next, the CPU 56 loads the contents of the switch-on buffer into the register (step S1004), and sets the switch-on buffer as switch input data (step S1005). The pointer is incremented by 1 (step S1006), the start port switch input bit pointed to by the pointer is loaded into the register (step S1007), and the logical product of the start port switch input bit and the switch input data is obtained (step S1008). In this case, when the number of processes is 1, the first start port switch input bit is loaded and the logical product of the switch input data is obtained. When the number of processes is 2, the second start port switch input is obtained. The bit is loaded and the logical product of the switch input data is taken. When the number of processes is 1 and the first start port switch 13a is on, the logical product operation result is 01 (H). When the number of processes is 2 and the second start port switch 14a is on, the logical product operation result is 02 (H). When the first start port switch 13a and the second start port switch 14a are not turned on, the logical product operation result is 00 (H).

  If the logical operation result is 0 (Y in step S1009), the process proceeds to step S1015. If the logical product operation result is not 0 (N in step S1009), it is determined that the first start winning opening 13 or the second starting winning opening 14 has been won, and the start opening information storage counter is loaded into the register. (Step S1010). The start port information storage counter is a counter that counts the number of remaining outputs of the start port signal (that is, the remaining number of start winnings that have not been output from the start port signal). Next, the CPU 56 adds 1 to the start port information storage counter (step S1011). Then, it is confirmed whether the calculation result (added result) is not 0 (step S1012). When the calculation result is 0 (N in step S1012), 1 is subtracted from the calculation result (step S1013). Then, the calculation result is stored in the start port information storage counter (step S1014).

  Next, the CPU 56 subtracts 1 from the number of processes (step S1015), and determines whether the number of processes is not 0 (step S1016). When the number of processes is not 0 (Y in step S1016), the process proceeds to step S1004. In this embodiment, since the gaming machine includes the first start winning opening 13 and the second starting winning opening 14, 2 is set as the initial value of the number of processes, and the processing of steps S1004 to S1016 is 2. Will be executed once.

  If it is determined in step S1016 that the number of processes is 0 (N in step S1016), the CPU 56 sets an initial value (00 (H)) in the information buffer formed in the RAM 55 (step S1017). Next, the CPU 56 sets the start port output bit position (bit 1 of the output port 1 in the example shown in FIG. 6) of the information output buffer formed in the RAM 55 (step S1018). Then, the CPU 56 sets the address of the start port information storage timer in the pointer (step S1019), and executes a winning timer setting process (step S1020).

  Next, the CPU 56 sets the winning output bit position (bit 6 of the output port 1 in the example shown in FIG. 6) of the information output buffer (step S1021). Then, the CPU 56 sets the address of the winning information storage timer in the pointer (step S1022), and executes a winning timer setting process (step S1023).

  In this embodiment, a common subroutine (winning timer setting process) is executed when the start opening signal is output externally and when the winning signal is output externally, so that the start opening output bit position of the information buffer is obtained. Is set and a start port signal is output, a winning output bit position of the information buffer is set, and a winning signal is output. Details of the winning timer setting process will be described later (see FIG. 41).

  Next, the CPU 56 loads the symbol determination number 1 information timer into the register (step S1031), reflects the state of the symbol determination number 1 information timer in the flag register (step S1032), and the symbol determination number 1 information timer times out. It is determined whether or not (step S1033). In this embodiment, in the special symbol variation processing (see step S303), when the variation time is timed out, when the variation of the special symbol is stopped, the symbol determination number 1 information timer outputs the symbol determination number output time (in this example, 0.500 seconds) is set, and when the symbol determination count output time has not elapsed, it is determined that the symbol determination count 1 information timer has not timed out, and when the symbol determination count output time has elapsed (symbol determination count) When the value 1 information timer value is 0), it is determined that the symbol determination time 1 information timer has timed out.

  If the symbol determination count 1 information timer has not timed out (N in step S1033), the symbol determination count 1 information timer is decremented by 1 (step S1034), and the calculation result is stored in the symbol determination count 1 information timer (step S1035). . Then, the design buffer count 1 output bit position of the information buffer (bit 0 of output port 1 in the example shown in FIG. 6) is set (step S1036). When the symbol determination number 1 output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. Is output from the output port 1 (becomes ON state). If the symbol determination number 1 information timer times out (Y in step S1033), the process of step S1036 is not executed, and as a result, the symbol determination number 1 signal is turned off.

  Each time the change of the first special symbol and the second special symbol is stopped (the stopped symbol is fixed) by the processing of steps S1031 to S1036 described above, the symbol determination number 1 signal is output as the symbol determination number output time (for example, 500 ms). Turns on.

  Next, the CPU 56 loads the special symbol process flag (step S1037), compares the value of the special symbol process flag with the special winning opening opening pre-processing designation value (“5”) (step S1038), and the special symbol process. It is determined whether the value of the flag is less than 5 (step S1039). When the value of the special symbol process flag is less than 5 (Y in step S1039), the process proceeds to step S1048. When the value of the special symbol process flag is 5 or more (N in Step S1039), the output buffer position of the jackpot of the information buffer is set (Step S1040). Further, the big output 2 output bit position of the information buffer is set (step S1041). When one output bit position of jackpot and two output bit positions of jackpot of the information buffer are set, the information buffer is set to an output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103. One signal and two jackpot signals are output from the output port 1 (become turned on).

  Further, the CPU 56 sets the 3 output bit positions of the big hit of the information buffer (step S1042). When the jackpot 3 output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103, so that the jackpot 3 signal is output from the output port 1. (Turns on).

  Further, the CPU 56 executes a low base check process for confirming whether or not the low base state is set (step S1048), and determines whether or not the low base state is set (step S1049). Specifically, the CPU 56 determines whether or not it is in the low base state by checking whether or not the time reduction flag that is set when shifting to the high base state is set. When not in the low base state (N in step S1049), that is, when the time reduction flag is set, the time reduction output bit position of the information buffer is set (step S1050). When the time-short output bit position is set, the time buffer signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1102 and outputting the output value to the output port 1 in step S1103. (Turns on) Further, the big output 2 output bit position of the information buffer is set (step S1051). When the jackpot 2 output bit position is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 1 in step S1103, whereby the jackpot 2 signal is output from the output port 1. (Turns on).

  By the processing of steps S1037 to S1051 described above, one big hit signal, two big hit signals, three big hit signals, and a short time signal are output (turned on) according to the type of big hit and the gaming state.

  Next, the CPU 56 loads the security signal information timer (step S1069), reflects the state of the security signal information timer in the flag register (step S1070), and determines whether the security signal information timer has timed out (step S1070). S1071). In this embodiment, it is determined that the detection difference between the second starting port switch 14a and the winning confirmation switch 14b has reached a predetermined value (10 in this example) or more, and it is determined that an abnormal winning is generated at the starting winning port. If the predetermined time (4 minutes in this example) is set in the security signal information timer (see steps S257 and S258 in the switch normality / abnormality check process), and the predetermined time has not elapsed, When it is determined that the signal information timer has not timed out and the predetermined time has elapsed (when the value of the security signal information timer is 0), it is determined that the security signal information timer has timed out.

  In this embodiment, when the power supply to the gaming machine is started and the initialization process is executed, a predetermined time (30 seconds in this example) is set in the security signal information timer (in the main process). When the predetermined time has not elapsed, it is determined that the security signal information timer has not timed out, and when the predetermined time has elapsed (when the value of the security signal information timer is 0), It is determined that the security signal information timer has timed out.

  If the security signal information timer has not timed out (N in step S1071), the security signal information timer is decremented by 1 (step S1072), and the calculation result is stored in the security signal information timer (step S1073). Then, the security signal output bit position of the information buffer (bit 7 of the output port 1 in the example shown in FIG. 6) is set (step S1074). When the security signal output bit position of the information buffer is set, the security signal is output from the output port 1 by setting the information buffer to the output value in the subsequent step S1102, and outputting the output value to the output port 1 in the step S1103. Is output (turns on). If the security signal information timer times out (Y in step S1071), the security signal is turned off as a result of not executing the process in step S1074.

  By the processing of steps S1069 to S1074 shown above, initialization processing is executed until 4 minutes have elapsed after the abnormal winning at the second start winning opening 14 is detected, or at the start of power supply to the gaming machine. Until 30 seconds elapse, a security signal is output using the common connector CN8 of the terminal board 160. If a new abnormal prize is detected during the output of the security signal, the output of the security signal is continued until 4 minutes have elapsed since the last abnormal prize was detected.

  Next, the CPU 56 checks whether or not the high-accuracy output permission flag is set (step S1075). Note that the high-accuracy output permission flag is set when the hot start process is executed at the start of power supply to the gaming machine (see step S9103). If the high-accuracy medium output permission flag is set, the CPU 56 checks whether or not the probability variation flag is set (step S1076). If the probability change flag is set, the CPU 56 sets the high-accuracy medium signal output bit position (bit 7 of the output port 0 in the example shown in FIG. 6) of the information buffer (step S1077). When the high-accuracy signal output bit position of the information buffer is set, the information buffer is set to the output value in the subsequent step S1102, and the output value is output to the output port 0 in step S1103. Output from output port 0 (becomes ON state). In this embodiment, after the power failure recovery, if the first big hit occurs, the high-accuracy output permission flag is reset (see step S136), and as a result, the high-accuracy medium signal is turned off.

  In this embodiment, the high-accuracy output permission flag is reset when the first big hit occurs. However, the timing for resetting the high-accuracy output permission flag is limited to that shown in this embodiment. I can't. For example, in a case where the probability variation state is terminated based on the fact that the variation display is executed a predetermined number of times after being controlled to the probability variation state, the certain number of variations display is terminated and the probability variation state is terminated. Sometimes, the high-accuracy medium output permission flag may be reset.

  If the probability change flag is set after the power failure is restored by the above steps S1075 to S1077, a high-accuracy signal is output until a predetermined condition is satisfied (in this example, until the first big hit occurs). Is turned on. That is, in this embodiment, as already described, even if the power supply to the gaming machine is stopped, the probability variation flag is held in the backup RAM for a predetermined period. Therefore, if the probability change state was controlled before the occurrence of a power failure, the probability change flag should be retained in the backup RAM. Until then, the output of the high-accuracy signal is continued.

  In this embodiment, since the high-accuracy output permission flag is reset when the first big hit occurs (see step S131 in FIG. 31), the high-accuracy signal is not output thereafter. Therefore, in this embodiment, if the predetermined condition is satisfied (in this example, if the first big hit occurs), the output of the high-accuracy signal is prohibited.

  In this embodiment, only the process of setting the high-accuracy medium output permission flag is performed at the time of executing the power failure recovery process of the main process, and it is confirmed whether or not the probability change flag is set in the information output process of step S31. However, the processing method for outputting the high-accuracy signal is not limited to that shown in this embodiment. For example, it is confirmed whether or not the probability change flag is set in the power failure recovery processing of the main processing, and if it is set, the high accuracy signal output bit position of the information buffer is set or A high accuracy signal may be output by performing processing such as setting a timer. Even when the probability variation flag is checked in the power failure recovery process and the output of the high-accuracy signal is started in this way, the high-level signal is output when a predetermined condition is satisfied, such as when the first big hit occurs. It may be configured to perform control so as to stop the output of the accuracy signal, and to control so as not to output the accuracy signal thereafter.

  In this embodiment, the output bit position of the corresponding signal in the information output processing shown in FIGS. 37 to 40 is set for each timer interrupt (steps S1036, S1040, S1041, S1060, S1046, S1050, S1051, S1074 and S1077), and steps S1102 and S1103 are executed to output externally from the output ports 0 and 1. However, regarding the output state of each signal, the value of the corresponding output bit is the same as the previous setting. It doesn't change unless it changes. For example, if the value of the corresponding output bit is set to “1”, the signal continues to be output while it is set.

  FIG. 41 is a flowchart showing the winning timer setting process executed in steps S1020 and S1023 of the information output process. In the winning timer setting process, the CPU 56 first loads the information storage timer pointed to by the pointer (step S2001), reflects the state of the loaded information storage timer in the flag register (step S2002), and a signal is being output. Is determined (step S2003). In this case, when the winning timer set process is executed in step S1020 of the information output process, the start port information storage timer is loaded and the state is reflected in the flag register, and whether or not the start port signal is being output. It will be determined. When the winning timer set process is executed in step S1023 of the information output process, the winning information storage timer is loaded and the state is reflected in the flag register to determine whether or not the winning signal is being output. Will do.

  The start port information storage timer is a timer for measuring an on time and an off time (for example, an on time of 100 ms and an off time of 100 ms) of the start port signal. If the value of the start port information storage timer is not 0, it is determined that the start port signal is being output. If the value of the start port information storage timer is 0, it is determined that the start port signal is not being output. The winning information storage timer is a timer for measuring an on time and an off time (for example, an on time of 100 ms and an off time of 100 ms) of the winning signal. If the value of the winning information storage timer is not 0, it is determined that the winning signal is being output. If the value of the winning information storage timer is 0, it is determined that the winning signal is not being output.

  If the signal (start port signal or winning signal) is being output (Y in step S2003), the process proceeds to step S2012. If the signal (start port signal or winning signal) is not being output (N in step S2003), the CPU 56 adds 1 to the pointer value (step S2004). In this embodiment, in the ROM 54, the start port information storage counter is set in the area next to the area where the start port information storage timer is set, and the area next to the area where the winning information storage timer is set. Is set with a winning information storage counter. Therefore, by executing the process of step S2004, the pointer value indicates the address of the start port information storage counter or the winning information storage counter.

  Next, the CPU 56 loads the information storage counter (start port information storage counter or winning information storage counter) pointed to by the pointer (step S2005), and the state of the loaded information storage counter (start port information storage counter or winning information storage counter) Is reflected in the flag register (step S2006), and it is determined whether there is a remaining number of output times of the signal (start port signal or winning signal) (step S2007).

  When the first start port switch 13a and the second start port switch 14a are turned on (N in step S1009), the start port information storage counter is incremented (the first start port switch 13a or the second start port switch 14a). 1 is added if either one is on, and 2 is added if both are on. (See step S1011.) Therefore, it is determined that there is a remaining number of output times of the start port signal. Become. In addition, when a winning occurs at any of the winning openings (the first starting winning opening 13, the second starting winning opening 14, the large winning opening, the normal winning openings 29, 30), the number of planned winning balls is ten. Each time it accumulates, the winning information storage counter is incremented (see step S5122), so it is determined that there is a remaining number of output times of the winning signal.

  If there is no remaining number of outputs of the signal (start port signal or winning signal) (Y in step S2007), the winning timer setting process is terminated. If there is a remaining number of output times of the signal (start port signal or winning signal) (N in step S2007), the CPU 56 decrements the upper storage counter (start port information storing counter or winning information storing counter) pointed to by the pointer. (Step S2008) The calculation result (the result obtained by subtracting 1) is stored in the information storage counter (start port information storage counter or winning information storage counter) (Step S2009). Then, the winning information operating time (50) is set in the register (step S2010). The winning information operating time (50) is a time for which a 4 ms timer interrupt is executed 50 times, that is, a time of 0.200 seconds (200 ms). In this embodiment, the case where the same value is set as the winning information operating time is shown when the start opening signal is output and when the winning signal is output. However, different values are set. Also good.

  Next, the CPU 56 subtracts 1 from the value of the pointer (step S2011). By executing the processing in step S2011, the pointer value returns to the state indicating the address of the start port information storage timer or the winning information storage timer again. Then, the process proceeds to step S2012.

  Next, if the winning information operating time is not set in step S2010, the CPU 56 subtracts 1 from the information storage timer (start port information storing timer or winning information storing timer) pointed to by the pointer, and the winning information operating time is determined in step S2010. If it is set, 1 is subtracted from the winning information operating time (step S2012). Then, the calculation result (the result obtained by subtracting 1) is stored in the information storage timer (start port information storage timer or winning information storage timer) pointed to by the pointer (step S2013).

  The CPU 56 compares the calculation result with the winning information on time (25) (step S2014), and determines whether the calculating result is shorter than the winning information on time (step S2015). The winning information on time (25) is a time for which a 4 ms timer interruption is executed 25 times, that is, a time of 0.100 seconds (100 ms).

  When the calculation result is not shorter than the winning information on time, that is, when the calculating result (remaining time of the starting information storing timer or the winning information storing timer) is longer than the winning information on time (100 ms) ( In step S2015 N), the CPU 56 loads the information buffer (step S2016), and obtains a logical sum of the loaded information buffer value and the information output buffer value (step S2017). Then, the CPU 56 stores the calculation result of step S2017 in the information buffer (step S2018).

  If the winning timer set process is executed in step S1020 of the information output process by executing the processes of steps S2016 to S2018, the value of the information output buffer in which the start port output bit is set in step S1018 Is obtained, the start port output bit position of the information buffer (bit 1 of the output port 1 in the example shown in FIG. 6) is set. When the start port output bit position of the information buffer is set, the information buffer is set to the output value in step S1102 of the subsequent information output process, and the output value is output to the output port 1 in step S1103. The mouth signal is output from the output port 1.

  Further, when the winning timer set process is executed in step S1023 of the information output process by executing the processes of steps S2016 to S2018, the value of the information output buffer in which the winning output bit is set in step S1011 Is obtained, the winning output bit position of the information buffer (bit 6 of the output port 1 in the example shown in FIG. 6) is set. Then, when the winning output bit position of the information buffer is set, the information buffer is set to the output value in step S1102 of the subsequent information output processing, and the output value is output to the output port 1 in step S1103. Is output from the output port 1.

  In steps S1002 to S1020 of the information output process and the winning timer setting process shown in FIG. 41, the first start winning opening 13 is won (the first start opening switch 13a is turned on) and the second starting winning opening 14 is won (the first When the 2 start port switch 14a is turned on), a start port signal is output. That is, after the start port signal is turned on for 100 ms, it is turned off for 100 ms. By inputting this start port signal to the hall computer, it is possible to recognize the number of winnings to the first start winning port 13 and the second starting winning port 14.

  Since the start port signal is turned on for 100 ms and then turned off for 100 ms, the next start port is turned on after the 100 ms off state even if a start winning is continuously generated in a short time. A signal is output. That is, the start port signals are output with an interval of at least 100 ms.

  Thus, since the start port signals are output at intervals of at least 100 ms, the hall computer can reliably grasp the total number of start winning prizes.

  In addition, by the information output processing steps S1021 to S1023 and the winning timer setting process shown in FIG. 41, any one of the winning ports (first starting winning port 13, second starting winning port 14, large winning port, ordinary winning port 29, A winning signal is output every time 10) a winning prize is generated and 10 planned award balls are accumulated. That is, after the winning signal is turned on for 100 ms, it is turned off for 100 ms. By inputting this winning signal to the hall computer, the expected number of winning balls can be recognized.

  Since the winning signal is turned on for 100 ms and then turned off for 100 ms, even if a start winning is continuously generated in a short time, the next winning signal is displayed after the off state for 100 ms. Is output. In other words, the winning signals are output with an interval of at least 100 ms.

  In this way, the winning signals are output with an interval of at least 100 ms, so that the hall computer can reliably grasp the total number of planned winning balls.

  In this embodiment, when the winning signal is output to the outside, first, the processing of step S2012 is executed to subtract the value of the winning information storage timer, and then the winning signals are executed by executing steps S2018, S1102, and S1103. However, the processing order of the subtraction processing of the winning information storage timer and the external output processing of the winning signal is not limited to that shown in this embodiment. For example, first, the same processing as in steps S2018, S1102, and S1103 is executed to execute the external output processing of the winning signal, and then the same processing as in step S2012 is performed to subtract the value of the winning information storage timer. Also good.

  Next, the output timing of the high-accuracy signal will be described. FIG. 42 is an explanatory diagram showing the output timing of the high-accuracy signal. In this embodiment, when the hot start process is executed at the start of power supply to the gaming machine (see step S91), the information output is based on the fact that the high-accuracy output permission flag is set (see step S9103). In the processing (see step S31), the processing of steps S1075 to S1103 is executed, and as shown in FIG. 42, the output of the high-accuracy signal to the external device such as the hall computer is started from the connector CN9 of the terminal board 160. Is done.

  Thereafter, the game control process can be executed, and when a game is played by the player, as shown in FIG. 42, the variable display is executed in accordance with the start winnings to the first starting winning port 13 and the second starting winning port 14 Is done. In this case, even if the fluctuation display is executed, if the fluctuation display result is “out of range”, the information output process (see step S31) is performed in step S1075 based on the fact that the high-accuracy output permission flag is maintained. Through the process of S1103, the output of the high-accuracy signal is continued.

  When the first big hit occurs as a result of the variable display, the high-accuracy output permission flag is reset at the end of the variable display (see step S136). Thereafter, when it is determined as N in step S1075 of the information output process (see step S31), the processes of steps S1076 and S1077 are not executed, and the output of the high-accuracy signal is stopped as shown in FIG.

  Next, the security signal output timing will be described. FIG. 43 is an explanatory diagram showing the output timing of the security signal. In this embodiment, when initialization processing is executed at the start of power supply to the gaming machine (see steps S10 to S14), a predetermined time (in this example, 30 seconds) is set in the security signal information timer. Based on the above (see step S14a), the processing of steps S1069 to S1074, S1102, and S1103 is executed in the information output processing (see step S31), and the connector CN8 of the terminal board 160 is connected as shown in FIG. A security signal is output to an external device such as a hall computer. Further, after the power supply to the gaming machine is started, the detection error between the detection number of the start port switch 14a and the detection number of the winning confirmation switch 14b becomes a predetermined value (10 in this example) or more. Even when it is determined that an abnormal winning at the second start winning opening 14 has occurred (see steps S121 to S127), a predetermined time (4 minutes in this example) is set in the security signal information timer. Based on the above (see step S128), the processing of steps S1069 to S1074, S1102, and S1103 is executed in the information output process (see step S31), and as shown in FIG. 43 (A), from the connector CN8 of the terminal board 160. A security signal is output to an external device such as a hall computer. As described above, in this embodiment, the common terminal board 160 is used when the initialization process is executed when power supply to the gaming machine is started and when the abnormal winning at the second start winning opening 14 is detected. A security signal is externally output from the connector CN8.

  Further, in this embodiment, when the security signal is being output to the outside, when an abnormal winning to the second start winning opening 14 is newly detected, the security signal output period is substantially extended, Finally, the output of the security signal is continued until a predetermined time (4 minutes in this example) has elapsed since the abnormal winning to the second start winning opening 14 was detected. For example, in the case where the output of the security signal is started based on the fact that the initialization process is executed when the power supply to the gaming machine is started, as shown in FIG. Security signal output should continue. However, as shown in FIG. 43B, even before 30 seconds have elapsed, the detection error between the number of detections of the second start port switch 14a and the number of detections of the winning confirmation switch 14b is a predetermined value (this In the example, there is a possibility that it becomes 10) or more and it is determined that an abnormal winning to the second start winning opening 14 has occurred. In this case, a predetermined time (4 minutes in this example) is overwritten and written in the security signal information timer based on the detection of the occurrence of the abnormal winning (see step S128), and the information output process (step S31). In step S1069 to S1074, S1102, and S1103, the security signal is output as it is as shown in FIG. However, since the value of the security signal information timer has been overwritten to 4 minutes, in this case, as shown in FIG. 43 (B), 4 minutes have elapsed since the abnormal winning to the start winning opening 14 was detected. Until then, the output of the security signal is continued, and the output of the security signal is substantially extended.

  Further, for example, in the case where the output of the security signal is started based on the detection of the abnormal winning at the second start winning opening 14, as shown in FIG. Security signal output should continue. However, as shown in FIG. 43C, even before the lapse of 4 minutes, the detection error between the number of detections of the second start port switch 14a and the number of detections of the winning confirmation switch 14b is a predetermined value (this In the example, 10) or more, there is a possibility that it is determined that a new abnormal winning to the second start winning opening 14 has occurred. In this case, a predetermined time (4 minutes in this example) is overwritten and written in the security signal information timer based on the newly detected occurrence of an abnormal winning (see step S128), and information output processing ( In step S31), the processing of steps S1069 to S1074, S1102, and S1103 is executed, and the output of the security signal is continued as shown in FIG. However, since the value of the security signal information timer is overwritten in 4 minutes, in this case, as shown in FIG. 43 (C), from the time when the abnormal winning to the second start winning opening 14 is newly detected. The output of the security signal is continued until 4 minutes have elapsed, and the output of the security signal is substantially extended.

  If an abnormal winning to the second start winning port 14 is detected while the security signal is already being output, the output of the security signal being output is terminated and the next security signal is output again. In this embodiment, as shown in FIGS. 43 (B) and 43 (C), the security signal is output by extending the output time of the security signal being output as it is. The processing load for the output process of the security signal is reduced, and the program capacity for the output process of the security signal is reduced. In other words, when it is configured to start the output of the next security signal after the output of the security signal being output is completed, the output of the next security signal is started after the output of the security signal is completed. For example, a process for measuring the interval time until completion is required, which increases the processing load and the program capacity. In contrast, in this embodiment, since the value of the security signal information timer is overwritten as it is, if only the process of setting the value of the security signal information timer is performed (see steps S14a and S128), the security signal is output. It is possible to prevent the increase in processing load and program capacity.

  Next, a description will be given of a common effect executed over a probability change notification effect, a non-probability change notification effect, and a plurality of variable displays. The common effect is an effect that is executed both when the gaming state is a high probability state (probability variation state) and when it is a normal state (low probability state: non-probability variation state).

  FIG. 44A shows an example of the probability change notification effect. The effect shown in FIG. 44 (A) is an effect of notifying the player that the game state is in a probable change state by the character image 9a of “probability change!”.

  FIG. 44 (B) shows an example of the effect in the probability variation latent state. The effect shown in FIG. 44 (B) is an effect that does not clearly notify whether or not the gaming state is the probability variation state by the character image 9b of “probability variation”. When an effect in the probability variation latent state is being executed, there are actually cases where the probability variation state and normal states are present.

  44 (C) to 44 (E) show examples of effects in the chance modes A, B, and C. The effect shown in FIG. 44C is an effect of notifying the player that there is a high probability of being in a probable change state by the character image 9c of “Large chance”. The effect shown in FIG. 44D is an effect of notifying the player that the possibility of being in a state of probability change is medium by the character image 9d of “In Chance”. The effect shown in FIG. 44 (E) is an effect of notifying the player that there is a low possibility of being in a probable change state by the character image 9e of “small chance”.

  FIG. 44 (F) shows an example of the non-probability change notification effect. The effect shown in FIG. 44 (F) is an effect of notifying the player that the game state is not in a probable change state (normal state) by the character image 9f of “Sorry!”.

  Next, the operation of the effect control means will be described. FIG. 45 is a flowchart showing main processing executed by the effect control microcomputer 100 (specifically, the effect control CPU 101) as effect control means mounted on the effect control board 80. The effect control CPU 101 starts executing the main process when the power is turned on. In the main processing, first, initialization processing is performed for clearing the RAM area, setting various initial values, and initializing a timer for determining the activation control activation interval (for example, 2 ms) (step S701). . Thereafter, the effect control CPU 101 executes a random number update process for updating the counter value of a counter for generating a predetermined random number (step S702). Then, the timer interrupt flag is monitored (step S703). If the timer interrupt flag is not set, the process proceeds to step S702. When a timer interrupt occurs, the effect control CPU 101 sets a timer interrupt flag in the timer interrupt process. If the timer interrupt flag is set, the effect control CPU 101 clears the flag (step S704), and executes the effect control process of steps S705 to S706.

  In the effect control process, the effect control CPU 101 first analyzes the received effect control command and performs a process of setting a flag according to the received effect control command (command analysis process: step S705).

  Next, the effect control CPU 101 performs effect control process processing (step S706). In the effect control process, the process corresponding to the current control state (effect control process flag) is selected from the processes corresponding to the control state, and display control of the effect display device 9 is executed.

  46 to 49 are flowcharts showing specific examples of command analysis processing (step S705). The effect control command received from the main board 31 is stored in the reception command buffer, but in the command analysis process, the effect control CPU 101 confirms the contents of the command stored in the command reception buffer.

  The effect control command transmitted from the game control microcomputer 560 is received by an interrupt process based on the effect control INT signal, and a ring buffer type command reception buffer capable of storing six 2-byte effect control commands. (Formed in RAM). A command reception number counter indicating in which area the received command is stored is used. The command reception number counter takes a value from 0 to 11. In the command analysis process, the effect control CPU 101 analyzes which command (see FIG. 11) is the effect control command stored in the command reception buffer.

  In the command analysis process, the effect control CPU 101 first checks whether or not a reception command is stored in the command reception buffer (step S611). Whether it is stored or not is determined by comparing the value of the command reception number counter with the read pointer. The case where both match is the case where the received command is not stored. When the reception command is stored in the command reception buffer, the effect control CPU 101 reads the reception command from the command reception buffer (step S612). When read, the value of the read pointer is incremented by +2 (step S613). The reason for +2 is that 2 bytes (1 command) are read at a time.

  If the received effect control command is a power-on specification command (initialization specification command) (step S615), the effect control CPU 101 displays an initial screen on the effect display device 9 indicating that the initialization process has been executed. Control is performed (step S616). The initial screen includes an initial display of predetermined decorative symbols.

  Further, if the received effect control command is a power failure recovery designation command (step S617), a predetermined power failure recovery screen (screen for displaying information notifying the player that the gaming state is continuing) is displayed. Display control is performed (step S618).

  If the received effect control command is a variation pattern command (step S621), the effect control CPU 101 stores the received variation pattern command in a variation pattern command storage area formed in the RAM (step S622). Then, a variation pattern command reception flag is set (step S623).

  If the received effect control command is a display result designation command (step S624), the effect control CPU 101 forms the received display result designation command (display result 1 designation command to display result 10 designation command) in the RAM. Is stored in the display result designation command storage area (step S625).

  If the command is the display result 2 designation command to the display result 10 designation command, the display result designation command is stored in the jackpot type storage area formed in the RAM (step S626).

  The jackpot type storage area is used to determine which type of jackpot was the last jackpot that occurred.

  If the received effect control command is a symbol confirmation designation command (step S627), the effect control CPU 101 sets a confirmed command reception flag (step S628).

  If the received effect control command is a jackpot start designation command (step S631), the effect control CPU 101 sets a jackpot start designation command reception flag (step S632).

  If the received effect control command is a special winning opening open designation command (step S635), the production control CPU 101 sets a special winning opening open designation command reception flag (step S636).

  If the received effect control command is a designation command after opening the big prize opening (step S637), the production control CPU 101 sets a designation command reception flag after opening the big prize opening (step S638).

  If the received effect control command is a jackpot end designation command (step S641), the effect control CPU 101 sets a jackpot end designation command reception flag (step S642).

  If the received effect control command is the first reserved memory number addition designation command (step S651), the effect control CPU 101 increments the value of the total reserved memory counter by 1 (step S652). In addition, the production control CPU 101 updates the display of the number of reserved memories in the total reserved memory display unit 18c (step S653). That is, the number of displayed images (for example, circles) is increased by one.

  If the received effect control command is the second reserved memory number addition designation command (step S657), the effect control CPU 101 increments the value of the total reserved memory counter by 1 (step S658). Further, the production control CPU 101 updates the display of the number of reserved memories in the total reserved memory display unit 18c (step S659). That is, the number of displayed images (for example, circles) is increased by one.

  If the received effect control command is the first reserved memory number subtraction designation command (step S665), the effect control CPU 101 decrements the value of the first reserved memory number counter by 1 (step S666). Also, the value of the summation pending storage counter is decremented by 1 (step S667). Then, the display of the number of reserved memories in the total reserved memory display unit 18c is updated (step S668). That is, the number of images (for example, circles) displayed on the summed hold storage display unit 18c is reduced by one. Specifically, for example, the leftmost image among the displayed images is deleted, and the other images are moved to the left side.

  If the received effect control command is the second reserved memory number subtraction designation command (step S670), the effect control CPU 101 decrements the value of the second reserved memory number counter by 1 (step S671). Also, the value of the summation pending storage counter is decremented by 1 (step S672). Then, the display of the number of reserved memories in the total reserved memory display unit 18c is updated (step S673). That is, the number of images (for example, circles) displayed on the summed hold storage display unit 18c is reduced by one.

  If the received effect control command is a high probability state designation command (step S680), the effect control CPU 101 sets a high probability flag (step S681). If the received effect control command is a low probability state designation command (step S682), the effect control CPU 101 resets the high probability flag (step S683). Further, a low probability transition flag indicating that the transition from the high probability state (probability change state) to the low probability state (normal state) is set (step S684).

  If the received effect control command is a high base state designation command (step S685), the effect control CPU 101 sets a high base flag (step S686). If the received effect control command is a low base state designation command (step S687), the effect control CPU 101 resets the high base flag (step S688). Further, a low base transition flag indicating that the transition has been made from the high base state to the low base state is set (step S689).

  If the received effect control command is a short time duration count designation command (step S691), the effect control CPU 101 stores the number of times (second byte of the command) designated by the short duration duration count designation command in the RAM (step S692). ). In addition, the number of times specified by the time reduction number specifying command is set in the time reduction counter (step S693).

  If the received effect control command is another command, effect control CPU 101 sets a flag corresponding to the received effect control command (step S699). Then, control goes to a step S611.

  FIG. 50 is an explanatory diagram showing random numbers used by the production control microcomputer 100. As shown in FIG. 50, in this embodiment, the production control microcomputer 100 has first to third final stop symbol determination random numbers SR1-1 to SR1-3, notice determination random number SR2, and chance mode determination. Random number SR3 and chance mode continuation number determination random number SR4 are used. Note that random numbers other than these may be used in order to enhance the effect.

  The random numbers SR1-1 to SR1-3 for determining the first to third final stop symbols are “left”, “middle”, “in” in the display area of the effect display device 9 as stop symbols that are variable display results of the decorative symbols. This is a random number used to determine a decorative symbol (final stop symbol) to be stopped and displayed in each “right” symbol display area. The final stop symbols are three decorative symbols that are finally stopped and displayed in each of the “left”, “middle”, and “right” symbol display areas when the variable display of the decorative symbols ends. The combination of the big hit symbols of the decorative symbols is determined by any one of the random numbers SR1-1 to SR1-3 for determining the first to third final stop symbols.

  The notice determination random number SR2 is a random number for determining whether or not to execute the notice effect and the type of the notice effect. The chance mode determination random number SR3 is a random number for determining which of the chance modes A, B, and C is used. The chance mode continuation number determination random number SR4 is a random number for determining the number of decorative pattern fluctuations that can be executed in the chance mode.

  FIG. 51 is a flowchart showing the effect control process (step S706) in the main process shown in FIG. In the effect control process, the effect control CPU 101 performs one of steps S800 to S807 according to the value of the effect control process flag. In each process, the following process is executed. In the effect control process, the display state of the effect display device 9 is controlled to realize variable display of decorative symbols, but control related to variable display of decorative symbols synchronized with the change of the first special symbol is also the second. Control related to variable display of decorative symbols synchronized with the variation of special symbols is also executed in one effect control process.

  Further, the variable display of the decorative symbol synchronized with the variation of the first special symbol and the variable display of the decorative symbol synchronized with the variation of the second special symbol may be executed by separate effect control process processing. Good.

  Fluctuation pattern command reception waiting process (step S800): It is confirmed whether or not a variation pattern command has been received from the game control microcomputer 560. Specifically, it is confirmed whether or not the variation pattern command reception flag set in the command analysis process is set. If the variation pattern command has been received, the value of the effect control process flag is changed to a value corresponding to the decorative symbol variation start process (step S801).

  Decoration symbol variation start processing (step S801): Control is performed so that the variation of the ornament symbol is started. Then, the value of the effect control process flag is updated to a value corresponding to the decorative symbol changing process (step S802).

  Decoration symbol variation processing (step S802): Controls the switching timing of each variation state (variation speed) constituting the variation pattern and monitors the end of the variation time. When the variation time ends, the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation stop process (step S803).

  Decoration symbol variation stop process (step S803): Based on the reception of the effect control command (design determination designation command) for instructing all symbols to stop, the variation of the ornament symbol is stopped and the display result (stop symbol) is derived and displayed. Take control. Then, the value of the effect control process flag is updated to a value corresponding to the jackpot display process (step S804) or the variation pattern command reception waiting process (step S800).

  Big hit display process (step S804): After the end of the variation time, control is performed to display a screen for notifying the effect display device 9 of the occurrence of the big hit. Then, the value of the effect control process flag is updated to a value corresponding to the in-round processing (step S805).

  In-round processing (step S805): Display control during round is performed. If the round end condition is satisfied, if the final round has not ended, the value of the effect control process flag is updated to a value corresponding to the post-round processing (step S806). If the final round has ended, the value of the effect control process flag is updated to a value corresponding to the jackpot end effect process (step S807).

  Post-round processing (step S806): Display control between rounds is performed. When the round start condition is satisfied, the value of the effect control process flag is updated to a value corresponding to the in-round process (step S805).

  Big hit end effect processing (step S807): In the effect display device 9, display control is performed to notify the player that the big hit game state has ended. Then, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800).

  FIG. 52 is a flowchart showing the variation pattern command reception waiting process (step S800) in the effect control process shown in FIG. In the variation pattern command reception waiting process, the effect control CPU 101 confirms whether or not the variation pattern command reception flag is set (step S811). If the variation pattern command reception flag is set, the variation pattern command reception flag is reset (step S812). Then, the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation start process (step S801) (step S813).

  FIG. 53 is a flowchart showing a decorative symbol variation start process (step S801) in the effect control process shown in FIG. In the decorative symbol variation start process, the effect control CPU 101 executes effect determination processing (step S821). The effect control CPU 101 also displays the decorative symbol display result (ie, the received display result specifying command and the variation pattern command) based on the data stored in the display result specifying command storage region and the variation pattern command storage region (that is, the received display result specifying command and the variation pattern command). A stop symbol is determined (step S822). The determined decorative symbol display result is stored in a decorative symbol display result storage area formed in the RAM.

  When the received display result designation command indicates a big hit (when the received display result designation command is one of the display result 2 designation command to the display result 10 designation command), the effect control CPU 101 The effect control CPU 101 determines a combination of decorative symbols having three symbols as stop symbols.

  And in the case of detachment, a combination of decorative symbols that does not have three symbols is determined. However, when a reach effect is involved, a combination of decorative symbols in which two left and right symbols are aligned is determined. Whether or not a reach effect is involved can be determined by a variation pattern command.

  Specifically, the effect control CPU 101 is, for example, a case where it is determined to be off, and a case where it is not determined to reach (specified by a variation pattern command). , SR1-1 to SR1-3 are extracted, the left symbol is determined using SR1-1, the middle symbol is determined using SR1-2, and the right symbol is determined using SR1-3. If the determined left and right symbols match, the right symbol is shifted by one symbol. When it is decided to reach (specified by the fluctuation pattern command), SR1-1 to SR1-2 are extracted, the left and right symbols are decided using SR1-1, and SR1-2 is used. Determine the middle symbol.

  As for the decorative symbol, a stop symbol that recalls a big hit is called a big hit symbol. A stop symbol that recalls a 15R jackpot is called a jackpot symbol. And a stop symbol that reminds of a loss is called a loss symbol.

  Then, the effect control CPU 101 selects a process table corresponding to the variation pattern indicated by the received variation pattern command (step S824). Then, the process timer in the process data 1 of the selected process table is started (step S825).

  In addition, the CPU 101 for effect control, according to the contents of the process data 1 (display control execution data 1, lamp control execution data 1, sound number data 1), effects device (effect display device 9 as an effect component, effect component as an effect component) Control of the various lamps and the speaker 27 as a production component is executed (step S826). For example, a command is output to the VDP 109 in order to display an image according to the variation pattern on the effect display device 9. In addition, a control signal (lamp control execution data) is output to the lamp driver board 35 in order to perform on / off control of various lamps. In addition, a control signal (sound number data) is output to the sound output board 70 in order to output sound from the speaker 27.

  Then, the effect control CPU 101 sets a value corresponding to the variation time specified by the variation pattern command in the variation time timer (step S827). Further, a predetermined time is set in the fluctuation control timer (step S828).

  Note that the predetermined time is, for example, 30 ms, and the presentation control CPU 101 writes image data indicating the display state of the left, middle, and right decorative patterns to the VRAM every time the predetermined time elapses, and image data in which the VDP 109 is written to the VRAM. Is output to the effect display device 9, and the effect display device 9 displays an image corresponding to the signal, whereby the variation of the decorative design is realized.

  Further, when writing the image data in a predetermined area of the VRAM, the effect control CPU 101 actually performs control to write the image data into the VRAM by, for example, a V blank interrupt process based on the V blank interrupt. Therefore, the effect control CPU 101 temporarily stores data to be written to the VRAM in a predetermined area of the RAM, and performs control to write the data in the predetermined area of the RAM to the VRAM by the V blank interrupt process. The V blank interrupt is an interrupt generated by the VDP 109 in the same cycle as the cycle of the vertical synchronization signal supplied to the effect display device 9. For example, when the screen change frequency (frame frequency) of the effect display device 9 is 30 Hz, the generation period of the V blank interruption is 33.3 ms, and when the frame frequency is 60 Hz, the occurrence of the V blank interruption is generated. The period is 16.7 ms. In this example, data is written to the VRAM by the V blank interrupt processing, but data may be written to the VRAM in other processing. Other processes are, for example, a timer interrupt based on a timer built in for production control, or a decorative symbol changing process. In addition, when the process which writes data in VRAM in other processes is performed, it is preferable to perform the process for synchronizing with an execution period and the period of V blank interruption regularly, for example.

  Thereafter, the value of the effect control process flag is set to a value corresponding to the decorative symbol changing process (step S802) (step S829).

  The process table is a table in which process data referred to when the effect control CPU 101 executes control of the effect device is set. That is, the effect control CPU 101 controls effect devices (effect components) such as the effect display device 9 according to the process data set in the process table. The process table includes data obtained by collecting a plurality of process timer set values and combinations of display control execution data, lamp control execution data, and sound number data (effect control execution data). The display control execution data includes data indicating each variation mode constituting the variation mode during the variable display time (variation time) of the variable display of the decorative symbols. Specifically, data relating to the change of the display screen of the effect display device 9 is described. The process timer set value is set with a change time in the form of the change.

  The process table is stored in the ROM of the effect control board 80. A process table is prepared for each variation pattern. In addition, a process table is also provided for executing effects related to jackpot notification and effects during the jackpot game.

  The effect control CPU 101 executes effect control according to the process data (effect control execution data) in the process table. That is, when the time according to the timer value set in the process timer set value has elapsed, according to the next effect control execution data in the process table, by repeating the process of controlling the light emitter such as the effect display device 9 and the LED, An effect such as a background during the change of a decorative pattern is realized.

  In this embodiment, the image data related to the variation of the decorative design is not set in the process table. The variation of the decorative pattern itself is directly controlled by the effect control CPU 101 without using the process table.

  In this embodiment, the effect control CPU 101 performs control so that the decorative pattern is variably displayed by the change pattern corresponding to the change pattern command on a one-to-one basis. The variation pattern to be used may be selected from a plurality of types of variation patterns corresponding to.

  FIG. 54 is a flowchart showing the effect determination process. In the effect determination process, the effect control CPU 101 confirms whether or not the change pattern is a change pattern with a reach effect (reach change pattern) (step S6001). If it is not a reach variation pattern, the process is terminated. In the case of the reach variation pattern, the effect control CPU 101 extracts the notice determination random number SR2 (step S6002). Then, using the notice determination table, it is determined whether or not the notice effect is to be executed, and if it is decided to be executed, the type of the notice effect is decided (step S6003).

  FIG. 55 is an explanatory diagram showing an example of the notice determination table. In the example shown in FIG. 55, a notice determination table (see FIG. 55 (A)) used in the case of a loss and a notice determination table (see FIG. 55 (B)) used when the display result of the decorative symbol is a big hit. )

  In any of the notice determination tables, a determination value to be compared with the notice determination random number, a determination value corresponding to not executing the notice effect, and a determination value corresponding to executing the notice effect A (notice A) The determination value corresponding to executing the notice effect B (notice B) is set.

  As shown in FIG. 55, in the case of a big hit, it is determined to execute the notice effect at a higher rate than in the case of a loss, and it is determined to execute the notice effect B at a higher rate.

  The notice effect B is an effect that is different in effect form from the notice effect A. For example, the notice effect B is executed using an image different from the character image used in the notice effect A.

  In this embodiment, the notice effect is not executed when the reach fluctuation pattern is not used, but the notice effect may be executed at a low rate even when the reach change pattern is not used. In this embodiment, whether or not to execute the notice effect is determined using one notice determination random number. First, the notice effect is executed using the notice determination random number. If it is determined whether or not to execute the notice effect, the kind of notice effect may be determined using a random number for determining the notice type.

  In step S6003, the effect control CPU 101 determines the contents ("notify the notice effect", "notice effect A", or "notice effect B") according to the determination value that matches the value of the random number for determining the notice. As a result, if it is decided to execute the notice effect, a notice flag is set and the kind of notice effect is stored in the RAM (step S6004). Also, a value corresponding to the time until the start time of the notice effect is set in the notice start timer (step S6005).

  Then, the CPU 101 for effect control does not deviate from the display result of the decorative design (when any of the display result 2 designation command to the display result 10 designation command is received) (step S6006), the accurate notification period. It is confirmed whether or not the counter value is 0 (step S6007). If it is 0, the process is terminated.

  If the value of the accurate notification period counter is not 0 (step S6007) and the decision control CPU 101 determines to execute the notification effect, the effect control CPU 101 will accurately notify if the type of the notification effect is the notification A. “5” is set in the period counter, and if it is the advance notice B, “10” is set in the accurate notification period counter (step S6009).

  When it is determined not to execute the notice effect, if the reach effect type is reach α, the accurate notification period counter is set to “5”, and if the reach effect is reach β, the accurate notification period counter is set to “7”. If reach γ, “10” is set in the accurate notification period counter (step S6010).

  When the value of the accurate notification period counter is not 0, the effect control CPU 101 decrements the value of the accurate notification period counter by -1 every time the decorative symbol change (variable display) is executed. Then, when a big hit occurs before the value of the accurate notification period counter becomes zero, the probability change notification effect (see FIG. 44A) or the non-probability change notification effect (see FIG. 44F) is executed.

  In other words, when it is decided to execute the notice effect in spite of the fact that it is out of date, if a big hit occurs within a predetermined period thereafter (in this example, until a predetermined number of fluctuations are completed), The game state is notified to the player (see steps S6006, S6008, and S6009). The predetermined period is different if the type of the notice effect is different (see step S6009). In addition, when a reach effect is executed in spite of a loss, when a big hit occurs within a predetermined period thereafter (in this example, until a predetermined number of fluctuations are completed), an accurate gaming state is determined as a game. (See steps S6006, S6008, and S6010). When the type of reach production is different, the predetermined period is different (see step S6010). Hereinafter, the predetermined period is also referred to as an accurate notification period.

  In this embodiment, when the accurate notification period has already been entered, the processing of steps S6008 to S6010 is not executed, but the processing of step S6008 is executed even during the accurate notification period, replacing the processing of step S6009. Then, “5” or “10” may be added to the accurate notification period counter, and “5”, “7”, or “10” may be added to the accurate notification period counter instead of the process of step S6010. In this embodiment, when it is decided to execute both the reach effect and the notice effect during variable display, only the process of step S6009 is executed with priority on the notice effect (step S6010). However, the effect control CPU 101 may be configured to execute the process of step S6010 in addition to the process of step S6009 when executing the notice effect. In that case, the value set in the process in step S6010 may be added to the value set in the process in step S6009 to set it in the accurate notification period counter, or the value set in the process in step S6009 and step S6010 may be set. The larger one of the values set in the process may be set in the accurate notification period counter.

  FIG. 56 is a flowchart showing the decorative symbol variation process (step S802) in the effect control process shown in FIG. In the decorative symbol variation process, the effect control CPU 101 decrements the values of the process timer, the variation time timer, and the variation control timer by 1 (steps S840A, S840B, and S840C). If the notice start timer is operating (if the value is not 0), the value of the notice start timer is decremented by 1 (step S840D).

  Further, the effect control CPU 101 checks whether or not the process timer has timed out (step S841). If the process timer has timed out, the process data is switched (step S842). That is, the process timer is started again by setting the process timer set value set next in the process table in the process timer (step S843). Further, the control state for the effect device (effect parts) is changed based on the display control execution data, lamp control execution data, and sound number data set next (step S844).

  If the notice effect timer has timed out (step S845), the effect control CPU 101 starts the notice effect (step S844). The effect control CPU 101 performs an effect (for example, display of a character image) according to the type of the notice effect stored in the RAM in the process of step S6004 in the process of step S846.

  In this embodiment, the effect control CPU 101 does not use the process table for the notice effect, but uses the process table in which data for executing the notice effect is set together with the effect during the change of the decorative design. It may be. In that case, the effect control CPU 101 selects a process table corresponding to the variation pattern and the type of the notice effect in the process of step S824 shown in FIG.

  If the variation control timer has timed out (step S847), the effect control CPU 101 displays the next display screen for the left middle right decorative symbol (30 ms after the previous decorative symbol display switching time). Image data of the power screen is created and written in a predetermined area of the VRAM (step S848). In this way, the effect control device 9 implements decorative pattern variation control. The VDP 109 outputs a signal based on data obtained by superimposing image data of a predetermined area and image data based on display control execution data set in the process table to the effect display device 9. As such, the effect control device 9 displays the background image, the character image, and the decorative design in the decorative design variation. Further, a predetermined value (for example, a value corresponding to 30 ms) is reset in the variation control timer (step S849).

  In addition, the effect control CPU 101 checks whether or not the variable time timer has timed out (step S851). When the variation time timer has timed out, the value of the effect control process flag is updated to a value corresponding to the decorative symbol variation stop process (step S803) (step S853). Even if the variable time timer has not timed out, if the confirmation command reception flag indicating that the symbol confirmation designation command has been received is set (step S852), the effect control CPU 101 executes the process of step S853.

  FIG. 57 is a flowchart showing a decoration symbol variation stop process (step S803) in the effect control process shown in FIG. In the decorative symbol variation stop process, the effect control CPU 101 resets the confirmed command reception flag if the confirmed command reception flag is set (step S8301). In addition, control for deriving and displaying a stop symbol is performed according to the data (data indicating the stop symbol) stored in the decorative symbol display result storage area (step S8302).

  If the value of the accurate notification period counter is not 0 (step S8303), the production control CPU 101 decrements the value of the accurate notification period counter by -1 (step S8304). When the value of the accurate notification period counter after -1 is not 0, it is confirmed whether or not the stop symbol is a big hit symbol (step S8306). If it is a big hit symbol, an accurate notification flag is set (step S8307). The accurate notification flag is referred to in the big hit end effect. Further, the effect control CPU 101 clears the value of the accurate notification period counter to 0 (step S8308).

  Further, the production control CPU 101 checks whether or not the value of the chance mode counter is 0 (step S8309). When the value of the chance mode counter is not 0, the value of the chance mode counter is decremented by 1 (step S8310).

  In the chance mode counter, a value other than 0 (specifically, the chance mode effect continues when the chance mode effect (any of the effects shown in FIGS. 44C to 44E) is started). The number of decorative symbol variations performed) is set.

  When the value of the chance mode counter after -1 is reduced to 0, the effect control CPU 101 ends the chance mode effect (step S8312). Specifically, the character images 9c, 9d, and 9e shown in FIGS. 44 (C) to 44 (E) are erased from the screen of the effect display device 9. Further, the chance mode flag is reset (step S8313). Note that any of the character images 9c, 9d, and 9e is displayed on the effect display device 9 before the chance mode effect ends.

  Further, the production control CPU 101 checks whether or not the probability variation latent mode flag is set (step S8314). If the probability variation latency mode flag is set, the value of the hour / times counter is decremented by 1 (step S8315). Note that a value corresponding to the number of time reductions is set in the time reduction counter in the process of step S693 shown in FIG.

  The effect control CPU 101 executes a chance mode setting process (step S8317) when the value of the time reduction counter reaches 0 (step S8316).

  FIG. 58 is a flowchart showing the chance mode setting process. In the chance mode setting process, the effect control CPU 101 resets the probability variation latent mode flag (step S8331). If the decorative symbol display result is a big hit symbol, the process ends (step S8332).

  If the display result of the decorative symbol is not a big hit symbol (it is a missing symbol), a chance mode determining random number SR3 is extracted (step S8333). Then, the type of chance mode is determined using the chance mode determination table (step S8334).

  FIG. 59 is an explanatory diagram of an example of the chance mode determination table. In the example shown in FIG. 59, the chance mode determination table (see FIG. 59 (A)) used when the last big hit is a 10R probability variable big hit, and the last big hit is a normal big hit with 50 short-time times. (In the example shown in FIG. 14, the chance mode determination table (see FIG. 59 (B)) used in the case of 15R normal big hit 1 or 10R normal big hit 1) There is a chance mode determination table (see FIG. 59C) that is used in the case of a normal big hit (in the example shown in FIG. 14, 15R normal big hit 2 or 10R normal big hit 2).

  In any chance mode determination table, determination values that are compared with chance mode determination random numbers and corresponding to chance modes A, B, and C are set.

  The effect control CPU 101 determines the content (“chance mode A”, “chance mode B”, or “chance mode C”) according to the determination value that matches the value of the chance mode determination random number in the process of step S8334. However, a chance mode flag (chance mode flag A, chance mode flag B or chance mode flag C) corresponding to the determined type of chance mode is set (step S8335).

  Further, the effect control CPU 101 extracts the chance mode continuation number determination random number SR4 (step S8336). Then, using the chance mode continuation count determination table, the continuation count of the chance mode (decorative pattern variation count) is determined (step S8337).

  FIG. 60 is an explanatory diagram of an example of the chance mode continuation count determination table. In the example shown in FIG. 60, the number of chance mode continuation times to be used when the last big hit is a normal big hit with 50 time reductions (in the example shown in FIG. 14, 15R normal big hit or 10R normal big hit 1) is determined. Table (see FIG. 60 (A)) and the chance to be used when the last big hit is a normal big hit with 30 time reductions (in the example shown in FIG. 14, 15R normal big hit or 10R normal big hit 2) There is a mode continuation count determination table (see FIG. 60B).

  In the process of step S 8337, the effect control CPU 101 uses the content (“10 times” or “20 times”) corresponding to the determination value that matches the value of the chance mode continuation number determination random number as the determination result. (Chance mode continuation count) is set in the chance mode counter (step S8338). If it is 10R probability variation big hit, 65536 (substantially infinite) is set in the chance mode counter. Therefore, in the case of 10R probability variation big hit, the chance mode (period in which the chance mode effect is executed) continues substantially until the next big hit occurs.

  Then, an effect (displaying any one of the character images 9c, 9d, and 9e shown in FIGS. 44C to 44E on the effect display device 9) according to the type of the chance mode determined in the process of step S8334 is started. (Step S8339). When executing the process of step S 8339, the effect control CPU 101 erases the character image 9 b of the effect in the probability variation latent state shown in FIG. 44B from the effect display device 9.

  As shown in FIG. 59, when the last big hit is a 10R probability variation big hit, the player has expectation in a shorter time period than when the last big hit is a normal big hit. The chance mode A effect (“chance is large” in the example shown in FIG. 44) is easily executed. In addition, when the last big hit is a normal big hit with 50 time reductions, compared to the case where the last big hit is a normal big hit with 30 time reductions, the game is performed in a shorter time period. Production of chance mode A that gives expectation to the person is easy to be executed.

  In other words, when the actual gaming state is a probable change state, the chance mode A effect is more likely to be executed, and when the actual gaming state is not the probabilistic state, the time-short state continues longer. Production of chance mode A is easy to be executed.

  Accordingly, the chance mode A effect that gives the player expectations can increase the player's sense of expectation with respect to the probability variation state, and even if the actual game state is not the probability variation state, the advantage (in this example, the number of time reductions) By controlling the occurrence frequency of the chance mode A effect according to the number of (increase / decrease), the player's expectation for the probable change state in the short time state (when the actual game state is the normal state) is not reduced. Can be.

  As shown in FIG. 60, the upper limit of the chance mode continuation count is 20 times. Therefore, it is possible to prevent the chance mode effect from being executed for a long period of time even though the actual gaming state is the normal state.

  Note that the type of jackpot that has occurred last is specified by a display result designation command stored in the jackpot type storage area (see step S626 in FIG. 46). This is because the contents of the big hit type storage area cannot be rewritten until the next big hit occurs.

  After performing the chance mode setting process in step S8317, the effect control CPU 101 confirms whether or not it has been decided to win the game (step S8321). Whether or not it is decided to win is confirmed by, for example, a display result designation command stored in the display result designation command storage area. In this embodiment, it can be confirmed whether or not it is determined to be a big hit based on the determined stop symbol. If it is not determined to be a big hit, the value of the effect control process flag is updated to a value corresponding to the variation pattern command reception waiting process (step S800) (step S8323).

  If it is determined to be a big hit, the CPU 101 for effect control updates the value of the effect control process flag to a value corresponding to the jackpot display process (step S804) (step S8322).

  FIG. 61 is a flowchart showing the jackpot end effect process (step S807) in the effect control process shown in FIG. In the jackpot end effect process, the effect control CPU 101 checks whether or not the jackpot end effect timer is set (step S871). If the big hit end effect timer is set, the process proceeds to step S875. If the jackpot end effect timer is not set, it is checked whether or not the jackpot end designation command reception flag is set (step S872). If the jackpot end designation command reception flag is set, the jackpot end designation command reception flag is reset (step S873), and the jackpot end presentation timer is set to the jackpot end presentation time (the time required for the jackpot end processing in the game control means). A value corresponding to (corresponding time) is set (step S874).

  In step S875, effect control CPU 101 decrements the value of the jackpot end effect timer. When the value of the big hit end effect timer becomes 0 (the big hit end time has elapsed) (step S876), the big hit type is 15R probability variation big hit (15R probability variation big hit 1, 15R probability variation big hit 2 or 15R probability variation big hit 3). If there is (step S880), a probability change notification effect (see FIG. 44A) is executed (step S881). When it is not the 15R probability variation big hit, the CPU 101 for effect control confirms whether or not the accurate notification flag (see step S8307 in FIG. 57) is set (step S882).

  When the accurate notification flag is set, the effect control CPU 101 resets the accurate notification flag (step S883), and the big hit type is the probability variation big hit (specifically, 10R probability variation big hit 1 or 10R probability variation big hit 2 ) Is confirmed (step S884).

  The effect control CPU 101 executes a probability change notification effect (see FIG. 44A) if it is a probability change big hit (step S885), and if it is not a probability change big hit, the non-probability notification effect (FIG. 44F). )) Is executed (step S886). Then, control goes to a step S889.

  When the accurate notification flag is not set, the effect control CPU 101 executes a probability variation latent effect (see FIG. 44B) (step S887). Then, the probability variation latent mode flag is set (step S888). Further, the value of the effect control process flag is updated to a value corresponding to the special symbol variation start designation command reception waiting process (step S801) (step S889).

  When the 15R probability variation big hit occurs by the control as described above, the player is clearly notified that the gaming state has become the probability variation state. In addition, if the probability change big hit (specifically, 10R probability change big hit) occurs when the accurate notification flag is set, the player is clearly notified that the gaming state has become the probability changed state, If it is not a probable big hit, the player is clearly notified that the game state is a normal state (non-probable change state). Note that, as described above, the accurate notification flag is the reach of the accurate notification period (a predetermined period after the decision to execute the notice effect in spite of being out of date, or in the event of being out of date. It is set when a big hit occurs during a predetermined period thereafter when it is decided to execute the effect.

  In other words, when it is decided to execute the notice effect in spite of being out of play, or when it is decided to execute the reach effect in spite of being out of play, it is continued for a predetermined period thereafter. Thus, when a big hit occurs, a privilege is given to the player that the gaming state is accurately notified. As a result, it is possible to alleviate a decrease in game motivation due to the display result being lost despite the execution of the announcement effect or the reach effect that increases the player's expectation for the big hit.

  In addition, when a 15R probability variation jackpot corresponding to the most advantageous game value for the player occurs, a probability variation notification effect is unconditionally executed, and an accurate gaming state is notified. Further, if a big hit other than the 15R probability change big hit occurs and it is not within the accurate notification period, the probability change latent mode is executed and the probability change latent effect is executed. The production control microcomputer 560 continuously executes the probability variation latent production until the chance mode is started. Note that the effect control microcomputer 560 continuously executes the chance mode effect during the chance mode duration period.

  Note that, when the accurate notification flag is set, the probability variation notification effect or the non-probability variation notification effect is not executed, but the probability variation latent mode or the chance mode may be shifted. When configured to shift to the chance mode (including the case of shifting from the probability variation latent mode), if the correct notification flag is set, the probability that the chance mode A is selected if the probability is changed If it is uncertain, the rate at which the chance mode C is selected is increased.

  In this embodiment, when the chance mode is entered, the specific chance mode effect (the chance mode A effect, the chance mode B effect, or the chance mode C effect) is continuously executed. Although the chance mode A, chance mode B, or chance mode C is maintained, the type of chance mode (chance mode A, chance mode B, or chance mode C) may be changed midway. The change is realized by, for example, a lottery using a random number. When the last big hit is a probable big hit, the mode shifts from the chance mode B to the chance mode A compared to the case where the normal big hit is made. This makes it easier to shift from chance mode C to chance mode B. Further, there may be a transition from chance mode A to chance mode B and a transition from chance mode B to chance mode C.

  Further, in this embodiment, in the case of 10R probability variable big hit, the chance mode continues until it is known that the next big hit occurs (see step S8338 in FIG. 58). When the number of times is set to a finite number and the variable display of the number of times is executed, the chance mode effect is ended (specifically, the character images 9c, 9d, and 9e shown in FIGS. 44C to 44E are effected). It may be deleted from the screen of the device 9). In that case, in the case of 10R probability variation big hit, the ratio determined as a large number of continuations is made higher than in the case of normal big hit (see FIG. 60).

  As described above, in this embodiment, the gaming state is a high probability state and the normal state (normal gaming state) in the high base state (time-short state) and the low base state shifted from the high base state. When the game state is controlled to the high probability state, the common effect (in this example, the probability variation latent effect and the chance mode effect) is executed, compared to the case where the game state is not controlled to the high probability state. The number of times is determined to be a large number at a high rate (in this example, the number of times of chance mode continuation is increased), and when the gaming state is in a high probability state, until the next big hit gaming state is controlled in the low base state A common effect is executed (in this example, in the case of 10R probability variable big hit, the chance mode continues until the next big hit occurs: step S8338 in FIG. When the game state is the normal game state, in the low base state, if the number of executions is determined to be a large number of times (in this example, 50 time reductions), the number of times is short (in this example, 30 time reductions). ) Is performed over a longer period of time than in the case determined in this case (in this example, 20 times: see FIG. 60), it is difficult to grasp whether the state is the high probability state or the normal gaming state. When performing an effect (in this example, a probabilistic latent effect and a chance mode effect), the expectation of the player's high probability state should not be reduced even when the actual game state is the normal game state Can do.

  In other words, the player's expectation increases when the number of times is 50, but in that case, since the common performance is continuously executed over a long period of time, the player's expectation is enhanced by the common performance. Can last.

  In the embodiment, the winning signal is output to the payout control microcomputer 370 based on the winning of the game ball in the first start winning opening 13 or the second starting winning opening 14. Without increasing the control burden of the gaming machine, it is possible to accurately grasp the gaming state when a predetermined payout condition is satisfied.

  In the present embodiment, the security signal is output to an external device such as a hall computer for a predetermined period when the gaming machine is turned on and the initialization process is executed. It is possible to prevent fraudulent acts performed when the machine is turned on.

  Note that the jackpot game may be configured to output four jackpot signals during the jackpot game based on the jackpot that shifts to the time-saving state after the jackpot game ends and when the game is controlled to the time-shortening state. As for the big hit 4 signals, it is desirable that the output timing is delayed according to the type of the big hit, similarly to the 3 big hit signals.

  Note that the present invention is not limited to application to a payout type gaming machine that pays out a predetermined number of winning balls in response to detection of winning balls, and a predetermined number of gaming balls are enclosed in a gaming machine and circulated for winning. The present invention can also be applied to an enclosed game machine that gives points according to the detection of a sphere.

  The present invention can be suitably applied to gaming machines such as pachinko gaming machines and slot machines.

DESCRIPTION OF SYMBOLS 1 Pachinko machine 9 Production display device 13 1st start winning opening 14 2nd starting winning opening 13a 1st starting opening switch 14a 2nd starting opening switch 14b Winning confirmation switch 15 Variable winning ball apparatus 31 Game control board (main board)
37 Dispensing control board 56 CPU
80 Production control board 100 Production control microcomputer 101 Production control CPU
160 Terminal Board 370 Discharge Control Microcomputer 371 Discharge Control CPU
560 Microcomputer for game control

Claims (1)

When a specific display resulting display result of the variable display is derived displayed in rows cormorants variable display means variable display based on the establishment of the start condition after a game medium has passed through the starting area favorable for the player controlled to a specific gaming state, a high probability state probability is improved for certain of the specific display resulting display result of variable display than when transition condition is normal gaming state based on the established is derived displayed A gaming machine to control
Predetermining means for deciding whether to control to the specific gaming state and whether to control to the high probability state before the display result of the variable display is derived and displayed;
After the specific gaming state ends, the gaming state control means for controlling the gaming state to a high-frequency state where the frequency of entering the starting area is higher than a low-frequency state where the frequency of entering the starting area is low. When,
Continuation number determination means for determining the number of executions of variable display in the high-frequency state as any of a plurality of times;
A common effect executing means for executing a common effect in the case where the gaming state is the high probability state and the case of the normal gaming state in the high frequency state and the low frequency state shifted from the high frequency state; With
When the gaming state is controlled to the high probability state, the continuation number determination means determines the number of executions to be a high number of times at a high rate compared to the case where the gaming state is not controlled to the high probability state,
When the gaming state is the high probability state, the common effect executing means executes the common effect until the game state is controlled to the specific gaming state, and the gaming state is the normal gaming state. Sometimes, in the low frequency state, when the continuation number determination unit determines the execution number to be a large number of times, the common effect is executed over a longer period than when the number of executions is determined to be a small number of times ,
A plurality of types of the common effects are provided,
The game machine characterized in that the common effect execution means executes any of a plurality of types of the common effects .

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