JP5735832B2 - Control circuit for switching power supply for driving light emitting element, light emitting device and electronic device - Google Patents

Description

  The present invention relates to a light emitting device.

  In recent years, light-emitting devices using light-emitting elements such as LEDs (light-emitting diodes) have been used as backlights and lighting devices for liquid crystal panels. FIG. 1 is a circuit diagram showing a configuration example of a light emitting device studied by the present inventors. The light-emitting device 1003 and its operation described here are not recognized as prior art by the present applicant. The light emitting device 1003 includes a plurality (n-channel) of LED strings 6_1 to 6_n, a switching power supply 1004, and a current driving circuit 1008.

Each LED string 6 includes a plurality of LEDs connected in series. The switching power supply 1004 boosts the input voltage _VIN and supplies the drive voltage _VOUT to one end on the anode side of the plurality of LED strings 6_1 to 6_n.

The current drive circuit 1008 adjusts the luminance of the LED string 6 by using analog dimming and burst dimming (also referred to as PWM dimming) together. The current source CSi (1 ≦ i ≦ n) is connected to one end on the cathode side of the corresponding LED string 6_i, and supplies a driving current I _LED corresponding to the target luminance to the LED string 6_i. Dimming based on the size of the drive current I _LED is called analog dimming.

The PWM controller 1009 generates dimming pulse signals PWM _{1 to} PWM _n having a duty ratio corresponding to the target luminance, and intermittently turns on the current sources CS1 to CSn at a duty ratio corresponding to the dimming pulse signal PWM. Let Thus, only during the on period (lighting _{period) T ON} corresponding to the duty ratio, the driving current _{I LED} to the LED string 6 will be flowing, the time average of the drive current _{I LED} is controlled, the brightness is adjusted.

The switching power supply 1004 includes an output circuit 1102 and a control IC 1100. The output circuit 1102 includes an inductor L1, a switching transistor M1, a rectifier diode D1, and an output capacitor C1. The control IC 1100 adjusts the drive voltage _VOUT by controlling the on / off duty ratio of the switching transistor M1.

The control IC 1100 sets the drive voltage V _OUT so that the voltage across the current source CS, that is, the potential V _LED at one end on the cathode side of the LED string 6 (referred to as a detection voltage) matches the predetermined reference voltage V _REF. Stabilize.

The error amplifier 22 amplifies an error between the lowest one of the detection voltages V _{LED1 to} V _LEDn of the plurality of channels (simply referred to as the detection voltage V _LED ) and the reference voltage V _REF to generate a feedback voltage V _FB . The error amplifier 22 includes a transconductance amplifier (gm amplifier) 21, a feedback switch SW1, a phase compensation resistor _RFB, and a capacitor _CFB . The feedback switch SW1 is turned on when the dimming pulse signal PWM indicates the lighting period. The gm amplifier 21 generates a current corresponding to an error between the detection voltage V _LED and the reference voltage V _REF . This current charges and discharges the capacitor C _{FB and} generates a feedback voltage V _FB at the feedback (FB) terminal.

The pulse modulator 20 generates a pulse signal S _PWM having a duty ratio corresponding to the feedback voltage V _FB . The driver DR drives the switching transistor M1 based on the pulse signal _SPWM . The driver 28 switches the switching transistor M1 only lighting period _{T ON} of the burst dimming, to stop switching the turn-off period _{T OFF.}

JP 2006-114324 A JP 2008-300208 A JP 2006-339298 A JP 2008-064477 A JP 2008-258428 A JP 2007-158083 A

The control IC 1100 needs to detect an open failure, a ground fault, and the like for each of the plurality of LED strings 6_1 to 6_n, and perform appropriate control or protection according to the detected state. To detect LED string 6_1~6_n each state, the LED terminal _LED 1 _{~LED n} respective detection voltages _V LED1 _{~V LEDn,} conceivable methods for comparing with a predetermined threshold voltage.

Focus on the i-th channel. The LED terminal LED _i of the channel, if the LED string 6_I is normally connected, the lighting period _{T ON} of the LED string 6_I, the detection voltage VLED _i of the LED terminal LED _i coincides with the reference voltage _{V REF.} That is, the detection voltage V _LEDi is higher than the threshold voltage.

On the other hand, when the LED string 6_i has an open failure, the detection voltage V _LEDi drops to near the ground potential. Even when the LED terminal LED _i is grounded (short-circuit failure) to the ground terminal, the detection voltage V _LEDi is also lowered to the vicinity of the ground potential. In addition, when the user does not use the i-th channel, the LED string 6_i is not connected to the LED terminal LED _i , so that the detection voltage V _LEDi drops to near the ground potential as in the case of an open failure.

That is, in the method of simply comparing the detection voltage V _LEDi of the LED terminal LED with the threshold voltage, an open state due to the disconnection of the LED string 6_1, an open state due to a failure of the LED string 6_i, or a short failure of the LED terminal is distinguished. Can not do it.

  This problem should not be regarded as a common general knowledge range in the field of the present invention. Furthermore, the above-mentioned examination itself has been conceived for the first time by the present applicant.

  The present invention has been made in view of such a problem, and one of exemplary purposes of an embodiment thereof is to provide a control circuit capable of distinguishing and detecting various states of a light emitting element.

  One embodiment of the present invention relates to a control circuit that controls a switching power supply that supplies a driving voltage to a first terminal of a light emitting element and generates a driving current that flows through the light emitting element. The control circuit is a control circuit that controls a switching power source that supplies a driving voltage to the first terminal of the light emitting element and generates a driving current that flows through the light emitting element, and is connected to the second terminal of the light emitting element. A current drive circuit that is connected to the terminal and the connection terminal and generates an intermittent drive current according to the dimming pulse signal, and generates a feedback voltage according to an error between a detection voltage generated at the connection terminal and a predetermined reference voltage An error amplifier, a pulse modulator that generates a pulse signal having a duty ratio according to a feedback voltage, a driver that drives a switching element of a switching power source based on the pulse signal, and a detection voltage that is lower than a predetermined threshold voltage An anomaly detection comparator that generates an anomaly detection signal that is asserted when the A pull-up circuit that supplies current to the connection terminal in the active state, and when the abnormality detection signal is asserted, the pull-up circuit is activated, and after the pull-up circuit is activated, the abnormality detection signal is asserted. And an abnormality detection circuit for detecting whether or not.

According to this aspect, when the light emitting element is not connected to the connection terminal, the detection voltage is pulled up to a high level by the pull-up circuit, becomes higher than the threshold voltage, and the abnormality detection signal is negated. On the other hand, when the connection terminal is grounded, the detection voltage is maintained at a low level, and thus becomes lower than the threshold voltage, and the abnormality detection signal is asserted. That is, according to this aspect, it is possible to distinguish and detect the disconnection of the light emitting element at the time of startup and the ground fault, and it is possible to perform protection processing or specific control corresponding to each.

The control circuit according to an aspect may further include a forced turn-off circuit that stops generation of the drive current by the current drive circuit for a predetermined period after the operation of the switching power supply is started. The abnormality detection circuit may activate the pull-up circuit when the abnormality detection signal is asserted during a predetermined period, and may detect whether the abnormality detection signal is asserted after the pull-up circuit is activated.
In this aspect, immediately after the switching power supply is activated, the detection voltage is applied when the light emitting element is not connected to the connection terminal from the beginning of the activation or when the connection terminal is grounded in the predetermined period in which the drive current is stopped. When the voltage is lower than the threshold voltage and the light emitting element is normally connected, the detection voltage is higher than the threshold voltage. According to this aspect, it is possible to detect a state in which the light emitting element is not connected from the beginning of the start, or a state in which the connection terminal is grounded from the start of the start, and it is possible to perform a protection process or specific control corresponding thereto. .

  The forced turn-off circuit may stop generating the drive current by the current drive circuit for a predetermined period after the drive current flowing through the light emitting element reaches a predetermined level.

  The forced turn-off circuit may stop the generation of the drive current by the current drive circuit for a predetermined period after the soft start voltage rising with time reaches a predetermined level.

The abnormality detection circuit activates the pull-up circuit when the abnormality detection signal is asserted during the period in which the current drive circuit generates the drive current, and determines whether the abnormality detection signal is asserted after the pull-up circuit is activated. May be detected.
When the light emitting element is detached from the connection terminal after starting (open failure) or the connection terminal is grounded, the abnormality detection signal is asserted. That is, according to this aspect, a failure after activation can be detected.

  Another embodiment of the present invention is a light-emitting device. The light emitting device includes a light emitting element and a switching power supply that supplies a driving voltage to one end of the light emitting element. The switching power supply includes an output circuit including a switching element and the control circuit described in any of the above that drives the switching element.

  Yet another embodiment of the present invention is an electronic device. This electronic device includes a liquid crystal panel and the above-described light emitting device provided as a backlight of the liquid crystal panel.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, various states of the light emitting element can be distinguished and detected.

It is a circuit diagram which shows the structural example of the light-emitting device which this inventor examined. It is a circuit diagram which shows the structure of an electronic device provided with the switching power supply which concerns on embodiment. FIG. 3 is a circuit diagram illustrating a configuration example of a clamp circuit in FIG. 2. It is a circuit diagram which shows the structure of a lighting detection circuit and a current source. It is a wave form diagram which shows operation | movement of the light-emitting device of FIG. It is a circuit diagram which shows the structure of the control IC which concerns on embodiment. FIG. 7 is a circuit diagram illustrating a specific configuration example of the abnormality detection circuit of FIG. 6. FIG. 8 is a flowchart showing the operation of the control IC of FIG.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are electrically connected to each other in addition to the case where the member A and the member B are physically directly connected. It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.
Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as their electric It includes cases where the connection is indirectly made through other members that do not substantially affect the general connection state, or that do not impair the functions and effects achieved by their combination.

  FIG. 2 is a circuit diagram illustrating a configuration of an electronic device including the switching power supply according to the embodiment.

  The electronic device 2 is a battery-driven device such as a notebook PC, a digital camera, a digital video camera, a mobile phone terminal, or a PDA (Personal Digital Assistant), and includes a light emitting device 3 and an LCD (Liquid Crystal Display) panel 5. The light emitting device 3 is provided as a backlight of the LCD panel 5.

  The light emitting device 3 includes LED strings 6_1 to 6_n that are light emitting elements, a current driving circuit 8, and a switching power supply 4.

Each LED string 6 includes a plurality of LEDs connected in series. The switching power supply 4 is a step-up DC / DC converter that boosts an input voltage (for example, battery voltage) _VIN input to the input terminal P1, and supplies an output voltage ( Drive voltage) V _OUT is generated. One end (anode) of each of the plurality of LED strings 6_1 to 6_n is commonly connected to the output line.

  The switching power supply 4 includes a control IC 100 and an output circuit 102. The output circuit 102 includes an inductor L1, a rectifier diode D1, a switching transistor M1, and an output capacitor C1. Since the topology of the output circuit 102 is general, description thereof is omitted. In addition, it is understood by those skilled in the art that there are various variations in the topology, and is not limited in the present invention.

The switching terminal P4 of the control IC 100 is connected to the gate of the switching transistor M1. The control IC 100 adjusts the ON / OFF duty ratio of the switching transistor M1 by feedback so that the output voltage _VOUT required for lighting the LED string 6 is obtained. The switching transistor M1 may be built in the control IC 100.

The current drive circuit 8 is connected to the other ends (cathodes) of the plurality of LED strings 6_1 to 6_n. Current drive circuit 8 supplies each LED string 6_1～6_N, intermittent depending on the target luminance, or a DC drive current _I LED1 _{~I LEDn.} Specifically, the current drive circuit 8 includes a plurality of current sources CS _{1 to} CS _n provided for each of the LED strings 6_1 to 6_n, and a PWM controller 9. The i-th current source CS _i is connected to the cathode of the corresponding i-th LED string 6 — i. The current source CS _{i switches} between an operation (active) state φ _ON for outputting the drive current I _LEDi and a stop state φ _OFF for stopping the drive current I _LEDi in accordance with the control signal PWM _i output from the PWM controller 9. Configured to be possible. The PWM controller 9 generates control signals PWM _{i to} PWM _n having a duty ratio corresponding to the target luminance, and outputs them to the current sources CS _{1 to} CS _n . Period control signal PWM _i is asserted (e.g., high level) (lighting period _{T ON),} the corresponding current source CS _i is the operating state phi _ON next, LED string 6_i lights up. During a period when the control signal PWM _i is negated (for example, at a low level) (light extinction period T _OFF ), the corresponding current source CS _i is in the stop state φ _OFF and the LED string 6 — i is extinguished. By controlling the time ratio between the lighting period T _ON and the extinguishing period T _OFF , the effective value (time average value) of the drive current I _LED flowing in the LED string 6 — i is controlled, and the luminance can be adjusted. The frequency of PWM drive by the current drive circuit 8 is several tens to several hundreds Hz.

  The current driving circuit 8 is integrated in the control IC 100. Alternatively, the control IC 100 and the current drive circuit 8 may be integrated on separate chips. They may constitute a single package (module) or separate packages.

The above is the overall configuration of the light emitting device 3. Next, the configuration of the control IC 100 will be described. The control IC 100 includes LED terminals LED ₁ to LED _n provided for the LED strings 6_1 to 6_n. Each LED terminal LED _i is connected to the cathode terminal of the corresponding LED string 6_i. The LED string need not be plural, and may be one.

  The control IC 100 mainly includes a pulse generator 19, a driver 28, a soft start circuit 32, a clamp circuit 40, and a lighting detection circuit 60.

Pulse generating unit 19, the lighting period _{T ON} of the LED string 6, a detection voltage corresponding to the output voltage _{V OUT} to generate a pulse signal _{S PWM} whose duty ratio is adjusted to coincide with a predetermined reference voltage _{V REF} . In FIG. 2, the detection voltage is the lowest one of the voltages (LED terminal voltages) V _{LED1 to} V _LEDn generated at the cathode terminal of the LED string 6, and is hereinafter referred to as V _LED .

The driver 28 generates a switching signal SWOUT based on the period T _ON when the dimming pulse signal PWM instructs lighting, and the pulse signal S _PWM , and drives the switching transistor M1. Further, the switching transistor M1 is fixed in the OFF state during the period T _{OFF in} which the dimming pulse signal PWM instructs to turn off.

Control in the lighting period _{T ON} IC 100 regulates the output voltage _{V OUT} of the switching power supply 4, the optimum voltage level for driving the LED strings 6_1～6_N. In extinction period _{T OFF,} the driving current _I LED1 _{~I LEDn} zero supplied to the LED string 6_1～6_N, i.e. the switching power supply 4 becomes the unloaded state. In the driver 28, the control IC 100 stops switching of the switching transistor M1 during the extinguishing period _TOFF .

Next, the configuration of the pulse generator 19 will be described. The pulse generator 19 includes an error amplifier 22 and a pulse modulator 20. The error amplifier 22 amplifies an error between the detection voltage V _LED and the reference voltage V _REF during the lighting period of the LED string 6 and generates a feedback voltage V _FB corresponding to the error.

The error amplifier 22 includes a gm amplifier 21, a feedback switch SW1, a phase compensation resistor _RFB, and a capacitor _CFB . The control IC 100 is provided with an FB terminal, and a resistor R _FB and a capacitor C _FB are externally connected in series between the FB terminal and an external ground terminal.

The gm amplifier 21 outputs (source or sink) a current corresponding to an error between the detection voltage V _LED generated between both ends of the current source CS and a predetermined reference voltage V _REF . Specifically, the gm amplifier 21 has a plurality of inverting input terminals (−) and one non-inverting input terminal (+). LED terminal voltages V _{LED1 to} V _LEDn are input to the plurality of inverting input terminals, respectively, and a reference voltage V _REF is input to the non-inverting input terminals. The error amplifier 22 generates a current corresponding to the error between the lowest LED terminal voltage (detection voltage) V _LED and the reference voltage V _REF .

The feedback switch SW1 is provided between the FB terminal and the output terminal of the gm amplifier 21, and is turned on in response to the dimming pulse signal PWM. The dimming pulse signal PWM is a logical sum of the dimming pulse signals PWM _{1 to} PWM _n of each channel, and becomes a predetermined level (for example, high level) when at least one channel indicates a lighting period.

Soft-start circuit 32, the standby signal STB is to instruct the return from the standby state of the normal operation, generates a soft start voltage V _SS that varies with time. Moreover, the soft-start circuit 32 outputs reaches a threshold voltage with a soft-start voltage _{V SS} asserts (high level) by the soft start completion signal (SS_END signal).

The lighting detection circuit 60 detects that the drive voltage _VOUT has risen to such an extent that the LED string 6 can emit light, and outputs a flag signal (LED_ON_ALL signal) that is asserted (high level) when detected. The LED_ON_ALL signal is at a high level when the drive voltage _VOUT is higher than a level at which at least one LED string 6 can emit light, and is at a high level when it is low. That is, the LED_ON_ALL signal is asserted (high level) when at least one LED string 6 can emit light.

  The OR gate 56 generates a START_OK signal by taking the logical sum of the LED_ON_ALL signal and the SS_END signal. That is, the START_OK signal takes a low level immediately after activation, and then transitions to a high level when the soft start is completed or when any LED is lit.

The clamp circuit 40 becomes active after the switching power supply 4 is started, in other words, for a certain period after the standby signal STB instructs to return from the standby state to the operating state. The active clamp circuit 40 controls the feedback voltage V _FB generated at the FB terminal to be equal to the soft start voltage V _SS regardless of the level of the detection voltage V _LED . The clamp circuit 40 has an enable terminal EN # (inverted logic), and is active while a signal input to the enable terminal EN # is at a low level. In the present embodiment, a START_OK signal is input to the enable terminal EN #.

The AND gate 23 controls the feedback switch SW1 based on the logical product of the START_OK signal and the dimming pulse signal PWM. Thus the feedback switch SW1, START_OK signal is high level, i.e. the clamp circuit 40 is inactive, and the pulse signal PWM dimming turned on during the period _{T ON} instructing lighting.

The pulse modulator 20 is, for example, a pulse width modulator, and generates a pulse signal S _PWM having a duty ratio corresponding to the feedback voltage V _FB and having a fixed period. Specifically, the duty ratio of the pulse signal S _PWM increases as the feedback voltage V _FB increases.

For example, the pulse modulator 20 includes an oscillator 24 and a PWM comparator 26. The oscillator 24 generates a periodic voltage V _OSC of a triangular wave or a sawtooth wave. The PWM comparator 26 compares the feedback voltage V _FB with the periodic voltage V _OSC and generates a PWM signal S _PWM having a level corresponding to the comparison result. Note that a pulse frequency modulator or the like may be used as the pulse modulator 20. The frequency of the PWM signal S _PWM is sufficiently higher than the frequency of PWM drive by the current drive circuit 8 and is several hundred kHz (for example, 600 kHz).

FIG. 3 is a circuit diagram showing a configuration example of the clamp circuit 40 of FIG. The clamp circuit 40 mainly includes a first transistor M11 of an N-channel MOSFET and a second transistor M12 that is complementary to the first transistor M11, that is, a P-channel MOSFET. The first terminal (source) of the first transistor M11 is connected to the FB terminal. The source of the second transistor M12 is connected to the control terminal (gate) of the first transistor M11, and the soft start voltage _VSS is input to the control terminal (gate) of the second transistor M12.

  An impedance circuit 51 is provided as a load for the first transistor M11. The impedance circuit 51 is provided between the FB terminal and the fixed voltage terminal (ground terminal). The impedance circuit 51 includes a resistor 11 and a switch M13. The inverter 54 inverts the START_OK signal and inputs it to the gate of the switch M13. Thus, the switch M13 is controlled so as to be turned on while the clamp circuit 40 is active.

  A current source 52 is provided as a load for the second transistor M12 between the source of the second transistor M12 and a fixed voltage terminal (power supply terminal).

When the gate-source voltage of each of the first transistor M11 and the second transistor M12 is written as V _T , the source potential of the transistor M12, that is, the gate potential of the transistor M11 is V _SS + V _T. The potential of the FB terminal, due to the low _{V T} than the gate potential of the transistor M11, is equal to the soft-start voltage _{V SS.}

  The off circuit 53 fixes the potential of the gate of the first transistor M11 to a level at which the first transistor M11 is turned off while the clamp circuit 40 is inactive. For example, the off circuit 53 can be configured by an N-channel MOSFET (transistor M14) that is provided between the gate of the first transistor M11 and a fixed voltage terminal (ground terminal) and has a START_OK signal input to its control terminal. When the START_OK signal becomes high level, the transistor M14 is turned on and the first transistor M11 is turned off.

The clamp circuit 40 becomes active during a period when the drive current I _LED flowing through the LED string 6 is lower than a predetermined level, and becomes inactive during a high period. From another point of view, the clamp circuit 40 becomes active during a period until the LED string 6 can emit light, and becomes inactive after the light emission becomes possible.

When the standby signal STB transitions to a high level, the soft start circuit 32 generates a soft start voltage V _SS by converting a digital counter 34 that counts up according to the clock signal CLK and a count value of the counter 34 into an analog voltage. A D / A converter 36 may be included. The counter 34 generates an SS_END signal that becomes a high level when the count value CNT reaches a predetermined value. SS_END signal becomes low level, high when a high level when the soft-start voltage _{V SS} is lower than the predetermined level.

  The soft start circuit 32 may be configured by a combination of a capacitor and a circuit that charges or discharges the capacitor.

Next, generation of the LED_ON_ALL signal by the lighting detection circuit 60 will be described. FIG. 4 is a circuit diagram showing the configuration of the lighting detection circuit 60 and the current source CS _i . FIG. 4 shows the configuration of one channel (i-th channel) among all n channels. The current source CS _i of the current drive circuit 8 includes a drive transistor M21, a current detection resistor R21, an operational amplifier OA1, and a dimming switch M22.

The ground terminal LED_GND is connected to an external ground potential. The drive transistor M21 and the current detection resistor R21 are sequentially provided in series between the LED terminal LED _i that is the cathode of the LED string 6 and the ground terminal LED_GND. The inverting input terminal of the operational amplifier OA1 is connected to a connection point between the driving transistor M21 and the current detection resistor R21, and a control voltage V _DIM indicating the driving current I _LEDi is applied to the non-inverting input terminal. The drive current I _LEDi is generated by the current source CS _i .
I _LEDi = V _DIM / R21

The dimming switch M22 is provided between the control terminal (gate) of the drive transistor M21 and the ground terminal LED_GND, and is controlled to be turned on and off according to the dimming pulse signal PWM _i . The inverter 63 inverts the dimming pulse signal PWM _i and inputs it to the gate of the dimming switch M22. During a period in which the dimming pulse signal PWM _i is at a low level (light extinction period T _OFF ), the dimming switch M22 is turned on, the gate of the driving transistor M21 is at a low level, and the driving transistor M21 is turned off.

Lighting detection circuit 60, the lighting period _{T ON} pulse signal PWM _i dimming instructs the lighting, by comparing the potential _{V G} of the gate of the driving transistor M21 and a predetermined level Va, through the LED string _{6 i} It is detected that the drive current I _LEDi has reached a predetermined level. The LED_ON _i signal indicating the detection result is at a low level when V _G > Va and is at a high level when V _G <Va.

Specifically, the lighting detection circuit 60 includes a transistor M31, a current source 62, a resistor 68, and a transistor M32. The source of the transistor M31, which is a P-channel MOSFET, is connected to the upper power supply terminal V _DD of the operational amplifier OA1, and the gate thereof is connected to the control terminal (gate) of the drive transistor M21. The current source 62 is provided between the drain of the transistor M31 and the lower power supply terminal (LED_GND) of the operational amplifier OA1. The transistor M32 is an N-channel MOSFET, its gate is connected to the drain of the transistor M31, and its source is connected to the lower power supply terminal (LED_GND). A resistor 68 is provided as a load for the transistor M32 between the drain of the transistor M32 and the upper power supply terminal _VDD .

The lighting detection circuit 60 generates an LED_ON _i signal according to the drain potential V _{D_M32} of the transistor M32. Inverter 65 inverts the output of inverter 63. The output signal of the inverter 65 has the same logic level as the dimming pulse signal PWM. The AND gate 67 generates a logical product of the dimming pulse signal PWM _i that is the output of the inverter 65 and the synchronous clock CLK, and the inverter INV1 inverts the output of the AND gate 67 and inputs it to the clock terminal of the flip-flop 69. To do. The inverter INV2 inverts the drain potential V _{D_M32} of the transistor M32 and _{inputs the} inverted _signal to the data terminal (D) of the flip-flop 69. The output of the flip-flop 69 becomes the LED_ON _i signal. The LED_ON _i signal is asserted (high level) when a certain level of drive current I _LEDi flows in the LED string 6 of the i-th channel, in other words, when the output voltage _VOUT is equal to or higher than a certain voltage level. The

The OR gate 71 calculates the logical sum of the LED_ON _{1 to} LED_ON _n signals of all channels and generates an LED_ON_ALL signal.

The above is the configuration of the light-emitting device 3. Next, the operation will be described.
FIG. 5 is a waveform diagram showing the operation of the light emitting device 3 of FIG. At time t1, the standby signal STB transitions to a high level, and activation of the switching power supply 4 is instructed. Start the soft-start voltage V _SS with the start begins to rise. At this time, the clamp circuit 40 is active, also the feedback voltage V _FB, to rise to follow the soft-start voltage V _SS. As a result, the duty ratio of the pulse signal S _PWM increases in accordance with the soft start voltage V _SS .

When the feedback voltage V _FB becomes higher than the lower limit level of the periodic voltage V _OSC (time t2), the pulse signal S _PWM is generated. The pulse signal PWM _i dimming while showing a lighting period _{T ON,} the switching signal SWOUT is generated by the driver 28, the switching transistor M1 is switched. The switching signal SWOUT is pulse-modulated at a frequency higher than that of the dimming pulse signal PWM _i, but the state of pulse modulation of the switching signal SWOUT is omitted in FIG.

The output voltage _VOUT rises while the switching transistor M1 is switched. Note while the output voltage _{V OUT} is low, even lighting period _{T ON} does not flow the driving current _{I LEDi.} Before the drive current _{I LEDi} starts to flow, the gate voltage _{V G} of the driving transistor M21 is the high level _{(V DD)} in the lighting period _{T ON,} OFF period _T pulse signal dimming the low level (0V) in _OFF PWM _i It repeats alternately in synchronization with.

As the output voltage V _OUT increases, the drive current I _LEDi increases. With the increase in the drive current _{I LEDi,} the gate voltage _{V G} of the driving transistor M21 in the lighting period _{T ON} starts to decrease. When it reaches a certain level the drive current _{I LEDi,} the gate voltage _{V G} is decreased to a predetermined level Va, the drain potential _{V D_M32} transistor M32 becomes high. The high level drain potential V _{D_M32} is taken into the flip-flop 69 by the synchronous clock CLK, and the LED_ON _i signal becomes high level. That is, it is detected that a certain level of drive current I _LEDi has started to flow (time t3).

When the LED_ON _i signal becomes high level, the clamp circuit 40 is switched to inactive and the feedback switch SW1 is turned on. Thereby, feedback according to the detection voltage V _LED becomes effective, and the feedback voltage V _FB becomes a level according to the error between the detection voltage V _LED and the reference voltage V _REF .

The above is the startup operation of the light emitting device 3.
According to the light emitting device 3, even when the duty ratio of the dimming pulse signal PWM is small when returning from the standby state, the feedback voltage V _FB , that is, the duty ratio of the pulse signal S _PWM is set to the soft start voltage. It can be increased so as to follow the V _SS, increases in a short time the output voltage V _OUT. Also, after a certain period from the start of the operation of the switching power supply 4 has elapsed, by releasing the control of the feedback voltage V _FB corresponding to the soft-start voltage V _SS clamp circuit 40 as inactive, the detection voltage V _LED is a reference voltage It is possible to shift to feedback control that approaches V _REF .

Immediately before the transition, the feedback voltage _{V FB} is equal to the soft-start voltage _{V SS,} after the migration, the voltage level determined according to the error of the detection voltage _{V LED} and the reference voltage _{V REF.} In this circuit, when a certain level of drive current I _LED starts to flow, the control shifts to feedback control, so that the two voltage levels can be brought close to each other. As a result, the feedback voltage V _FB largely fluctuates before and after the transition, and the output voltage _VOUT can be prevented from fluctuating.

The lighting detection circuit 60 of the clamp circuit 40 detects that a predetermined level of the drive current I _LED has started to flow based on the voltage V _G of the control terminal of the drive transistor M21. This has the following advantages compared to the case of detecting based on the OVP voltage V _OVP corresponding to the output voltage V _OUT .

Voltage drop (forward voltage) _{V F} when the level of the driving current _{I LED} in the LED string 6 is flowing, the size and the drive current _{I LED,} vary according to the number of LED included in the LED string 6 is there. Therefore, when detecting whether driving voltage _{V OUT} by OVP voltage _{V OVP} is rising to a sufficient level, in accordance with the LED string 6, it is necessary to optimize the threshold level to be compared with the OVP voltage _{V OVP} . The detection based on the voltage of the control terminal of the drive transistor M21 has an advantage that it is not necessary to change the threshold level according to the LED string 6. This is a very important merit in the control IC 100 in which versatility for driving various LED strings 6 is required.

  Next, a technique for detecting an open fault, a short fault, and no connection of the LED string 6 for each channel will be described. This technique can be used in combination with or separately from the control IC 100 described above.

  FIG. 6 is a circuit diagram showing a configuration of the control IC 100a according to the embodiment. FIG. 6 representatively shows only the i-th channel.

In addition to the configuration described above, the control IC 100a mainly includes an abnormality detection comparator COMP_OPEN _i for each channel, a forced turn-off circuit 80_i for each channel, a pull-up circuit 90_i for each channel, and an abnormality detection circuit 70.

The abnormality detection comparator COMP_OPEN _i compares the detection voltage V _LEDi of the corresponding LED terminal (connection terminal) LED _i with a predetermined threshold voltage V _{OPEN_DET} . A transistor M90 is provided between the input terminal of the abnormality detection comparator COMP_OPEN _i and the LED terminal LED _i . When a high level voltage of V _REG = 5 V, for example, is input to the gate of the transistor M90, the transistor M90 is turned on, and the detection voltage V _LEDi is input to the abnormality detection comparator COMP_OPEN.

For example, V _{OPEN_DET} is set to about 0.2V. Then, the abnormality detection comparator COMP_OPEN _i generates an abnormality detection signal OPEN_DET _i that is asserted (for example, high level) when V _LEDi <V _{OPEN_DET} .

The feedback voltage comparator COMP_FB compares the feedback voltage V _FB generated at the FB terminal with a predetermined threshold voltage V _{FB_DET} . For example, the threshold voltage V _{FB_DET} is about 4V. The feedback voltage comparator COMP_FB is asserted when V _FB > V _{FB_DET} . When an abnormality occurs in the feedback of the i-th channel due to a failure or the like, and the detection voltage V _LEDi decreases near the ground voltage, the feedback voltage V _FB jumps to a high level. That is, the feedback voltage comparator COMP_FB can also detect that the detection voltage V _LEDi is out of the normal level.

The forced turn-off circuit 80 stops the generation of the drive current I _LED by the current drive circuit 8 for a predetermined period τ _DET after the operation of the switching power supply 4 is started. For example, the above-mentioned START_OK signal is input to the forced turn-off circuit 80 as a trigger for stopping the drive current I _LED . When the START_OK signal transitions (asserts) from the low level to the high level, in other words, when a certain period of time has elapsed after the start of the activation operation of the switching power supply 4, the forced turn-off circuit 80 further changes the current flowing through the LED string 6 to a predetermined level. When the level reaches or the soft start voltage V _SS reaches a predetermined level, the generation of the driving current I _LEDi by the current source CS _i is stopped for a predetermined time τ _DET when the soft start voltage V _SS reaches the predetermined level. The signal used as a trigger is not limited to the START_OK signal, and other signals that are asserted at a certain time after the switching power supply 4 is activated, for example, an SS_END signal or an LED_ON signal may be used.

For example, the PWM controller 9 includes a hysteresis comparator 91 and an OR gate 93. The hysteresis comparator 91 compares an external dimming pulse signal PWM_EXT with a threshold voltage, and generates a dimming pulse signal PWM _i ′ for each channel. The OR gate receives dimming pulse signals PWM _{1 to} PWM _n for all channels and generates a dimming pulse signal PWM that is the logical sum of them.

For example, the forced turn-off circuit 80 includes a one-shot circuit 82 and an AND gate 84. When the START_OK signal serving as a trigger is asserted, the one-shot circuit 82 generates a pulse signal PULSE that is at a low level for a predetermined time τ _DET . The AND gate 84 generates a dimming pulse signal PWM _i that is a logical product of the dimming pulse signal PWM _i ′ signal and the pulse signal PULSE. The dimming pulse signal PWM _i becomes low level for a predetermined time τ _DET regardless of the level of the dimming pulse signal PWM _i ′, and the generation of the drive current I _LEDi by the current source CS _i is stopped. The configuration of the forced turn-off circuit 80 is not limited to that shown in FIG.

The soft start circuit 32a in FIG. 6 includes a capacitor C _SS , a current source 33, and a comparator 35. By charging the capacitor C _SS with the current source 33, a soft start voltage V _SS that increases with time is generated in the capacitor C _SS . The comparator 35 compares the soft start voltage V _SS with the threshold voltage V _{SS_END} and generates a soft start end signal (SS_END signal) that is asserted (high level) when V _SS > V _{SS_END} . Of course, the soft start circuit 32 of FIG. 3 or another configuration may be used instead of the soft start circuit 32a.

Pull-up circuit 90, an active state, the inactive state is configured to switch between the current supply to the LED terminal LED _i in the active state, to pull up the potential of the LED terminal LED _i. The active state and inactive state of the pull-up circuit 90 are controlled by an LEDi_OFF signal described later.

A configuration example of the pull-up circuit 90 will be described. The current source 92 generates a current Ic. Transistors 94 and 96 form a current mirror circuit and copy current Ic. The current Ic is supplied to the LED terminal LED _i through the transistor M90. The transistor 98 is provided between the gate and source of the transistor M94. When the transistor 98 is turned on, the transistors 94 and 96 are turned off, and the output current Ic of the pull-up circuit 90 becomes zero.

The abnormality detection circuit 70 receives the abnormality detection signals OPEN_DET 1 to _n for each channel, the feedback detection signal FB_DET, and the dimming pulse signals PWM 1 to _n for each channel. Based on these signals, the abnormality detection circuit 70 switches the active state and inactive state of the pull-up circuit 90, and performs protection processing and specific control. Specifically, for each channel, the abnormality detection circuit 70 asserts an LED off signal (LEDi_OFF signal) that is asserted when the corresponding LED string 6_i is to be stopped, and when the LED strings 6_1 to 6_n of all the channels are to be stopped. All latch signals (ALL_LATCH signal) to be asserted are generated.

  Next, the function and configuration of the abnormality detection circuit 70 will be described. FIG. 7 is a circuit diagram showing a specific configuration example of the abnormality detection circuit 70 of FIG. FIG. 7 shows only the configuration of the first channel in detail. The other channels are configured in the same manner as the first channel.

  The abnormality detection circuit 70 includes an abnormality (open, ground fault) detection function at startup and an abnormality (open, ground fault) detection function at normal operation.

  The abnormality detection circuit 70 includes a first detection unit 74_i, a second detection unit 76_i, a first OR gate OR1_i, and a third AND gate AND3_1 provided for each channel. The abnormality detection circuit 70 includes a counter 72, a third OR gate OR3, a fourth OR gate OR4, a fourth flip-flop FF4, a fifth flip-flop FF5, and a fourth AND gate AND4 that are provided in common for all channels.

The first detection unit 74_i is provided for detecting an abnormality at the time of activation. When the abnormality detection signal OPEN_DET _i is asserted (high level) during a predetermined period τ _DET in which the generation of the drive current I _LEDi is stopped, 1 The detection signal FF1_Q1 is asserted (high level).

The first detection unit 74_i includes a first flip-flop FF1_i. The corresponding abnormality detection signal OPEN_DET _i is input to the data terminal (D) of the first flip-flop FF1_i, and the PULSE signal from the one-shot circuit 82 is input to the clock terminal. The PULSE signal has a positive edge after a predetermined time τ _{DET is} detected after the START_OK signal is asserted. The abnormality detection signal OPEN_DET _i is latched by this positive edge.

The second detection unit 76_i is provided for detecting an abnormality during normal operation after the completion of the soft start, and generates a second detection signal FF2_Qi that is asserted when the abnormal state continues for a predetermined period T _CP during normal operation.

  The second detection unit 76_i includes a third detection unit 78_i, a second AND gate AND2_i, and a second flip-flop FF2_i.

  The third detection unit 78_i periodically transitions to a low level in a normal state during normal operation, and the third detection signal FF3_Qi that maintains a high level without transitioning to a low level when an abnormal state is detected. Is generated.

The third detection unit 78_i includes a second OR gate OR2_i, a first AND gate AND1_i, and a third flip-flop FF3_i. The second OR gate OR2_i generates a logical sum of the corresponding dimming pulse signal PWM _i and the output FF3_Qi of the corresponding third flip-flop FF3_i. The first AND gate AND1_i generates a logical product of the SS_END signal, the output of the corresponding second OR gate OR2_i, and the corresponding abnormality detection signal OPEN_DET _i . The output of the first AND gate AND1_i is input to the reset terminal (inverted logic) of the corresponding third flip-flop FF3_i. The data terminal (D) of the third flip-flop FF3_i is fixed at a high level, and the system clock CLK is input to the clock terminal.

The LED terminal LED _i, if the LED string 6_i is normally connected, the lighting period _{T ON} in which the dimming pulse signal PWM _i becomes a high _level, since the _{V LEDi>} V _{OPEN_DET,} the abnormality detection signal OPEN_DET _i is Negated (low level). As a result, the output of the first AND gate AND1_i changes to low level, the third flip-flop FF3_i is reset, and the abnormality detection signal FF3_Qi changes to low level.

On the other hand, when the open failure or ground fault on the LED terminal LED _i occurs in the lighting period _{T ON} in which the dimming pulse signal PWM _i becomes a high _level, since the _{V LEDi <V OPEN_DET,} the abnormality detection signal OPEN_DET _i is asserted (High level). As a result, since the output of the first AND gate AND1_i does not transition to the low level, the third flip-flop FF3_i is not reset, and the abnormality detection signal FF3_Qi that is the output of the third flip-flop FF3_i continues to maintain the high level.

The counter 72 and the third OR gate OR3 constitute a timer circuit 73. The timer circuit 73 is a timer circuit 73 any channel of the abnormality detection signal FF3_Qi is to generate a predetermined period of time _{T CP,} when sustained high level asserted (high level) by the count completion signal (COUNT_END signal). The timer circuit 73 asserts the COUNT_END signal when assertion of the LED_GND_DET signal described later continues for a predetermined time T _CP .

  The third OR gate OR3 periodically changes to a low level in a normal state, and generates a reset signal RST that is fixed to a high level when an abnormality occurs. The third OR gate OR3 is a logical sum of the output signals FF3_Q1 to FF3_Qn of the third flip-flops FF3_1 to FF3_n of each channel and a ground fault detection signal (LED_GND_DET signal) indicating that one of the LED terminals is grounded. Is input to the reset terminal (inverted logic) of the counter 72 as the reset signal RST.

The counter 72 counts up in synchronization with the clock CLK input to the clock terminal. In a normal state, a signal input to the reset terminal (inverted logic) of the counter 72 periodically changes to a low level in synchronization with the pulse dimming signal PWM _i, and the counter 72 is reset every cycle. On the other hand, when any abnormality is detected, the reset terminal does not change to the low level. That is, when persistent is abnormal state time, the count-up without counter 72 is reset advances, when the count value reaches a predetermined value corresponding to the time T _CP, the count end signal (COUNT_END signal) is asserted (high level) Is done.

The second AND gate AND2_i generates a logical product of the COUNT_END signal and the output FF3_Qi of the corresponding third flip-flop FF3_i, and inputs the logical product to the clock terminal of the corresponding second flip-flop FF2_i. The data terminal (D) of the second flip-flop FF2_i is fixed at a high level. The second detection signal FF2_Qi, which is the output of the second flip-flop FF2_i, is asserted when the abnormal state continues for a predetermined period T _CP during normal operation.

  The first OR gate OR1_i generates a logical sum of the first detection signal FF1_Qi from the corresponding first detection unit 74_i and the second detection signal FF2_Qi from the corresponding second detection unit 76_i, and drives the corresponding LED string 6_i. LEDi_OFF signal that is asserted (high level) when the signal is to be stopped is generated. That is, the LEDi_OFF signal is asserted when an abnormality is detected at startup or when an abnormality is detected during normal operation. This LEDi_OFF signal is also used to switch the active state and inactive state of the corresponding pull-up circuit 90_i.

The third AND gate AND3_i generates a logical product of the corresponding LEDi_OFF signal, the corresponding abnormality detection signal OPEN_DET _i, and the FB_DET signal. The fourth OR gate OR4 generates a logical sum of the outputs of the third AND gates AND3_1 to AND3_n of all channels. The fourth AND gate AND4 generates an LED_GND_DET signal that is a logical product of the SS_END signal and the output of the fourth OR gate OR4. That is, as a result of pull-up by the pull-up circuit 90_i, when the abnormality detection signal OPEN_DET _i is still asserted, the LED_GND_DET signal is asserted.

  A high-level voltage is input to the data terminal (D) of the fourth flip-flop FF4, a COUNT_END signal is input to its clock terminal, and LED_GND_DET is input to its reset terminal (inverted logic).

  A high level voltage is input to the data terminal (D) of the fifth flip-flop FF5, and an output FF4_Q of the fourth flip-flop FF4 is input to the clock terminal. The output of the fifth flip-flop FF5 is output as the ALL_LATCH signal.

  The above is the configuration of the abnormality detection circuit 70. Next, the operation will be described. FIG. 8 is a flowchart showing the operation of the control IC 100a of FIG.

When the standby signal STB for the control IC 100a instructs the transition from the standby state to the operation state, the activation sequence by the control IC 100a starts (S100). Then, it waits until the end of the soft start or the lighting of the LED string 6 (N in S102). When the SS_END signal is asserted or the LED_ON signal is asserted (Y in S102), the forced turn-off circuit 80 stops the drive current I _LED for a predetermined period τ _DET (S104). As a result, when V _LEDi > V _{OPEN_DET} (Y in S106), normal activation is performed assuming that the LED string 6_i is normally connected to the LED terminal LED _i (S108).

When V _LEDi <V _{OPEN_DET} (N in S106), the output OPEN_DET _i of the abnormality detection comparator COMP_OPEN is asserted, and the first detection signal FF1_Qi is asserted by the first detection unit 74_i, and it is determined that there is an abnormality at startup Is done. Then, the LEDi_OFF signal that is the output of the first OR gate OR1_i is asserted, and the pull-up circuit 90_i becomes active (ON) (S110).

When the pull-up circuit 90_i becomes active, the current Ic is supplied to the LED terminal LED _i . If LED string 6_i the LED terminal LED _i is not connected, the LED terminal LED _i is pulled up by the pull-up circuit _{90_I,} (Y of S112) _{V LEDi>} V _{OPEN_DET} next, the abnormality detection signal OPEN_DET _i is negated (low Level). When the abnormality detection signal OPEN_DET _i continues to be negated, the output of the first AND gate AND1_i remains at the low level, the third flip-flop FF3_Qi maintains the high level, the count operation by the counter 72 proceeds, and the COUNT_END signal is eventually asserted. Thereby, the second detection signal FF2_Qi is asserted, and it is determined that the i-th channel is not used (S114). In this case, the control IC 100a does not use only the i-th channel, and continues to drive the LED strings 6_i of other channels.

Even if the pull-up circuit 90_i becomes active, if the LED terminal LED _i is grounded, the LED terminal LED _i is not pulled up. As a result, V _LEDi <V _{OPEN_DET} (N in S112), and OPEN_DET _i is asserted.
At this time, since the detection voltage V _LEDi is near the ground voltage, the feedback voltage V _FB rises to near the power supply voltage, and the COMP_FB signal is asserted. The LEDi_OFF signal is also asserted. Therefore, the output of the third AND gate AND3_i becomes high level. Since the SS_END signal is also asserted, the output of the fourth AND gate AND4, that is, the LED_GND_DET signal is asserted (high level) (S130). When the state in which the LED_GND_DET signal is asserted continues, the reset signal RST, which is the output of the third OR gate OR3, maintains the high level, the count by the counter 72 advances, and the COUNT_END signal is asserted eventually. When the COUNT_END signal is asserted, the ALL_LATCH signal is asserted (S132). If there is even one ground fault channel, the circuit may be damaged. Therefore, when the ALL_LATCH signal is asserted, the control IC 100a stops the switching power supply 4 and the current drive circuit 8.

The process returns to step S108. If no abnormality is detected in the predetermined period τ _DET immediately after startup, the LED strings 6_1 to 6_n are driven through a normal startup sequence (normal operation state). In the normal operation state, the detected voltage _{V LEDi} in lighting period _{T ON} pulse dimming signal PWM _i is asserted is compared with the threshold voltage _{V OPEN_DET.} When V _LEDi > V _{OPEN_DET} (Y in S120), it is determined that the LED string 6_i is normal, and the normal operation state continues.

In the lighting period _{T ON,} when the _{V LEDi <V OPEN_DET} (S120 of N), the output of the 1AND gate AND1 is sustained high level, the third flip-flop FF3_1 is not reset, therefore the counter 72 is also not reset. As a result, the count up of the counter 72 proceeds (N in S122), and when a cycle having an abnormal state continues, the COUNT_END signal is asserted (Y in S122). As a result, the output FF2_Qi of the second flip-flop FF2_i is asserted, and the LEDi_OFF signal is asserted. As a result, the pull-up circuit 90_i becomes active (S124). As a result, when V _LEDi > _{VOPEN_DET} is detected (Y in S126), it is determined that an open failure has occurred in the i-th channel (S128). In this case, the control IC 100a stops driving only the i-th channel and continues driving other channels.

When V _LEDi <V _{OPEN_DET} (N in S126), the abnormality detection signal OPEN_DET _i is asserted. As a result, the LED_GND_DET signal is asserted (S130), and it is determined that there is a ground fault (S132). In this case, driving of all channels is stopped.

The above is the operation of the control IC 100a.
According to the control IC 100a, immediately after the switching power supply 4 is started, a predetermined period τ _{DET in} which the drive current I _LED stops is provided, and the detection voltage V _LED in that period is compared with the threshold voltage, so can state LED string 6_i the terminal LED _i is not connected, or LED terminal LED _i detects a state in which the ground fault.

Further, by providing the pull-up circuit 90_i, it is possible to determine whether the LED terminal LED _i is open or grounded immediately after startup or during normal operation.

Furthermore, since an open state can be detected for each channel, when it is determined that a certain LED terminal LED _i is open, driving can be stopped only for that channel, and driving can be continued for other channels.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and various modifications may exist in each of those constituent elements, each processing process, and a combination thereof. Hereinafter, such modifications will be described.

When the type of the LED string 6 is determined in advance, the clamp circuit 40 may be switched between active and inactive based on the OVP voltage V _OVP .
Alternatively, it may be switched active, inactive based on a voltage drop V _R21 occurring in the current detection resistor R21.

  Those skilled in the art can design another circuit having a function equivalent to that of the abnormality detection circuit 70 of FIG. 7 by a combination of a known digital circuit and analog circuit, and such a circuit is also included in the scope of the present invention. It is.

  Those skilled in the art will appreciate that MOSFETs and bipolar transistors can be substituted. Further, a modification in which the N channel and the P channel, the NPN type and the PNP type are appropriately replaced, and the power supply terminal and the ground terminal are inverted is also included in the scope of the present invention.

  In the embodiment, a non-insulated switching power supply using an inductor has been described, but the present invention can also be applied to an insulating switching power supply using a transformer.

  In the embodiment, the electronic apparatus has been described as an application of the light emitting device 3, but the application is not particularly limited and can be used for lighting or the like.

  In this embodiment, the setting of the high level and low level logic signals of each signal is an example, and can be freely changed by appropriately inverting it with an inverter or the like.

  Although the present invention has been described using specific terms based on the embodiments, the embodiments only illustrate the principles and applications of the present invention, and the embodiments are defined in the claims. Many variations and modifications of the arrangement are permitted without departing from the spirit of the present invention.

SW1 ... feedback switch, OA1 ... operational amplifier, L1 ... inductor, C1 ... output capacitor, D1 ... rectifier diode, M1 ... switching transistor, 2 ... electronic device, 3 ... light emitting device, 4 ... switching power supply, 5 ... LCD panel, 6 DESCRIPTION OF SYMBOLS ... LED string, 8 ... Current drive circuit, 9 ... PWM controller, M11 ... 1st transistor, M12 ... 2nd transistor, M13 ... 3rd transistor, M14 ... 4th transistor, 19 ... Pulse generation part, 20 ... Pulse modulator 21 ... gm amplifier, M21 ... driving transistor, R21 ... current detection resistor, 22 ... error amplifier, M22 ... dimming switch, 24 ... oscillator, 26 ... PWM comparator, 28 ... driver, 32 ... soft start circuit, 34 ... Counter, 36 ... D / A converter, 40 ... Class 60 ... Lighting detection circuit, 70 ... Abnormality detection circuit, 80 ... Forced extinction circuit, 82 ... One-shot circuit, 84 ... AND gate, COMP_OPEN ... Abnormality detection comparator, COMP_FB ... Feedback voltage comparator, 90 ... Pull-up Reference numeral 94, AND gate, 100, control IC, 102, output circuit, PWM, pulse signal for dimming.

Claims (8)

A control circuit for controlling a switching power supply for supplying a driving voltage to the first terminal of the light emitting element and generating a driving current flowing in the light emitting element;
A connection terminal to which the second terminal of the light emitting element is to be connected;
A current drive circuit that is connected to the connection terminal and generates an intermittent drive current according to the dimming pulse signal;
An error amplifier that generates a feedback voltage according to an error between a detection voltage generated at the connection terminal and a predetermined reference voltage;
A pulse modulator that generates a pulse signal having a duty ratio corresponding to the feedback voltage;
A driver for driving a switching element of the switching power supply based on the pulse signal;
An abnormality detection comparator that generates an abnormality detection signal that is asserted when the detection voltage is lower than a predetermined threshold voltage;
A pull-up circuit configured to switch between an active state and an inactive state according to a control input, and supplying a current to the connection terminal in the active state;
When the abnormality detection signal is asserted, the pull-up circuit is activated by the control input , and an abnormality detection circuit that detects whether the abnormality detection signal is asserted in the active state of the pull-up circuit;
A control circuit comprising: A forced turn-off circuit for stopping generation of the drive current by the current drive circuit for a predetermined period after the operation of the switching power supply is started;
The abnormality detection circuit activates the pull-up circuit when the abnormality detection signal is asserted during the predetermined period, and detects whether the abnormality detection signal is asserted after activating the pull-up circuit. The control circuit according to claim 1.   3. The control according to claim 2, wherein the forced turn-off circuit stops generation of the drive current by the current drive circuit for the predetermined period after the drive current flowing through the light emitting element reaches a predetermined level. circuit.   The said forced light-off circuit stops generation | occurrence | production of the said drive current by the said current drive circuit for the said predetermined period after the soft start voltage which raises with time reaches a predetermined level, The said drive current generation is characterized by the above-mentioned. Control circuit. The abnormality detection circuit is
Whether the abnormality detection signal is asserted after the pull-up circuit is activated when the abnormality detection signal is asserted during a period in which the current driving circuit generates the driving current, and the pull-up circuit is activated The control circuit according to claim 1, wherein:   The abnormality detection circuit is
  When the abnormality detection signal is asserted by the abnormality detection comparator, the pull-up circuit is activated, and when the abnormality detection signal is not asserted by the abnormality detection comparator, the pull-up circuit is inactive.
  6. The method according to claim 1, wherein after the pull-up circuit is activated by the abnormality detection signal, the abnormality detection comparator detects again whether the abnormality detection signal is asserted. Control circuit according to. A light emitting element;
A switching power supply for supplying a driving voltage to one end of the light emitting element;
The switching power supply comprises:
An output circuit including a switching element;
The control circuit according to any one of claims 1 to 6 , which drives the switching element;
A light emitting device comprising: LCD panel,
The light emitting device according to claim 7 provided as a backlight of the liquid crystal panel;
An electronic device comprising:

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