JP5735250B2 - Switching control device, power conversion device, and integrated circuit - Google Patents

Description

  The present invention relates to a switching control device, a power conversion device, and an integrated circuit.

  Electromagnetic interference (EMI) caused by transient high-frequency current generated during switching in power converters that convert power by switching elements on and off, including switching regulators and charge pump circuits Noise can occur. In recent years, with the increase in electronic devices that handle radio waves and high-frequency electrical signals (especially information communication devices that handle digital signals such as mobile phones and personal computers), home appliances that are commonly used in ordinary households are the sources of noise. There is a possibility.

  This EMI noise may affect the operation of surrounding devices, and it is necessary to reduce the EMI noise particularly for mobile phones and medical devices that handle radio waves.

  Japanese Patent Application Laid-Open No. 2007-209130 (Patent Document 1) discloses a switching in a pulse width modulation (PWM) control circuit that determines on / off timing of a switching element of a power conversion device having a switching element. EMI noise can be reduced without changing the PWM carrier frequency by setting the timing with the smaller EMI noise level as the fixed period and controlling the pulse width of the larger timing among the on timing of the device and the switching device off timing. Disclosure technology is disclosed.

JP 2007-209130 A

  According to Japanese Patent Laying-Open No. 2007-209130 (Patent Document 1), since the generation cycle of the timing at which the noise level increases is temporally dispersed, the peak value of the EMI noise level is reduced.

  However, in a technique such as Japanese Patent Application Laid-Open No. 2007-209130 (Patent Document 1), although the peak value of the EMI noise level is reduced, the frequency of the generated EMI noise does not change. The peak occurs.

  For this reason, when the frequency band of this EMI noise is close to the operating frequency, radio frequency, or the like of surrounding devices, there is a possibility that the influence on these devices cannot be reduced.

  The present invention has been made to solve such a problem, and an object of the present invention is to reduce the influence on the surrounding devices due to the EMI noise generated when the switching element is driven.

  The switching control device according to the present invention includes a PWM signal generation unit and a buffer circuit, and drives the switching element according to a control command. The PWM signal generation unit generates a timing signal for driving the switching element based on the pulse signal from the oscillator and the control command. In response to the timing signal, the buffer circuit periodically changes the gate current supplied to the gate of the switching element to change the switching speed.

  Preferably, the buffer circuit includes a plurality of buffers. The buffer circuit changes the gate current by periodically controlling the plurality of buffers.

  Preferably, the buffer circuit changes the gate current by changing the number of buffers supplying the gate current among the plurality of buffers in accordance with the timing signal.

  Preferably, the plurality of buffers include first and second buffers. The second buffer operates at a rate of once every two cycles of the operation of the first buffer.

  Preferably, the second buffer is set to supply a gate current equal to that of the first buffer.

  Preferably, the second buffer is set to supply a gate current different from that of the first buffer.

  Preferably, the gate current is set to a different value for each of the plurality of buffers. The buffer circuit further includes a switching unit for switching the plurality of buffers in response to the timing signal in order to change the gate current.

  A power conversion device according to the present invention includes a switching element, a PWM signal generation unit, and a buffer circuit, and converts power from a power source and supplies it to a load by an on / off operation of the switching element according to a control command. . The PWM signal generation unit generates a timing signal for driving the switching element based on the pulse signal from the oscillator and the control command. In response to the timing signal, the buffer circuit periodically changes the gate current supplied to the gate of the switching element to change the switching speed.

  Preferably, the power conversion device is a converter that performs at least one of step-up and step-down of a DC voltage from a power source.

  An integrated circuit according to the present invention includes a switching element, an oscillator, a PWM signal generation unit, and a buffer circuit, and converts power from a power source to a load by on / off operation of the switching element according to a control command. The power converter to be supplied is controlled. The PWM signal generation unit generates a timing signal for driving the switching element based on the pulse signal from the oscillator and the control command. In response to the timing signal, the buffer circuit periodically changes the gate current supplied to the gate of the switching element to change the switching speed.

  According to the present invention, the frequency of the EMI noise generated when the switching element is driven can be dispersed and the peak generated at a specific frequency can be suppressed, so that the influence of the EMI noise on the surrounding devices is reduced. can do.

It is a functional block diagram of a power converter device provided with the switching control apparatus according to Embodiment 1. It is a figure which shows an example of the EMI noise signal when the rise and fall of a gate signal are steep. It is a figure which shows an example of an EMI noise signal in case the rise and fall of a gate signal are gentle. It is a figure which shows the example of the relationship between an EMI noise level and a frequency at the time of changing the rise time and fall time of a gate signal. 3 is a time chart for explaining the state of each signal in the first embodiment. It is a figure which shows the example of an integrated circuit provided with the switching control apparatus according to Embodiment 1. FIG. It is a functional block diagram of a power converter device provided with the switching control apparatus according to the modification of Embodiment 1. FIG. It is a functional block diagram of a power converter device provided with the switching control apparatus according to Embodiment 2.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a functional block diagram of a power conversion device 100 including a switching control device 200 according to the first embodiment.

  Referring to FIG. 1, power conversion device 100 includes a power supply node 120, a switching control device 200, a coil L1, a switching element TR1, a capacitor C1, and a resistor R1, for example, an LED (Light Emitting Diode). A predetermined DC voltage is supplied to the load 110 such as. In FIG. 1, a configuration using an N-type metal oxide field effect transistor (MOSFET) as the switching element TR1 will be described. However, the switching element TR1 uses a bipolar transistor or another transistor. be able to.

  One end of coil L1 is connected to power supply node 120, and the other end is connected to the drain of switching element TR1. The source of the switching element TR1 is grounded, and the gate is connected to the output of the switching control device 200.

  One end of the load 110 is connected to the drain of the switching element TR1 via the diode D1, and the other end is grounded via the resistor R1. The diode D1 is connected with the direction from the drain of the switching element TR1 toward the load 110 as the forward direction.

  That is, coil L1 and switching element TR1 operate as a chopper circuit, boost the voltage of power supply node 120 according to the duty of the gate signal generated by switching control device 200, and supply it to load 110.

  The capacitor C1 is connected between the drain of the switching element TR1 and the ground, and smoothes the voltage supplied to the load 110.

  A connection node between the load 110 and the resistor R1 is connected to an input of the switching control device 200, and a feedback circuit is formed.

  Switching control device 200 includes a PWM signal generation unit 210, an oscillator 220, and a buffer circuit 205. The buffer circuit 205 includes buffers 230 and 231 and a modulation unit 240.

  The PWM signal generation unit 210 receives a boost command SIG from an external control device (not shown), a reference voltage REF, a feedback signal FB, and an oscillation signal OSC from the oscillator 220. The PWM signal generation unit 210 compares the deviation between the reference voltage REF and the feedback signal FB with a carrier signal generated based on the oscillation signal OSC, and generates a PWM signal that becomes the gate signal of the switching element TR1. . Then, the PWM signal generation unit 210 outputs the generated PWM signal to the buffers 230 and 231 in accordance with the boost command SIG.

  The buffers 230 and 231 are connected in parallel between the PWM signal generation unit 210 and the gate of the switching element TR1. The buffers 230 and 231 supply a predetermined gate voltage to the gate of the switching element TR1 based on the PWM signal from the PWM signal generation unit 210. When the PWM signal is turned on, the buffers 230 and 231 increase the gate voltage applied to the gate by supplying a gate current and charging the gate with charges. Further, when the PWM signal is turned off, the buffers 230 and 231 lower the gate voltage by discharging the charge charged in the gate. Depending on the magnitude of this gate current, the rising and falling slopes (that is, the switching speed) of the gate signal are determined. Note that the magnitudes of the gate currents that can be supplied to each of the buffers 230 and 231 may be the same or different.

  The buffer 230 is always active, and supplies a gate current to the gate of the switching element TR1 at the same timing as the PWM signal from the PWM signal generation unit 210.

  The buffer 231 is activated when the enable signal EN from the modulation unit 240 is set to ON, and supplies a gate current to the gate of the switching element TR1 according to the PWM signal from the PWM signal generation unit 210. On the other hand, the buffer 231 is inactive when the enable signal EN is set to OFF, and does not supply a gate current even when receiving a PWM signal.

  Modulator 240 receives oscillation signal OSC from oscillator 220. Then, the modulation unit 240 modulates the received oscillation signal OSC, generates an enable signal EN at the modulated timing, and outputs the enable signal EN to the buffer 231.

  In the first embodiment, for example, modulation section 240 sets enable signal EN to ON with a period twice that of oscillation signal OSC of oscillator 220. As a result, the gate current is output from the buffer 231 at a frequency of once every two cycles of the PWM signal. The switching speed changes between when the gate current is supplied only by the buffer 230 and when the gate current is supplied from both the buffers 230 and 231.

  Next, the relationship between the switching speed of the gate signal and the EMI noise generated by the switching operation will be described with reference to FIGS. FIG. 2 is a diagram illustrating an example of the EMI noise signal when the rise and fall of the gate signal are steep. FIG. 3 is a diagram showing an example of the EMI noise signal when the rise and fall of the gate signal are gentle.

  2 and 3, generally, the frequency component of the generated EMI noise is correlated with the rise and fall times of the gate signal of the switching element, and the higher the gate signal changes, the higher the frequency component. EMI noise including frequency components is generated. That is, in the case of FIG. 2, that is, when the supplied gate current is large and the rise and fall of the gate signal are steep, the higher frequency components are included in the EMI noise generated compared to the case of FIG. Become.

  FIG. 4 shows the relationship between the EMI noise level and the noise frequency fn. In the case of FIG. 2, the noise level peaks in the high frequency region as shown by the curve W1 in FIG. The noise level peaks in a region where the frequency is lower than that of the curve W1, as indicated by a dashed curve W2 in FIG.

  Therefore, when switching is performed by alternately repeating the case of FIG. 2 and the case of FIG. 3, the curves W1 and W2 are averaged over time, and the noise level peak generated as shown by the curve W3 in FIG. 4 is relaxed. In addition, the generated frequency components are dispersed in time.

  FIG. 5 is a time chart for explaining the state of each signal in the first embodiment. In FIG. 5, the horizontal axis represents time, and the vertical axis represents the oscillation signal OSC of the oscillator 220, the enable signal EN of the modulation unit 240, the PWM signal of the PWM signal generation unit 210, the operating state of the buffers 230 and 231, The state of the gate signal supplied to the gate of the switching element TR1 is also shown.

  Referring to FIG. 5, the oscillation signal OSC is a pulse signal having a constant period T. The enable signal EN is a signal that is alternately turned on and off every period T.

  The PWM signal is a pulse waveform having a period T according to a duty ratio determined from the deviation of the reference voltage REF and the feedback signal FB and the carrier signal, that is, a pulse waveform having a pulse width D where the duty ratio = D / T. .

  Since the buffer 230 is always active as described above, the buffer 230 operates in synchronization with the PWM signal.

  On the other hand, since the buffer 231 becomes active when the enable signal EN is on, the buffer 231 operates every 2T period, that is, at times t1 to t2 and t5 to t6 in FIG.

  As a result, at times t1 to t2 and t5 to t6 when both the buffers 230 and 231 are in the operating state, the gate current is supplied from both buffers, so that the rise and fall of the gate signal become steep. On the other hand, from time t3 to t4 when the buffer 231 is stopped, only the gate current from the buffer 230 is supplied, so that the rise and fall of the gate signal become gentle.

  Therefore, as described above, the frequency of the generated EMI noise differs between time t1 to t2, t5 to t6, and time t3 to t4. As a result, the noise level peak is reduced. As a result, it is possible to reduce the influence of EMI noise on surrounding devices.

  In the above-described example, the buffer 231 is configured to be active at a period twice as long as the period T. However, the buffer 231 may be activated at a period that is three times or four times, for example. Further, the gate current supplied in each buffer is appropriately set according to the switching speed of a desired gate signal. However, it should be noted that the slower the switching speed, that is, the smaller the slope, the greater the switching loss in the switching element TR1, so it is necessary to set the gate current within the allowable switching loss range. Should.

  In the above example, the configuration in which the gate current is changed using two buffers has been described. However, the same function as the above buffer circuit can be achieved by using one buffer capable of setting a plurality of levels of gate current. It can also be configured to be realized.

  FIG. 6 shows an example in which the switching control device 200 and the switching element TR1 are packaged as an integrated circuit 150 in the power conversion device 100 shown in FIG. An overcurrent protection unit 170 and an overvoltage protection unit 160 are added to the integrated circuit 150 as necessary.

  The overcurrent protection unit 170 detects the current flowing through the source of the switching element TR1, and when the detected current exceeds the threshold, the operation of the switching control device 200 is stopped to protect the device.

  The overvoltage protection unit 160 detects the voltage on the power supply side of the load 110, and when the detected voltage exceeds a threshold value, stops the operation of the switching control device 200 to protect the device.

[Modification of Embodiment 1]
In the first embodiment described above, the configuration in which two buffers are provided and the switching speed of the gate signal is changed by setting each operation period to a different period has been described. However, the number of buffers is two. Not limited to three or more cases.

  FIG. 7 is a functional block diagram of a power conversion device 100A including a switching control device 200A having three buffers, in which another buffer 232 is added to the switching control device 200 of FIG. In FIG. 7, the description of the elements overlapping with those in FIG. 1 will not be repeated.

  In this modification, the buffer circuit 205A includes buffers 230, 231, 232, and a modulation unit 240. Modulation section 240 outputs enable signals EN1 and EN2 to buffer 231 and buffer 232, respectively. The buffer 231 and the buffer 232 are activated when the enable signals EN1 and EN2 are turned on, respectively. In the above example, the buffer is active when the enable signal is on. However, the logic of the enable signal is not limited to this. For example, the buffer is active when the enable signal is off. It may be set.

  By appropriately setting the enable signals EN1 and EN2 and the gate current that can be supplied from each buffer, the switching speed of the gate signal can be changed to, for example, three stages or four stages. Then, since the frequency of the generated EMI noise can be further dispersed, it is possible to reduce the influence of the EMI noise on surrounding devices.

[Embodiment 2]
In the first embodiment and its modification, the configuration in which the switching speed of the gate signal is changed by changing the number of buffers that supply the gate current in the plurality of buffers has been described.

  In the second embodiment, a configuration will be described in which a plurality of buffers having different gate currents that can be supplied are set, and the switching speed of the gate signal is changed by switching the buffer to be used according to the PWM signal.

  FIG. 8 is a functional block diagram of a power conversion device 100B including the switching control device 200B according to the second embodiment. In FIG. 8, the description of the same elements as those in FIG. 1 will not be repeated.

  Referring to FIG. 8, switching control device 200B has a configuration in which buffer circuit 205 is replaced with buffer circuit 205B in switching control device 200 of FIG. Buffer circuit 205B includes buffers 230B and 231B and a switching unit 250.

  The buffers 230B and 231B are set so that the gate currents that can be supplied have different values.

  Buffer 230B is connected between the gate of switching element TR1 and terminal T0 of switching unit 250. Buffer 231B is connected between the gate of switching element TR1 and terminal T1 of switching unit 250.

  The switching unit 250 switches the connection between the terminals T0 and T1 and the PWM signal generation unit 210 alternately according to the oscillation signal OSC from the oscillator 220.

  By adopting such a configuration and appropriately setting the buffers 230B and 231B, the switching speed of the gate signal can be changed for each period of the PWM signal. As a result, the frequency of the generated EMI noise can be dispersed, so that the influence of the EMI noise on surrounding devices can be reduced.

In the second embodiment, the number of buffers may be three or more.
In the present embodiment, the configuration in which the power conversion device is a boost converter that boosts the DC power supply voltage to a desired voltage has been described as an example. However, the configuration of the power conversion device is not limited thereto. In other words, if the power is converted by the on / off operation of the switching element, it can be used as a step-down converter that steps down the DC power supply voltage, a converter that converts AC power into DC power, an inverter that converts DC power into AC power, etc. Is also applicable.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  100, 100A, 100B Power conversion device, 110 load, 120 power node, 150 integrated circuit, 160 overvoltage protection unit, 170 overcurrent protection unit, 200, 200A, 200B switching control device, 205, 205A, 205B buffer circuit, 210 PWM Signal generation unit, 220 oscillator, 230, 230B, 231, 231B, 232 buffer, 240 modulation unit, 250 switching unit, C1 capacitor, D1 diode, L1 coil, R1 resistor, T0, T1 terminal, TR1 switching element.

Claims (9)

A switching control device for driving a switching element according to a control command,
A PWM signal generator for generating a timing signal for driving the switching element, based on a pulse signal from an oscillator and the control command;
A buffer circuit configured to change a switching speed by periodically changing a gate current supplied to the gate of the switching element in response to the timing signal ;
The buffer circuit includes first and second buffers,
Changing the gate current by periodically controlling the first and second buffers;
Said second buffer that runs once every 2 or more integer multiples of the period of operation of the first buffer, the switching control unit. The said buffer circuit changes the said gate current by changing the number of the buffers which supply the said gate current among the said 1st and 2nd buffers according to the said timing signal. The switching control device described. Before Stories second buffer operates once every two cycles of operation of said first buffer, the switching control device according to claim 1. The switching control device according to claim 1 , wherein the second buffer is set to supply a gate current equal to that of the first buffer.   The switching control device according to claim 1, wherein the second buffer is set to supply a gate current different from that of the first buffer. The gate current is set to different values in the first and second buffer,
The buffer circuit is
The switching control device according to claim 2, further comprising a switching unit configured to switch the first and second buffers in response to the timing signal in order to change the gate current. A power converter for converting power from a power source and supplying it to a load by an on / off operation of a switching element according to a control command,
The switching element;
A PWM signal generator for generating a timing signal for driving the switching element, based on a pulse signal from an oscillator and the control command;
A buffer circuit configured to change a switching speed by periodically changing a gate current supplied to the gate of the switching element in response to the timing signal ;
The buffer circuit includes first and second buffers,
Changing the gate current by periodically controlling the first and second buffers;
Said second buffer that runs once every 2 or more integer multiples of the period of operation of the first buffer, the power conversion device. The power converter according to claim 7 , wherein the power converter is a converter that performs at least one of step-up and step-down of a DC voltage from the power source. An integrated circuit for controlling a power conversion device that converts power from a power source and supplies it to a load by an on / off operation of a switching element according to a control command,
The switching element;
An oscillator,
A PWM signal generator for generating a timing signal for driving the switching element, based on the pulse signal from the oscillator and the control command;
A buffer circuit configured to change a switching speed by periodically changing a gate current supplied to the gate of the switching element in response to the timing signal ;
The buffer circuit includes first and second buffers,
Changing the gate current by periodically controlling the first and second buffers;
The integrated circuit , wherein the second buffer operates at a rate of once every two or more integer multiples of the operation of the first buffer .

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