JP5733150B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device including a step of forming a plating layer on a surface electrode of a semiconductor wafer.

  Manufacturing of a semiconductor device comprising a step of preparing a semiconductor wafer having a front surface electrode of a semiconductor element formed on the front surface and a back surface electrode of the semiconductor element formed on the back surface, and a plating step of forming a plating layer on the front surface electrode of the semiconductor wafer The method is disclosed in Patent Documents 1 and 2.

  Specifically, in Patent Document 1, in the plating process, a plating layer is formed on both the front electrode and the back electrode, and the plating layer is also formed on the side surface of the semiconductor wafer in addition to the front electrode and the back electrode. Is disclosed.

  Patent Document 2 discloses that in the plating step, the surface electrode is subjected to a plating treatment in a state where the surface electrode is exposed and the surface electrode is covered.

JP 2010-205991 A JP 2010-182807 A

  By the way, in the case where the plating layer is formed on the front electrode and the plating layer is not formed on the back electrode, the front surface electrode is exposed and the semiconductor wafer is covered with the back electrode as in Patent Document 2. It is necessary to immerse in the plating solution. This is because an unnecessary plating layer is formed on the back electrode, thereby preventing the electrical resistance of the back electrode from fluctuating (increasing).

  In addition, when forming a plating layer on the surface electrode of the semiconductor wafer, if the plating layer is formed on the outer peripheral portion or the back surface of the semiconductor wafer, the plating layer formed on the surface electrode of the semiconductor wafer may vary. Is generally known (see, for example, paragraph 0019 of Patent Document 2).

  As a countermeasure, it is conceivable to immerse the semiconductor wafer in a plating solution in a state where the surface electrode of the semiconductor wafer is exposed and other than the surface electrode of the semiconductor wafer is covered.

  However, actually, the inventor forms a Zn—NiP—Au plating layer by exposing the surface electrode made of Al of the semiconductor wafer and covering all of the side and back surfaces of the semiconductor wafer other than the surface electrode of the semiconductor wafer. As a result, formation failure (defect) of the Zn plating layer occurred, and as a result, the Au plating layer could not be formed without unevenness. It is generally known that the formation of the Au plating layer requires the formation of a Zn plating layer.

  In addition, not only when forming a Zn plating layer on a surface electrode made of Al, but also when forming a plating layer other than Zn on a surface electrode made of a material other than Al, it is desirable that the plating layer can be formed without defects. It is.

  In view of the above points, the present invention provides a plating on the surface electrode while suppressing the influence of the electrical resistance of the back electrode due to the formation of an unnecessary plating layer on the back electrode when forming the plating layer on the surface electrode. An object of the present invention is to provide a method for manufacturing a semiconductor device in which a layer can be formed without defects.

  In order to achieve the above object, the present inventor has intensively studied, exposing the surface electrode formed on the surface of the semiconductor wafer and covering the back surface of the semiconductor wafer, when immersing the semiconductor wafer in the plating solution, It has been experimentally found that when at least a part of the side surface of the semiconductor wafer is exposed, a plating layer can be formed on the surface electrode without any defect, and the present invention has been completed.

  Incidentally, in the above-mentioned Patent Document 1, for example, in FIG. 2, the plating film 4 is formed in the entire area of the metal layer 2 on the one surface 1a, and the one surface 1a on which the plating film 4 is formed is shown in FIG. As can be seen, this is the back side of the semiconductor wafer. Therefore, in patent document 1, the back surface of a semiconductor wafer is coat | covered and the semiconductor wafer is not immersed in a plating solution.

  Moreover, in the above-mentioned Patent Document 2, when the front surface electrode is plated, the back electrode of the semiconductor wafer is covered (see FIG. 3), but it is not described until the side surface of the semiconductor wafer is covered. . In FIG. 3 of Patent Document 2 after the plating process, the plating layers 11 and 12 are illustrated on the emitter electrode 6, but the plating layer is not illustrated on the side surface of the semiconductor wafer, and the side surface of the semiconductor wafer is illustrated. It is not described that a plating layer is formed on the surface.

In the invention according to claim 1 , in the plating step, the back surface (1b) of the semiconductor wafer is covered with the covering material (11) having the opening (13), and the front surface electrode (2) and the side surface (1c) of the semiconductor wafer are covered. And the semiconductor wafer (1) is immersed in a plating solution in a state in which only a part of the back surface (1b) is exposed through the opening.
The part of the exposed portion of the back surface (1b) is a region where no semiconductor element is formed.

  According to this, a plating layer can be formed in a surface electrode without a defect. Moreover, according to this, only a plating layer is formed in the area | region where the semiconductor element of the semiconductor wafer is not formed, and it can prevent that an unnecessary plating layer is formed in the back surface electrode of a semiconductor element.

According to the second aspect of the present invention, in the plating step, the semiconductor wafer (1) is plated with the plating solution in a state where only the front surface electrode (2), the side surface (1c), and the back surface (1b) of the semiconductor wafer are exposed. Soak in
The part of the exposed portion of the back surface (1b) is provided on all of the plurality of chips and is provided only on a part of one chip.

  According to this, a plating layer can be formed in a surface electrode without a defect. In this case, a plating layer is formed on a part of the back electrode of the semiconductor element in each chip. However, compared to the case where the plating layer is formed over the entire back electrode of each chip, the electrical resistance of the back electrode is reduced. Can be kept low.

  Furthermore, according to this, the mark which shows that plating was able to be formed in the surface electrode (2) can be provided to a back surface electrode (1b). Although it is unclear whether or not plating has been formed even if the front electrode (2) is inspected, the back electrode (1b) can be unevenly colored by plating, so that the plating on the front electrode (2) can be performed. The presence or absence of formation can be confirmed.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim is an example which shows a corresponding relationship with the specific means as described in embodiment mentioned later.

It is an upper surface perspective view of the semiconductor wafer at the time of the plating process in 1st Embodiment. It is sectional drawing of the semiconductor wafer at the time of the plating process in 1st Embodiment. It is sectional drawing of the surface electrode and plating layer after the plating process in 1st Embodiment. It is a conceptual diagram of the plating reaction at the time of the plating process in 1st Embodiment. It is sectional drawing of the semiconductor wafer at the time of the plating process in 2nd Embodiment. It is a conceptual diagram of the plating reaction at the time of the plating process in 2nd Embodiment. It is sectional drawing of the semiconductor wafer at the time of the plating process in 3rd Embodiment. It is a conceptual diagram of the plating reaction at the time of the plating process in 3rd Embodiment.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are given the same reference numerals in the drawings in order to simplify the description.

(First embodiment)
The method of manufacturing a semiconductor device according to the present invention includes a step of preparing a semiconductor wafer having a front surface electrode of a semiconductor element formed on the front surface and a back surface electrode of the semiconductor element formed on the back surface, and forming a plating layer on the front surface electrode of the semiconductor wafer The present invention is applied to a method of manufacturing a semiconductor device that performs a plating step of performing and a step of dicing a semiconductor wafer into a plurality of chips after the plating step.

  The prepared semiconductor wafer is a semiconductor wafer made of SiC, and the semiconductor element formed on the semiconductor wafer made of SiC is a vertical semiconductor element, for example, an SBD (Schottky barrier diode) or MOSFET. . In the case of SBD, the anode electrode is the front electrode, and the cathode electrode is the back electrode. In the case of MOSFET, a gate electrode and a source electrode are front surface electrodes, and a drain electrode is a back surface electrode.

  For example, after forming a plurality of semiconductor element structures on the surface side of a semiconductor wafer, an Al layer or an Al alloy layer as a surface electrode is formed on the surface of the semiconductor wafer by vapor deposition or sputtering, and on the back surface of the semiconductor wafer, A Ti / Ni / Au layer as a back electrode is formed by vapor deposition or sputtering. In the step of preparing a semiconductor wafer, a semiconductor wafer on which surface electrodes and the like are thus formed is prepared.

  In the plating step, a Zn plating layer, a Ni-P plating layer, and an Au plating layer are sequentially formed on the surface of the Al layer or Al alloy layer as the surface electrode. FIG. 1 shows a top perspective view of a semiconductor wafer during the plating step, and FIGS. 2A and 2B show cross-sectional views of the semiconductor wafer during the plating step. FIG. 3 shows a cross-sectional view of the surface electrode and the plating layer after the plating step.

  Specifically, first, as shown in FIGS. 1 and 2A, a back surface protection film 11 is attached to the back surface 1 b of the semiconductor wafer 1. A surface electrode 2 of a semiconductor element is formed for each chip on the surface 1a of the semiconductor wafer 1 to which the film 11 is attached. 1 and 2, for convenience, the surface electrode 2 is shown in a size corresponding to a chip, and one surface electrode 2 indicates the range of one chip.

  The film 11 is a covering material that covers the back surface 1 b of the semiconductor wafer 1, and another covering material may be used instead of the film 11. At this time, for example, the adhesive 12 is applied to the back surface 1b of the semiconductor wafer 1 and the film 11 is attached.

  As a result, as shown in FIG. 2A, the surface electrode 2 and the entire side surface 1c of the semiconductor wafer 1 are exposed and the entire back surface 1b of the semiconductor wafer 1 is covered.

  Incidentally, a protective film is usually formed on the surface 1a of the semiconductor wafer 1, and the surface electrode 2 is exposed from the protective film.

  2A shows a state in which the entire side surface 1c of the semiconductor wafer 1 is exposed. However, only a part of the side surface 1c of the semiconductor wafer 1 may be exposed. When only a part of the side surface 1c of the semiconductor wafer 1 is exposed, for example, after the film 11 is pasted, the adhesive 12 is separately attached to the side surface 1c of the semiconductor wafer 1 or bonded to the back surface 1b of the semiconductor wafer 1 When a large amount of the agent 12 is applied and the film 11 is attached, the adhesive 12 protrudes from the semiconductor wafer 1, and the protruding adhesive 12 covers a part of the side surface 1 c of the semiconductor wafer 1.

  In this state, the semiconductor wafer 1 is immersed in a plating solution, thereby forming a plating layer 3 on the surface electrode 2 as shown in FIG. Specifically, by immersing the semiconductor wafer 1 in the order of the plating solution for forming Zn, the plating solution for forming the Ni-P layer, and the plating solution for forming the Au layer, as shown in FIG. On the surface, a Zn plating layer 4, a Ni-P plating layer 5, and an Au plating layer 6 are formed in this order. In FIG. 3, the Zn plating layer 4 is shown in the plating layer 3. However, since the Zn plating layer 4 is replaced with Ni when the Ni—P plating layer 5 is formed, finally, Presumed not to exist.

  At this time, since the entire or part of the side surface 1c of the semiconductor wafer 1 is in contact with the plating solution, the plating layer 3 is also formed on the side surface 1c of the semiconductor wafer 1 as shown in FIG.

  Thus, by performing a plating process, the Zn plating layer 4 can be formed in the surface electrode 2 without a defect, As a result, the Au plating layer 6 can be reliably formed in the uppermost part of the surface electrode 2.

  The reason is presumed as follows. In FIG. 4, the conceptual diagram of the plating reaction at the time of a plating process is shown. In FIG. 4, the front surface electrode 2 is exposed from the protective film 7 on the front surface 1 a of the semiconductor wafer 1, and the back surface electrode 8 is covered with the film 11 on the back surface 1 b of the semiconductor wafer 1. The state when 1 is immersed in a plating solution is shown.

As shown in FIG. 4, in the surface electrode 2, Al is ionized and removed (Al → Al ³⁺ + 3e ⁻ ), and in the removed part, a part of electrons generated by the ionization of Zn ions in the plating solution And becomes Zn (Zn ²⁺ + 2e ⁻ → Zn). Furthermore, the remainder of the electrons generated by the ionization of Al escape to the side surface 1c of the semiconductor wafer 1, and at this position, the Zn ions in the plating solution receive the electrons and become Zn (1 / 2Zn ²⁺ e ⁻ → 1 / 2Zn), a Zn plating layer 4 is formed on the side surface 1c of the semiconductor wafer 1.

  Thus, according to the present embodiment, since the remainder of the electrons generated by the ionization of Al can be released to the side surface 1c of the semiconductor wafer 1, the surface electrode 2 can be surely caused to have a plating reaction, and the surface It is estimated that the Zn plating layer 4 can be formed on the electrode 2 without unevenness.

  In general, since the Ni—P plating layer and the Au plating layer can be easily formed on the surface of the Zn layer, the Ni—P plating layer 5 and the Au plating layer 6 can be reliably formed on the surface electrode 2. . In addition, after the formation of the Zn plating layer 4, the Ni—P plating layer 5 and the Au plating layer 6 can be formed in a state where the side surface 1 c of the semiconductor wafer 1 is covered.

  Although the case where the Zn plating layer 4 is formed on the Al layer or the Al alloy layer as the surface electrode 2 has been described here, the plating solution is compared with ions that escape from the surface electrode as in the relationship between Al and Zn. If the valence of ions in the electrode is small and the size of the ions that escape from the surface electrode and the size of the ions in the plating solution are close to each other, the surface electrode and the plating layer may be made of other metals. However, as in the present embodiment, it is considered that the plating layer can be formed evenly on the surface electrode.

  By the way, when a semiconductor device is manufactured using a semiconductor wafer made of SiC, SiC is more expensive than other semiconductor wafers. Therefore, the manufacturing cost of the semiconductor device increases only by using a semiconductor wafer made of SiC.

  On the other hand, according to the present embodiment, as described above, the Au layer 6 can be formed on the surface electrode 2 by a plating method, and the plating method can form the Au layer at a lower cost than the sputtering method. Manufacturing cost can be suppressed. Incidentally, since the surface electrode 2 has a minute pattern shape, when it is formed by the sputtering method, the non-formation region of the Au layer is masked with a resist, and the step of removing the resist after sputtering is necessary. The Au layer can be formed at a lower cost by the plating method.

(Second Embodiment)
This embodiment is the same as the first embodiment except that the exposed portion of the semiconductor wafer during the plating step is different from the first embodiment. Below, a different point from 1st Embodiment is demonstrated.

  5A and 5B are cross-sectional views of the semiconductor wafer during the plating process in the present embodiment. As shown in FIG. 5A, in the plating process, a back surface protection film 11 is attached to the back surface 1b of the semiconductor wafer 1, and the front electrode 2, the side surface 1c of the semiconductor wafer 1, and a part of the back surface 1b are exposed. And a state other than a part of the back surface 1b of the semiconductor wafer 1 is covered. That is, only a part of the back surface 1b of the semiconductor wafer 1 is exposed.

  In the present embodiment, a part of the back surface 1b serving as the exposed portion is a portion corresponding to a region where no semiconductor element is formed. Here, the region where the semiconductor element is not formed is an outer peripheral portion of the semiconductor wafer 1 or a dicing line.

  Moreover, in this embodiment, since a part of back electrode contacts a plating solution, it comprises with a noble metal rather than the metal which plating a back electrode. When forming a Zn plating layer, a back surface electrode can be comprised by Ti / Ni / Au, for example.

  In FIG. 5A, the side surface 1c of the semiconductor wafer 1 is partially covered with the adhesive 12 so that a part of the side surface 1c of the semiconductor wafer 1 is exposed. The entire area of 1c may be exposed.

  As a method of exposing only a part of the back surface 1b of the semiconductor wafer 1, for example, as shown in FIG. 5A, the film 11 is exposed when the film 11 is attached to the back surface 1b of the semiconductor wafer 1. An opening 13 is provided in advance in the film 11 at a position facing a part of the back surface 1 b, and after the adhesive 12 is applied to the film 11, the film 11 is bonded to the semiconductor wafer 1. Moreover, after affixing the film 11 to the back surface 1b of the semiconductor wafer 1, the opening 13 may be formed in a part of the film 11 by laser irradiation or the like.

  Moreover, when exposing the part corresponding to an outer peripheral part among the back surfaces 1b of the semiconductor wafer 1, the shape of the opening part 13 is made into ring shape, for example.

  In this state, the plating layer 3 is formed on the surface of the surface electrode 2 as shown in FIG. 5B by immersing the semiconductor wafer 1 in the plating solution, as in the first embodiment. The plating layer 3 is the same as that in the first embodiment (see FIG. 3). In this embodiment, in addition to the side surface 1c of the semiconductor wafer 1, a part of the back surface 1b (region where the semiconductor element is not formed) is also in contact with the plating solution, so that the side surface 1c of the semiconductor wafer 1 and a part of the back surface ( The plating layer 3 is also formed in a region where no semiconductor element is formed.

  Thus, by performing the plating step, the Zn plating layer 4 can be formed on the surface electrode 2 without any defects in the present embodiment. As a result, the Au plating layer 6 is formed on the uppermost portion of the surface electrode 2. Can be reliably formed.

  The reason is presumed as follows. In FIG. 6, the conceptual diagram of the plating reaction at the time of a plating process is shown.

  As shown in FIG. 6, in this embodiment, in addition to letting the remainder of electrons generated by ionization of Al in the front surface electrode 2 escape to the side surface 1 c of the semiconductor wafer 1, in the part of the back surface 1 b of the semiconductor wafer 1. Therefore, it is presumed that the plating reaction can be surely caused on the surface electrode 2 and the Zn plating layer 4 can be formed on the surface electrode without any unevenness.

(Third embodiment)
This embodiment is the same as the second embodiment except for the specific position of a part of the back surface of the semiconductor wafer that is exposed during the plating process. Below, a different point from 2nd Embodiment is demonstrated.

  7A and 7B are cross-sectional views of the semiconductor wafer during the plating process in the present embodiment. As shown in FIG. 7A, in this embodiment, a part of the exposed portion of the back surface 1b of the semiconductor wafer 1 is provided on all of the plurality of chips cut from the semiconductor wafer in the dicing process, and It is provided only for a part. For example, one exposed portion is formed for each chip. A plurality of exposed portions may be formed for one chip.

  In FIG. 7A, a part of the side surface 1c of the semiconductor wafer 1 is exposed, but the entire side surface 1c of the semiconductor wafer 1 may be exposed. Further, as a method of exposing only a part of the back surface 1b of the semiconductor wafer 1, a method similar to that of the second embodiment can be employed.

  In this state, the plating layer 3 is formed on the surface of the surface electrode 2 as shown in FIG. 7B by immersing the semiconductor wafer 1 in the plating solution as in the first embodiment. The plating layer 3 is the same as that in the first embodiment (see FIG. 3). In the present embodiment, in addition to the side surface 1c of the semiconductor wafer 1, a part of the back surface 1b (a part of the back surface electrode in all chips) is also in contact with the plating solution. The plating layer 3 is also formed on the portion (a part of the back surface electrode in all the chips).

  Thus, by performing the plating step, the Zn plating layer 4 can be formed on the surface electrode 2 without any defects in the present embodiment. As a result, the Au plating layer 6 is formed on the uppermost portion of the surface electrode 2. Can be reliably formed.

  The reason is presumed as follows. In FIG. 8, the conceptual diagram of the plating reaction at the time of a plating process is shown.

  As shown in FIG. 8, in the present embodiment, in addition to letting the remainder of electrons generated by ionization of Al in the front surface electrode 2 escape to the side surface 1 c of the semiconductor wafer 1, in the part of the back surface 1 b of the semiconductor wafer 1. Can also escape. In particular, in the present embodiment, electrons can escape from the front surface electrode 2 through the semiconductor wafer 1 to the back surface electrode 8 in the shortest distance for each region to be a chip. Thereby, it is speculated that the plating reaction can be surely caused on the surface electrode 2 and the Zn plating layer 4 can be formed on the surface electrode 2 without unevenness.

  By the way, in this embodiment, as shown in FIG.7 (b), in each chip | tip, the plating layer 3 is formed in a part of back electrode of a semiconductor element, and after the dicing process, each plating layer 3 was formed, and each Although the back electrode of the chip is solder-connected to the external terminal, the influence on the electrical resistance of the back electrode can be suppressed to a lower level as compared with the case where a plating layer is formed over the entire area of the back electrode of each chip.

  In order to suppress the influence on the electrical resistance of the back surface electrode, a part of the back surface of the semiconductor wafer exposed during the plating process should be an end portion in which current hardly flows in the back surface electrode of each chip. preferable.

  In the present embodiment, as shown in FIG. 7B, since the plating layer 3 is formed on a part of the back electrode of the semiconductor element in each chip, the plating layer of the back electrode is formed on the surface of each chip. This can be used as a mark that a plating layer is formed on the electrode.

(Other embodiments)
In each of the above-described embodiments, a semiconductor wafer made of SiC is used. However, the present invention is applicable not only to SiC but also to a semiconductor wafer such as Si. However, as described in the first embodiment, the valence of ions in the plating solution is smaller than the ions that escape from the surface electrode as in the relationship between Al and Zn, and the size of the ions that escape from the surface electrode It is considered necessary to have a close relationship with the size of ions in the plating solution.

  Examples 1-4 of the present invention and Comparative Examples 1 and 2 are shown below.

  In Examples 1 to 4, a SiC wafer 1 having an Al layer as the front electrode 2 formed on the front surface 1a and a Ti / Ni / Au layer as the back electrode 8 formed on the back surface 1b is prepared. On the other hand, by the plating method described in the first to third embodiments, the steps shown in Table 1 below are sequentially performed, and the Zn plating layer 4, the Ni—P plating layer 5, and the Au plating layer 6 are formed on the surface electrode 2. Were formed in order.

  Examples 1 and 2 correspond to the first embodiment. In Example 1, the entire side surface 1c of the semiconductor wafer 1 was exposed. In Example 2, a part of the side surface 1c of the semiconductor wafer 1 was exposed. It was in a state. Then, a plating solution for forming Zn (Steps 4 and 6 in Table 1), a plating solution for forming a Ni-P layer (Step 7 in Table 1), and a plating solution for forming an Au layer (Step 8 in Table 1). The semiconductor wafer 1 was dipped in order.

  Example 3 corresponds to the second embodiment. In Example 3, a part of the side surface 1b of the semiconductor wafer 1 is exposed, and the outer periphery of the back surface 1b of the semiconductor wafer 1 where no semiconductor element is formed. The semiconductor wafer 1 was immersed in the plating solution in the same manner as in Examples 1 and 2, with only the part corresponding to the part exposed.

  Example 4 corresponds to the third embodiment, and in Example 4, the entire side surface 1b of the semiconductor wafer 1 is exposed, and one chip is provided for every chip on the back surface 1b of the semiconductor wafer 1. With the exposed portion formed, the semiconductor wafer 1 was immersed in a plating solution as in Examples 1 and 2.

  In Comparative Examples 1 and 2, the semiconductor wafer 1 was immersed in a plating solution in the same manner as in Examples 1 and 2 with the entire side surface 1c and the entire back surface 1b of the semiconductor wafer 1 covered.

  And the plating layer 3 formed in each Example and the comparative example was evaluated. The evaluation results are shown in Table 2. The side surface opening ratio and the back surface opening ratio in Table 2 are results calculated from the area of the plating layer 3 formed on the side surface 1c and the back surface 1b of the semiconductor wafer 1.

表２に示すように、比較例１、２では、表面電極２にＡｕめっき層６を欠陥無く形成することができなかったが、実施例１〜４では、表面電極２にＡｕめっき層６を欠陥無く形成することができた。

As shown in Table 2, in Comparative Examples 1 and 2, the Au plating layer 6 could not be formed on the surface electrode 2 without any defects, but in Examples 1 to 4, the Au plating layer 6 was formed on the surface electrode 2. It was possible to form without defects.

  Further, from the results of Examples 1 and 2, when the entire surface of the back surface 1b of the semiconductor wafer 1 is covered and the side surface 1c of the semiconductor wafer 1 is exposed, and is immersed in the plating solution, It can be seen that if the plating layer 3 is formed in a region of 57.9% or more with respect to the entire area of the side surface 1c, the Au plating layer 6 can be finally formed on the surface electrode 2 without any defects.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1a The surface of a semiconductor wafer 1b The back surface of a semiconductor wafer 1c The side surface of a semiconductor wafer 2 Surface electrode 4 Zn plating layer (plating layer)
5 Ni-P plating layer (plating layer)
6 Au plating layer (plating layer)
8 Back electrode 11 Film (coating material)

Claims (2)

It has a front surface (1a), a back surface (1b) opposite to the front surface, and a side surface (1c), a surface electrode (2) of a semiconductor element is formed on the front surface (1a), and the semiconductor is formed on the back surface (1b). Preparing a semiconductor wafer (1) on which the back electrode (8) of the element is formed;
In the manufacturing method of the semiconductor device which has a plating process of forming a plating layer (3) on the surface electrode (2) of the semiconductor wafer (1),
The plating step covers the back surface (1b) with a covering material (11) having an opening (13), exposes the surface electrode (2) and the side surface (1c), and passes through the opening. In a state where only a part of the back surface (1b) is exposed, the semiconductor wafer (1) is immersed in a plating solution,
The method of manufacturing a semiconductor device, wherein the part of the exposed portion of the back surface (1b) is a region where the semiconductor element is not formed. It has a front surface (1a), a back surface (1b) opposite to the front surface, and a side surface (1c), a surface electrode (2) of a semiconductor element is formed on the front surface (1a), and the semiconductor is formed on the back surface (1b). Preparing a semiconductor wafer (1) on which the back electrode (8) of the element is formed;
A plating step of forming a plating layer (3) on the surface electrode (2) of the semiconductor wafer (1);
In the method for manufacturing a semiconductor device, the method includes a step of dicing the semiconductor wafer (1) into a plurality of chips after the plating step.
The plating step is performed by immersing the semiconductor wafer (1) in a plating solution in a state where only the surface electrode (2), the side surface (1c), and a part of the back surface (1b) are exposed.
The method for manufacturing a semiconductor device, wherein the part of the exposed portion of the back surface (1b) is provided on all of the plurality of chips and only on a part of the one chip.

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