JP5728102B1 - MMIC integrated circuit module - Google Patents
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Abstract
【課題】MMIC集積回路モジュールにおける誘電体基板の反りに起因する導波管の伝搬損失増加を防止する。【解決手段】MIC集積回路モジュールに横型導波管101、曲げ導波管102、縦型導波管103を形成する。これにより、誘電体基板(1、2、4)1枚あたりの開口部面積を小さくでき、よって、誘電体基板に加わる積層の応力に起因する反りを小さくでき、反りに起因する導波管の伝搬損失増加を防止できる。【選択図】図1An increase in propagation loss of a waveguide due to warping of a dielectric substrate in an MMIC integrated circuit module is prevented. A horizontal waveguide 101, a bending waveguide 102, and a vertical waveguide 103 are formed in an MIC integrated circuit module. As a result, the opening area per dielectric substrate (1, 2, 4) can be reduced, and hence the warpage caused by the stress of the lamination applied to the dielectric substrate can be reduced, and the waveguide caused by the warpage can be reduced. An increase in propagation loss can be prevented. [Selection] Figure 1
Description
本発明は、MMIC集積回路モジュールにおける誘電体基板の反りに起因する導波管の伝搬損失増加を防止する技術に関する。 The present invention relates to a technique for preventing an increase in propagation loss of a waveguide caused by warpage of a dielectric substrate in an MMIC integrated circuit module.
図4は、従来のMMIC集積回路モジュールの断面図である。図5は、図4のB−B矢視図である。 FIG. 4 is a cross-sectional view of a conventional MMIC integrated circuit module. 5 is a BB arrow view of FIG.
金属ベース7に切削形成された導波管8内の台座71には、MMIC3と該MMIC3への給電配線および信号配線を形成した誘電体基板9が実装される。金属フタ20には、金属ベース7と同様切削加工により、導波管8の一部、遮蔽部2a、IC格納部2bが形成される。 On the base 71 in the waveguide 8 cut and formed in the metal base 7, the dielectric substrate 9 on which the MMIC 3 and the power supply wiring and signal wiring to the MMIC 3 are formed is mounted. A part of the waveguide 8, the shielding part 2 a, and the IC storage part 2 b are formed on the metal lid 20 by cutting as with the metal base 7.
MMIC3の回路領域31には、送受信用のアンプや変調器等の回路が形成される。回路領域31と外部配線ピン30は、誘電体基板9や誘電体基板9上のパッド9Pなどを介して接続される。 In the circuit area 31 of the MMIC 3, circuits such as transmission / reception amplifiers and modulators are formed. The circuit region 31 and the external wiring pin 30 are connected via the dielectric substrate 9 and the pads 9P on the dielectric substrate 9.
導波管結合部32は、導波管8のTE10モードからMMIC3における伝送線路の導波管モードへの変換機能を有する。効率良く導波管8のTE10モードと結合するために導波管8のおよそ中央に導波管結合部32が配置される。遮蔽部2aは、IC格納部2bへ電磁波が漏れないように、導波管8より1段低く形成される。 The waveguide coupling unit 32 has a function of converting the TE 10 mode of the waveguide 8 to the waveguide mode of the transmission line in the MMIC 3. In order to efficiently couple with the TE10 mode of the waveguide 8, the waveguide coupling portion 32 is disposed at approximately the center of the waveguide 8. The shield 2a is formed one step lower than the waveguide 8 so that electromagnetic waves do not leak into the IC storage 2b.
導波管8の開口部81には、例えば、金属ホーン(図示せず)などが接続される。 For example, a metal horn (not shown) or the like is connected to the opening 81 of the waveguide 8.
図4等に示した従来のMIC集積回路モジュールは、誘電体基板の実装が必要である他、外部の電源や外部配線ピンのサイズが大きくなるため、小型化が困難だった。また、金属ベース、金属フタにより導波管を形成するには、高精度の切削技術や特殊なメッキ技術が必要であり、高コストが課題だった。 In the conventional MIC integrated circuit module shown in FIG. 4 and the like, it is difficult to reduce the size because the dielectric substrate needs to be mounted and the size of the external power supply and the external wiring pin becomes large. In addition, in order to form a waveguide with a metal base and a metal lid, high-precision cutting technology and special plating technology are required, and high cost has been a problem.
例えば、金属ベースに代え、多層誘電体基板を用いることで、小型化と加工コストの低減が実現できる。 For example, by using a multilayer dielectric substrate instead of a metal base, downsizing and reduction in processing cost can be realized.
しかしながら、多層誘電体基板を用いると、積層の応力により、誘電体基板に反りが生じることがある。そして、反りが原因で電磁波の漏れが生じ、導波管の伝搬損失が増加する可能性がある。 However, when a multilayer dielectric substrate is used, the dielectric substrate may be warped due to the stress of lamination. Then, electromagnetic wave leakage may occur due to warpage, and propagation loss of the waveguide may increase.
本発明は、上記の課題に鑑みてなされたものであり、その目的とするところは、MMIC集積回路モジュールにおける誘電体基板の反りに起因する導波管の伝搬損失増加を防止することにある。 The present invention has been made in view of the above problems, and an object of the present invention is to prevent an increase in propagation loss of a waveguide due to warping of a dielectric substrate in an MMIC integrated circuit module.
上記の課題を解決するために、本発明に係るMMIC集積回路モジュールは、開口部が形成された第1誘電体基板と、前記第1誘電体基板の一方面に積層され、前記開口部の一部に面した前記第1誘電体基板の部分である台座と前記開口部とをあわせた領域にあわせて開口部が形成された第2誘電体基板と、前記台座の前記一方面に実装されるMMICと、前記第1誘電体基板の他方面に積層され、前記第1誘電体基板の開口部における前記台座に接していない領域にあわせて開口部が形成された第3誘電体基板と、前記第1誘電体基板、前記第2誘電体基板および前記第3誘電体基板の開口部を囲むように当該第1誘電体基板、第2誘電体基板および第3誘電体基板に設けられる貫通ビアおよび金属層と、前記第2誘電体基板の前記一方面側に配置され、前記第1誘電体基板の開口部に向けて開口する凹部が形成された金属フタとを備え、前記金属フタの凹部において、前記第3誘電体基板の開口部に対向する部分は、前記MMICの方向に傾いている斜面部であることを特徴とする。 In order to solve the above-described problems, an MMIC integrated circuit module according to the present invention includes a first dielectric substrate having an opening formed thereon, and is stacked on one surface of the first dielectric substrate. A second dielectric substrate having an opening formed in accordance with a region where the pedestal that is the portion of the first dielectric substrate facing the portion and the opening is combined, and mounted on the one surface of the pedestal An MMIC, a third dielectric substrate laminated on the other surface of the first dielectric substrate, and having an opening formed in a region not in contact with the pedestal in the opening of the first dielectric substrate; A through hole provided in the first dielectric substrate, the second dielectric substrate, and the third dielectric substrate so as to surround openings of the first dielectric substrate, the second dielectric substrate, and the third dielectric substrate; A metal layer and the one surface of the second dielectric substrate; Disposed toward the opening of the first dielectric substrate and a metal lid with a recess formed to open in the concave portion of the metal lid, the portion facing the opening of the third dielectric substrate , and wherein the inclined surface portion der Rukoto which are inclined in the direction of the MMIC.
本発明によれば、MMIC集積回路モジュールにおける誘電体基板の反りに起因する導波管の伝搬損失増加を防止できる。 ADVANTAGE OF THE INVENTION According to this invention, the propagation loss increase of the waveguide resulting from the curvature of the dielectric substrate in a MMIC integrated circuit module can be prevented.
以下、本発明の実施の形態について図面を参照して説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[第1の実施の形態]
図1は、第1の実施形態に係るMMIC集積回路モジュールの断面図である。図2は、図1のA−A矢視図である。図3は、図1のMMIC集積回路モジュールの上面図である。
[First Embodiment]
FIG. 1 is a cross-sectional view of the MMIC integrated circuit module according to the first embodiment. FIG. 2 is an AA arrow view of FIG. FIG. 3 is a top view of the MMIC integrated circuit module of FIG.
図1に示すように、MMIC集積回路モジュールは、開口部11が形成された第1誘電体基板1と、第1誘電体基板1の一方面(図では上側の面)に積層され、開口部11の一部に面した第1誘電体基板1の部分である台座12と開口部11とをあわせた領域にあわせて開口部21が形成された第2誘電体基板2と、台座12の前記一方面(図では上側の面)に実装されるMMIC(モノリシックマイクロ波集積回路:monolithic microwave integrated circuit)3と、第1誘電体基板1の他方面(図では下側の面)に積層され、第1誘電体基板1の開口部11における台座12に接していない領域111にあわせて開口部41が形成された(図では3枚)の第3誘電体基板4と、第1誘電体基板1の開口部11を囲むように第1誘電体基板1に設けられる貫通ビア1Aおよび金属層1Bと、第2誘電体基板2の開口部21を囲むように第2誘電体基板2に設けられる貫通ビア2Aおよび金属層2Bと、第3誘電体基板4の開口部41を囲むように第3誘電体基板4に設けられる貫通ビア4Aおよび金属層4Bと、第2誘電体基板2の一方面側(図では上側の面)に配置され、第1誘電体基板1の開口部11に向けて開口する凹部51が形成された金属フタ5とを備えることを特徴とする。 As shown in FIG. 1, the MMIC integrated circuit module is laminated on a first dielectric substrate 1 having an opening 11 formed on one surface (the upper surface in the figure) of the first dielectric substrate 1 and the opening A second dielectric substrate 2 in which an opening 21 is formed in accordance with a region where the pedestal 12 which is a part of the first dielectric substrate 1 facing a part of the substrate 11 and the opening 11 are combined; MMIC (monolithic microwave integrated circuit) 3 mounted on one side (upper side in the figure) and the other side (lower side in the figure) of the first dielectric substrate 1 are laminated, A third dielectric substrate 4 (three in the figure) in which an opening 41 is formed in accordance with a region 111 not in contact with the pedestal 12 in the opening 11 of the first dielectric substrate 1, and the first dielectric substrate 1 The first dielectric substrate 1 is provided so as to surround the opening 11 of the first dielectric substrate 1. Through-via 1A and metal layer 1B, through-via 2A and metal layer 2B provided in second dielectric substrate 2 so as to surround opening 21 of second dielectric substrate 2, and opening of third dielectric substrate 4 41, a through via 4A and a metal layer 4B provided in the third dielectric substrate 4 so as to surround the first dielectric substrate 1, and a first dielectric substrate 1 disposed on one surface side (the upper surface in the drawing) of the second dielectric substrate 2. And a metal lid 5 formed with a recess 51 that opens toward the opening 11.
このような構成により、MMIC集積回路モジュールには、横型導波管101、曲げ導波管102、縦型導波管103が形成される。つまり、L字型の導波管が形成される。導波管の高さは、例えば、0.8mmであり、幅は、例えば、0.4mmである。この場合、H面曲げ導波管となる。導波管として機能させるためには、同一の誘電体基板における貫通ビアの間隔を、導波管を伝搬する電磁波の波長の1/4以下とするのが好ましい。これにより、貫通ビアの間から電磁波が漏れず、導波管として機能する。金属層と貫通ビアには、例えば、導電性銀フィラーを混入した銀ペーストを用いる。 With such a configuration, the horizontal waveguide 101, the bending waveguide 102, and the vertical waveguide 103 are formed in the MMIC integrated circuit module. That is, an L-shaped waveguide is formed. The height of the waveguide is, for example, 0.8 mm, and the width is, for example, 0.4 mm. In this case, it becomes an H-plane bending waveguide. In order to function as a waveguide, it is preferable that the interval between through vias in the same dielectric substrate is ¼ or less of the wavelength of the electromagnetic wave propagating through the waveguide. Thereby, electromagnetic waves do not leak from between the through vias and function as a waveguide. For the metal layer and the through via, for example, a silver paste mixed with a conductive silver filler is used.
各誘電体基板には、低温焼成セラミックスLTCC(Low Temperature Confired Ceramics)やポリイミド等を用いることができ、厚さは例えば100μm(ミクロン)程度である。 Each dielectric substrate can be made of low temperature fired ceramics (LTCC), polyimide, or the like, and has a thickness of about 100 μm (micron), for example.
誘電体基板の数は、本実施の形態の数に限らず、例えば、縦型導波管103を長くすべく、第3誘電体基板4を4枚以上設けてもよい。 The number of dielectric substrates is not limited to the number of the present embodiment, and for example, four or more third dielectric substrates 4 may be provided in order to lengthen the vertical waveguide 103.
ここで、比較例として、曲げ導波管102、縦型導波管103を設けず、横型導波管101を図左側に延長したMMIC集積回路モジュールを考える。 Here, as a comparative example, consider an MMIC integrated circuit module in which the bending waveguide 102 and the vertical waveguide 103 are not provided, and the horizontal waveguide 101 is extended to the left side of the figure.
本実施の形態のMMIC集積回路モジュールと比較例のMMIC集積回路モジュールとで、導波管の実質的な長さを同じにした場合、本実施の形態のMMIC集積回路モジュールの導波管はL字型なので、誘電体基板1枚あたりの開口部面積を小さくできる。よって、誘電体基板に加わる積層の応力に起因する反りを小さくでき、反りに起因する導波管の伝搬損失増加を防止できる。 When the MMIC integrated circuit module of the present embodiment and the MMIC integrated circuit module of the comparative example have the same substantial length of the waveguide, the waveguide of the MMIC integrated circuit module of the present embodiment is L Since it is a letter shape, the opening area per dielectric substrate can be reduced. Therefore, the warpage due to the stress of the lamination applied to the dielectric substrate can be reduced, and an increase in the propagation loss of the waveguide due to the warpage can be prevented.
MMIC3は、回路領域31と、回路領域31に接続された導波管結合部32を有する。回路領域31には、送受信用のアンプや変調器等の回路が形成される。導波管結合部32は、横型導波管101のTE10モードからMMIC3における伝送線路の導波管モードへの変換機能を有する。 The MMIC 3 includes a circuit region 31 and a waveguide coupling portion 32 connected to the circuit region 31. In the circuit area 31, circuits such as amplifiers and modulators for transmission and reception are formed. The waveguide coupling unit 32 has a function of converting the TE10 mode of the horizontal waveguide 101 to the waveguide mode of the transmission line in the MMIC 3.
MMIC3は、例えば、集積回路を形成した化合物半導体である。MMIC3は、例えば、導電性を有する接着剤により、台座12に固定される。 The MMIC 3 is, for example, a compound semiconductor that forms an integrated circuit. The MMIC 3 is fixed to the pedestal 12 with, for example, a conductive adhesive.
なお、MMIC3を実装したポリマー基板などの上に導波管結合部32を形成しても、同様の構成となる。 Even if the waveguide coupling portion 32 is formed on a polymer substrate or the like on which the MMIC 3 is mounted, the same configuration is obtained.
導波管結合部32は、例えば、MMIC3の厚さや第1誘電体基板1の厚さや枚数を適宜選択することにより、横型導波管101のH面中央に配置されるのが好ましい。このような配置により、効率的な結合変換が可能となる。 The waveguide coupling portion 32 is preferably arranged at the center of the H surface of the horizontal waveguide 101 by appropriately selecting the thickness of the MMIC 3 and the thickness and number of the first dielectric substrate 1, for example. Such an arrangement enables efficient coupling conversion.
凹部51は、金等でメッキされている。また、凹部51の、曲げ導波管102を構成する部分は、斜面部511となっており、インピーダンスの変化を抑えることができる。つまり、横型導波管101からの電磁波を縦型導波管103へ導波し、縦型導波管103からの電磁波を横型導波管101へ導波するようになっている。斜面部511の表面は平面であり滑らかであることが好ましいが、階段状でもよい。この場合、階段の段差は波長の1/10程度であることが好ましい。 The recess 51 is plated with gold or the like. Moreover, the part which comprises the bending waveguide 102 of the recessed part 51 becomes the slope part 511, and can suppress the change of an impedance. That is, the electromagnetic wave from the horizontal waveguide 101 is guided to the vertical waveguide 103, and the electromagnetic wave from the vertical waveguide 103 is guided to the horizontal waveguide 101. The surface of the slope portion 511 is preferably flat and smooth, but may be stepped. In this case, the step of the staircase is preferably about 1/10 of the wavelength.
また、凹部51の、横型導波管101を構成する部分は、横型導波管101の高さに応じた高さとなっているが、凹部51の、台座12に対向する部分は、横型導波管101から、図では右方向(後述のIC格納部514)に電磁波が漏れないように、1段低い遮蔽部512となっている。また、遮蔽部512に連なるIC格納部514は、MMIC3やパッド2Pと接触しないように設計される。 Further, the portion of the recess 51 that constitutes the horizontal waveguide 101 has a height corresponding to the height of the horizontal waveguide 101, but the portion of the recess 51 that faces the pedestal 12 is the horizontal waveguide. The shielding portion 512 is one step lower so that the electromagnetic wave does not leak from the tube 101 in the right direction (an IC storage portion 514 described later) in the drawing. Further, the IC storage unit 514 connected to the shielding unit 512 is designed so as not to contact the MMIC 3 and the pad 2P.
図2に示すように、横型導波管101、曲げ導波管102の周囲に貫通ビア(1A、2A、4A)と金属層(1B、2Bなど)が形成される。 As shown in FIG. 2, through vias (1A, 2A, 4A) and metal layers (1B, 2B, etc.) are formed around the horizontal waveguide 101 and the bent waveguide 102.
導波管の短辺側のE面壁Eは、金属層1Bで構成される。また、導波管の長辺側のH面壁Hには、貫通ビア(1A、2A、4A)と金属層(2Bなど)が形成されている。 The E-face wall E on the short side of the waveguide is composed of the metal layer 1B. Further, through-vias (1A, 2A, 4A) and metal layers (2B, etc.) are formed on the H-side wall H on the long side of the waveguide.
横型導波管101のインピーダンスは、導波管のサイズや貫通ビアの配置により制御可能であり、導波管結合部32との結合効率が最大となるようにするのが好ましい。 The impedance of the horizontal waveguide 101 can be controlled by the size of the waveguide and the arrangement of through vias, and it is preferable that the coupling efficiency with the waveguide coupling portion 32 is maximized.
また、縦型導波管103をE面、H面の方向に徐々に広げることによりホーンアンテナを形成してもよい。 Further, the horn antenna may be formed by gradually expanding the vertical waveguide 103 in the direction of the E plane and the H plane.
第2誘電体基板2の上側の面には、MMIC3への給電配線や信号配線(共に不図示)および接続用のパッド2Pが形成される。 On the upper surface of the second dielectric substrate 2, a power supply wiring and signal wiring (both not shown) to the MMIC 3 and a connection pad 2P are formed.
また、MMIC集積回路モジュールは、金属フタ5における凹部51の周囲部分52と該周囲部分に対向する第2誘電体基板2の金属層2Bとの間に挟持される基板の反りによる微小な空隙を塞ぐために、さらに複数のスタッドバンプ6を備えてもよい。スタッドバンプ6は、例えば、金で形成される。また金属層2Bや貫通ビア2A等と同電位となる。 Further, the MMIC integrated circuit module has a minute gap due to the warp of the substrate sandwiched between the peripheral portion 52 of the recess 51 in the metal lid 5 and the metal layer 2B of the second dielectric substrate 2 facing the peripheral portion. In order to close it, a plurality of stud bumps 6 may be further provided. The stud bump 6 is made of, for example, gold. Further, it has the same potential as the metal layer 2B, the through via 2A, or the like.
スタッドバンプ6は、第2誘電体基板2の金属層2Bの無い部分において、給電配線、信号配線、パッド2Pと導通しないように配置される。 The stud bump 6 is arranged so as not to be electrically connected to the power supply wiring, the signal wiring, and the pad 2P in a portion where the metal layer 2B of the second dielectric substrate 2 is not present.
スタッドバンプ6は、例えば、球形であり、その中心同士の配置間隔を波長の1/4以下(例えば、200μm)とすることで、金属フタ5と金属層2Bの間から電磁波が漏れるのを防止できる。 The stud bump 6 has, for example, a spherical shape, and prevents the electromagnetic waves from leaking between the metal lid 5 and the metal layer 2B by setting the arrangement interval between the centers to ¼ or less of the wavelength (for example, 200 μm). it can.
各誘電体基板において積層による反りがない理想状態では、各スタッドバンプ6は不要である。しかし、反りがある場合は、上記のようにスタッドバンプ6の中心同士の配置間隔を例えば波長の1/4以下として電磁波の漏れ防止を図った上で、図1で最も下の第3誘電体基板4の下側面(底面)に対し、金属フタ5の上面が平行となるように、各スタッドバンプ6サイズを個別に調整(レベリング調整)することが好ましい。 In an ideal state where there is no warpage due to lamination in each dielectric substrate, each stud bump 6 is not necessary. However, if there is a warp, the arrangement distance between the centers of the stud bumps 6 is set to, for example, ¼ or less of the wavelength as described above to prevent leakage of electromagnetic waves, and the lowest third dielectric in FIG. It is preferable to individually adjust (leveling adjustment) the size of each stud bump 6 so that the upper surface of the metal lid 5 is parallel to the lower surface (bottom surface) of the substrate 4.
以上のように、本実施の形態に係るMIC集積回路モジュールによれば、横型導波管101、曲げ導波管102、縦型導波管103を形成したことで、誘電体基板1枚あたりの開口部面積を小さくでき、よって、誘電体基板に加わる積層の応力に起因する反りを小さくでき、反りに起因する導波管の伝搬損失増加を防止できる。 As described above, according to the MIC integrated circuit module according to the present embodiment, the horizontal waveguide 101, the bending waveguide 102, and the vertical waveguide 103 are formed. The area of the opening can be reduced, so that the warp caused by the stress of the lamination applied to the dielectric substrate can be reduced, and an increase in the propagation loss of the waveguide caused by the warp can be prevented.
また、本実施の形態のMMIC集積回路モジュールは、誘電体基板を積層して構成するので、誘電体基板に貫通ビアや配線を施すことで、MMICへの給電や信号供給ができ、また、導波管を一体形成できるので、MMIC集積回路モジュールを小型化することができる。また、金属ベースが不要であり、よって、高精度の切削技術や特殊なメッキ技術が不要であるから、加工コストを低減できる。 In addition, since the MMIC integrated circuit module according to the present embodiment is formed by stacking dielectric substrates, power can be supplied to the MMIC and signals can be supplied by providing through vias and wiring on the dielectric substrate. Since the wave tube can be integrally formed, the MMIC integrated circuit module can be reduced in size. In addition, a metal base is not required, and therefore high-precision cutting technology and special plating technology are not required, so that the processing cost can be reduced.
1…第1誘電体基板
1A、2A、4A…貫通ビア
1B、2B、4B…金属層
2…第2誘電体基板
3…MMIC
4…第3誘電体基板
5…金属フタ
6…スタッドバンプ
7…金属ベース
11…開口部
12…台座
21…開口部
31…回路領域
32…導波管結合部
41…開口部
51…凹部
52…周囲部分
101…横型導波管
102…曲げ導波管
103…縦型導波管
111…領域
511…斜面部
512…遮蔽部
514…IC格納部
E…E面壁
H…H面壁
DESCRIPTION OF SYMBOLS 1 ... 1st dielectric substrate 1A, 2A, 4A ... Through-via 1B, 2B, 4B ... Metal layer 2 ... 2nd dielectric substrate 3 ... MMIC
DESCRIPTION OF SYMBOLS 4 ... 3rd dielectric substrate 5 ... Metal lid 6 ... Stud bump 7 ... Metal base 11 ... Opening part 12 ... Base 21 ... Opening part 31 ... Circuit area 32 ... Waveguide coupling part 41 ... Opening part 51 ... Concave part 52 ... Surrounding portion 101 ... Horizontal waveguide 102 ... Bending waveguide 103 ... Vertical waveguide 111 ... Region 511 ... Slope portion 512 ... Shielding portion 514 ... IC storage portion E ... E surface wall H ... H surface wall
Claims (2)
前記第1誘電体基板の一方面に積層され、前記開口部の一部に面した前記第1誘電体基板の部分である台座と前記開口部とをあわせた領域にあわせて開口部が形成された第2誘電体基板と、
前記台座の前記一方面に実装されるMMICと、
前記第1誘電体基板の他方面に積層され、前記第1誘電体基板の開口部における前記台座に接していない領域にあわせて開口部が形成された第3誘電体基板と、
前記第1誘電体基板、前記第2誘電体基板および前記第3誘電体基板の開口部を囲むように当該第1誘電体基板、第2誘電体基板および第3誘電体基板に設けられる貫通ビアおよび金属層と、
前記第2誘電体基板の前記一方面側に配置され、前記第1誘電体基板の開口部に向けて開口する凹部が形成された金属フタと
を備え、
前記金属フタの凹部において、前記第3誘電体基板の開口部に対向する部分は、前記MMICの方向に傾いている斜面部である
ことを特徴とするMMIC集積回路モジュール。 A first dielectric substrate having an opening formed thereon;
The first dielectric substrate is laminated on one surface, and an opening is formed in accordance with a region where the pedestal that is a portion of the first dielectric substrate facing a part of the opening and the opening is combined. A second dielectric substrate;
MMIC mounted on the one surface of the pedestal;
A third dielectric substrate laminated on the other surface of the first dielectric substrate and having an opening formed in a region not in contact with the pedestal in the opening of the first dielectric substrate;
Through vias provided in the first dielectric substrate, the second dielectric substrate, and the third dielectric substrate so as to surround the openings of the first dielectric substrate, the second dielectric substrate, and the third dielectric substrate. And with a metal layer,
A metal lid disposed on the one surface side of the second dielectric substrate and formed with a recess that opens toward the opening of the first dielectric substrate ;
In the recess of the metal cover, the portion facing the opening of the third dielectric substrate, MMIC integrated circuit module, wherein the Ru slope portion der which is inclined in the direction of the MMIC.
を備えることを特徴とする請求項1記載のMMIC集積回路モジュール。 2. The MMIC integrated circuit according to claim 1, further comprising: a plurality of stud bumps sandwiched between a peripheral portion of the concave portion of the metal lid and a metal layer of the second dielectric substrate facing the peripheral portion. module.
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Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07307605A (en) * | 1994-05-13 | 1995-11-21 | Nec Corp | Composite high frequency circuit module |
JPH11243307A (en) * | 1997-11-26 | 1999-09-07 | Trw Inc | Millimetric wave ltcc package |
JP2002280809A (en) * | 2001-03-21 | 2002-09-27 | Toshiba Corp | United structure of high frequency component and high frequency transmission line conversion circuit |
JP2004254068A (en) * | 2003-02-20 | 2004-09-09 | Mitsubishi Electric Corp | High frequency transmitting and receiving module |
WO2008111391A1 (en) * | 2007-03-14 | 2008-09-18 | Mitsubishi Electric Corporation | High frequency package |
JP2010004336A (en) * | 2008-06-20 | 2010-01-07 | Nec Corp | Hollow tube, member, and bonding method |
WO2010114079A1 (en) * | 2009-03-31 | 2010-10-07 | 京セラ株式会社 | Circuit board, high frequency module, and radar apparatus |
JP2011010242A (en) * | 2009-06-29 | 2011-01-13 | Kyocera Corp | High-frequency substrate and high-frequency module |
-
2014
- 2014-02-13 JP JP2014025115A patent/JP5728102B1/en not_active Expired - Fee Related
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07307605A (en) * | 1994-05-13 | 1995-11-21 | Nec Corp | Composite high frequency circuit module |
JPH11243307A (en) * | 1997-11-26 | 1999-09-07 | Trw Inc | Millimetric wave ltcc package |
JP2002280809A (en) * | 2001-03-21 | 2002-09-27 | Toshiba Corp | United structure of high frequency component and high frequency transmission line conversion circuit |
JP2004254068A (en) * | 2003-02-20 | 2004-09-09 | Mitsubishi Electric Corp | High frequency transmitting and receiving module |
WO2008111391A1 (en) * | 2007-03-14 | 2008-09-18 | Mitsubishi Electric Corporation | High frequency package |
JP2010004336A (en) * | 2008-06-20 | 2010-01-07 | Nec Corp | Hollow tube, member, and bonding method |
WO2010114079A1 (en) * | 2009-03-31 | 2010-10-07 | 京セラ株式会社 | Circuit board, high frequency module, and radar apparatus |
JP2011010242A (en) * | 2009-06-29 | 2011-01-13 | Kyocera Corp | High-frequency substrate and high-frequency module |
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