JP5725129B2 - Manufacturing method of semiconductor device having vertical MOSFET of super junction structure - Google Patents

Manufacturing method of semiconductor device having vertical MOSFET of super junction structure Download PDF

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JP5725129B2
JP5725129B2 JP2013222256A JP2013222256A JP5725129B2 JP 5725129 B2 JP5725129 B2 JP 5725129B2 JP 2013222256 A JP2013222256 A JP 2013222256A JP 2013222256 A JP2013222256 A JP 2013222256A JP 5725129 B2 JP5725129 B2 JP 5725129B2
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JP2014132638A (en
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浩次 江口
浩次 江口
洋平 小田
洋平 小田
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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Description

本発明は、第１半導体層に形成したトレンチ内に第２半導体層をエピタキシャル成長させてスーパージャンクション（以下、ＳＪという）構造を形成するＳＪ構造の縦型ＭＯＳＦＥＴを備えた半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device including a vertical MOSFET having an SJ structure in which a second semiconductor layer is epitaxially grown in a trench formed in a first semiconductor layer to form a super junction (hereinafter referred to as SJ) structure. It is.

従来より、ｎ型カラムとｐ型カラムとが交互に繰り返し形成されたＳＪ構造を有する半導体装置が知られている（例えば、特許文献１参照）。ＳＪ構造の半導体装置を製造する際には、例えば図９（ａ）に示すように、ｎ+型シリコン基板Ｊ１の表面にｎ-型層Ｊ２をエピタキシャル成長させた半導体基板Ｊ３を用いて行われている。図９（ｂ）に示すように、ｎ-型層Ｊ２にトレンチＪ４を形成したのち、図９（ｃ）に示すように、そのトレンチＪ４内にｐ-型層Ｊ５をエピタキシャル成長させる。そして、図１０（ａ）に示すように、表面の平坦化研磨によってトレンチＪ４の外に形成されたｐ-型層Ｊ５を除去してトレンチＪ４内にのみ残す。これにより、ｎ-型層Ｊ２からなるｎ型カラムとｐ-型層Ｊ５からなるｐ型カラムが交互に繰り返されたＰＮカラムを有するＳＪ構造を形成している。 Conventionally, a semiconductor device having an SJ structure in which n-type columns and p-type columns are alternately and repeatedly formed is known (see, for example, Patent Document 1). When manufacturing a semiconductor device having an SJ structure, for example, as shown in FIG. 9A, a semiconductor substrate J3 in which an n − type layer J2 is epitaxially grown on the surface of an n + type silicon substrate J1 is used. Yes. As shown in FIG. 9B, after forming a trench J4 in the n − -type layer J2, a p − -type layer J5 is epitaxially grown in the trench J4 as shown in FIG. 9C. Then, as shown in FIG. 10A, the p − -type layer J5 formed outside the trench J4 is removed by planarization of the surface and is left only in the trench J4. Thus, an SJ structure having a PN column in which an n-type column composed of an n − -type layer J2 and a p-type column composed of a p − -type layer J5 are alternately repeated is formed.

その後、図１０（ｂ）に示すように、ＳＪ構造を形成した後で、ｐ-型層Ｊ６をエピタキシャル成長させたのち、その後のデバイス形成工程を行う。例えば、図１０（ｃ）に示すように、ｎ+型ソース領域Ｊ７、トレンチゲート構造Ｊ８や表面電極Ｊ９および裏面電極Ｊ１０の形成工程などを従来と同様の手法によって行う。このような手法により、ＳＪ構造の縦型ＭＯＳトランジスタを製造している。 Thereafter, as shown in FIG. 10B, after the SJ structure is formed, the p − -type layer J6 is epitaxially grown, and then a subsequent device formation step is performed. For example, as shown in FIG. 10C, the n + -type source region J7, the trench gate structure J8, the front surface electrode J9, the back surface electrode J10, and the like are formed by a method similar to the conventional method. A vertical MOS transistor having an SJ structure is manufactured by such a method.

特開２０１２−０６４６６０号公報JP 2012-064660 A

しかしながら、ｐ-型層Ｊ５をトレンチＪ４内に埋め込むようにエピタキシャル成長させた後で行うｐ-型層Ｊ５およびｎ-型層Ｊ２の表面の平坦化研磨のバラツキが大きく、ＰＮカラムの深さがばらついて精度良く所望の深さにすることができなかった。これは、エピタキシャル成長自体の精度の問題もあるが、それ以上にｐ-型層Ｊ５およびｎ-型層Ｊ２の平坦化研磨が同じ半導体材料（例えばシリコン）の研磨加工となり、狙いの膜厚で研磨ストップを行うのが原理的に難しいためである。そして、このようにＰＮカラムの深さのバラツキが発生すると、半導体装置の耐圧がばらつき、デバイス特性が悪化するという問題を発生させる。 However, there is a large variation in planarization polishing of the surfaces of the p − type layer J5 and the n − type layer J2 after epitaxial growth so that the p − type layer J5 is buried in the trench J4, and the depth of the PN column varies. Therefore, the desired depth could not be obtained with high accuracy. This is due to the accuracy of the epitaxial growth itself, but the planarization polishing of the p − type layer J5 and the n − type layer J2 becomes the polishing process of the same semiconductor material (for example, silicon), and the target film thickness is polished. This is because it is difficult in principle to perform the stop. When the variation in the depth of the PN column occurs in this way, there arises a problem that the breakdown voltage of the semiconductor device varies and the device characteristics deteriorate.

また、ＳＪ構造を形成した後でＳＪ構造の上にｐ-型層Ｊ６をエピタキシャル成長させているが、ＳＪ構造の表面とｐ-型層Ｊ６との構造間の処理によって上側のｐ-型層Ｊ６が異常成長し、デバイス特性を悪化させるという問題もある。ここでいう構造間の処理とは、ＳＪ構造を形成した後で行われるＳＪ構造の表面の平坦化研磨やｐ-型層Ｊ６の成長前のウェハ洗浄のことであり、この処理次第で結晶欠陥が発生し、その結晶欠陥が引き継がれることでｐ型層が異常成長することがある。 Further, p on the SJ structure after forming the SJ structure - but -type layer J6 are epitaxially grown, the surface of the SJ structure and p - upper by processing between the structure of the mold layer J6 of p - type layer J6 However, there is also a problem that the device characteristics are deteriorated due to abnormal growth. The treatment between structures here means planarization polishing of the surface of the SJ structure performed after the SJ structure is formed and wafer cleaning before the growth of the p − -type layer J6. May occur and the p-type layer may grow abnormally when the crystal defects are taken over.

また、ｐ-型層Ｊ６の形成工程を独立して行っていることから、製造工程が増加し、製造コストが高くなるという問題もある。 In addition, since the p − -type layer J6 is formed independently, there is a problem that the manufacturing process increases and the manufacturing cost increases.

本発明は上記点に鑑みて、ＰＮカラムの深さのバラツキを抑制してデバイス特性の悪化を抑制でき、かつ、製造工程の簡略化を図ることができるＳＪ構造の縦型ＭＯＳＦＥＴを備えた半導体装置の製造方法を提供することを第１の目的とする。また、第１導電型の第１半導体層に形成したトレンチ内に第２導電型の第２半導体層を埋め込んでＳＪ構造を形成したのち、第１半導体層の上に第２導電型層を形成する際に、第２導電型層の異常成長を抑制し、デバイス特性の悪化を抑制することを第２の目的とする。   In view of the above, the present invention is a semiconductor including a vertical MOSFET having an SJ structure that can suppress the variation in the depth of the PN column, suppress the deterioration of device characteristics, and can simplify the manufacturing process. It is a first object to provide a method for manufacturing an apparatus. In addition, after forming the SJ structure by burying the second conductive type second semiconductor layer in the trench formed in the first conductive type first semiconductor layer, the second conductive type layer is formed on the first semiconductor layer. In this case, the second object is to suppress abnormal growth of the second conductivity type layer and to suppress deterioration of device characteristics.

上記目的を達成するため、請求項１ないし９に記載の発明では、半導体材料で構成された基板（１１）の表面（１１ａ）側に、第１導電型の第１半導体層（１２）が形成された半導体基板（１０）を用意したのち、第２半導体層のうち縦型ＭＯＳＦＥＴを形成してチップとして用いるメイン領域の少なくとも一部を含むように第１凹部（１２ａ）を形成することで、第１半導体層に段差を付ける。また、第１凹部内を含めて第１半導体層の上にマスク（１４）を配置し、該マスクを用いてメイン領域における第１凹部内において、第１半導体層をエッチングすることでトレンチ（１５）を形成する。そして、マスクのうちの少なくとも第１凹部内に形成されている部分を除去したのち、トレンチ内および第１凹部内を埋め込みつつ第１半導体層の上に、第２導電型の第２半導体層（１６）をエピタキシャル成長させ、第２半導体層を平坦化研磨することで、第２半導体層をトレンチおよび第１凹部に残し、トレンチ内に残された第２半導体層による第２導電型カラムと第１半導体層による第１導電型カラムとが交互に繰り返されたＰＮカラムを有するＳＪ構造を形成する。その後、ＳＪ構造の上に、第２導電型のチャネル層（１７）と該チャネル層に接する第１導電型のソース領域（１８）を形成すると共に、チャネル層の表面にゲート絶縁膜（２２）を介してゲート電極（２３）を形成し、さらに半導体基板の表面側にソース領域に電気的に接続されるソース電極（２５）を形成すると共に、半導体基板の裏面側に半導体材料で構成された基板の裏面に接続されるドレイン電極（２６）を形成することで縦型ＭＯＳＦＥＴを形成することを特徴としている。 In order to achieve the above object, in the invention described in claims 1 to 9, a first semiconductor layer (12) of the first conductivity type is formed on the surface (11a) side of a substrate (11) made of a semiconductor material. After preparing the semiconductor substrate (10), the first recess (12a) is formed so as to include at least a part of the main region used as a chip by forming the vertical MOSFET in the second semiconductor layer. A step is provided in the first semiconductor layer. Further, a mask (14) is disposed on the first semiconductor layer including the inside of the first recess, and the first semiconductor layer is etched in the first recess in the main region by using the mask to thereby form the trench (15 ). Then, after removing at least a portion of the mask formed in the first recess, the second conductivity type second semiconductor layer (on the first semiconductor layer (while filling the trench and the first recess) ( 16) is epitaxially grown, and the second semiconductor layer is planarized and polished to leave the second semiconductor layer in the trench and the first recess, and the second conductivity type column and the first semiconductor column formed by the second semiconductor layer left in the trench An SJ structure having a PN column in which the first conductivity type column by the semiconductor layer is alternately repeated is formed. Thereafter, a second conductivity type channel layer (17) and a first conductivity type source region (18) in contact with the channel layer are formed on the SJ structure, and a gate insulating film (22) is formed on the surface of the channel layer. And a source electrode (25) electrically connected to the source region on the front surface side of the semiconductor substrate, and a semiconductor material on the back surface side of the semiconductor substrate. A vertical MOSFET is formed by forming a drain electrode (26) connected to the back surface of the substrate.

このように、第１半導体層に第１凹部を形成しておき、トレンチを埋め込むように第２半導体層を形成する際に、第１凹部内も埋め込まれるようにしている。このため、第２半導体層のうち第１凹部内に形成された部分をＳＪ構造の上に形成される第２導電型層として用いることができる。   In this way, the first recess is formed in the first semiconductor layer, and when the second semiconductor layer is formed so as to fill the trench, the inside of the first recess is also filled. For this reason, the part formed in the 1st recessed part among the 2nd semiconductor layers can be used as a 2nd conductivity type layer formed on SJ structure.

このため、第２導電型カラムを形成するための第２導電型層とＳＪ構造の上に形成される第２導電型層を同じ第２半導体層によって構成することができ、同時に形成することができるので、製造工程の簡略化を図ることができる。また、ＳＪ構造を構成してからＳＪ構造の上の第２導電型層を形成する場合のように、ＰＮカラムの表面の平坦化研磨やウェハ洗浄などのＰＮカラムの表面と第２半導体層との構造間の処理を行う必要がない。よって、半導体装置の耐圧がばらつくことを抑制でき、デバイス特性の悪化を抑制することが可能となる。   Therefore, the second conductivity type layer for forming the second conductivity type column and the second conductivity type layer formed on the SJ structure can be constituted by the same second semiconductor layer and can be formed simultaneously. Therefore, the manufacturing process can be simplified. Further, as in the case of forming the second conductivity type layer on the SJ structure after forming the SJ structure, the surface of the PN column such as planarization polishing of the surface of the PN column or wafer cleaning, the second semiconductor layer, It is not necessary to perform processing between the structures. Therefore, variation in the breakdown voltage of the semiconductor device can be suppressed, and deterioration of device characteristics can be suppressed.

請求項７に記載の発明は、第２半導体層を形成する工程の前に、第１半導体層のうち縦型ＭＯＳＦＥＴが形成されるセル領域の周辺領域となる外周領域において第３凹部（１２ｃ）を形成する工程を有し、第２半導体層を形成する工程では、第３凹部内を埋め込むように第１半導体層の上に第２半導体層を形成することを特徴としている。   According to the seventh aspect of the present invention, before the step of forming the second semiconductor layer, the third recess (12c) in the outer peripheral region that is the peripheral region of the cell region in which the vertical MOSFET is formed in the first semiconductor layer. The step of forming the second semiconductor layer is characterized in that the second semiconductor layer is formed on the first semiconductor layer so as to fill the third recess.

このように、第１半導体層に第３凹部を形成しておき、その第３凹部内にも第２半導体層を埋め込むようにしている。このようにすれば、第２半導体層を平坦化研磨する際に、仮に第１半導体層の上において第２半導体層が除去されて第１半導体層が露出するまで研磨されたとしても、第３凹部内に第２半導体層を残せる。このため、外周領域において確実にリサーフ層（４０）が構成されるようにすることができる。   As described above, the third recess is formed in the first semiconductor layer, and the second semiconductor layer is embedded in the third recess. In this way, when the second semiconductor layer is planarized and polished, even if the second semiconductor layer is removed on the first semiconductor layer until the first semiconductor layer is exposed, the third semiconductor layer is removed. The second semiconductor layer can be left in the recess. For this reason, a RESURF layer (40) can be reliably comprised in an outer peripheral area | region.

請求項１０に記載の発明では、半導体材料で構成された基板（１１）の表面（１１ａ）側に、第１導電型の第１半導体層（１２）が形成された半導体基板（１０）を用意したのち、第１半導体層の上にマスク（１４）を配置し、該第１半導体層のうち縦型ＭＯＳＦＥＴを形成してチップとして用いるメイン領域において該第１半導体層をエッチングすることでトレンチ（１５）を形成する。また、トレンチ内を埋め込みつつ、第１半導体層のうちトレンチの外側の部分の上にも、第２導電型の第２半導体層（１６）をエピタキシャル成長させることで、トレンチ内に残された第２半導体層による第２導電型カラムと第１半導体層による第１導電型カラムとが交互に繰り返されたＰＮカラムを有するＳＪ構造を形成する。そして、ＳＪ構造の上に、第２導電型のチャネル層（１７）と該チャネル層に接する第１導電型のソース領域（１８）を形成すると共に、チャネル層の表面にゲート絶縁膜（２２）を介してゲート電極（２３）を形成し、さらに半導体基板の表面側にソース領域に電気的に接続されるソース電極（２５）を形成すると共に、半導体基板の裏面側に基板の裏面に接続されるドレイン電極（２６）を形成することで縦型ＭＯＳＦＥＴを形成することを特徴としている。 In the invention described in claim 10, a semiconductor substrate (10) is prepared in which a first semiconductor layer (12) of the first conductivity type is formed on the surface (11a) side of a substrate (11) made of a semiconductor material. After that, a mask (14) is disposed on the first semiconductor layer, and a vertical MOSFET is formed in the first semiconductor layer, and the first semiconductor layer is etched in a main region used as a chip to thereby form a trench ( 15) is formed. Further, the second conductivity type second semiconductor layer (16) is epitaxially grown on the outer portion of the first semiconductor layer while filling the trench, whereby the second semiconductor layer remaining in the trench is formed. An SJ structure having a PN column in which a second conductivity type column by a semiconductor layer and a first conductivity type column by a first semiconductor layer are alternately repeated is formed. A second conductivity type channel layer (17) and a first conductivity type source region (18) in contact with the channel layer are formed on the SJ structure, and a gate insulating film (22) is formed on the surface of the channel layer. And a source electrode (25) electrically connected to the source region is formed on the front side of the semiconductor substrate, and connected to the back side of the substrate on the back side of the semiconductor substrate. A vertical MOSFET is formed by forming a drain electrode (26).

このように、第１半導体層に形成したトレンチ内に第２半導体層を形成したのち、引き続いて第１半導体層のうちトレンチの外側の部分の上にも第２半導体層を形成するようにしている。つまり、トレンチ内に第２半導体層を埋め込んだ後に第１半導体層および第２半導体層の平坦化研磨などの構造間の処理を行うことなく、更に第１半導体層のうちトレンチの外側の部分の上に第２半導体層を形成している。このため、第１半導体層の上に第２導電型層を形成する際に、第２導電型層の異常成長を抑制でき、デバイス特性の悪化を抑制することが可能となる。   As described above, after the second semiconductor layer is formed in the trench formed in the first semiconductor layer, the second semiconductor layer is formed also on the portion of the first semiconductor layer outside the trench. Yes. That is, after the second semiconductor layer is embedded in the trench, the inter-structure processing such as planarization polishing of the first semiconductor layer and the second semiconductor layer is not performed, and the portion of the first semiconductor layer outside the trench is further processed. A second semiconductor layer is formed thereon. For this reason, when forming a 2nd conductivity type layer on a 1st semiconductor layer, the abnormal growth of a 2nd conductivity type layer can be suppressed, and it becomes possible to suppress deterioration of a device characteristic.

なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係の一例を示すものである。   In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

本発明の第１実施形態にかかるＳＪ構造のトレンチゲート型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which has a trench gate type vertical MOSFET of the SJ structure concerning 1st Embodiment of this invention. 図１に続くＳＪ構造のトレンチゲート型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device having the trench gate type vertical MOSFET of the SJ structure following FIG. 1; 図２に続くＳＪ構造のトレンチゲート型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。FIG. 3 is a cross-sectional view showing a manufacturing step of the semiconductor device having the trench gate type vertical MOSFET of the SJ structure following FIG. 2; 本発明の第２実施形態にかかるＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which has the planar type | mold vertical MOSFET of SJ structure concerning 2nd Embodiment of this invention. 本発明の第３実施形態にかかるＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which has the planar type | mold vertical MOSFET of SJ structure concerning 3rd Embodiment of this invention. 図５に続くＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device having the planar vertical MOSFET having the SJ structure following FIG. 5; 図６に続くＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。FIG. 7 is a cross-sectional view showing a manufacturing step of the semiconductor device having the planar vertical MOSFET having the SJ structure following FIG. 6; 他の実施形態にかかるＳＪ構造のトレンチゲート型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which has the trench gate type vertical MOSFET of the SJ structure concerning other embodiment. 従来のＳＪ構造のトレンチゲート構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which has the vertical MOSFET of the trench gate structure of the conventional SJ structure. 図９に続くＳＪ構造のトレンチゲート構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device having the vertical MOSFET of the trench gate structure of the SJ structure following FIG. 9.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

（第１実施形態）
本発明の第１実施形態にかかる半導体装置の製造方法について、図１および図２を参照して説明する。なお、ここではＳＪ構造の縦型ＭＯＳＦＥＴとして、トレンチゲート型の縦型ＭＯＳＦＥＴを備えた半導体装置を例に挙げて説明する。 (First embodiment)
A method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. Here, a semiconductor device including a trench gate type vertical MOSFET will be described as an example of the vertical MOSFET having the SJ structure.

〔図１（ａ）に示す工程〕
表面１１ａおよび裏面１１ｂを有する半導体材料で構成された基板としてのｎ+型シリコン基板１１の表面１１ａに、第１半導体層に相当するｎ-型層１２をエピタキシャル成長させた半導体基板１０を用意する。ｎ+型シリコン基板１１は、ドレイン領域として機能する部分であり、ｎ-型層１２よりもｎ型不純物濃度が高くされている。ｎ-型層１２は、ドリフト層として機能と共にＰＮカラムにおけるｎ型カラムを構成する部分である。 [Step shown in FIG. 1 (a)]
A semiconductor substrate 10 is prepared by epitaxially growing an n − type layer 12 corresponding to a first semiconductor layer on a surface 11a of an n + type silicon substrate 11 as a substrate composed of a semiconductor material having a front surface 11a and a back surface 11b. The n + type silicon substrate 11 functions as a drain region, and has an n type impurity concentration higher than that of the n − type layer 12. The n − type layer 12 functions as a drift layer and constitutes an n type column in the PN column.

〔図１（ｂ）に示す工程〕
半導体基板１０の表面側において、ｎ-型層１２の表面にＣＶＤ（Chemical Vapor Deposition）法や熱酸化などによって酸化膜１３を形成する。その後、酸化膜１３の上に図示しないレジストを配置し、フォトリソグラフィ工程を経て、縦型ＭＯＳＦＥＴなどを形成してチップとして利用するメイン領域においてレジストを開口させると共に、スクライブ領域においてもレジストを開口させる。このとき、メイン領域とスクライブ領域の境界位置についてはレジストが残るようにしている。次いで、エッチング工程を行い、レジストの開口位置において酸化膜１３を開口させる。 [Step shown in FIG. 1B]
On the surface side of the semiconductor substrate 10, an oxide film 13 is formed on the surface of the n − -type layer 12 by a CVD (Chemical Vapor Deposition) method or thermal oxidation. After that, a resist (not shown) is disposed on the oxide film 13, and through a photolithography process, a vertical MOSFET or the like is formed to open the resist in the main region used as a chip and open the resist also in the scribe region. . At this time, the resist remains at the boundary position between the main area and the scribe area. Next, an etching process is performed to open the oxide film 13 at the opening position of the resist.

そして、レジストを除去し、酸化膜１３をマスクとして、ＲＩＥ（Reactive Ion Etching）法や、Ｏ2とＣ4Ｆ8およびＳＦ6を交互に繰り返し導入して底部エッチングおよびポリマー膜による側壁保護を繰り返し行うＢＯＳＣＨ法などの異方性エッチングを行う。具体的には、ｎ-型層１２を所定深さ２．５〜３．５μｍ程度除去する程度エッチングする。これにより、ｎ-型層１２のメイン領域に凹部１２ａが形成されることで、メイン領域とスクライブ領域との間に段差が付けられる。また、このとき同時に、スクライブ領域に後工程においてマスク合わせなどを行う際のアライメントのターゲットとなる凹部１２ｂが形成される。そして、メイン領域とスクライブ領域との境界位置、具体的にはメイン領域における外縁部の少なくとも一部にｎ-型層１２が凸状に残される。この後、酸化膜１３を除去する。 Then, the resist is removed, and using the oxide film 13 as a mask, the RIE (Reactive Ion Etching) method and O 2 , C 4 F 8 and SF 6 are alternately introduced repeatedly to repeat the bottom etching and the side wall protection by the polymer film. An anisotropic etching such as a BOSCH method is performed. More specifically, the n − -type layer 12 is etched so as to remove a predetermined depth of about 2.5 to 3.5 μm. As a result, the recess 12a is formed in the main region of the n − -type layer 12, thereby providing a step between the main region and the scribe region. At the same time, a recess 12b is formed in the scribe region, which serves as an alignment target when performing mask alignment or the like in a subsequent process. Then, the n − -type layer 12 is left in a convex shape at the boundary position between the main region and the scribe region, specifically, at least a part of the outer edge portion in the main region. Thereafter, the oxide film 13 is removed.

〔図２（ａ）に示す工程〕
再び、半導体基板１０の表面側において、ｎ-型層１２を覆うようにＣＶＤ法や熱酸化などによって酸化膜１４を０．２〜０．３μｍの厚みで形成する。その後、酸化膜１４の上に図示しないレジストを配置し、フォトリソグラフィ工程を経てトレンチ形成予定位置においてレジストを開口させると共にその開口位置において酸化膜１４を開口させる。そして、レジストを除去し、酸化膜１４をマスクとして、ＲＩＥやＢＯＳＣＨ法などの異方性エッチングを行う。具体的には、凹部１２ａ内において、ｎ-型層１２を所定深さ、例えばｎ-型層１２の厚みと同等もしくはそれよりも若干浅くエッチングする。これにより、ｎ-型層１２の所望位置にＳＪ構造形成用の例えばストライプ状とされたトレンチ１５が形成される。 [Step shown in FIG. 2 (a)]
Again, on the surface side of the semiconductor substrate 10, the oxide film 14 is formed to a thickness of 0.2 to 0.3 μm by CVD or thermal oxidation so as to cover the n − -type layer 12. Thereafter, a resist (not shown) is disposed on the oxide film 14, and the resist is opened at a trench formation planned position through a photolithography process, and the oxide film 14 is opened at the opening position. Then, the resist is removed, and anisotropic etching such as RIE or BOSCH is performed using the oxide film 14 as a mask. Specifically, in the recess 12a, the n − type layer 12 is etched to a predetermined depth, for example, equal to or slightly shallower than the thickness of the n − type layer 12. Thus, for example, a stripe-shaped trench 15 for forming the SJ structure is formed at a desired position of the n − -type layer 12.

〔図２（ｂ）に示す工程〕
酸化膜１４のうちトレンチ１５から離れた位置に形成されている部分については残し、トレンチ１５の開口部周辺に配置されている部分、具体的には凹部１２ａ内に形成されている部分については除去する。 [Step shown in FIG. 2 (b)]
A portion of the oxide film 14 formed at a position away from the trench 15 is left, and a portion disposed around the opening of the trench 15, specifically, a portion formed in the recess 12 a is removed. To do.

例えば、酸化膜１４の上に再びレジストを配置したのち、半導体基板１０のうち縦型ＭＯＳＦＥＴなどを形成してチップとして利用するメイン領域においてレジストを開口させる。そして、アライメントのターゲットを形成する領域であってダイシング時にカットされるスクライブ領域をレジストで覆った状態でエッチングすることで、酸化膜１４をパターニングする。または、水素アニールを行うことで、酸化膜１４のうちトレンチ１５の開口部周辺に形成された部分を後退させる。例えば、１０．６ｋＰａ（８０Ｔｏｒｒ）以下の減圧雰囲気において、温度を１１００℃とし時間を１０分間とした水素アニールや、温度を１１７０℃とし時間を２分間とした水素アニールを行うことで、酸化膜１４のうちのトレンチ１５の開口部周辺を除去できる。   For example, after a resist is again arranged on the oxide film 14, a vertical MOSFET or the like is formed in the semiconductor substrate 10, and the resist is opened in a main region used as a chip. Then, the oxide film 14 is patterned by etching in a state where a scribe region which is a region where an alignment target is formed and which is cut during dicing is covered with a resist. Alternatively, a portion of the oxide film 14 formed around the opening of the trench 15 is retreated by performing hydrogen annealing. For example, in a reduced pressure atmosphere of 10.6 kPa (80 Torr) or less, hydrogen annealing is performed at a temperature of 1100 ° C. and a time of 10 minutes, or a hydrogen annealing at a temperature of 1170 ° C. and a time of 2 minutes. The periphery of the opening of the trench 15 can be removed.

その後、半導体基板１０の表面側において、凹部１２ａおよびトレンチ１５内を含めｎ-型層１２の表面に、例えばｐ型不純物濃度が２×１０15〜５×１０15ｃｍ-3となるように第２半導体層に相当するｐ-型層１６をエピタキシャル成長させる。このとき、凹部１２ａおよび各トレンチ１５内が完全に埋め込まれるようにしつつ、ｎ-型層１２の上にもｐ-型層１６が形成されるようなオーバーエピタキシャル成長とし、例えばｎ-型層１２の上に５〜７μｍ程度の厚みでｐ-型層１６を形成する。 Thereafter, on the surface side of the semiconductor substrate 10, on the surface of the n − -type layer 12 including the inside of the recess 12 a and the trench 15, the p-type impurity concentration is set to 2 × 10 15 to 5 × 10 15 cm −3 , for example. A p − type layer 16 corresponding to two semiconductor layers is epitaxially grown. At this time, over-epitaxial growth is performed such that the p − -type layer 16 is also formed on the n − -type layer 12 while the recesses 12a and the trenches 15 are completely buried, for example, the n − -type layer 12 A p − type layer 16 is formed thereon with a thickness of about 5 to 7 μm.

〔図３（ａ）に示す工程〕
まず、ｐ-型層１６のうち酸化膜１４よりも半導体基板１０から突き出した部分、すなわちｎ-型層１２に形成された凹部１２ａ以外の凸状部分から突き出した部分をＣＭＰ（Chemical Mechanical Polishing）などの表面の平坦化研磨によって除去する。このときには、研磨対象となるｐ-型層１６と異なる酸化膜１４を終点検出用のストッパとして用いることができるため、精度良く平坦化研磨を停止できる。 [Step shown in FIG. 3 (a)]
First, a portion of the p − type layer 16 that protrudes from the semiconductor substrate 10 relative to the oxide film 14, that is, a portion that protrudes from a convex portion other than the concave portion 12 a formed in the n − type layer 12 is CMP (Chemical Mechanical Polishing). Etc. are removed by surface flattening polishing. At this time, since the oxide film 14 different from the p − type layer 16 to be polished can be used as a stopper for detecting the end point, the planarization polishing can be stopped with high accuracy.

続いて、酸化膜１４をエッチングする。これにより、スクライブ領域やメイン領域におけるスクライブ領域の近傍において酸化膜１４が除去されて、露出したｎ-型層１２とｐ-型層１６との間に段差が形成される。このため、再度ＣＭＰなどによる表面の平坦化研磨を行うことで、当該段差が無くなるようにｎ-型層１２およびｐ-型層１６を平坦化研磨する。これにより、ｐ-型層１６のうちトレンチ１５内に形成された部分によってＳＪ構造におけるｐ型カラムが構成されると共に、ＳＪ構造の上にもｐ-型層１６が同時に形成された構造が完成する。 Subsequently, the oxide film 14 is etched. As a result, the oxide film 14 is removed in the vicinity of the scribe region in the scribe region or the main region, and a step is formed between the exposed n − -type layer 12 and the p − -type layer 16. For this reason, the n − type layer 12 and the p − type layer 16 are flattened and polished so that the level difference is eliminated by performing flattening and polishing of the surface again by CMP or the like. As a result, a p-type column in the SJ structure is formed by the portion of the p − -type layer 16 formed in the trench 15, and a structure in which the p − -type layer 16 is simultaneously formed on the SJ structure is also completed. To do.

なお、この表面平坦化の際に、ｎ-型層１２およびｐ-型層１６という同じ半導体材料（シリコン）の研磨加工となるため、表面平坦化のストッパとなるものが無い。しかしながら、酸化膜１４の膜厚が０．２〜０．３μｍと非常に薄いため、ストッパが無くても時間制御などだけで大きなバラツキなく平坦化研磨が行える。また、ＰＮカラムの表面とｐ-型層１６との構造間の処理を行う訳ではないので、仮に多少のバラツキがあったとしても、半導体装置の耐圧が大きくばらつくことも無い。 In addition, since the same semiconductor material (silicon) as the n − -type layer 12 and the p − -type layer 16 is polished during the surface flattening, there is no stopper for the surface flattening. However, since the oxide film 14 has a very thin film thickness of 0.2 to 0.3 [mu] m, even if there is no stopper, flattening polishing can be performed without much variation only by time control or the like. In addition, since the process between the surface of the PN column and the p − -type layer 16 is not performed, even if there is some variation, the breakdown voltage of the semiconductor device does not vary greatly.

〔図３（ｂ）に示す工程〕
この後の工程については従来と同様であるが、例えば以下の製造工程を行っている。すなわち、ｎ型カラムを構成するｎ-型層１２の上におけるｐ-型層１６の表層部にｐ型不純物をイオン注入してｐ-型チャネル層１７を形成する。また、ｐ-型チャネル層１７の表層部にｎ型不純物をイオン注入してｎ+型ソース領域１８を形成する。このとき、必要に応じて、メイン領域の外縁部において凸状に残された部分にもｎ型不純物をイオン注入し、ｎ+型層２７を形成することで、ｎ-型層１２との導通を図ることができ、このｎ+型層２７を通じてｎ-型層１２を所定電位に固定することができる。 [Step shown in FIG. 3B]
The subsequent steps are the same as in the prior art, but the following manufacturing steps are performed, for example. That is, the p − type channel layer 17 is formed by ion implantation of p type impurities into the surface layer portion of the p − type layer 16 on the n − type layer 12 constituting the n type column. Further, an n + type source region 18 is formed by ion implantation of n type impurities into the surface layer portion of the p − type channel layer 17. At this time, if necessary, an n-type impurity is ion-implanted into a portion left in a convex shape at the outer edge of the main region to form an n + -type layer 27, thereby conducting the n − -type layer 12. The n − type layer 12 can be fixed to a predetermined potential through the n + type layer 27.

このように、メイン領域の外縁部に凸部を残し、ｎ+型層２７を形成して電位固定できるようにすることで、外周領域において所望の耐圧を確保できる。つまり、もしもこの凸部がない構造の場合、ｎ-型層１２の表面側の電位を固定できず、所望の耐圧を確保することができない。 In this manner, by leaving a convex portion at the outer edge of the main region and forming the n + -type layer 27 so that the potential can be fixed, a desired breakdown voltage can be secured in the outer peripheral region. That is, if the structure does not have this convex portion, the potential on the surface side of the n − -type layer 12 cannot be fixed, and a desired breakdown voltage cannot be ensured.

また、ｐ-型チャネル層１７のうちのｐ型カラムの上に形成された部分を中心としてｐ型不純物をイオン注入することでｐ+型ボディ層１９を形成すると共に、このｐ+型ボディ層１９の表層部にｐ+型コンタクト領域２０を形成する。また、ｐ-型チャネル層１７を貫通してｎ-型層１２のうちｎ型カラムを構成する部分に達するゲートトレンチ２１を形成する。さらに、ゲートトレンチ２１の内壁面を覆うようにゲート絶縁膜２２を形成すると共に、ゲートトレンチ２１内を埋め込むようにゲート絶縁膜２２上にゲート電極２３を形成する。また、半導体基板１０の表面側において、層間絶縁膜２４の形成工程やゲート配線およびソース電極２５の形成工程を行う。そして、半導体基板１０の裏面側において、ｎ+型シリコン基板１１の裏面１１ｂに接続されるドレイン電極２６の形成工程を行うことにより、ｎチャネルのトレンチゲート型の縦型ＭＯＳＦＥＴが形成される。その後、ダイシングによりチップ単位に分割することでＳＪ構造の縦型ＭＯＳＦＥＴを備えた半導体装置が完成する。 Further, p - the p-type impurity around a portion formed on the p-type column of the type channel layer 17 thereby forming a p + -type body layers 19 by ion implantation, the p + -type body layer A p + -type contact region 20 is formed in 19 surface layers. In addition, a gate trench 21 that penetrates the p − -type channel layer 17 and reaches a portion of the n − -type layer 12 constituting the n-type column is formed. Further, the gate insulating film 22 is formed so as to cover the inner wall surface of the gate trench 21, and the gate electrode 23 is formed on the gate insulating film 22 so as to fill the gate trench 21. Further, on the surface side of the semiconductor substrate 10, an interlayer insulating film 24 forming process and a gate wiring and source electrode 25 forming process are performed. Then, on the back side of the semiconductor substrate 10, a drain electrode 26 connected to the back surface 11 b of the n + -type silicon substrate 11 is formed, whereby an n-channel trench gate type vertical MOSFET is formed. Thereafter, the semiconductor device including the vertical MOSFET having the SJ structure is completed by dividing into chips by dicing.

以上説明した本実施形態にかかる半導体装置の製造方法によれば、ｎ-型層１２に凹部１２ａを形成しておき、トレンチ１５を埋め込むようにｐ-型層１６を形成する際に、凹部１２ａ内も埋め込まれるようにしている。このため、ｐ-型層１６のうち凹部１２ａ内に形成された部分をＳＪ構造の上に形成されるｐ型層として用いることができる。 According to the manufacturing method of the semiconductor device according to the present embodiment described above, when the recess 12a is formed in the n − -type layer 12 and the p − -type layer 16 is formed so as to fill the trench 15, the recess 12a The inside is also embedded. Therefore, a portion of the p − type layer 16 formed in the recess 12a can be used as a p type layer formed on the SJ structure.

このため、ｐ型カラムを形成するためのｐ型層とＳＪ構造の上に形成されるｐ型層を同じｐ-型層１６によって構成することができ、同時に形成することができるので、製造工程の簡略化を図ることができる。また、ＳＪ構造を構成してからＳＪ構造の上のｐ型層を形成する場合のように、ＰＮカラムの表面の平坦化研磨が行われないし、平坦化研磨やウェハ洗浄などのＰＮカラムの表面とｐ-型層１６との構造間の処理を行う必要がない。よって、半導体装置の耐圧がばらつくことを抑制でき、デバイス特性の悪化を抑制することが可能となる。 Therefore, the p-type layer for forming the p-type column and the p-type layer formed on the SJ structure can be constituted by the same p − -type layer 16 and can be formed at the same time. Can be simplified. Further, as in the case where the p-type layer on the SJ structure is formed after the SJ structure is formed, the surface of the PN column is not flattened and the surface of the PN column such as flattening polishing or wafer cleaning is not performed. There is no need to perform processing between the structures of the p - type layer 16 and the p - type layer 16. Therefore, variation in the breakdown voltage of the semiconductor device can be suppressed, and deterioration of device characteristics can be suppressed.

さらに、凹部１２ａの形成工程を、スクライブ領域に形成されるアライメントのターゲットとなる凹部１２ｂの形成と同時に行うようにしている。このため、凹部１２ａの形成工程と凹部１２ｂの形成工程を共通化することができ、さらに製造工程の簡略化を図ることが可能となる。   Further, the step of forming the recess 12a is performed simultaneously with the formation of the recess 12b serving as an alignment target formed in the scribe region. For this reason, the formation process of the recessed part 12a and the formation process of the recessed part 12b can be made common, and also it becomes possible to aim at simplification of a manufacturing process.

（第２実施形態）
本発明の第２実施形態について説明する。本実施形態は、第１実施形態に対して半導体装置に形成される縦型ＭＯＳＦＥＴをプレーナ型に変更したものであり、その他については第１実施形態と同様であるため、第１実施形態と異なる部分についてのみ説明する。 (Second Embodiment)
A second embodiment of the present invention will be described. This embodiment is different from the first embodiment in that the vertical MOSFET formed in the semiconductor device is changed to a planar type with respect to the first embodiment, and the others are the same as the first embodiment. Only the part will be described.

図４を参照して、本実施形態にかかる縦型ＭＯＳＦＥＴの製造方法について説明する。   With reference to FIG. 4, the manufacturing method of the vertical MOSFET concerning this embodiment is demonstrated.

まず、第１実施形態で説明した図１（ａ）、（ｂ）、図２（ａ）、（ｂ）の工程を行ったのち、図４（ａ）の工程として、第１実施形態で説明した図３（ａ）と同様の工程を行う。これにより、半導体基板１０の表面側において、凹部１２ａおよびトレンチ１５内を含めｎ-型層１２の表面にｐ-型層１６をエピタキシャル成長させ、さらにｐ-型層１６が凹部１２ａ内に残された構造が構成される。つまり、ＳＪ構造を構成するｐ型カラムおよびＳＪ構造の上にｐ-型層１６が既に形成された構造が形成される。これらの工程は基本的に第１実施形態と全く同じで構わない。ただし、ＳＪ構造の上に残るｐ-型層１６の膜厚については、後述するｎ型接続層３０をイオン注入によって形成する際に、ＳＪ構造上のｐ-型層１６を貫通してｎ型接続層３０が形成できる程度の膜厚となるようにしている。 First, after performing the steps of FIGS. 1A, 1B, 2A, and 2B described in the first embodiment, the steps of FIG. 4A will be described in the first embodiment. The same process as in FIG. As a result, on the surface side of the semiconductor substrate 10, the p − type layer 16 was epitaxially grown on the surface of the n − type layer 12 including the inside of the recess 12a and the trench 15, and the p − type layer 16 was left in the recess 12a. Structure is constructed. That is, a p-type column constituting the SJ structure and a structure in which the p − -type layer 16 is already formed on the SJ structure are formed. These steps may be basically the same as those in the first embodiment. However, regarding the film thickness of the p − type layer 16 remaining on the SJ structure, the n − type layer penetrates the p − type layer 16 on the SJ structure when an n type connection layer 30 described later is formed by ion implantation. The thickness is such that the connection layer 30 can be formed.

そして、図４（ｂ）に示す工程において、プレーナ型の縦型ＭＯＳＦＥＴの各構成要素を形成するための製造工程を行う。   Then, in the process shown in FIG. 4B, a manufacturing process for forming each component of the planar type vertical MOSFET is performed.

すなわち、ＳＪ構造上のｐ-型層１６の表層部にｐ型不純物をイオン注入してｐ-型チャネル層１７を形成すると共に、ｐ-型チャネル層１７の表層部にｎ型不純物をイオン注入してｎ+型ソース領域１８を形成する。また、ｐ-型チャネル層１７のうちｐ-型層１６の上に形成された部分を中心としてｐ型不純物をイオン注入することでｐ+型ボディ層１９を形成すると共に、このｐ+型ボディ層１９の表層部にｐ+型コンタクト領域２０を形成する。さらに、各ｐ+型コンタクト領域２０の間に配置された隣り合うｎ+型ソース領域１８の間において、ｎ+型ソース領域１８から所定間隔離間した位置にｎ型不純物をイオン注入することで、ｐ-型チャネル層１７からｎ-型層１２に達するｎ型接続層３０を形成する。このｎ型接続層３０は、ｐ-型チャネル層１７におけるチャネル形成部に接しつつｐ-型層１６を貫通してｎ-型層１２のうちｎ型カラムを構成する部分に達するように形成される。このため、ｎ型接続層３０は、プレーナ型の縦型ＭＯＳＦＥＴが動作する際の電流経路となってオン抵抗を低減させる役割を果たす。 Ie, p on SJ structure - by ion-implanting the p-type impurity in a surface portion of the mold layer 16 p - to form a mold channel layer 17, p - ion implanting an n-type impurity into the surface portion of the mold channel layer 17 Thus, the n + type source region 18 is formed. Further, a p + type body layer 19 is formed by ion implantation of p type impurities centering on a portion of the p − type channel layer 17 formed on the p − type layer 16, and this p + type body is also formed. A p + -type contact region 20 is formed in the surface layer portion of the layer 19. Further, n-type impurities are ion-implanted at a predetermined distance from the n + -type source region 18 between adjacent n + -type source regions 18 arranged between the p + -type contact regions 20, An n-type connection layer 30 reaching the n − -type layer 12 from the p − -type channel layer 17 is formed. The n-type connection layer 30 is formed so as to pass through the p − -type layer 16 while being in contact with the channel forming portion in the p − -type channel layer 17 and reach a portion constituting the n-type column of the n − -type layer 12. The For this reason, the n-type connection layer 30 serves as a current path when the planar vertical MOSFET operates, and plays a role of reducing the on-resistance.

さらに、少なくともｐ-型チャネル層１７の表面を覆うゲート絶縁膜２２を形成すると共に、ゲート絶縁膜２２上にゲート電極２３を形成する。また、半導体基板１０の表面側において、層間絶縁膜２４の形成工程やゲート配線およびソース電極２５の形成工程を行う。そして、半導体基板１０の裏面側において、ｎ+型シリコン基板１１の裏面１１ｂに接続されるドレイン電極２６の形成工程を行うことにより、ｎチャネルのプレーナ型の縦型ＭＯＳＦＥＴが形成される。その後、ダイシングによりチップ単位に分割することでＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを備えた半導体装置が完成する。 Further, a gate insulating film 22 that covers at least the surface of the p − -type channel layer 17 is formed, and a gate electrode 23 is formed on the gate insulating film 22. Further, on the surface side of the semiconductor substrate 10, an interlayer insulating film 24 forming process and a gate wiring and source electrode 25 forming process are performed. Then, on the back surface side of the semiconductor substrate 10, an n-channel planar vertical MOSFET is formed by performing a process of forming the drain electrode 26 connected to the back surface 11 b of the n + -type silicon substrate 11. Thereafter, the semiconductor device including the planar type vertical MOSFET having the SJ structure is completed by dividing into chips by dicing.

このように、第１実施形態と同様の製造方法をプレーナ型の縦型ＭＯＳＦＥＴを備えた半導体装置についても適用することができ、第１実施形態と同様の効果を得ることができる。   As described above, the same manufacturing method as that of the first embodiment can be applied to the semiconductor device including the planar type vertical MOSFET, and the same effect as that of the first embodiment can be obtained.

（第３実施形態）
本発明の第３実施形態について説明する。本実施形態は、第２実施形態に対して半導体装置の外周耐圧構造を考慮に入れた製造方法としたものであり、その他については第２実施形態と同様であるため、第２実施形態と異なる部分についてのみ説明する。 (Third embodiment)
A third embodiment of the present invention will be described. The present embodiment is a manufacturing method that takes into account the peripheral breakdown voltage structure of the semiconductor device with respect to the second embodiment, and is otherwise the same as the second embodiment, and is different from the second embodiment. Only the part will be described.

図５〜図７を参照して、本実施形態にかかる縦型ＭＯＳＦＥＴの製造方法、つまりＳＪ構造を有するプレーナ型の縦型ＭＯＳＦＥＴを備えた半導体装置において、外周耐圧構造の形成工程も含めた製造方法について説明する。   Referring to FIGS. 5 to 7, a vertical MOSFET manufacturing method according to the present embodiment, that is, a semiconductor device including a planar vertical MOSFET having an SJ structure, including a step of forming an outer peripheral breakdown voltage structure. A method will be described.

まず、図５（ａ）に示す工程では、表面１１ａおよび裏面１１ｂを有する半導体材料で構成された基板としてのｎ+型シリコン基板１１の表面１１ａに、第１半導体層に相当するｎ-型層１２をエピタキシャル成長させたものを用意する。そして、第１実施形態で説明した図１（ｂ）に示す工程を行って、凹部１２ａ、１２ｂを形成する。続いて、図示しないマスクを用いたフォトエッチング工程により、ｎ-型層１２のうち外周領域に相当する部分に凹部１２ｃを形成する。具体的には、メイン領域のうちの縦型ＭＯＳＦＥＴが形成される領域をセル領域として、その外周領域においてリサーフ層を形成することによって外周耐圧構造とするが、このリサーフ層となる部分において凹部１２ｃを形成している。 First, in the step shown in FIG. 5A, an n − -type layer corresponding to the first semiconductor layer is formed on the surface 11a of an n + -type silicon substrate 11 as a substrate made of a semiconductor material having a front surface 11a and a back surface 11b. 12 is prepared by epitaxial growth. And the recessed part 12a, 12b is formed by performing the process shown in FIG.1 (b) demonstrated in 1st Embodiment. Subsequently, a recess 12c is formed in a portion corresponding to the outer peripheral region of the n − -type layer 12 by a photoetching process using a mask (not shown). Specifically, the region where the vertical MOSFET is formed in the main region is defined as the cell region, and the RESURF layer is formed in the outer peripheral region to form the outer peripheral withstand voltage structure. Is forming.

その後、図５（ｂ）に示す工程では、凹部１２ｃ内を埋め込むようにｎ-型層１２の表面にｐ-型層１６をエピタキシャル成長させ、必要に応じて表面を平坦化研磨する。このとき、例えばｎ-型層１２の表面にｐ-型層１６が３〜７μｍの膜厚で残るようにしている。これにより、凹部１２ｃ内において凹部１２ｃが形成されていない部分よりもｐ-型層１６が厚くされた半導体基板１０が形成される。 Thereafter, in the step shown in FIG. 5B, the p − -type layer 16 is epitaxially grown on the surface of the n − -type layer 12 so as to fill the recess 12c, and the surface is planarized and polished as necessary. At this time, for example, the p − type layer 16 remains on the surface of the n − type layer 12 with a film thickness of 3 to 7 μm. As a result, the semiconductor substrate 10 is formed in which the p − type layer 16 is thicker than the portion of the recess 12c where the recess 12c is not formed.

この後は、図６（ａ）、（ｂ）、図７（ａ）、（ｂ）に示す工程において、第１、第２実施形態で説明した図２（ａ）、（ｂ）、図４（ａ）、（ｂ）と同様の工程を行う。これにより、外周耐圧構造として、セル領域よりも外周領域において、ｐ-型層１６が深くまで形成されることでリサーフ層４０が構成されたＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを備えた半導体装置が完成する。 Thereafter, in the steps shown in FIGS. 6A, 6B, 7A, and 7B, FIGS. 2A, 2B, and 4 described in the first and second embodiments. Steps similar to (a) and (b) are performed. Thereby, as a peripheral breakdown voltage structure, a semiconductor device provided with a planar vertical MOSFET of SJ structure in which the RESURF layer 40 is formed by forming the p − -type layer 16 deeper in the peripheral region than in the cell region. Is completed.

このように、外周耐圧構造としてリサーフ層を形成する場合を考慮した製造方法とすることもできる。このようにしても、第２実施形態と同様の効果を得ることができる。   Thus, it can also be set as the manufacturing method which considered the case where a RESURF layer is formed as an outer periphery pressure | voltage resistant structure. Even if it does in this way, the effect similar to 2nd Embodiment can be acquired.

なお、第２実施形態でもｐ-型層１６を外周領域にも形成しているため、凹部１２ｃを形成しなくても、第２実施形態に示した製造方法によって外周領域にリサーフ層４０を構成することができる。しかしながら、図７（ａ）に示したように、ｐ-型層１６の表面の平坦化研磨を行ったときに、ｎ-型層１２が露出する程度までｐ-型層１６が除去されてしまうことも有り得る。その場合においても、図７（ｂ）と同様の工程を行うことで、ＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを備えた半導体装置を製造することができる。その場合、外周領域にｐ-型層１６が残らなくなりリサーフ層４０を構成することができなくなる。このため、本実施形態のようにｎ-型層１２に凹部１２ｃを形成しておき、予め外周領域においてセル領域よりもｐ-型層１６を厚く形成しておくことで、確実にリサーフ層４０が構成されるようにすることができる。 Since the p − type layer 16 is also formed in the outer peripheral region in the second embodiment, the RESURF layer 40 is formed in the outer peripheral region by the manufacturing method shown in the second embodiment without forming the recess 12c. can do. However, as shown in FIG. 7A, when the surface of the p − -type layer 16 is planarized and polished, the p − -type layer 16 is removed to the extent that the n − -type layer 12 is exposed. It is possible. Even in that case, the semiconductor device including the planar type vertical MOSFET having the SJ structure can be manufactured by performing the same process as in FIG. In that case, the p − -type layer 16 does not remain in the outer peripheral region, and the RESURF layer 40 cannot be formed. Therefore, the recess 12c is formed in the n − -type layer 12 as in the present embodiment, and the p − -type layer 16 is formed thicker than the cell region in the outer peripheral region in advance, so that the RESURF layer 40 is surely formed. Can be configured.

また、ｎ-型層１２の表面が露出する程度まで平坦化研磨を行った場合、ｎ-型層１２も研磨され得るのでＰＮカラムの深さにバラツキが生じる可能性がある。しかしながら、ｎ型接続層３０によって低オン抵抗化が図れるため、ｐ-型層１６が残るような条件で平坦化研磨を行えば良く、従来のようにｎ-型層１２を露出させることが必須の構成ではない。このため、仮にｎ-型層１２が研磨されたとしても研磨量は非常に少なく、殆どＰＮカラムの深さのバラツキによる耐圧バラツキは生じないで済む。 Further, when planarization polishing is performed to such an extent that the surface of the n − -type layer 12 is exposed, the n − -type layer 12 can also be polished, so that the PN column depth may vary. However, since the on-resistance can be reduced by the n-type connection layer 30, planarization polishing may be performed under the condition that the p − -type layer 16 remains, and it is essential to expose the n − -type layer 12 as in the prior art. It is not a configuration of. For this reason, even if the n − -type layer 12 is polished, the amount of polishing is very small, and there is almost no variation in pressure resistance due to variations in the depth of the PN column.

（他の実施形態）
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。 (Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

例えば、上記第３実施形態に示すように外周耐圧構造を考慮に入れた製造方法を第１実施形態に示したようなトレンチゲート型の縦型ＭＯＳＦＥＴを備えた半導体装置の製造方法に適用することもできる。具体的には、第３実施形態で説明した図７（ａ）の工程まで行ったのち、第１実施形態で説明した図３（ｂ）と同様の工程を行うことで、図８に示すようなトレンチゲート型の縦型ＭＯＳＦＥＴとする。このように、トレンチゲート型の縦型ＭＯＳＦＥＴを備えた半導体装置を製造する際にも、ｎ-型層１２に予め凹部１２ｃを形成しておくことで、平坦化研磨後にも少なくとも凹部１２ｃ内にｐ-型層１６が残る。これにより、リサーフ層４０が構成されるようにでき、第３実施形態と同様の効果を得ることができる。 For example, as shown in the third embodiment, the manufacturing method taking into account the peripheral withstand voltage structure is applied to the manufacturing method of the semiconductor device including the trench gate type vertical MOSFET as shown in the first embodiment. You can also. Specifically, after performing the process up to FIG. 7A described in the third embodiment, the same process as that in FIG. 3B described in the first embodiment is performed, as shown in FIG. A trench gate type vertical MOSFET is used. As described above, even when a semiconductor device including a trench gate type vertical MOSFET is manufactured, by forming the recess 12c in the n − type layer 12 in advance, at least in the recess 12c even after the planarization polishing. The p - type layer 16 remains. Thereby, the RESURF layer 40 can be comprised and the effect similar to 3rd Embodiment can be acquired.

また、上記各実施形態では、第１導電型をｎ型、第２導電型をｐ型としたｎチャネルタイプのＭＯＳＦＥＴを例に挙げて説明したが、各構成要素の導電型を反転させたｐチャネルタイプのＭＯＳＦＥＴに対しても本発明を適用することができる。   In each of the above-described embodiments, an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. The present invention can also be applied to a channel type MOSFET.

また、上記実施形態では、メイン領域とスクライブ領域との間において段差が形成されるように第１凹部１２ａを形成したが、これらの領域の間以外の場所に段差が形成されるように第１凹部１２ａを形成しても良い。例えば、チップ単位に分割する前のウェハにおいては、メイン領域およびスクライブ領域の他に、これらの外周部においてチップ化されない不要領域が存在する。このため、メイン領域およびスクライブ領域と不要領域との間に段差が形成されるように、例えばメイン領域およびスクライブ領域を含むように第１凹部１２ａを形成しても良い。また、メイン領域のうちの外周部に段差が形成されるようにしても良い。その場合、メイン領域の少なくとも一部、具体的にはセル領域を含むように第１凹部１２ａを形成すれば良い。   Moreover, in the said embodiment, although the 1st recessed part 12a was formed so that a level | step difference might be formed between a main area | region and a scribe area | region, it is 1st so that a level | step difference may be formed in places other than between these area | regions. The recess 12a may be formed. For example, in the wafer before being divided into chips, in addition to the main area and the scribe area, there are unnecessary areas that are not formed into chips in the outer periphery. For this reason, the first recess 12a may be formed so as to include, for example, the main region and the scribe region so that a step is formed between the main region and the scribe region and the unnecessary region. Further, a step may be formed on the outer peripheral portion of the main region. In that case, the first recess 12a may be formed so as to include at least a part of the main region, specifically, the cell region.

さらに、上記実施形態では、ＳＪ構造を形成する際のＰＮカラムの深さのバラツキを抑制できるように、第１凹部１２ａを形成する場合を例に挙げて説明した。しかしながら、平坦化研磨などの構造間の処理に基づくｐ-型層１６の異常成長に関しては、第１凹部１２ａを形成するか否かにかかわらず抑制可能である。すなわち、ｎ-型層１２に形成したトレンチ１５内にｐ-型層１６を埋め込みつつ、更に引き続きｎ-型層１２のうちトレンチ１５の外側の部分の上にもｐ-型層１６を形成することで、ｐ-型層１６の異常成長を抑制でき、デバイス特性の悪化を抑制することが可能となる。 Furthermore, in the above embodiment, the case where the first recess 12a is formed has been described as an example so as to suppress the variation in the depth of the PN column when forming the SJ structure. However, abnormal growth of the p − -type layer 16 based on processing between structures such as planarization polishing can be suppressed regardless of whether or not the first recess 12a is formed. That, n - while buried type layer 16, further continue n - - p in the mold layer 12 in the formed trench 15 also p on the outer portion of the trench 15 of the type layer 12 - -type layer 16 Thus, abnormal growth of the p − -type layer 16 can be suppressed, and deterioration of device characteristics can be suppressed.

１０ 半導体基板
１１ ｎ+型シリコン基板（基板）
１２ ｎ-型層（第１半導体層）
１２ａ〜１２ｃ 凹部
１３、１４ 酸化膜（マスク）
１５ トレンチ
１６ ｐ-型層
１７ ｐ型チャネル層
１８ ｎ+型ソース領域
２３ ゲート電極
２４ 層間絶縁膜
２５ ソース電極
２６ ドレイン電極
３０ ｎ型接続層 10 Semiconductor substrate 11 n + type silicon substrate (substrate)
12 n - -type layer (first semiconductor layer)
12a to 12c Recesses 13, 14 Oxide film (mask)
15 trench 16 p − type layer 17 p type channel layer 18 n + type source region 23 gate electrode 24 interlayer insulating film 25 source electrode 26 drain electrode 30 n type connection layer

Claims (12)

半導体材料で構成された基板（１１）の表面（１１ａ）側に、第１導電型の第１半導体層（１２）が形成された半導体基板（１０）を用意する工程と、
前記第１半導体層のうち縦型ＭＯＳＦＥＴを形成してチップとして用いるメイン領域の少なくとも一部を含むように第１凹部（１２ａ）を形成することで、前記第１半導体層に段差を付ける工程と、
前記第１凹部内を含めて前記第１半導体層の上にマスク（１４）を配置し、該マスクを用いて前記メイン領域における前記第１凹部内において、前記第１半導体層をエッチングすることでトレンチ（１５）を形成する工程と、
前記マスクのうちの少なくとも前記第１凹部内に形成されている部分を除去したのち、前記トレンチ内および前記第１凹部内を埋め込みつつ前記第１半導体層の上に、第２導電型の第２半導体層（１６）をエピタキシャル成長させる工程と、
前記第２半導体層を平坦化研磨することで、前記第２半導体層を前記トレンチおよび前記第１凹部に残し、前記トレンチ内に残された前記第２半導体層による第２導電型カラムと前記第１半導体層による第１導電型カラムとが交互に繰り返されたＰＮカラムを有するスーパージャンクション構造を形成する工程と、
前記スーパージャンクション構造の上に、第２導電型のチャネル層（１７）と該チャネル層に接する第１導電型のソース領域（１８）を形成すると共に、前記チャネル層の表面にゲート絶縁膜（２２）を介してゲート電極（２３）を形成し、さらに前記半導体基板の表面側に前記ソース領域に電気的に接続されるソース電極（２５）を形成すると共に、前記半導体基板の裏面側に前記基板の裏面に接続されるドレイン電極（２６）を形成することで縦型ＭＯＳＦＥＴを形成する工程と、を含んでいることを特徴とするスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。 Preparing a semiconductor substrate (10) having a first semiconductor layer (12) of the first conductivity type formed on a surface (11a) side of a substrate (11) made of a semiconductor material;
Forming a step in the first semiconductor layer by forming a first recess (12a) so as to include at least a part of a main region used as a chip by forming a vertical MOSFET in the first semiconductor layer. ,
A mask (14) is disposed on the first semiconductor layer including the inside of the first recess, and the first semiconductor layer is etched in the first recess in the main region using the mask. Forming a trench (15);
After removing at least a portion of the mask formed in the first recess, a second conductivity type second layer is formed on the first semiconductor layer while filling the trench and the first recess. Epitaxially growing the semiconductor layer (16);
By planarizing and polishing the second semiconductor layer, the second semiconductor layer is left in the trench and the first recess, and the second conductivity type column is formed by the second semiconductor layer left in the trench and the second semiconductor layer. Forming a super junction structure having a PN column in which a first conductivity type column of one semiconductor layer is alternately repeated;
A second conductivity type channel layer (17) and a first conductivity type source region (18) in contact with the channel layer are formed on the super junction structure, and a gate insulating film (22) is formed on the surface of the channel layer. ), A source electrode (25) electrically connected to the source region is formed on the front surface side of the semiconductor substrate, and the substrate is formed on the back surface side of the semiconductor substrate. Forming a vertical MOSFET by forming a drain electrode (26) connected to the back surface of the semiconductor device. A method of manufacturing a semiconductor device having a vertical MOSFET having a super junction structure. 前記段差を付ける工程では、前記メイン領域とダイシング時にカットされるスクライブ領域との境界位置まで前記第１凹部を形成し、前記メイン領域と前記スクライブ領域の間に段差を付けることを特徴とする請求項１に記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。   The step of forming a step includes forming the first recess to a boundary position between the main region and a scribe region cut during dicing, and forming a step between the main region and the scribe region. A manufacturing method of a semiconductor device having the vertical MOSFET having a super junction structure according to Item 1. 前記段差を付ける工程では、前記メイン領域とダイシング時にカットされるスクライブ領域との境界位置において、前記メイン領域における外縁部の少なくとも一部に前記第１半導体層が凸状に残されるようにすることを特徴とする請求項１または２に記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。   In the step of providing the step, the first semiconductor layer is left in a convex shape at least at a part of the outer edge of the main region at a boundary position between the main region and a scribe region cut during dicing. 3. A method of manufacturing a semiconductor device having a vertical MOSFET having a super junction structure according to claim 1 or 2. 前記第１半導体層が凸状に残された位置に、前記第１半導体層との導通をとる第１導電型不純物層（２７）を形成する工程を含んでいることを特徴とする請求項３に記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。   4. The method includes forming a first conductivity type impurity layer (27) that is electrically connected to the first semiconductor layer at a position where the first semiconductor layer is left in a convex shape. A manufacturing method of a semiconductor device having the vertical MOSFET having the super junction structure described in 1. 前記スクライブ領域にアライメントのターゲットとなる第２凹部（１２ｂ）を形成する工程を行うことを特徴とする請求項２ないし４のいずれか１つに記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。   5. The semiconductor device having a vertical MOSFET with a super junction structure according to claim 2, wherein a step of forming a second recess (12b) serving as an alignment target in the scribe region is performed. Manufacturing method. 前記第２凹部（１２ｂ）を形成する工程を、前記段差を付ける工程における前記第１凹部の形成と同時に行うことを特徴とする請求項５に記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。   6. The semiconductor device having a vertical MOSFET with a super junction structure according to claim 5, wherein the step of forming the second recess (12b) is performed simultaneously with the formation of the first recess in the step of forming the step. Manufacturing method. 前記第２半導体層を形成する工程の前に、前記第１半導体層のうち前記縦型ＭＯＳＦＥＴが形成されるセル領域の周辺領域となる外周領域において第３凹部（１２ｃ）を形成する工程を有し、
前記第２半導体層を形成する工程では、前記第３凹部内を埋め込むように前記第１半導体層の上に前記第２半導体層を形成することを特徴とする請求項１ないし６のいずれか１つに記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。 Before the step of forming the second semiconductor layer, there is a step of forming a third recess (12c) in an outer peripheral region that is a peripheral region of the cell region in which the vertical MOSFET is formed in the first semiconductor layer. And
7. The step of forming the second semiconductor layer, wherein the second semiconductor layer is formed on the first semiconductor layer so as to fill the third recess. The manufacturing method of the semiconductor device which has vertical MOSFET of the super junction structure as described in one. 前記縦型ＭＯＳＦＥＴを形成する工程は、
前記第１半導体層にて構成される第１導電型カラムの上において、第２導電型不純物をイオン注入して前記チャネル層を形成する工程と、
前記チャネル層の表層部に第１導電型不純物をイオン注入して前記ソース領域を形成する工程と、
前記チャネル層を貫通して前記第１導電型カラムに達するゲートトレンチ（２１）を形成する工程と、
前記ゲートトレンチの内壁面に前記ゲート絶縁膜を形成すると共に、前記ゲート絶縁膜の表面に前記ゲート電極を形成する工程と、を含む、トレンチゲート型の縦型ＭＯＳＦＥＴを形成する工程であることを特徴とする請求項１ないし７のいずれか１つに記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。 The step of forming the vertical MOSFET includes:
Forming a channel layer by ion-implanting a second conductivity type impurity on a first conductivity type column composed of the first semiconductor layer;
Forming a source region by ion-implanting a first conductivity type impurity into a surface layer portion of the channel layer;
Forming a gate trench (21) passing through the channel layer and reaching the first conductivity type column;
Forming the gate insulating film on the inner wall surface of the gate trench and forming the gate electrode on the surface of the gate insulating film, and forming a trench gate type vertical MOSFET. 8. A method of manufacturing a semiconductor device having a super junction structure vertical MOSFET according to claim 1. 前記縦型ＭＯＳＦＥＴを形成する工程は、
前記第１半導体層にて構成される第１導電型カラムの上において、第２導電型不純物をイオン注入して前記チャネル層を形成する工程と、
前記チャネル層の表層部に第１導電型不純物をイオン注入して前記ソース領域を形成する工程と、
前記ソース領域から所定間隔離間した位置に第１導電型不純物をイオン注入して、前記チャネル層から前記第１半導体層に達する第１導電型接続層（３０）を形成する工程と、
前記チャネル層の表面に前記ゲート絶縁膜を形成すると共に、前記ゲート絶縁膜の表面に前記ゲート電極を形成する工程と、を含む、プレーナ型の縦型ＭＯＳＦＥＴを形成する工程であることを特徴とする請求項１ないし７のいずれか１つに記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。 The step of forming the vertical MOSFET includes:
Forming a channel layer by ion-implanting a second conductivity type impurity on a first conductivity type column composed of the first semiconductor layer;
Forming a source region by ion-implanting a first conductivity type impurity into a surface layer portion of the channel layer;
Ion-implanting a first conductivity type impurity at a position spaced apart from the source region to form a first conductivity type connection layer (30) reaching the first semiconductor layer from the channel layer;
Forming the gate insulating film on the surface of the channel layer and forming the gate electrode on the surface of the gate insulating film, and forming a planar type vertical MOSFET. A method for manufacturing a semiconductor device comprising a vertical MOSFET having a super junction structure according to any one of claims 1 to 7. 半導体材料で構成された基板（１１）の表面（１１ａ）側に、第１導電型の第１半導体層（１２）が形成された半導体基板（１０）を用意する工程と、
前記第１半導体層の上にマスク（１４）を配置したのち、該第１半導体層のうち縦型ＭＯＳＦＥＴを形成してチップとして用いるメイン領域において該第１半導体層をエッチングすることでトレンチ（１５）を形成する工程と、
前記トレンチ内を埋め込みつつ、前記第１半導体層のうち前記トレンチの外側の部分の上にも、第２導電型の第２半導体層（１６）をエピタキシャル成長させることで、前記トレンチ内に残された前記第２半導体層による第２導電型カラムと前記第１半導体層による第１導電型カラムとが交互に繰り返されたＰＮカラムを有するスーパージャンクション構造を形成する工程と、
前記スーパージャンクション構造の上に、第２導電型のチャネル層（１７）と該チャネル層に接する第１導電型のソース領域（１８）を形成すると共に、前記チャネル層の表面にゲート絶縁膜（２２）を介してゲート電極（２３）を形成し、さらに前記半導体基板の表面側に前記ソース領域に電気的に接続されるソース電極（２５）を形成すると共に、前記半導体基板の裏面側に前記基板の裏面に接続されるドレイン電極（２６）を形成することで縦型ＭＯＳＦＥＴを形成する工程と、を含んでいることを特徴とするスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。 Preparing a semiconductor substrate (10) having a first semiconductor layer (12) of the first conductivity type formed on a surface (11a) side of a substrate (11) made of a semiconductor material;
After the mask (14) is disposed on the first semiconductor layer, a trench (15) is formed by etching the first semiconductor layer in a main region used as a chip by forming a vertical MOSFET in the first semiconductor layer. )
The second conductivity type second semiconductor layer (16) is also epitaxially grown on the portion of the first semiconductor layer outside the trench while being buried in the trench, thereby remaining in the trench. Forming a super junction structure having a PN column in which a second conductivity type column of the second semiconductor layer and a first conductivity type column of the first semiconductor layer are alternately repeated;
A second conductivity type channel layer (17) and a first conductivity type source region (18) in contact with the channel layer are formed on the super junction structure, and a gate insulating film (22) is formed on the surface of the channel layer. ), A source electrode (25) electrically connected to the source region is formed on the front surface side of the semiconductor substrate, and the substrate is formed on the back surface side of the semiconductor substrate. Forming a vertical MOSFET by forming a drain electrode (26) connected to the back surface of the semiconductor device. A method of manufacturing a semiconductor device having a vertical MOSFET having a super junction structure. 半導体材料で構成された基板（１１）の表面（１１ａ）側に、第１導電型の第１半導体層（１２）が形成された半導体基板（１０）と、
前記第１半導体層の一部がエッチングされて形成された第１凹部（１２ａ）と、
前記第１凹部により前記第１半導体層に形成された段差によって構成され、前記第１半導体層のうち前記第１凹部の外側に位置している凸部と、
前記第１凹部内において前記第１半導体層がエッチングされることで形成されたトレンチ（１５）と、
前記トレンチ内および前記第１凹部内を埋め込みつつ前記第１半導体層の上にエピタキシャル成長させられた第２導電型の第２半導体層（１６）とを有し、
前記トレンチ内の前記第２半導体層による第２導電型カラムと前記第１半導体層による第１導電型カラムとが交互に繰り返されたＰＮカラムを有するスーパージャンクション構造が構成されていると共に、
前記スーパージャンクション構造の上に、第２導電型のチャネル層（１７）と該チャネル層に接する第１導電型のソース領域（１８）と、前記チャネル層の表面にゲート絶縁膜（２２）を介して形成されたゲート電極（２３）と、前記ソース領域に電気的に接続されるソース電極（２５）とが備えられ、かつ、前記半導体基板の裏面側に前記基板の裏面に接続されるドレイン電極（２６）が備えられた縦型ＭＯＳＦＥＴが形成されていることを特徴とするスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置。 A semiconductor substrate (10) in which a first semiconductor layer (12) of a first conductivity type is formed on a surface (11a) side of a substrate (11) made of a semiconductor material;
A first recess (12a) formed by etching a part of the first semiconductor layer;
A protrusion formed by a step formed in the first semiconductor layer by the first recess, the protrusion being located outside the first recess in the first semiconductor layer;
A trench (15) formed by etching the first semiconductor layer in the first recess;
A second semiconductor layer of a second conductivity type (16) epitaxially grown on the first semiconductor layer while filling the trench and the first recess,
A super junction structure having a PN column in which a second conductivity type column by the second semiconductor layer in the trench and a first conductivity type column by the first semiconductor layer are alternately repeated;
On the super junction structure, a second conductivity type channel layer (17), a first conductivity type source region (18) in contact with the channel layer, and a gate insulating film (22) on the surface of the channel layer. A drain electrode connected to the back surface of the semiconductor substrate on the back surface side of the semiconductor substrate, and a gate electrode (23) formed in this manner and a source electrode (25) electrically connected to the source region A semiconductor device having a vertical MOSFET having a super junction structure, wherein the vertical MOSFET provided with (26) is formed. 前記凸部には、前記第１半導体層との導通をとる第１導電型不純物層（２７）が形成されていることを特徴とする請求項１１に記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置。   The vertical MOSFET having a super junction structure according to claim 11, wherein a first conductivity type impurity layer (27) that conducts with the first semiconductor layer is formed on the convex portion. Semiconductor device.
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