JP5724997B2 - Manufacturing method of semiconductor device having vertical MOSFET of super junction structure - Google Patents

Manufacturing method of semiconductor device having vertical MOSFET of super junction structure Download PDF

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JP5724997B2
JP5724997B2 JP2012268413A JP2012268413A JP5724997B2 JP 5724997 B2 JP5724997 B2 JP 5724997B2 JP 2012268413 A JP2012268413 A JP 2012268413A JP 2012268413 A JP2012268413 A JP 2012268413A JP 5724997 B2 JP5724997 B2 JP 5724997B2
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JP2014116410A (en
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浩次 江口
浩次 江口
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Denso Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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Description

本発明は、第１半導体層に形成したトレンチ内に第２半導体層をエピタキシャル成長させてスーパージャンクション（以下、ＳＪという）構造を形成するＳＪ構造の縦型ＭＯＳＦＥＴを備えた半導体装置の製造方法に関するものである。   The present invention relates to a method for manufacturing a semiconductor device including a vertical MOSFET having an SJ structure in which a second semiconductor layer is epitaxially grown in a trench formed in a first semiconductor layer to form a super junction (hereinafter referred to as SJ) structure. It is.

従来より、ｎ型カラムとｐ型カラムとが交互に繰り返し形成されたＳＪ構造を有する半導体装置が知られている（例えば、特許文献１参照）。ＳＪ構造の半導体装置を製造する際には、例えば図９（ａ）に示すように、ｎ+型シリコン基板Ｊ１の表面にｎ-型層Ｊ２をエピタキシャル成長させた半導体基板Ｊ３を用いて行われている。図９（ｂ）に示すように、ｎ-型層Ｊ２にトレンチＪ４を形成したのち、図９（ｃ）に示すように、そのトレンチＪ４内にｐ-型層Ｊ５をエピタキシャル成長させる。そして、図１０（ａ）に示すように、表面の平坦化研磨によってトレンチＪ４の外に形成されたｐ-型層Ｊ５を除去してトレンチＪ４内にのみ残す。これにより、ｎ-型層Ｊ２からなるｎ型カラムとｐ-型層Ｊ５からなるｐ型カラムが交互に繰り返されたＰＮカラムを有するＳＪ構造を形成している。 Conventionally, a semiconductor device having an SJ structure in which n-type columns and p-type columns are alternately and repeatedly formed is known (see, for example, Patent Document 1). When manufacturing a semiconductor device having an SJ structure, for example, as shown in FIG. 9A, a semiconductor substrate J3 in which an n − type layer J2 is epitaxially grown on the surface of an n + type silicon substrate J1 is used. Yes. As shown in FIG. 9B, after forming a trench J4 in the n − -type layer J2, a p − -type layer J5 is epitaxially grown in the trench J4 as shown in FIG. 9C. Then, as shown in FIG. 10A, the p − -type layer J5 formed outside the trench J4 is removed by planarization of the surface and is left only in the trench J4. Thus, an SJ structure having a PN column in which an n-type column composed of an n − -type layer J2 and a p-type column composed of a p − -type layer J5 are alternately repeated is formed.

その後、図１０（ｂ）に示すように、ＳＪ構造を形成した後で、ｐ-型層Ｊ６をエピタキシャル成長させたのち、その後のデバイス形成工程を行う。例えば、図１０（ｃ）に示すように、ｎ+型ソース領域Ｊ７、トレンチゲート構造Ｊ８や表面電極Ｊ９および裏面電極Ｊ１０の形成工程などを従来と同様の手法によって行う。このような手法により、ＳＪ構造の縦型ＭＯＳトランジスタを製造している。 Thereafter, as shown in FIG. 10B, after the SJ structure is formed, the p − -type layer J6 is epitaxially grown, and then a subsequent device formation step is performed. For example, as shown in FIG. 10C, the n + -type source region J7, the trench gate structure J8, the front surface electrode J9, the back surface electrode J10, and the like are formed by a method similar to the conventional method. A vertical MOS transistor having an SJ structure is manufactured by such a method.

特開２０１２−０６４６６０号公報JP 2012-064660 A

しかしながら、ｐ-型層Ｊ５をトレンチＪ４内に埋め込むようにエピタキシャル成長させた後で行うｐ-型層Ｊ５およびｎ-型層Ｊ２の表面の平坦化研磨のバラツキが大きく、ＰＮカラムの深さがばらついて精度良く所望の深さにすることができなかった。これは、エピタキシャル成長自体の精度の問題もあるが、それ以上にｐ-型層Ｊ５およびｎ-型層Ｊ２の平坦化研磨が同じ半導体材料（例えばシリコン）の研磨加工となり、狙いの膜厚で研磨ストップを行うのが原理的に難しいためである。そして、このようにＰＮカラムの深さのバラツキが発生すると、半導体装置の耐圧がばらつき、デバイス特性が悪化するという問題を発生させる。 However, there is a large variation in planarization polishing of the surfaces of the p − type layer J5 and the n − type layer J2 after epitaxial growth so that the p − type layer J5 is buried in the trench J4, and the depth of the PN column varies. Therefore, the desired depth could not be obtained with high accuracy. This is due to the accuracy of the epitaxial growth itself, but the planarization polishing of the p − type layer J5 and the n − type layer J2 becomes the polishing process of the same semiconductor material (for example, silicon), and the target film thickness is polished. This is because it is difficult in principle to perform the stop. When the variation in the depth of the PN column occurs in this way, there arises a problem that the breakdown voltage of the semiconductor device varies and the device characteristics deteriorate.

また、ＳＪ構造を形成した後でＳＪ構造の上にｐ-型層Ｊ６をエピタキシャル成長させているが、ＳＪ構造の表面とｐ-型層Ｊ６との構造間の処理によって上側のｐ-型層Ｊ６が異常成長し、デバイス特性を悪化させるという問題もある。ここでいう構造間の処理とは、ＳＪ構造を形成した後で行われるＳＪ構造の表面の平坦化研磨やｐ型層の成長前のウェハ洗浄のことであり、この処理次第でｐ型層が異常成長することがある。 Further, p on the SJ structure after forming the SJ structure - but -type layer J6 are epitaxially grown, the surface of the SJ structure and p - upper by processing between the structure of the mold layer J6 of p - type layer J6 However, there is also a problem that the device characteristics are deteriorated due to abnormal growth. The treatment between structures here refers to planarization polishing of the surface of the SJ structure performed after the SJ structure is formed and wafer cleaning before the growth of the p-type layer. May grow abnormally.

本発明は上記点に鑑みて、デバイス特性の悪化を抑制できるＳＪ構造の縦型ＭＯＳＦＥＴを備えた半導体装置の製造方法を提供することを目的とする。   The present invention has been made in view of the above points, and an object of the present invention is to provide a method of manufacturing a semiconductor device including a vertical MOSFET having an SJ structure capable of suppressing deterioration of device characteristics.

上記目的を達成するため、請求項１に記載の発明では、半導体材料で構成された基板（１１）の表面（１１ａ）側に、第１導電型の第１半導体層（１２）と第２導電型の第２半導体層（１３）が形成された半導体基板（１０）を用意したのち、第２半導体層の上にマスク（１４）を配置し、該マスクを用いて第２半導体層および第１半導体層をエッチングすることで、第２半導体層を貫通して第１半導体層に達するトレンチ（１５）を形成する。そして、マスクのうちの少なくともトレンチの周辺に位置している部分を除去してから、トレンチ内を埋め込みつつ第２半導体層の上に、第２導電型の第３半導体層（１６）をエピタキシャル成長させたのち、第３半導体層をトレンチに残しつつ第３半導体層を平坦化研磨し、トレンチ内に残された第３半導体層による第２導電型カラムと第１半導体層による第１導電型カラムとが交互に繰り返されたＰＮカラムを有するＳＪ構造を形成する。その後、ＳＪ構造の上に、第２導電型のチャネル層（１７）と該チャネル層に接する第１導電型のソース領域（１８）を形成すると共に、チャネル層の表面にゲート絶縁膜（２２）を介してゲート電極（２３）を形成し、さらに半導体基板の表面側にソース領域に電気的に接続されるソース電極（２５）を形成すると共に、半導体基板の裏面側に半導体材料で構成される基板の裏面に接続されるドレイン電極（２６）を形成することで縦型ＭＯＳＦＥＴを形成することを特徴としている。
In order to achieve the above object, according to the first aspect of the present invention, the first conductive type first semiconductor layer (12) and the second conductive layer are formed on the surface (11a) side of the substrate (11) made of a semiconductor material. After preparing a semiconductor substrate (10) on which a second semiconductor layer (13) of a type is formed, a mask (14) is disposed on the second semiconductor layer, and the second semiconductor layer and the first semiconductor layer are formed using the mask. By etching the semiconductor layer, a trench (15) penetrating the second semiconductor layer and reaching the first semiconductor layer is formed. Then, after removing at least a portion of the mask located around the trench, the third semiconductor layer (16) of the second conductivity type is epitaxially grown on the second semiconductor layer while filling the trench. After that, the third semiconductor layer is planarized and polished while leaving the third semiconductor layer in the trench, and the second conductivity type column by the third semiconductor layer left in the trench and the first conductivity type column by the first semiconductor layer, Form an SJ structure with PN columns repeated alternately. Thereafter, a second conductivity type channel layer (17) and a first conductivity type source region (18) in contact with the channel layer are formed on the SJ structure, and a gate insulating film (22) is formed on the surface of the channel layer. And a source electrode (25) electrically connected to the source region on the surface side of the semiconductor substrate, and a semiconductor material on the back side of the semiconductor substrate. A vertical MOSFET is formed by forming a drain electrode (26) connected to the back surface of the substrate.

このように、第２導電型カラムを形成するためのトレンチを形成する前に予め第１半導体層の上に第２半導体層を形成しておき、その第２半導体層の表面からトレンチを形成している。そして、トレンチ内および第２半導体層の上に第２導電型カラムを形成するための第３半導体層を形成している。   Thus, before forming the trench for forming the second conductivity type column, the second semiconductor layer is formed in advance on the first semiconductor layer, and the trench is formed from the surface of the second semiconductor layer. ing. A third semiconductor layer for forming the second conductivity type column is formed in the trench and on the second semiconductor layer.

このため、ＳＪ構造を構成してから第３半導体層を形成する場合のように、ＰＮカラムの表面の平坦化研削が行われないし、ＰＮカラムの表面と第３半導体層との構造間の処理を行う必要もない。したがって、第３半導体層を平坦化研磨しても、ＰＮカラムの深さに影響を与えることはない。よって、半導体装置の耐圧がばらつくことを抑制でき、デバイス特性の悪化を抑制することが可能となる。   Therefore, as in the case where the third semiconductor layer is formed after the SJ structure is formed, the surface of the PN column is not flattened and processed between the structure of the PN column surface and the third semiconductor layer. There is no need to do. Therefore, even if the third semiconductor layer is planarized and polished, the depth of the PN column is not affected. Therefore, variation in the breakdown voltage of the semiconductor device can be suppressed, and deterioration of device characteristics can be suppressed.

請求項２に記載の発明は、半導体基板を用意する工程では、第１半導体層のうち縦型ＭＯＳＦＥＴが形成されるセル領域の周辺領域となる外周領域において凹部（１２ａ）を形成したのち、該凹部内を埋め込むように第１半導体層の上に第２半導体層を形成したものを半導体基板として用意することを特徴としている。   According to the second aspect of the present invention, in the step of preparing the semiconductor substrate, the concave portion (12a) is formed in the outer peripheral region that is the peripheral region of the cell region in which the vertical MOSFET is formed in the first semiconductor layer. A semiconductor substrate is prepared by forming a second semiconductor layer on the first semiconductor layer so as to fill the recess.

このように、第１半導体層に凹部を形成しておき、その凹部内にも第２半導体層を埋め込むようにしている。このため、第３半導体層を平坦化研磨する際に、仮に第２半導体層が除去されて第１半導体層が露出するまで研磨されたとしても、凹部内に第２半導体層を残せる。このため、外周領域において確実にリサーフ層（４０）が構成されるようにすることができる。   In this way, a recess is formed in the first semiconductor layer, and the second semiconductor layer is embedded in the recess. Therefore, when the third semiconductor layer is planarized and polished, even if the second semiconductor layer is removed and the first semiconductor layer is exposed, the second semiconductor layer can remain in the recess. For this reason, a RESURF layer (40) can be reliably comprised in an outer peripheral area | region.

なお、上記各手段の括弧内の符号は、後述する実施形態に記載の具体的手段との対応関係の一例を示すものである。   In addition, the code | symbol in the bracket | parenthesis of each said means shows an example of a corresponding relationship with the specific means as described in embodiment mentioned later.

本発明の第１実施形態にかかるＳＪ構造のトレンチゲート型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which has a trench gate type vertical MOSFET of the SJ structure concerning 1st Embodiment of this invention. 図１に続くＳＪ構造のトレンチゲート型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。FIG. 3 is a cross-sectional view showing a manufacturing process of the semiconductor device having the trench gate type vertical MOSFET of the SJ structure following FIG. 1; 本発明の第２実施形態にかかるＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which has the planar type | mold vertical MOSFET of SJ structure concerning 2nd Embodiment of this invention. 本発明の第３実施形態にかかるＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which has the planar type | mold vertical MOSFET of SJ structure concerning 3rd Embodiment of this invention. 図４に続くＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。FIG. 5 is a cross-sectional view showing a manufacturing process of the semiconductor device having the planar vertical MOSFET having the SJ structure following FIG. 4. 図５に続くＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。FIG. 6 is a cross-sectional view showing a manufacturing process of the semiconductor device having the planar vertical MOSFET having the SJ structure following FIG. 5; 図６（ａ）に示す平坦化研磨において、ｎ-型層１２が露出する程度までｐ-型層１３およびｐ-型層１６が除去されたときの様子を示した断面図である。FIG. 7 is a cross-sectional view showing a state when the p − -type layer 13 and the p − -type layer 16 are removed to the extent that the n − -type layer 12 is exposed in the planarization polishing shown in FIG. 他の実施形態にかかるＳＪ構造のトレンチゲート型の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which has the trench gate type vertical MOSFET of the SJ structure concerning other embodiment. 従来のＳＪ構造のトレンチゲート構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。It is sectional drawing which shows the manufacturing process of the semiconductor device which has the vertical MOSFET of the trench gate structure of the conventional SJ structure. 図９に続くＳＪ構造のトレンチゲート構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造工程を示す断面図である。FIG. 10 is a cross-sectional view showing a manufacturing step of the semiconductor device having the vertical MOSFET of the trench gate structure of the SJ structure following FIG. 9.

以下、本発明の実施形態について図に基づいて説明する。なお、以下の各実施形態相互において、互いに同一もしくは均等である部分には、同一符号を付して説明を行う。   Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

（第１実施形態）
本発明の第１実施形態にかかる半導体装置の製造方法について、図１および図２を参照して説明する。なお、ここではＳＪ構造の縦型ＭＯＳＦＥＴとして、トレンチゲート型の縦型ＭＯＳＦＥＴを備えた半導体装置を例に挙げて説明する。 (First embodiment)
A method of manufacturing a semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. Here, a semiconductor device including a trench gate type vertical MOSFET will be described as an example of the vertical MOSFET having the SJ structure.

〔図１（ａ）に示す工程〕
表面１１ａおよび裏面１１ｂを有する半導体材料で構成された基板としてのｎ+型シリコン基板１１の表面１１ａに、第１半導体層に相当するｎ-型層１２と第２半導体層に相当するｐ-型層１３をエピタキシャル成長させた半導体基板１０を用意する。ｎ+型シリコン基板１１は、ドレイン領域として機能する部分であり、ｎ-型層１２よりもｎ型不純物濃度が高くされている。ｎ-型層１２は、ドリフト層として機能と共にＰＮカラムにおけるｎ型カラムを構成する部分である。ｐ-型層１３は、チャネル形成や図示しないが外周での耐圧構造を構成するためのものであり、例えば３〜７μｍの厚みとされている。 [Step shown in FIG. 1 (a)]
An n − type layer 12 corresponding to the first semiconductor layer and a p − type corresponding to the second semiconductor layer are formed on the surface 11a of the n + type silicon substrate 11 as a substrate made of a semiconductor material having the front surface 11a and the back surface 11b. A semiconductor substrate 10 on which the layer 13 is epitaxially grown is prepared. The n + type silicon substrate 11 functions as a drain region, and has an n type impurity concentration higher than that of the n − type layer 12. The n − type layer 12 functions as a drift layer and constitutes an n type column in the PN column. The p − -type layer 13 is for forming a channel or a breakdown voltage structure on the outer periphery (not shown), and has a thickness of 3 to 7 μm, for example.

〔図１（ｂ）に示す工程〕
半導体基板１０の表面側において、ｐ-型層１３を覆うようにＣＶＤ（Chemical Vapor Deposition）法や熱酸化などによって酸化膜１４を０．２〜０．３μｍの厚みで形成する。その後、酸化膜１４の上に図示しないレジストを配置し、フォトエッチング工程を経てトレンチ形成予定位置においてレジストを開口させると共にその開口位置において酸化膜１４を開口させる。そして、レジストを除去し、酸化膜１４をマスクとして、ＲＩＥ（Reactive Ion Etching）法や、Ｏ2とＣ4Ｆ8およびＳＦ6を交互に繰り返し導入して底部エッチングおよびポリマー膜による側壁保護を繰り返し行うＢＯＳＣＨ法などの異方性エッチングを行う。具体的には、ｐ-型層１３を貫通してｎ-型層１２を所定深さ、例えばｎ-型層１２の厚みと同等もしくはそれよりも若干浅くエッチングする。これにより、ｎ-型層１２の所望位置にＳＪ構造形成用の例えばストライプ状とされたトレンチ１５が形成される。 [Step shown in FIG. 1B]
On the surface side of the semiconductor substrate 10, an oxide film 14 having a thickness of 0.2 to 0.3 μm is formed by a CVD (Chemical Vapor Deposition) method or thermal oxidation so as to cover the p − -type layer 13. Thereafter, a resist (not shown) is disposed on the oxide film 14, and the resist is opened at a position where a trench is to be formed through a photoetching process, and the oxide film 14 is opened at the opening position. Then, the resist is removed, and using the oxide film 14 as a mask, the RIE (Reactive Ion Etching) method and O 2 , C 4 F 8 and SF 6 are alternately introduced repeatedly to repeatedly perform bottom etching and side wall protection with a polymer film. An anisotropic etching such as a BOSCH method is performed. Specifically, the n − -type layer 12 is etched through the p − -type layer 13 to a predetermined depth, for example, equal to or slightly shallower than the thickness of the n − -type layer 12. Thus, for example, a stripe-shaped trench 15 for forming the SJ structure is formed at a desired position of the n − -type layer 12.

〔図１（ｃ）に示す工程〕
酸化膜１４のうちトレンチ１５から離れた位置に形成されている部分については残し、トレンチ１５の開口部周辺に配置されている部分については除去する。 [Step shown in FIG. 1 (c)]
A portion of the oxide film 14 formed at a position away from the trench 15 is left, and a portion disposed around the opening of the trench 15 is removed.

例えば、酸化膜１４の上に再びレジストを配置したのち、半導体基板１０のうち縦型ＭＯＳＦＥＴなどを形成してチップとして利用するメイン領域においてレジストを開口させる。そして、アライメントのターゲットを形成する領域であってダイシング時にカットされるスクライブ領域をレジストで覆った状態でエッチングすることで、酸化膜１４をパターニングする。または、水素アニールを行うことで、酸化膜１４のうちトレンチ１５の開口部周辺に形成された部分を後退させる。例えば、１０．６ｋＰａ（８０Ｔｏｒｒ）以下の減圧雰囲気において、温度を１１００℃とし時間を１０分間とした水素アニールや、温度を１１７０℃とし時間を２分間とした水素アニールを行うことで、酸化膜１４のうちのトレンチ１５の開口部周辺を除去できる。   For example, after a resist is again arranged on the oxide film 14, a vertical MOSFET or the like is formed in the semiconductor substrate 10, and the resist is opened in a main region used as a chip. Then, the oxide film 14 is patterned by etching in a state where a scribe region which is a region where an alignment target is formed and which is cut during dicing is covered with a resist. Alternatively, a portion of the oxide film 14 formed around the opening of the trench 15 is retreated by performing hydrogen annealing. For example, in a reduced pressure atmosphere of 10.6 kPa (80 Torr) or less, hydrogen annealing is performed at a temperature of 1100 ° C. and a time of 10 minutes, or a hydrogen annealing at a temperature of 1170 ° C. and a time of 2 minutes. The periphery of the opening of the trench 15 can be removed.

その後、半導体基板１０の表面側において、トレンチ１５内を含めｐ-型層１３の表面に、例えばｐ型不純物濃度が２×１０15〜５×１０15ｃｍ-3となるように第３半導体層に相当するｐ-型層１６をエピタキシャル成長させる。このとき、各トレンチ１５内が完全に埋め込まれるようにしつつ、ｐ-型層１３の上にもｐ-型層１６が形成されるようなオーバーエピタキシャル成長とし、例えばｐ-型層１３の上に５〜７μｍ程度の厚みでｐ-型層１６を形成する。 Thereafter, on the surface side of the semiconductor substrate 10, the third semiconductor layer is formed on the surface of the p − -type layer 13 including the inside of the trench 15 so that the p-type impurity concentration is 2 × 10 15 to 5 × 10 15 cm −3 , for example. A p − -type layer 16 corresponding to is epitaxially grown. At this time, while as each trench 15 is completely filled, p - also on the p type layer 13 - and over epitaxial growth, such as type layer 16 is formed, for example, p - on the type layer 13 5 The p − -type layer 16 is formed with a thickness of about ˜7 μm.

〔図２（ａ）に示す工程〕
まず、ｐ-型層１６のうち酸化膜１４よりも半導体基板１０から突き出した部分をＣＭＰ（Chemical Mechanical Polishing）などの表面の平坦化研磨によって除去する。このときには、研磨対象となるｐ-型層１６と異なる酸化膜１４を終点検出用のストッパとして用いることができるため、精度良く平坦化研磨を停止できる。 [Step shown in FIG. 2 (a)]
First, a portion of the p − -type layer 16 protruding from the semiconductor substrate 10 rather than the oxide film 14 is removed by planarization polishing of the surface such as CMP (Chemical Mechanical Polishing). At this time, since the oxide film 14 different from the p − type layer 16 to be polished can be used as a stopper for detecting the end point, the planarization polishing can be stopped with high accuracy.

続いて、酸化膜１４をエッチングする。これにより、スクライブ領域やメイン領域におけるスクライブ領域の近傍において酸化膜１４が除去されて、露出したｐ-型層１３とｐ-型層１６との間に段差が形成される。このため、再度ＣＭＰなどによる表面の平坦化研磨を行うことで、当該段差が無くなるようにｐ-型層１３およびｐ-型層１６を平坦化研磨する。これにより、ＳＪ構造を構成するｐ型カラムおよびＳＪ構造の上にｐ-型層１３が既に形成された構造が完成する。 Subsequently, the oxide film 14 is etched. As a result, the oxide film 14 is removed in the vicinity of the scribe region in the scribe region or the main region, and a step is formed between the exposed p − -type layer 13 and the p − -type layer 16. For this reason, the p − -type layer 13 and the p − -type layer 16 are flattened and polished so that the level difference is eliminated by performing planarization polishing of the surface again by CMP or the like. As a result, a p-type column constituting the SJ structure and a structure in which the p − -type layer 13 is already formed on the SJ structure are completed.

なお、この表面平坦化の際に、ｐ-型層１３およびｐ-型層１６という同じ半導体材料（シリコン）の研磨加工となるため、表面平坦化のストッパとなるものが無い。しかしながら、酸化膜１４の膜厚が０．２〜０．３μｍと非常に薄いため、ストッパが無くても時間制御などだけで大きなバラツキなく平坦化研磨が行える。また、ＰＮカラムの表面とｐ-型層１３との構造間の処理を行う訳ではないので、仮に多少のバラツキがあったとしても、半導体装置の耐圧が大きくばらつくことも無い。 In addition, since the same semiconductor material (silicon) as the p − type layer 13 and the p − type layer 16 is polished during the surface flattening, there is no stopper for the surface flattening. However, since the oxide film 14 has a very thin film thickness of 0.2 to 0.3 [mu] m, even if there is no stopper, flattening polishing can be performed without much variation only by time control or the like. Further, since the process between the surface of the PN column and the p − type layer 13 is not performed, even if there is some variation, the breakdown voltage of the semiconductor device does not vary greatly.

〔図２（ｂ）に示す工程〕
この後の工程については従来と同様であるが、例えば以下の製造工程を行っている。すなわち、ｎ型カラムを構成するｎ-型層１２の上におけるｐ-型層１３の表層部にｐ型不純物をイオン注入してｐ-型チャネル層１７を形成する。また、ｐ-型チャネル層１７の表層部にｎ型不純物をイオン注入してｎ+型ソース領域１８を形成する。また、ｐ-型チャネル層１７のうちのｐ-型層１６の上に形成された部分を中心としてｐ型不純物をイオン注入することでｐ+型ボディ層１９を形成すると共に、このｐ+型ボディ層１９の表層部にｐ+型コンタクト領域２０を形成する。また、ｐ-型チャネル層１７を貫通してｎ-型層１２のうちｎ型カラムを構成する部分に達するゲートトレンチ２１を形成する。さらに、ゲートトレンチ２１の内壁面を覆うようにゲート絶縁膜２２を形成すると共に、ゲートトレンチ２１内を埋め込むようにゲート絶縁膜２２上にゲート電極２３を形成する。また、半導体基板１０の表面側において、層間絶縁膜２４の形成工程やゲート配線およびソース電極２５の形成工程を行う。そして、半導体基板１０の裏面側において、ｎ+型シリコン基板１１の裏面１１ｂに接続されるドレイン電極２６の形成工程を行うことにより、ｎチャネルのトレンチゲート型の縦型ＭＯＳＦＥＴが形成される。その後、ダイシングによりチップ単位に分割することでＳＪ構造の縦型ＭＯＳＦＥＴを備えた半導体装置が完成する。 [Step shown in FIG. 2 (b)]
The subsequent steps are the same as in the prior art, but the following manufacturing steps are performed, for example. That is, the p − type channel layer 17 is formed by ion implantation of p type impurities into the surface layer portion of the p − type layer 13 on the n − type layer 12 constituting the n type column. Further, an n + type source region 18 is formed by ion implantation of n type impurities into the surface layer portion of the p − type channel layer 17. In addition, a p + type body layer 19 is formed by ion-implanting a p type impurity around the portion of the p − type channel layer 17 formed on the p − type layer 16, and this p + type A p + -type contact region 20 is formed in the surface layer portion of the body layer 19. In addition, a gate trench 21 that penetrates the p − -type channel layer 17 and reaches a portion of the n − -type layer 12 constituting the n-type column is formed. Further, the gate insulating film 22 is formed so as to cover the inner wall surface of the gate trench 21, and the gate electrode 23 is formed on the gate insulating film 22 so as to fill the gate trench 21. Further, on the surface side of the semiconductor substrate 10, an interlayer insulating film 24 forming process and a gate wiring and source electrode 25 forming process are performed. Then, on the back side of the semiconductor substrate 10, a drain electrode 26 connected to the back surface 11 b of the n + -type silicon substrate 11 is formed, whereby an n-channel trench gate type vertical MOSFET is formed. Thereafter, the semiconductor device including the vertical MOSFET having the SJ structure is completed by dividing into chips by dicing.

以上説明した本実施形態にかかる半導体装置の製造方法によれば、ｐ型カラムを形成するためのトレンチ１５を形成する前に予めｎ-型層１２の上にｐ-型層１３を形成しておき、そのｐ-型層１３の表面からトレンチ１５を形成している。そして、トレンチ１５内およびｐ-型層１３の上にｐ型カラムを形成するためのｐ-型層１６を形成している。 According to the manufacturing method of the semiconductor device according to the present embodiment described above, the p − -type layer 13 is formed on the n − -type layer 12 in advance before forming the trench 15 for forming the p-type column. The trench 15 is formed from the surface of the p − type layer 13. A p − type layer 16 for forming a p type column is formed in the trench 15 and on the p − type layer 13.

このため、ＳＪ構造を構成してからｐ-型層１３を形成する場合のように、ＰＮカラムの表面の平坦化研磨が行われないし、平坦化研磨やウェハ洗浄などのＰＮカラムの表面とｐ-型層１３との構造間の処理を行う必要がない。したがって、ｐ-型層１６を平坦化研磨しても、ＰＮカラムの深さに影響を与えることはない。よって、半導体装置の耐圧がばらつくことを抑制でき、デバイス特性の悪化を抑制することが可能となる。 Therefore, as in the case where the p − type layer 13 is formed after the SJ structure is formed, the surface of the PN column is not flattened, and the surface of the PN column such as flattening polishing or wafer cleaning and the p - there is no need to perform processing between the structure of the mold layer 13. Therefore, even if the p − -type layer 16 is planarized and polished, the depth of the PN column is not affected. Therefore, variation in the breakdown voltage of the semiconductor device can be suppressed, and deterioration of device characteristics can be suppressed.

（第２実施形態）
本発明の第２実施形態について説明する。本実施形態は、第１実施形態に対して半導体装置に形成される縦型ＭＯＳＦＥＴをプレーナ型に変更したものであり、その他については第１実施形態と同様であるため、第１実施形態と異なる部分についてのみ説明する。 (Second Embodiment)
A second embodiment of the present invention will be described. This embodiment is different from the first embodiment in that the vertical MOSFET formed in the semiconductor device is changed to a planar type with respect to the first embodiment, and the others are the same as the first embodiment. Only the part will be described.

図３を参照して、本実施形態にかかる縦型ＭＯＳＦＥＴの製造方法について説明する。   With reference to FIG. 3, the manufacturing method of the vertical MOSFET concerning this embodiment is demonstrated.

まず、第１実施形態で説明した図１（ａ）〜（ｃ）と同様の工程を行った後、図３（ａ）の工程において、第１実施形態で説明した図２（ａ）と同様の工程を行う。これにより、ＳＪ構造を構成するｐ型カラムおよびＳＪ構造の上にｐ-型層１３が既に形成された構造が形成される。これらの工程は基本的に第１実施形態と全く同じで構わない。ただし、ｐ-型層１３の膜厚については、後述するｎ型接続層３０をイオン注入によって形成する際に、ｐ-型層１３を貫通してｎ型接続層３０が形成できる程度の膜厚となるようにしている。 First, after performing the same processes as in FIGS. 1A to 1C described in the first embodiment, the process in FIG. 3A is similar to that in FIG. 2A described in the first embodiment. The process is performed. As a result, a p-type column constituting the SJ structure and a structure in which the p − -type layer 13 is already formed on the SJ structure are formed. These steps may be basically the same as those in the first embodiment. However, p - the thickness of the mold layer 13, when forming the n-type contact layer 30 to be described later by ion implantation, p - thickness such that type layer 13 n-type contact layer 30 through the can be formed It is trying to become.

そして、図３（ｂ）に示す工程において、プレーナ型の縦型ＭＯＳＦＥＴの各構成要素を形成するための製造工程を行う。   Then, in the process shown in FIG. 3B, a manufacturing process for forming each component of the planar type vertical MOSFET is performed.

すなわち、ｐ-型層１３の表層部にｐ型不純物をイオン注入してｐ-型チャネル層１７を形成すると共に、ｐ-型チャネル層１７の表層部にｎ型不純物をイオン注入してｎ+型ソース領域１８を形成する。また、ｐ-型チャネル層１７のうちｐ-型層１６の上に形成された部分を中心としてｐ型不純物をイオン注入することでｐ+型ボディ層１９を形成すると共に、このｐ+型ボディ層１９の表層部にｐ+型コンタクト領域２０を形成する。さらに、各ｐ+型コンタクト領域２０の間に配置された隣り合うｎ+型ソース領域１８の間において、ｎ+型ソース領域１８から所定間隔離間した位置にｎ型不純物をイオン注入することで、ｐ-型チャネル層１７からｎ-型層１２に達するｎ型接続層３０を形成する。このｎ型接続層３０は、ｐ-型チャネル層１７におけるチャネル形成部に接しつつｐ-型層１３を貫通してｎ-型層１２のうちのｎ型カラムを構成する部分に達するように形成される。このため、ｎ型接続層３０は、プレーナ型の縦型ＭＯＳＦＥＴが動作する際の電流経路となってオン抵抗を低減させる役割を果たす。 That is, p-type impurities are ion-implanted into the surface layer portion of the p − -type layer 13 to form the p − -type channel layer 17, and n-type impurities are ion-implanted into the surface layer portion of the p − -type channel layer 17 to form n + A mold source region 18 is formed. Further, a p + type body layer 19 is formed by ion implantation of p type impurities centering on a portion of the p − type channel layer 17 formed on the p − type layer 16, and this p + type body is also formed. A p + -type contact region 20 is formed in the surface layer portion of the layer 19. Further, n-type impurities are ion-implanted at a predetermined distance from the n + -type source region 18 between adjacent n + -type source regions 18 arranged between the p + -type contact regions 20, An n-type connection layer 30 reaching the n − -type layer 12 from the p − -type channel layer 17 is formed. This n-type connection layer 30 is formed so as to reach the portion of the n − -type layer 12 that constitutes the n-type column through the p − -type layer 13 while being in contact with the channel forming portion in the p − -type channel layer 17. Is done. For this reason, the n-type connection layer 30 serves as a current path when the planar vertical MOSFET operates, and plays a role of reducing the on-resistance.

さらに、少なくともｐ-型チャネル層１７の表面を覆うゲート絶縁膜２２を形成すると共に、ゲート絶縁膜２２上にゲート電極２３を形成する。また、半導体基板１０の表面側において、層間絶縁膜２４の形成工程やゲート配線およびソース電極２５の形成工程を行う。そして、半導体基板１０の裏面側において、ｎ+型シリコン基板１１の裏面１１ｂに接続されるドレイン電極２６の形成工程を行うことにより、ｎチャネルのプレーナ型の縦型ＭＯＳＦＥＴが形成される。その後、ダイシングによりチップ単位に分割することでＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを備えた半導体装置が完成する。 Further, a gate insulating film 22 that covers at least the surface of the p − -type channel layer 17 is formed, and a gate electrode 23 is formed on the gate insulating film 22. Further, on the surface side of the semiconductor substrate 10, an interlayer insulating film 24 forming process and a gate wiring and source electrode 25 forming process are performed. Then, on the back surface side of the semiconductor substrate 10, an n-channel planar vertical MOSFET is formed by performing a process of forming the drain electrode 26 connected to the back surface 11 b of the n + -type silicon substrate 11. Thereafter, the semiconductor device including the planar type vertical MOSFET having the SJ structure is completed by dividing into chips by dicing.

このように、第１実施形態と同様の製造方法をプレーナ型の縦型ＭＯＳＦＥＴを備えた半導体装置についても適用することができ、第１実施形態と同様の効果を得ることができる。   As described above, the same manufacturing method as that of the first embodiment can be applied to the semiconductor device including the planar type vertical MOSFET, and the same effect as that of the first embodiment can be obtained.

（第３実施形態）
本発明の第３実施形態について説明する。本実施形態は、第２実施形態に対して半導体装置の外周耐圧構造を考慮に入れた製造方法としたものであり、その他については第２実施形態と同様であるため、第２実施形態と異なる部分についてのみ説明する。 (Third embodiment)
A third embodiment of the present invention will be described. The present embodiment is a manufacturing method that takes into account the peripheral breakdown voltage structure of the semiconductor device with respect to the second embodiment, and is otherwise the same as the second embodiment, and is different from the second embodiment. Only the part will be described.

図４〜図６を参照して、本実施形態にかかる縦型ＭＯＳＦＥＴの製造方法、つまりＳＪ構造を有するプレーナ型の縦型ＭＯＳＦＥＴを備えた半導体装置において、外周耐圧構造の形成工程も含めた製造方法について説明する。   4 to 6, the vertical MOSFET manufacturing method according to the present embodiment, that is, the semiconductor device including the planar vertical MOSFET having the SJ structure, including the step of forming the outer peripheral withstand voltage structure. A method will be described.

まず、図４（ａ）に示す工程では、表面１１ａおよび裏面１１ｂを有する半導体材料で構成された基板としてのｎ+型シリコン基板１１の表面１１ａに、第１半導体層に相当するｎ-型層１２をエピタキシャル成長させたものを用意する。そして、図示しないマスクを用いたフォトエッチング工程により、ｎ-型層１２のうち外周領域に相当する部分に凹部１２ａを形成する。具体的には、縦型ＭＯＳＦＥＴが形成される領域をセル領域として、その外周領域においてリサーフ層を形成することによって外周耐圧構造とするが、このリサーフ層となる部分において凹部１２ａを形成している。 First, in the step shown in FIG. 4A, an n − -type layer corresponding to the first semiconductor layer is formed on the surface 11a of an n + -type silicon substrate 11 as a substrate made of a semiconductor material having a front surface 11a and a back surface 11b. 12 is prepared by epitaxial growth. Then, a recess 12a is formed in a portion corresponding to the outer peripheral region of the n − type layer 12 by a photoetching process using a mask (not shown). Specifically, a region where the vertical MOSFET is formed is a cell region, and a RESURF layer is formed in the outer peripheral region to form an outer peripheral withstand voltage structure. However, a concave portion 12a is formed in a portion serving as the RESURF layer. .

その後、図４（ｂ）に示す工程では、凹部１２ａ内を埋め込むようにｎ-型層１２の表面にｐ-型層１３をエピタキシャル成長させ、必要に応じて表面を平坦化研磨する。このとき、例えばｎ-型層１２の表面にｐ-型層１３が３〜７μｍの膜厚で残るようにしている。これにより、凹部１２ａ内において凹部１２ａが形成されていない部分よりもｐ-型層１３が厚くされた半導体基板１０が形成される。 Thereafter, in the step shown in FIG. 4B, the p − type layer 13 is epitaxially grown on the surface of the n − type layer 12 so as to fill the recess 12a, and the surface is planarized and polished as necessary. At this time, for example, the p − type layer 13 remains on the surface of the n − type layer 12 with a film thickness of 3 to 7 μm. As a result, the semiconductor substrate 10 is formed in which the p − type layer 13 is thicker than the portion of the recess 12a where the recess 12a is not formed.

この後は、図５（ａ）、（ｂ）、図６（ａ）、（ｂ）に示す工程において、第１実施形態で説明した図１（ｂ）、（ｃ）および第２実施形態で説明した図３（ａ）、（ｂ）と同様の工程を行う。これにより、外周耐圧構造として、セル領域よりも外周領域において、ｐ-型層１６が深くまで形成されることでリサーフ層４０が構成されたＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを備えた半導体装置が完成する。 Thereafter, in the steps shown in FIGS. 5A, 5B, 6A, and 6B, the steps shown in FIGS. 1B, 1C, and 2 described in the first embodiment are used. The same steps as described in FIGS. 3A and 3B are performed. Thereby, as a peripheral breakdown voltage structure, a semiconductor device provided with a planar vertical MOSFET of SJ structure in which the RESURF layer 40 is formed by forming the p − -type layer 16 deeper in the peripheral region than in the cell region. Is completed.

このように、外周耐圧構造としてリサーフ層を形成する場合を考慮した製造方法とすることもできる。このようにしても、第２実施形態と同様の効果を得ることができる。   Thus, it can also be set as the manufacturing method which considered the case where a RESURF layer is formed as an outer periphery pressure | voltage resistant structure. Even if it does in this way, the effect similar to 2nd Embodiment can be acquired.

なお、第２実施形態でも、ｐ-型層１３を外周領域にも形成しているため、凹部１２ａを形成しなくても、第２実施形態に示した製造方法によって外周領域にリサーフ層４０を構成することができる。しかしながら、図６（ａ）に示すｐ-型層１３およびｐ-型層１６の表面の平坦化研磨を行ったときに、例えば、図７（ａ）に示すように、ｎ-型層１２が露出する程度までｐ-型層１３およびｐ-型層１６が除去されてしまうことも有り得る。その場合においても、図７（ｂ）に示すように、図６（ｂ）と同様の工程を行うことで、ＳＪ構造のプレーナ型の縦型ＭＯＳＦＥＴを備えた半導体装置を製造することができる。その場合、外周領域にｐ-型層１６が残らなくなりリサーフ層４０を構成することができなくなる。このため、本実施形態のようにｎ-型層１２に凹部１２ａを形成しておき、予め外周領域においてセル領域よりもｐ-型層１３を厚く形成しておくことで、確実にリサーフ層４０が構成されるようにすることができる。 In the second embodiment, since the p − -type layer 13 is also formed in the outer peripheral region, the RESURF layer 40 is formed in the outer peripheral region by the manufacturing method shown in the second embodiment without forming the recess 12a. Can be configured. However, p shown in FIG. 6 (a) - when subjected to flattening polishing of the surface of the mold layer 16, for example, as shown in FIG. 7 (a), n - - -type layer 13 and the p -type layer 12 is The p − type layer 13 and the p − type layer 16 may be removed to the extent that they are exposed. Even in such a case, as shown in FIG. 7B, a semiconductor device including a planar vertical MOSFET having an SJ structure can be manufactured by performing the same process as in FIG. 6B. In that case, the p − -type layer 16 does not remain in the outer peripheral region, and the RESURF layer 40 cannot be formed. Therefore, the recess 12a is formed in the n − -type layer 12 as in the present embodiment, and the p − -type layer 13 is formed thicker than the cell region in the outer peripheral region in advance, so that the RESURF layer 40 is surely formed. Can be configured.

また、ｎ-型層１２の表面が露出する程度まで平坦化研磨を行った場合、ｎ-型層１２も研磨され得るのでＰＮカラムの深さにバラツキが生じる可能性がある。しかしながら、ｎ型接続層３０によって低オン抵抗化が図れるため、ｐ-型層１３が残るような条件で平坦化研磨を行えば良く、従来のようにｎ-型層１２を露出させることが必須の構成ではない。このため、仮にｎ-型層１２が研磨されたとしても研磨量は非常に少なく、殆どＰＮカラムの深さのバラツキによる耐圧バラツキは生じないで済む。 Further, when planarization polishing is performed to such an extent that the surface of the n − -type layer 12 is exposed, the n − -type layer 12 can also be polished, so that the PN column depth may vary. However, since the on-resistance can be reduced by the n-type connection layer 30, planarization polishing may be performed under the condition that the p − -type layer 13 remains, and it is essential to expose the n − -type layer 12 as in the prior art. It is not a configuration of. For this reason, even if the n − -type layer 12 is polished, the amount of polishing is very small, and there is almost no variation in pressure resistance due to variations in the depth of the PN column.

（他の実施形態）
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。 (Other embodiments)
The present invention is not limited to the embodiment described above, and can be appropriately changed within the scope described in the claims.

例えば、上記第３実施形態に示すように外周耐圧構造を考慮に入れた製造方法を第１実施形態に示したようなトレンチゲート型の縦型ＭＯＳＦＥＴを備えた半導体装置の製造方法に適用することもできる。具体的には、第３実施形態で説明した図３（ａ）、（ｂ）、図４（ａ）、（ｂ）および図５（ａ）と同様の工程を行ったのち、第１実施形態で説明した図２（ｂ）と同様の工程を行うことで、図８に示すようなトレンチゲート型の縦型ＭＯＳＦＥＴとする。このように、トレンチゲート型の縦型ＭＯＳＦＥＴを備えた半導体装置を製造する際にも、ｎ-型層１２に予め凹部１２ａを形成しておくことで、平坦化研磨後にも少なくとも凹部１２ａ内にｐ-型層１３が残る。これにより、リサーフ層４０が構成されるようにでき、第３実施形態と同様の効果を得ることができる。 For example, as shown in the third embodiment, the manufacturing method taking into account the peripheral withstand voltage structure is applied to the manufacturing method of the semiconductor device including the trench gate type vertical MOSFET as shown in the first embodiment. You can also. Specifically, after performing the same steps as in FIGS. 3A, 3B, 4A, 4B and 5A described in the third embodiment, the first embodiment is performed. A trench gate type vertical MOSFET as shown in FIG. 8 is obtained by performing the same process as that shown in FIG. As described above, also in manufacturing a semiconductor device including a trench gate type vertical MOSFET, by forming the recess 12a in the n − type layer 12 in advance, at least in the recess 12a even after the planarization polishing. The p − type layer 13 remains. Thereby, the RESURF layer 40 can be comprised and the effect similar to 3rd Embodiment can be acquired.

また、上記各実施形態では、第１導電型をｎ型、第２導電型をｐ型としたｎチャネルタイプのＭＯＳＦＥＴを例に挙げて説明したが、各構成要素の導電型を反転させたｐチャネルタイプのＭＯＳＦＥＴに対しても本発明を適用することができる。   In each of the above-described embodiments, an n-channel type MOSFET in which the first conductivity type is n-type and the second conductivity type is p-type has been described as an example. The present invention can also be applied to a channel type MOSFET.

１０ 半導体基板
１１ ｎ+型シリコン基板（基板）
１２ ｎ-型層（第１半導体層）
１２ａ 凹部
１３、１６ ｐ-型層（第２半導体層、第３半導体層）
１４ 酸化膜（マスク）
１５ トレンチ
１７ ｐ型チャネル層
１８ ｎ+型ソース領域
２３ ゲート電極
２５ ソース電極
２６ ドレイン電極
３０ ｎ型接続層 10 Semiconductor substrate 11 n + type silicon substrate (substrate)
12 n - -type layer (first semiconductor layer)
12a recesses 13, 16 p - -type layer (a second semiconductor layer, the third semiconductor layer)
14 Oxide film (mask)
15 trench 17 p-type channel layer 18 n + type source region 23 gate electrode 25 source electrode 26 drain electrode 30 n-type connection layer

Claims (4)

半導体材料で構成された基板（１１）の表面（１１ａ）側に、第１導電型の第１半導体層（１２）が形成されると共に該第１半導体層（１２）の上に第２導電型の第２半導体層（１３）が形成された半導体基板（１０）を用意する工程と、
前記第２半導体層の上にマスク（１４）を配置し、該マスクを用いて前記第２半導体層および前記第１半導体層をエッチングすることで、前記第２半導体層を貫通して前記第１半導体層に達するトレンチ（１５）を形成する工程と、
前記マスクのうちの少なくとも前記トレンチの周辺に位置している部分を除去したのち、前記トレンチ内を埋め込みつつ前記第２半導体層の上に、第２導電型の第３半導体層（１６）をエピタキシャル成長させる工程と、
前記第３半導体層を平坦化研磨し、前記第３半導体層を前記トレンチに残しつつ前記第２半導体層を露出させ、前記トレンチ内に残された前記第３半導体層による第２導電型カラムと前記第１半導体層による第１導電型カラムとが交互に繰り返されたＰＮカラムを有するスーパージャンクション構造を形成する工程と、
前記スーパージャンクション構造の上に、第２導電型のチャネル層（１７）と該チャネル層に接する第１導電型のソース領域（１８）を形成すると共に、前記チャネル層の表面にゲート絶縁膜（２２）を介してゲート電極（２３）を形成し、さらに前記半導体基板の表面側に前記ソース領域に電気的に接続されるソース電極（２５）を形成すると共に、前記半導体基板の裏面側に前記基板の裏面に接続されるドレイン電極（２６）を形成することで縦型ＭＯＳＦＥＴを形成する工程と、を含んでいることを特徴とするスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。 A first semiconductor layer (12) of the first conductivity type is formed on the surface (11a) side of the substrate (11) made of a semiconductor material, and the second conductivity type is formed on the first semiconductor layer (12). Preparing a semiconductor substrate (10) on which the second semiconductor layer (13) is formed;
A mask (14) is disposed on the second semiconductor layer, and the second semiconductor layer and the first semiconductor layer are etched using the mask, thereby penetrating the second semiconductor layer and the first semiconductor layer. Forming a trench (15) reaching the semiconductor layer;
After removing at least a portion of the mask located around the trench, a third semiconductor layer (16) of the second conductivity type is epitaxially grown on the second semiconductor layer while filling the trench. A process of
Planarizing and polishing the third semiconductor layer, exposing the second semiconductor layer while leaving the third semiconductor layer in the trench, and a second conductivity type column formed by the third semiconductor layer remaining in the trench; Forming a super junction structure having a PN column in which the first conductivity type column by the first semiconductor layer is alternately repeated;
A second conductivity type channel layer (17) and a first conductivity type source region (18) in contact with the channel layer are formed on the super junction structure, and a gate insulating film (22) is formed on the surface of the channel layer. ), A source electrode (25) electrically connected to the source region is formed on the front surface side of the semiconductor substrate, and the substrate is formed on the back surface side of the semiconductor substrate. Forming a vertical MOSFET by forming a drain electrode (26) connected to the back surface of the semiconductor device. A method of manufacturing a semiconductor device having a vertical MOSFET having a super junction structure. 前記半導体基板を用意する工程では、
前記第１半導体層のうち前記縦型ＭＯＳＦＥＴが形成されるセル領域の周辺領域となる外周領域において凹部（１２ａ）を形成したのち、該凹部内を埋め込むように前記第１半導体層の上に前記第２半導体層を形成したものを前記半導体基板として用意することを特徴とする請求項１に記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。 In the step of preparing the semiconductor substrate,
A recess (12a) is formed in an outer peripheral region that is a peripheral region of a cell region in which the vertical MOSFET is formed in the first semiconductor layer, and then the first semiconductor layer is formed on the first semiconductor layer so as to be embedded in the recess. 2. The method of manufacturing a semiconductor device having a vertical MOSFET having a super junction structure according to claim 1, wherein a semiconductor substrate on which a second semiconductor layer is formed is prepared as the semiconductor substrate. 前記縦型ＭＯＳＦＥＴを形成する工程は、
前記第１半導体層にて構成される第１導電型カラムの上において、第２導電型不純物をイオン注入して前記チャネル層を形成する工程と、
前記チャネル層の表層部に第１導電型不純物をイオン注入して前記ソース領域を形成する工程と、
前記チャネル層を貫通して前記第１導電型カラムに達するゲートトレンチ（２１）を形成する工程と、
前記ゲートトレンチの内壁面に前記ゲート絶縁膜を形成すると共に、前記ゲート絶縁膜の表面に前記ゲート電極を形成する工程と、を含む、トレンチゲート型の縦型ＭＯＳＦＥＴを形成する工程であることを特徴とする請求項１または２に記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。 The step of forming the vertical MOSFET includes:
Forming a channel layer by ion-implanting a second conductivity type impurity on a first conductivity type column composed of the first semiconductor layer;
Forming a source region by ion-implanting a first conductivity type impurity into a surface layer portion of the channel layer;
Forming a gate trench (21) passing through the channel layer and reaching the first conductivity type column;
Forming the gate insulating film on the inner wall surface of the gate trench and forming the gate electrode on the surface of the gate insulating film, and forming a trench gate type vertical MOSFET. 3. A method of manufacturing a semiconductor device having a vertical MOSFET having a super junction structure according to claim 1 or 2. 前記縦型ＭＯＳＦＥＴを形成する工程は、
前記第１半導体層にて構成される第１導電型カラムの上において、第２導電型不純物をイオン注入して前記チャネル層を形成する工程と、
前記チャネル層の表層部に第１導電型不純物をイオン注入して前記ソース領域を形成する工程と、
前記ソース領域から所定間隔離間した位置に第１導電型不純物をイオン注入して、前記チャネル層から前記第１半導体層に達する第１導電型接続層（３０）を形成する工程と、
前記チャネル層の表面に前記ゲート絶縁膜を形成すると共に、前記ゲート絶縁膜の表面に前記ゲート電極を形成する工程と、を含む、プレーナ型の縦型ＭＯＳＦＥＴを形成する工程であることを特徴とする請求項１または２に記載のスーパージャンクション構造の縦型ＭＯＳＦＥＴを有する半導体装置の製造方法。 The step of forming the vertical MOSFET includes:
Forming a channel layer by ion-implanting a second conductivity type impurity on a first conductivity type column composed of the first semiconductor layer;
Forming a source region by ion-implanting a first conductivity type impurity into a surface layer portion of the channel layer;
Ion-implanting a first conductivity type impurity at a position spaced apart from the source region to form a first conductivity type connection layer (30) reaching the first semiconductor layer from the channel layer;
Forming the gate insulating film on the surface of the channel layer and forming the gate electrode on the surface of the gate insulating film, and forming a planar type vertical MOSFET. A method of manufacturing a semiconductor device comprising the vertical MOSFET having a super junction structure according to claim 1.
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