JP5724487B2 - Image processing apparatus, image forming apparatus, and power saving method - Google Patents

Description

  The present invention relates to an image processing apparatus, an image forming apparatus, and a power saving method, and more particularly, an image processing apparatus that improves power saving by optimizing power control and reference clock control of a high-speed serial bus connecting an engine and a controller. The present invention relates to an image forming apparatus and a power saving method.

  Image processing apparatuses and image forming apparatuses such as scanner apparatuses, copying apparatuses, printer apparatuses, facsimile apparatuses, and composite apparatuses are required to have higher functions and higher speeds. In addition to controlling the engine unit that performs necessary image processing and the controller unit that performs image processing such as image rotation, editing, etc., the request and response are separated, and the next step is performed without waiting for the response. A high-speed split transaction bus (high-speed serial bus) such as PCI (Peripheral Component Interconnect) Express (hereinafter referred to as PCIe) that can issue the above request has been used. In an image processing apparatus or an image forming apparatus in which a controller unit and an engine unit are connected by PCIe, a reference clock is connected from the SSCG (Spread Spectrum Clock Generator) of the controller unit to the PCIe interface of the engine unit and the controller unit. (Reference clock) is supplied.

  On the other hand, in image processing apparatuses and image forming apparatuses, in recent years, there has been a demand for power saving (energy saving), such as the elapse of a preset waiting time in a standby state and the operation of a power saving key for shifting to a power saving mode. When a power saving mode transition factor occurs, the power supply to the engine unit etc. is turned off to shift to the power saving mode to reduce power consumption, key operation on the operation display unit, operation request such as printing from an external device, An image processing apparatus and an image forming apparatus having a power saving mode for resuming power supply to an engine unit or the like when a power saving mode return factor such as setting of a document on a scanner unit occurs have appeared.

  An image processing apparatus or an image forming apparatus having such a power saving mode needs to control the link state of PCIe when turning on / off the power supply to the engine unit. Conventionally, when returning from the power saving mode, After the power of the engine unit is turned on, the PCIe link is established and put into the standby state (L0). When shifting to the power saving mode, the PCIe link state is set to sleep before the engine unit power is turned off. The state (L2) is set.

  In addition, in an image processing apparatus or an image forming apparatus in which the controller unit and the engine unit are connected by PCIe, the PCIe reference clock supplied from the controller unit to the engine unit is also controlled in accordance with the power on / off of the engine unit. As a reference clock control method, a method of controlling by hardware and a method of controlling by software are known. In the method of controlling by hardware, when a signal for monitoring the power state of the engine side is output from the engine unit to the controller unit and input to the output control terminal of the clock generator of the controller unit, the engine side power is turned on. When the clock supply from the clock generator of the controller unit is started and the power of the engine unit is turned off, the clock supply from the clock generator is stopped. In the method controlled by software, the transition of the PCIe to the sleep state (L2) is monitored by software, and when the transition is detected, the clock is stopped by register control of the clock generator (see Patent Document 1, etc.).

  However, in the prior art, in the method of controlling the PCIe reference clock supplied from the controller unit to the engine unit by hardware, the power state of the engine unit is input to the clock generator and the power of the engine unit is When is turned off, the reference clock from the clock generator to the PCIe is turned off, so the reference clock cannot be turned off until the power of the engine unit is reduced, and the PCIe link state is the sleep state (L2). The reference clock is supplied to the PCIe until the power of the engine unit is turned off after the shift to, so that power is wasted.

  In the method of controlling the PCIe reference clock supplied from the controller unit to the engine unit by software, the clock generator register is detected by software after detecting that the PCIe link state has shifted to the sleep state (L2). Since the reference clock is stopped by the access, the reference clock is turned off until the clock is stopped by the register access of the clock generator by software after detecting that the PCIe link state has shifted to the sleep state (L2). During this time, power is wasted.

  In addition, in the method controlled by software, while the clock stop processing is performed by software, other processing cannot be performed, and the completion of the transition to the power saving mode is delayed by that amount. It becomes.

  Therefore, the present invention provides an image processing apparatus, an image forming apparatus, and a power saving method for further improving power saving by quickly stopping the reference clock to the high speed serial bus when the high speed serial bus enters a sleep state. The purpose is to do.

In order to achieve the above object, the present invention is configured such that engine means for performing various image processing and control means for controlling the engine means are connected via an engine side interface and a control side interface via a high-speed serial bus. In an image processing apparatus that supplies a reference clock that defines the operation of the high-speed serial bus from a clock generation means to the interface and the control-side interface, when it is detected that the high-speed serial bus is in a sleep state, at least the engine side The output of the reference clock to the interface is stopped , and power supply / power supply stop to the engine means by the power supply means for supplying power independently to the engine means and the control means is controlled. ~ side When the output of the reference clock to the interface is stopped, it is characterized by stopping the supply of power to the engine unit by said power supply means.

  According to the present invention, when the high-speed serial bus enters the sleep state, the reference clock to the high-speed serial bus can be quickly stopped to further improve power saving.

The principal part block block diagram of the compound apparatus to which one Example of this invention is applied. The principal part block block diagram of the compound apparatus of 2nd Example. The state of PCIe and the timing diagram of the principal part of a compound apparatus. The figure which shows the signal logic of the state of PCIe and the principal part of a composite apparatus. FIG. 9 is a block diagram of a main part of a printer apparatus that performs error processing according to a second embodiment. The principal part block block diagram of the compound apparatus of 3rd Example. The state of PCIe of 3rd Example, and the timing diagram of the principal part of a composite apparatus. The figure which shows the state of PCIe of 3rd Example, and the signal logic of the principal part of a composite apparatus. FIG. 10 is a block diagram of a main part of a printer apparatus that performs error processing according to a third embodiment.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, since the Example described below is a suitable Example of this invention, various technically preferable restrictions are attached | subjected, However, The range of this invention is unduly limited by the following description. However, not all the configurations described in the present embodiment are essential constituent elements of the present invention.

  FIG. 1 is a diagram illustrating a first embodiment of an image processing apparatus, an image forming apparatus, and a power saving method according to the present invention. FIG. 1 illustrates a first embodiment of the image processing apparatus, the image forming apparatus, and the power saving method according to the present invention. It is a principal part block block diagram of the compound apparatus 1 to which the Example was applied.

  In FIG. 1, a composite apparatus (image processing apparatus, image forming apparatus) 1 includes an engine unit 2, a controller unit 3, a PSU (Power Supply Unit) 4, a main switch 5, and the like. An operation display unit, an external interface connected to an external device such as a personal computer PC via a network, a facsimile unit, and the like are provided.

  The PSU 4 (power supply means) is connected to a commercial power supply of 100 V via a main switch 5 via a plug (not shown), and when the main switch 5 is turned on, the commercial power supply is supplied. The PSU 4 includes a transformer, a rectifier circuit, a regulator circuit, and the like. After converting and rectifying commercial power to a predetermined voltage, the controller power Pc is supplied to the controller unit 3 as stable DC power through the regulator circuit. The engine power Pe is supplied to the engine unit 2.

  The engine unit (engine means) 2 is a general term for engines such as scanners and plotters. For example, an image scanner using a CCD (Charge Coupled Device) or the like is used as the scanner, and generally includes an ADF (automatic document feeder). A plurality of originals are set in the ADF, and the ADF feeds the set originals one by one to the original reading position of the scanner. The scanner scans the document conveyed from the ADF, reads an image of the document with a predetermined resolution, binarizes it, and outputs it to the controller unit 3. The plotter is, for example, an electrophotographic recording apparatus or the like, and the plotter records and outputs an image of a document read by a scanner or a received image received by a facsimile communication unit or a network communication unit (not shown) on a recording sheet. The necessary report is recorded and output on a recording medium such as paper or film (hereinafter simply referred to as paper).

  The engine unit 2 includes an engine ASIC (Application Specific Integrated Circuit) 21. The engine ASIC 21 performs various types of image processing on the image data of the document read by the scanner, and sends the image data to the controller unit 3. Further, the engine unit 2 uses the engine ASIC 21 to perform image processing suitable for printing out the image data sent from the controller unit 3 by the plotter unit. The engine ASIC 21 is supplied with engine ASIC power supply power (interface supply power) Pea based on the engine power supply power Pe from the PSU 4.

  The controller unit (control means) 3 includes a controller CPU (Central Processing Unit) 31, an operation display I / F, a main memory, a ROM, various I / Os (Input / Output), a controller ASIC 32, a hard disk, a clock generator 33, and the like. Under the control of the controller CPU 31, the control of the engine unit 2 and the overall control of the composite apparatus 1, drawing, communication, reading / writing of image data to / from the hard disk, operation acquisition on the operation display unit, and display on the operation display unit Data control and necessary image processing on the image data by the controller ASIC 32 are performed. The controller ASIC 31 is supplied with the controller ASIC power supply power Pca based on the controller power supply power Pc from the PSU 4.

  The engine ASIC 21 and the controller ASIC 32 are connected by a PCIe (high-speed serial bus) 6, and the engine ASIC 21 and the controller ASIC 32 are each an LTSSM register (bus sleep state detection) indicating the state of the LTSSM (Link Training and Status State Machine) of the PCIe 6. Means) 21a and 32a. The link state of PCIe6 can be known from the contents of the LTSSM register 21a and the LTSSM register 32a, and the state of PCIe6 can be set by setting the values of the LTSSMs 21a and 32a. The engine ASIC 21 has a PCIe 6 engine side interface, and the controller ASIC 32 has a PCIe 6 control side interface.

  The clock generator (clock generation means) 33 generates a reference clock (reference clock) for operating the PCIe 6, and outputs the engine / reference clock Ce to the engine ASIC 21 and the controller / reference clock Cc to the controller ASIC 32. The clock generator 33 includes an EN (Enable) pin 33a. When the input signal of the EN pin 33a becomes a low level, the clock generator 33 stops oscillation of the reference clock, and the input signal of the EN pin 33a is high (high). ) When it reaches the level, oscillation of the reference clock starts.

  The PCIe 6 has a state (state) such as a standby state (L0), a sleep state (L2), and the link state of the PCIe 6 is normally provided in the LTSSM register 32a provided in the controller ASIC 32 or the engine ASIC 21. It is represented by the value of the LTSSM register 21a. Then, the controller ASIC 32 sets the clock control signal Sc output to the EN pin 33a of the clock generator 33 to the low level when the value of the LTSSM register 32a becomes the sleep state (L2), and in other states Then, the clock control signal Sc is set to the high level. That is, at the moment when PCIe 6 is in the L2 state (sleep state), the clock control signal Sc output from the controller ASIC 32 to the EN pin 33a of the clock generator 33 becomes Low level, and the EN pin 33a of the clock generator 33 is The engine reference clock Ce and the controller reference clock Cc output from the clock generator 33 are stopped.

  The controller ASIC 21 and the clock generator 33 are connected via a communication path 34, and a program executed by the controller CPU 31 controls a register in the clock generator 33 via the controller ASIC 32 and the communication path 34. The reference clock Ce and the controller reference clock Cc are ON / OFF controlled. Therefore, the controller ASIC 32 functions as a clock control unit.

  The ON / OFF control of the reference clocks Ce and Cc output from the clock generator 33 by the controller ASIC 32 may be simultaneously ON / OFF controlled for the engine reference clock Ce and the controller reference clock Cc as described above. Only the engine reference clock Ce may be ON / OFF controlled.

  The multifunction device 1 has a power saving mode, and causes a power saving mode transition factor such as when a preset waiting time has elapsed in the standby state or when the power saving mode key of the operation display unit is operated. Is generated, the controller ASIC 32 sets the power control signal Sp output to the PSU 4 to the low level, the key operation on the operation display unit, the operation request such as printing from the external device, the setting of the document on the scanner unit, etc. When the power saving mode return factor is generated, the power control signal Sp is set to the high level. Therefore, the controller ASIC 32 functions as power control means.

  The PSU 4 stops supplying the engine power supply Pe supplied to the engine unit 2 when the power control signal Sp from the controller ASIC 32 becomes low level, and supplies it when the power control signal Sp changes from low level to high level. Supply of the engine power supply power Pe to the stopped engine unit 2 is started.

  Next, the operation of this embodiment will be described. The composite apparatus 1 of this embodiment appropriately controls the reference clocks Ce and Cc of the PCIe 6 at the time of shifting to the power saving mode and returning from the power saving mode, thereby further reducing power consumption.

  That is, in the composite apparatus 1, the engine ASIC 21 of the engine unit 2 and the controller ASIC 32 of the controller unit 3 are connected by the PCIe 6, and data is transferred between the engine ASIC 21 and the controller ASIC 32 via the PCIe 6 at high speed.

  When the preset waiting time elapses in the standby state or when a power saving mode transition factor such as an operation of the power saving mode key of the operation display unit occurs, the CPU 31 causes the controller ASIC 32 to The power control signal Sp output from the controller ASIC 32 to the PSU 4 is switched to the Low level, and the supply of the engine power source Pe from the PSU 4 to the engine unit 2 is stopped.

  When the supply of the engine power supply Pe supplied from the PSU 4 is stopped, the engine unit 2 stops the supply of the engine ASIC power supply Pea supplied to the engine ASIC 21. The engine reference clock Ce supplied from the clock generator 33 must also be stopped.

  Therefore, in the composite apparatus 1, the program executed by the CPU 31 controls a register in the clock generator 33 via the communication path 34 to stop the engine reference clock Ce supplied from the clock generator 33 to the engine ASIC 21. When the software method or the controller ASIC 32 sets the clock control signal Sc output to the EN pin 33a of the clock generator 33 to a low level when the value of the LTSSM register 32a is in the sleep state (L2), the clock generator 33 causes the engine to The engine reference clock Ce is stopped by one of the hardware methods for stopping the engine reference clock Ce output to the ASIC 21.

  When the power saving mode return factor such as a key operation on the operation display unit, an operation request for printing from an external device, an original setting on the scanner unit, or the like occurs, the multifunction device 1 outputs the controller ASIC 32 to the PSU 4 The power control signal Sp that is being operated is set to the High level, and the PSU 4 starts supplying the engine power supply power Pe to the engine unit 2. When the supply of the engine power supply power Pe is resumed, the engine unit 2 resumes the supply of the engine ASIC power supply power Pea to the engine ASIC 21. Then, for example, the CPU 31 causes the clock generator 33 to start supplying the engine / reference clock Ce to the engine ASIC 21 by register control of the clock generator 33 via the controller ASIC 32, establishes the link of PCIe 6, and enters the standby state ( L0).

  As described above, in the composite apparatus 1 of this embodiment, the engine unit (engine unit) 2 that performs various image processing and the controller unit (control unit) 3 that controls the engine unit 2 are controlled by the engine ASIC 21 serving as an engine-side interface. Engine reference clock, which is a reference clock that regulates the operation of PCIe 6 from the clock generator (clock generating means) 33 to the engine ASIC 21 and the controller ASIC 32, is connected to the engine ASIC 21 and the controller ASIC 32 via the controller ASIC 32 as a side interface. When Ce and controller reference clock Cc are supplied and it is detected that the link state of PCIe 6 is in the sleep state, at least the clock generator 33 generates an engine. It has stopped the output of the engine reference clock Ce to the SIC21.

  Therefore, when the high-speed serial bus enters the sleep state, the reference clock to the high-speed serial bus can be quickly stopped, and power saving can be further improved.

  Further, the composite apparatus 1 of this embodiment supplies power independently from the PSU 4 to the engine unit 2 and the controller unit 3, and the output of the engine reference clock Ce from the clock generator 33 to the engine ASIC 21 is stopped. The power supply to the engine unit 2 is stopped.

  Therefore, the engine reference clock Ce can be prevented from being supplied before the engine power supply Pe is started to be supplied to the engine unit 2, so that a failure of the device can be prevented. The time from the start of the supply of the power supply Pe to the start of the supply of the reference clock Ce can be minimized, and the PCIe 6 can be quickly linked up to shorten the startup time.

  The controller / reference clock Cc may be turned ON / OFF at the same time as the engine / reference clock Ce is turned ON / OFF (oscillation start / oscillation stop).

  In this way, it is possible to stop the oscillation of all the reference clocks Ce and Cc that are unnecessary for the PCIe 6, and it is possible to further reduce power consumption.

  2 to 5 are diagrams illustrating a second embodiment of the image processing apparatus, the image forming apparatus, and the power saving method of the present invention. FIG. 2 illustrates the image processing apparatus, the image forming apparatus, and the power saving method of the present invention. It is a principal part block block diagram of the compound apparatus 100 to which 2nd Example of this is applied.

  This embodiment is applied to the same composite apparatus 100 as the composite apparatus 1 of the first embodiment. In the description of this embodiment, the same components as those of the composite apparatus 1 of the first embodiment are used. Are given the same reference numerals and the description thereof is omitted or simplified.

  In FIG. 2, a composite apparatus (image processing apparatus, image forming apparatus) 100 includes an engine unit 102, a controller unit 103, a PSU 4, a main switch 5, and the like, and engine power is supplied from the PSU 4 to the engine unit 102 and the controller unit 103, respectively. Electric power Pe and controller power supply power Pc are supplied.

  The engine unit (engine means) 102 is a generic term for engines such as a scanner and a plotter, like the engine unit 2 of the first embodiment, and includes an engine ASIC 21 similar to the engine unit 2 of the first embodiment. In addition, a voltage monitoring unit 121 is provided. The controller unit (control means) 103 includes a CPU 31, a controller ASIC 32, and a clock generator 33 that are the same as those of the composite apparatus 1 of the first embodiment, and a clock control circuit 131.

  The voltage monitoring unit (voltage detection means) 121 of the engine unit 102 detects the voltage of the engine ASIC power supply Pea supplied to the engine ASIC 21 and outputs the detected voltage detection signal Sv to the clock control circuit 131 of the controller unit 103. . The voltage monitoring unit 121 asserts the voltage detection signal Sv when the detected voltage value of the engine ASIC power supply power Pea is equal to or higher than a preset specified voltage.

  In addition to the voltage detection signal Sv from the voltage monitoring unit 121, the clock control signal Sc and the link-up signal Su are input from the controller ASIC 32 to the clock control circuit 131 of the controller unit 103.

  The clock control signal Sc is output from the controller ASIC 32 as in the first embodiment, but the output destination is not the EN pin 33a of the clock generator 33 but the clock control circuit 131. Similarly to the first embodiment, the controller ASIC 32 sets the clock control signal Sc output to the EN pin 33a of the clock generator 33 to the low level when the value of the LTSSM register 32a becomes L2, In other states, the clock control signal Sc is set to the high level.

  Further, the controller ASIC 32 outputs to the clock control circuit 131 a link up signal Su that becomes High level when the link probability of PCIe 6 is high and becomes Low level when the link is disconnected. The output control of the link-up signal Su from the controller ASIC 32 to the clock control circuit 131 may be performed by a program of the controller CPU 31, or the controller ASIC 32 may be performed by hardware.

  Based on the link up signal Su from the controller ASIC 32, the clock control circuit 131 determines whether the PCIe 6 is in a state of establishing a link or a state of disconnecting the link, and in a state of establishing the link of the PCIe 6 When the voltage detection signal Sv is asserted, the clock EN control signal Sec output to the EN pin 33a of the clock generator 33 is set to High level, and supply of the engine reference clock Ce to the engine ASIC 21 by the clock generator 33 is started. If the clock control signal Sc from the controller ASIC 32 becomes low level while the PCIe6 link is disconnected, the clock EN control signal Sec output to the EN pin 33a of the clock generator 33 is set to low level. To stop the supply of the engine reference clock Ce to the engine ASIC21 by the clock generator 33. Therefore, the controller ASIC 32 and the clock control circuit 131 function as clock control means as a whole, and the controller ASIC 32 also functions as power control means as in the first embodiment.

  Next, the operation of this embodiment will be described. The composite apparatus 100 according to the present embodiment more appropriately controls the reference clocks Ce and Cc of the PCIe 6 when returning from the power saving mode, and appropriately turns ON / OFF the engine power supply power Pe to the engine unit 102. Control to further reduce power consumption.

  That is, when returning from the power saving mode, the CPU 31 starts the supply of the engine reference clock Ce from the clock generator 33 to the engine ASIC 21 by the register control of the clock generator 33 via the controller ASIC 32 and the communication path 34. When the clock generator 33 starts supplying the engine reference clock Ce to the engine ASIC 21, the CPU 31 sets the power control signal Ps from the controller ASIC 32 to the PSU 4 to High level, and then the engine ASIC power supply power Pea to the engine ASIC 21. After waiting for a predetermined waiting time until the voltage of the voltage rises to the predetermined voltage, register control of the clock generator 33 is performed via the controller ASIC 32 and the communication path 34, and the clock is Tsu the click generator 33 to initiate supply to the engine ASIC21 engine reference clock Ce, by establishing a link PCIe6, shifts to the standby state (L0).

  However, after the power control signal Ps to the PSU 4 is set to the high level by software control, the operation safety is set as a predetermined waiting time until the voltage of the engine ASIC power supply power Pea to the engine ASIC 21 rises to the predetermined voltage. In order to ensure, it is necessary to set a maximum value, which may result in excessive waiting time. As a result, the start of link training for PCIe 6 is delayed, and it is necessary to improve the speed of operation and power reduction.

  Therefore, in the composite apparatus 100 of the present embodiment, the engine unit 102 is provided with a voltage monitoring unit 121 that detects the voltage value of the engine ASIC power supply power Pea to the engine ASIC 21 by hardware, and the controller unit 103 includes the voltage monitoring unit 121. A clock control circuit 131 is provided for controlling the clock EN control signal Sec to the EN pin 33a of the clock generator 33 on the basis of the voltage detection signal Sv of the clock generator 33 to control the start and stop of the supply of the engine reference clock Ce.

  That is, as shown in FIG. 3, when the multifunction apparatus 100 enters the sleep state (state ST1) that is L2 where establishment of the link of PCIe6 is started, the link-up signal Su becomes a high level. The voltage detection signal Sv output to the clock control circuit 131 by the voltage monitoring unit 121 that detects the voltage value of the engine ASIC power supply power Pea to the ASIC 21 and the clock control signal Sc output from the controller ASIC 32 to the clock control circuit 131 are low level. is there. At this time, the clock EN control signal Sec output from the clock control circuit 131 to the EN pin 33a of the clock generator 33 is at the Low level. That is, as shown in FIG. 4, in the state ST1, only the link up signal Su is at the high level (1), and the other signals Sv, Sc, and Sec are at the low level (0).

  Thereafter, supply of the engine power supply Pe from the PSU 4 to the engine unit 102 is started, and the voltage value of the engine ASIC power supply Pea supplied to the engine ASIC 21 becomes equal to or higher than a predetermined voltage. When the voltage detection signal Sv output to 131 becomes High level, the clock control circuit 131 sets the clock EN control signal Sec output to the EN pin 33a of the clock generator 33 to High level, and the clock generator 33 sends to the engine ASIC 21. The state ST2 starts to supply the engine reference clock Ce. That is, as shown in FIG. 4, in the state ST2, the link up signal Su, the voltage detection signal Sv, and the clock EN control signal Sec are at a high level, and only the clock control signal Sc is at a low level (0).

  When the link of PCIe6 is established and the state of PCIe6 is in the standby state (L0), the clock control signal Sc is also at the high level. At this time, the clock EN control signal Sec remains at the high level, The clock generator 33 is in the state ST3 in which the oscillation of the engine reference clock Ce to the engine ASIC 21 is continued. That is, as shown in FIG. 4, in the state ST3, all the signals Su, Sv, Sc, and Sec are at the high level (1).

  Here, when a factor for shifting to the power saving mode occurs, the link-up signal Su output from the controller ASIC 32 to the clock control circuit 131 becomes the low level in order to disconnect the link of the PCIe 6. The EN control signal Sec remains at the high level, and the clock generator 33 enters the state ST4 in which the engine reference clock Ce is continuously oscillated to the engine ASIC 21. That is, as shown in FIG. 4, in the state ST4, only the link up signal Su is at the low level (0), and the other signals Sv, Sc, and Sec are at the high level (1).

  Thereafter, when the state of the PCIe 6 becomes a sleep state (L2), the clock control signal Sc output from the controller ASIC 32 to the clock control circuit 131 becomes Low level, and the clock control circuit 131 outputs to the EN pin 33a of the clock generator 33. The clock EN control signal Sec is switched to the Low level, and the clock generator 33 enters the state ST5 in which the oscillation of the engine reference clock Ce to the engine ASIC 21 is stopped. That is, as shown in FIG. 4, in the state TS5, only the voltage detection signal Sv is at the high level (1), and the other signals Su, Sc, and Sec are at the low level (0).

  When the controller ASIC 32 sets the power control signal Sp to the PSU 4 to a low level (0), the controller ASIC 32 stops the supply of the engine power supply power Pe supplied to the engine unit 102 by the PSU 4 and the engine supplied to the engine ASIC 21. The supply of the ASIC power supply power Pea is stopped (Low level), and the state becomes the state ST6 where the clock EN control signal Sec and the engine reference clock Ce remain at the Low level. That is, as shown in FIG. 4, in this state ST6, all signals Su, Sv, Sc, and Sec are at the low level (0).

  As described above, the composite apparatus 100 according to the present embodiment detects the voltage of the engine ASIC power supply power Pea supplied to the engine ASIC 21 based on the engine power supply power Pe supplied to the engine unit 102, and detects the engine When supply of the engine power supply power Pe to the unit 102 is started and the voltage of the engine ASIC power supply power Pea becomes equal to or higher than a predetermined reference voltage, output of the engine reference clock Ce from the clock generator 33 to the engine ASIC 21 is started. ing.

  Therefore, it is possible to prevent the engine / reference clock Ce from being supplied before the supply of the engine power supply power Pe to the engine unit 102 is started, thereby preventing a failure of the device and the engine. The time from the start of the supply of the power supply Pe to the start of the supply of the reference clock Ce can be minimized, and the PCIe 6 can be quickly linked up to shorten the startup time.

  In the composite apparatus 100 according to the present embodiment, when the PCIe 6 is disconnected, if the PCIe 6 does not enter the sleep state (L2) after waiting for a predetermined time, the error signal Se is sent from the clock control circuit 131 as shown in FIG. The program may be output to the controller ASIC 32 and notified to the program executed by the controller CPU 31 via the controller ASIC 32.

  In other words, the clock control circuit 131 outputs an error signal Se to the controller ASIC 32 and outputs the error signal Se to the controller ASIC 32 when the PCIe 6 does not enter the sleep state (L2) even after waiting for a predetermined time when the PCIe 6 is disconnected. It functions as an abnormality determination means that notifies a running program.

  By executing the program, the controller CPU (abnormality notification means) 31 displays, for example, a message indicating that an error has occurred on the operation display unit, or transmits an error message to the computer in the service center via the network. In such a manner, an error occurrence is notified to the user or service person.

  Further, when the controller CPU 31 recognizes that it is abnormal, the controller CPU 31 performs register control of the clock generator 33 through the communication path 34 from the controller ASIC 32 even if the PCIe 6 has not shifted to the sleep state (L2). The supply of the engine reference clock Ce to the engine ASIC 21 by the clock generator 33 is stopped, and the power control signal Sp output to the PSU 4 is set to the low level (0) by the controller ASIC 32 so that the PSU 4 causes the engine unit 102 to The supply of the engine power supply Pe supplied to the engine may be stopped.

  In this way, it is possible to notify the user or service person of an abnormality of PCIe6, and it is possible to quickly cope with the abnormality of PCIe6.

  Even if PCIe 6 is abnormal, it is possible to stop the supply of the engine / reference clock Ce and stop the supply of the engine power supply power Pe to shift to the power saving mode.

  6 to 9 are diagrams illustrating a third embodiment of the image processing apparatus, the image forming apparatus, and the power saving method of the present invention. FIG. 5 illustrates the image processing apparatus, the image forming apparatus, and the power saving method of the present invention. It is a principal block block diagram of the compound apparatus 110 to which 3rd Example of this is applied.

  The present embodiment is applied to a composite apparatus 110 similar to the composite apparatus 100 of the second embodiment. In the description of this embodiment, the same components as those of the composite apparatus 100 of the second embodiment are used. Are given the same reference numerals and the description thereof is omitted or simplified.

  In FIG. 5, a composite apparatus (image processing apparatus, image forming apparatus) 110 includes an engine unit 102, a controller unit 113, a PSU 4, a main switch 5, and the like, and engine power is supplied from the PSU 4 to the engine unit 102 and the controller unit 113. Electric power Pe and controller power supply power Pc are supplied.

  The engine unit 102 includes an engine ASIC 21 similar to that of the composite device 100 of the second embodiment, and also includes a voltage monitoring unit 121. The controller unit 113 includes a CPU 31 similar to that of the composite device 100 of the second embodiment. And a controller ASIC 32 and a clock generator 33, and a clock control circuit 132.

  The voltage monitoring unit 121 of the engine unit 102 detects the voltage of the engine ASIC power supply Pea supplied to the engine ASIC 21 and outputs the detected voltage detection signal Sv to the clock control circuit 132 of the controller unit 113. The voltage monitoring unit 121 asserts the voltage detection signal Sv when the detected voltage value of the engine ASIC power supply power Pea is equal to or higher than a preset specified voltage.

  In addition to the voltage detection signal Sv from the voltage monitoring unit 121, the clock control circuit 132 of the controller unit (control means) 113 receives a clock from the controller ASIC 32, as in the clock control circuit 131 of the composite apparatus 100 of the second embodiment. A control signal Sc and a link-up signal Su are input.

  Similarly to the clock control circuit 131 of the second embodiment, the clock control circuit (clock control means) 132 disconnects the link whether the PCIe 6 is in a state where the link is established based on the link up signal Su from the controller ASIC 32. When the voltage detection signal Sv is asserted in a state where the PCIe 6 link is established, the clock EN control signal Sec output to the EN pin 33a of the clock generator 33 is set to a high level. When the clock reference signal Ce from the controller ASIC 32 becomes low level in a state where the supply of the engine reference clock Ce to the engine ASIC 21 by the clock generator 33 is started and the link of the PCIe 6 is disconnected, the EN pin 3 of the clock generator 33 And a clock EN control signal Sec that outputs to a to the Low level to stop the supply of the engine reference clock Ce to the engine ASIC21 by the clock generator 33.

  Further, the clock control circuit (power control means) 132 outputs a power control signal Sp for controlling power supply / supply stop of the engine power supply Pe from the PSU 4 to the engine unit 102 to the PSU 4, and waits in advance in a standby state. When a power saving mode transition factor occurs, such as when the power saving mode key of the operation display unit is operated when time has elapsed, the power control signal Sp output to the PSU 4 is set to the low level, and the operation display unit When a power-saving mode return factor such as a key operation, an operation request such as printing from an external device, or setting of a document on the scanner unit occurs, the power control signal Sp is set to a high level.

  That is, in the composite apparatus 110 of the present embodiment, the clock control circuit 132 outputs the power control signal Sp that the controller ASIC 32 has output to the PSU 4 in the first and second embodiments.

  Next, the operation of this embodiment will be described. The composite apparatus 110 according to the present embodiment controls the start / stop of supply of the engine power supply power Pe from the PSU 4 to the engine unit 102 by hardware using a power control signal Sp from the clock control circuit 132 to the PSU 4.

  That is, as illustrated in FIG. 6, when the complex apparatus 110 enters the sleep state (state ST1) that is L2 where the establishment of the link of PCIe6 is started, the link-up signal Su becomes High level and the clock control circuit 132 Sets the power control signal Sp output to the PSU 4 to the high level. At this time, as in FIG. 3, the voltage monitoring unit 121 for detecting the voltage value of the engine ASIC power supply power Pea to the engine ASIC 21 is the clock control circuit. The voltage detection signal Sv output to 132 and the clock control signal Sc output from the controller ASIC 32 to the clock control circuit 132 are at a low level. At this time, the clock EN control signal Sec output from the clock control circuit 132 to the EN pin 33a of the clock generator 33 is at the Low level. That is, as shown in FIG. 7, in the state ST1, the link up signal Su and the power control signal Sp are at the high level (1), and the other signals Sv, Sc, and Sec are at the low level (0).

  Thereafter, supply of the engine power supply Pe from the PSU 4 to the engine unit 102 is started, and the voltage value of the engine ASIC power supply Pea supplied to the engine ASIC 21 becomes equal to or higher than a predetermined voltage. When the voltage detection signal Sv output to 132 becomes High level, the clock control circuit 132 sets the clock EN control signal Sec output to the EN pin 33a of the clock generator 33 to High level, and the clock generator 33 supplies the engine ASIC 21. The state ST2 starts to supply the engine reference clock Ce. That is, as shown in FIG. 7, in the state ST2, the link up signal Su, the voltage detection signal Sv, the clock EN control signal Sec, and the power control signal Sp are at a high level, and only the clock control signal Sc is at a low level (0). ).

  When the link of PCIe6 is established and the state of PCIe6 is in the standby state (L0), the clock control signal Sc is also at the high level. At this time, the clock EN control signal Sec remains at the high level, The clock generator 33 is in the state ST3 in which the oscillation of the engine reference clock Ce to the engine ASIC 21 is continued. That is, as shown in FIG. 7, in the state ST3, all signals Su, Sv, Sc, and Sec are at a high level (1).

  When a factor for shifting to the power saving mode occurs, the link up signal Su output from the controller ASIC 32 to the clock control circuit 132 goes to a low level in order to disconnect the link of the PCIe 6. The control signal Sec remains at the high level, the clock generator 33 enters the state ST4 where the oscillation of the engine reference clock Ce to the engine ASIC 21 is continued, the power control signal Sp remains at the high level, and the PSU 4 The engine power supply Pe is continuously supplied to the engine unit 102. That is, as shown in FIG. 7, in the state ST4, only the link up signal Su is at the low level (0), and the other signals Sv, Sc, Sec, and Sp are at the high level (1).

  Thereafter, when the state of the PCIe 6 becomes a sleep state (L2), the clock control signal Sc output from the controller ASIC 32 to the clock control circuit 132 becomes a low level, and the clock control circuit 132 outputs to the EN pin 33a of the clock generator 33. The clock EN control signal Sec is switched to the Low level to stop the oscillation of the engine reference clock Ce from the clock generator 33 to the engine ASIC 21, and at the same time, the power control signal Sp to the PSU 4 is changed from the High level to the Low level. Is switched to state ST5 in which the supply of the engine power supply Pe from the PSU 4 to the engine unit 102 is stopped. That is, as shown in FIG. 7, in the state TS5, only the voltage detection signal Sv is at the high level (1), and the other signals Su, Sc, Sec, Sp are at the low level (0).

  Then, the controller ASIC 32 stops the supply of the engine ASIC power supply power Pea supplied to the engine ASIC 21 in the state ST5 (Low level), and the clock EN control signal Sec and the engine reference clock Ce remain at the Low level. In this state ST6, the oscillation of the engine reference clock Ce stops and the engine power supply power Pe is turned off. That is, as shown in FIG. 7, in this state ST6, all the signals Su, Sv, Sc, and Sec are at the low level (0).

  As described above, the composite apparatus 100 according to the present embodiment detects the voltage of the engine ASIC power supply power Pea supplied to the engine ASIC 21 based on the engine power supply power Pe supplied to the engine unit 102, and detects the engine When supply of the engine power supply power Pe to the unit 102 is started and the voltage of the engine ASIC power supply power Pea becomes equal to or higher than a predetermined reference voltage, output of the engine reference clock Ce from the clock generator 33 to the engine ASIC 21 is started. ing.

  Therefore, it is possible to prevent the engine / reference clock Ce from being supplied before the supply of the engine power supply power Pe to the engine unit 102 is started, thereby preventing a failure of the device and the engine. The time from the start of the supply of the power supply Pe to the start of the supply of the reference clock Ce can be minimized, and the PCIe 6 can be quickly linked up to shorten the startup time.

  In addition, the clock control circuit 132 can control the start / stop of supply of the engine power supply power Pe from the PSU 4 to the engine unit 102 by hardware, and can control more quickly and while reducing the load on the controller CPU 31. can do.

  In the composite apparatus 110 according to the present embodiment, when PCIe 6 is disconnected, if PCIe 6 does not enter the sleep state (L2) after waiting for a predetermined time, an error signal Se is sent from the clock control circuit 132 as shown in FIG. The program may be output to the controller ASIC 32 to notify the program executed by the controller CPU 31 via the controller ASIC 32, and supply of the engine power supply Pe to the engine unit 102 by the PSU 4 may be stopped.

  In other words, the clock control circuit 132 as the power control means outputs the error signal Se to the controller ASIC 32 when the PCIe 6 is not in the sleep state (L2) even after waiting for a predetermined time when the PCIe 6 is disconnected. Via the controller CPU 31 and functions as an abnormality determination means for switching the power control signal Sp output to the PSU 4 to the low level (0).

  By executing the program, the controller CPU (abnormality notification means) 31 displays, for example, a message indicating that an error has occurred on the operation display unit, or transmits an error message to the computer in the service center via the network. In such a manner, an error occurrence is notified to the user or service person.

  Further, when the controller CPU 31 recognizes that it is abnormal, the controller CPU 31 performs register control of the clock generator 33 through the communication path 34 from the controller ASIC 32 even if the PCIe 6 has not shifted to the sleep state (L2). The supply of the engine reference clock Ce to the engine ASIC 21 by the clock generator 33 is stopped.

  In this case, the clock control circuit 132 may only switch the power control signal Sp to the low level (0) even if it does not have the function of outputting the error signal Se.

  In this way, it is possible to notify the user or service person of an abnormality of PCIe6, and it is possible to quickly cope with the abnormality of PCIe6.

  Even if PCIe 6 is abnormal, it is possible to stop the supply of the engine / reference clock Ce and stop the supply of the engine power supply power Pe to shift to the power saving mode.

  The invention made by the present inventor has been specifically described based on the preferred embodiments. However, the present invention is not limited to that described in the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  The present invention relates to an image processing apparatus having a power saving mode in which an engine unit and a controller unit are connected by PCIe, an image forming apparatus such as a copying apparatus, a facsimile apparatus, a printer apparatus, and a composite apparatus equipped with the image processing apparatus, and It can be used for a power saving method.

1 Compound device 2 Engine unit 3 Controller unit 4 PSU
5 Main switch 21 Engine ASIC
21a LTSSM register 31 Controller CPU
32 Controller ASIC
32a LTSM register 33 clock generator 33a EN pin Pe engine power supply Pea engine ASIC power supply Pc controller power supply Pca controller ASIC power supply Sc clock control signal Ce engine reference clock Cc controller reference clock Sp power control signal 100 composite device 102 engine Unit 103 controller unit 121 voltage monitoring unit 131 clock control circuit Sv voltage detection signal Su link up signal Se error signal ST1 to ST6 state 110 composite device 113 controller unit 132 clock control circuit

JP 2008-154212 A

Claims (6)

Engine means for performing various image processing;
Control means for controlling the engine means;
A high-speed serial bus connecting the engine means and the control means;
An engine side interface of the high-speed serial bus mounted on the engine means;
A control-side interface of the high-speed serial bus mounted on the control means;
Bus sleep state detecting means for detecting a sleep state of the high-speed serial bus;
A clock generating means for generating a reference clock for defining the operation of the high-speed serial bus and outputting the reference clock to the engine-side interface and the control-side interface;
When the clock generation means controls the output of the reference clock to the engine side interface and the control side interface, and the bus sleep state detection means detects that the high-speed serial bus is in a sleep state, at least the engine Clock control means for stopping the output of the reference clock to the side interface;
Power supply means for independently supplying power to the engine means and the control means;
When power supply / power supply stop by the power supply means to the engine means is controlled, and output of the reference clock from the clock generation means to the engine side interface is stopped by the clock control means, the power Power control means for stopping power supply to the engine means by the supply means;
An image processing apparatus comprising: The image processing apparatus includes:
Voltage detection means for detecting a voltage of interface supply power supplied to the engine side interface based on power supplied from the power supply means to the engine;
In addition,
The clock control means includes
When the supply of power from the power supply means to the engine means is started and the voltage detection means detects that the voltage of the interface supply power is equal to or higher than a predetermined reference voltage, the clock generation means causes the engine to The image processing apparatus according to claim 1 , wherein output of the reference clock to the side interface is started . The image processing apparatus includes:
After the start of disconnection of the link of the high-speed serial bus, the abnormality determination is performed based on whether or not the state in which the bus sleep state detection means has not detected the transition to the sleep state of the high-speed serial bus has elapsed for a predetermined time Means,
When the abnormality determination unit determines that an abnormality has occurred, an abnormality notification unit that performs an abnormality notification to the outside;
The image processing apparatus according to claim 1 or claim 2, wherein in that it comprises. The clock control means includes
When the abnormality determination unit determines that an abnormality has occurred, the clock generation unit stops outputting the reference clock to the engine-side interface,
The power control means includes
The image processing apparatus according to claim 3, wherein when the abnormality determination unit determines that an abnormality has occurred, the power supply to the engine unit by the power supply unit is stopped .   In an image forming apparatus that includes an image processing unit and forms an image on a recording medium based on at least image data that has been subjected to image processing by the image processing unit, the image processing unit is any one of claims 1 to 4. An image forming apparatus comprising the image processing apparatus described above. Engine means for performing various image processing and control means for controlling the engine means are connected by a high-speed serial bus via the engine side interface and the control side interface, and the engine side interface and the control side interface are connected with the clock generation means from the clock generation means. A power saving method in an image processing apparatus that supplies a reference clock that defines the operation of a high-speed serial bus,
A bus sleep state detection processing step for detecting a sleep state of the high-speed serial bus; and
Controlling the output of the reference clock to the engine side interface and the control side interface by the clock generation means, and detecting that the high-speed serial bus is in a sleep state in the bus sleep state detection processing step, A clock control processing step for stopping output of the reference clock to at least the engine-side interface;
The power supply means for supplying power to the engine means and the control means independently controls power supply / power supply stop to the engine means, and the clock control processing step causes the clock generation means to control the engine side. A power control step of stopping power supply to the engine means by the power supply means when output of the reference clock to the interface is stopped;
A power saving method comprising:

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