JP5723435B2 - Multi-chip system and its register setting method - Google Patents

Description

  The present embodiment relates to a multi-chip system and a register setting method thereof, and more specifically, in a multi-chip system including two or more single chips that perform the same function and a master chip that controls the same. The present invention relates to a multi-chip system capable of simultaneously “writing” to all slave chips during a register “write” operation, and a register setting method thereof.

  The contents described in this part merely provide background information for this embodiment, and do not constitute conventional technology.

  FIG. 1 is a diagram illustrating the configuration of a general multi-chip system.

As shown in FIG. 1, the multi-chip system includes two or more slave chips that perform the same function and a master chip that controls them. The master chip drives the system by controlling the registers of each slave chip using a general-purpose interface method such as I ² C (Inter Integrated Circuit) or SPI (Serial Peripheral Interface). Each slave chip is distinguished by a fixed chip ID assigned uniquely. When performing a 'write' / 'read' operation to the register of each slave chip, the master chip first transmits a chip ID, and the transmitted chip ID is transmitted to its fixed chip ID at the interface decoding unit of the slave chip. If they match, perform a 'write' / 'read' operation.

  On the other hand, in the initial setting process for the operation of the multi-chip system, there is a case where the same data is written to the same address of all the slave chips. For example, in the case of a diversity reception system, an initial setting value is set for each slave chip for channel frequency tuning, and the diversity system is operated. In particular, channel frequency tuning time is one of the important performance factors. . According to the conventional method, while setting the register, changing the fixed chip ID of each slave chip and giving a 'write' command to each slave chip individually, the initial setting time acts as a factor of performance degradation To come.

  In this embodiment, in a multi-chip system composed of two or more slave chips that perform the same function and a master chip that controls the slave chips, it is possible to simultaneously write to all slave chips during register write operation. It is a main object to provide a multi-chip system and a register setting method thereof.

  According to one aspect of the present embodiment, in a multi-chip system including a plurality of slave chips and a master chip that controls the plurality of slave chips, the plurality of slave chips include a common chip ID and a fixed chip ID. Is set, and the master chip simultaneously performs a 'write' command to the plurality of slave chips using the common chip ID, and individually to the plurality of slave chips using the fixed chip ID. A multi-chip system is provided that is configured to perform a 'write' instruction.

  The common chip ID is a logical chip ID commonly assigned to the plurality of slave chips, and the fixed chip ID is a physical chip ID assigned to each of the plurality of slave chips. It is characterized by.

  The plurality of slave chips may be configured to perform the “write” operation when a chip ID used for the command matches a common chip ID or a fixed chip ID of the plurality of slave chips.

The master chip and the plurality of slave chips can be configured to be connected via an I ² C (Inter Integrated Circuit) or SPI (Serial Peripheral Interface) bus.

  According to another aspect of the present embodiment, in a method of operating a multi-chip system comprising a plurality of slave chips set with a common chip ID and a fixed chip ID, and a master chip that controls the plurality of slave chips, The master chip uses the common chip ID or the fixed chip ID to instruct the plurality of slave chips to perform a 'write' operation, and the plurality of slave chips share the chip ID used for the command. A method of operating a multi-chip system including a process of performing the 'write' operation when it matches a chip ID or one's own fixed chip ID.

  As described above, according to this embodiment, the number of 'write' instructions transmitted from the master chip to each slave chip in the multi-chip system can be reduced, and as a result, the register setting time of each slave chip can be reduced. Can be shortened.

1 is a diagram illustrating a configuration of a general multi-chip system. FIG. FIG. 6 is a diagram illustrating a multi-chip in which a master chip is connected to a plurality of slave chips through an I ² C bus according to an embodiment of the present invention. 6 is an example of a protocol when writing a register of a plurality of slave chips using an I ² C interface in a multi-chip system according to an embodiment of the present invention; FIG. 3 is a diagram illustrating a multi-chip in which a master chip is connected to a plurality of slave chips through an SPI bus according to an embodiment of the present invention. FIG. 6 is an example of a protocol for writing registers of a plurality of slave chips using an SPI interface in a multi-chip system according to an embodiment of the present invention; 6 is a flowchart illustrating an operation sequence of interface protocol decoding of each slave chip during a register 'write' operation according to an embodiment of the present invention. 5 is a flowchart illustrating a register 'read' operation sequence according to an exemplary embodiment of the present invention.

  Hereinafter, some embodiments of the present invention will be described in detail through exemplary drawings. In adding reference numerals to the components of each drawing, it should be noted that the same components are given the same reference numerals as much as possible even if they are displayed on different drawings. I must. In the description of the present invention, if it is determined that a specific description of a related known configuration or function can obscure the gist of the present invention, a detailed description thereof will be omitted.

  Throughout the specification, when a part “includes” or “comprises” a component, this does not exclude other components, unless specifically stated to the contrary, It can be further included. In addition, terms such as '...' and 'module' described in the specification mean a unit for processing at least one function or operation, and this means that hardware, software, or hardware and software are connected. It can be realized by combination.

A multi-chip system according to an embodiment of the present invention includes two or more slave chips having the same function and a master chip for controlling the slave chips. Each slave chip includes a fixed chip ID and a common chip. ID is assigned. The fixed chip ID of the slave chip is a physical chip ID generally determined by several pins, and the common chip ID may be a logical chip ID commonly assigned to each slave chip. The master chip drives the system by controlling the registers of each slave chip using a general-purpose interface method such as I ² C (Inter Integrated Circuit) or SPI (Serial Peripheral Interface). In particular, according to an embodiment of the present invention, the master chip not only sets a register to each desired slave chip using a fixed chip ID, but also uses a common chip ID during a register 'write' operation of the slave chip. Register can be set to all slave chips at the same time.

Hereinafter, a register setting operation according to an embodiment of the present invention in a multi-chip system to which the I ² C interface is applied will be described with reference to FIGS.

FIG. 2 is a diagram illustrating a multi-chip in which a master chip is connected to a plurality of slave chips through an I ² C bus according to an embodiment of the present invention.

The I ² C interface is a synchronous communication standard developed by Philips for communication applications between microprocessors and low-speed peripheral devices. The I ² C bus includes SCL (Serial Clock) and SDA (Serial Data), which are bidirectional open drain (Open Drain) lines, and each node operates in a master-slave (Master-Slave) form.

SCL is a clock line for synchronization of communication, and SDA is a data line. The master chip outputs a clock for synchronization to the SCL, and the slave chip outputs or inputs data via the SDA in accordance with the clock output to the SCL. Since data is exchanged with only one SDA line, the I ² C bus can only perform half-duplex communication. Since both the SCL line and the SDA line are open drains, a pull-up resistor (Pull-up Resistor) must be connected to each of the two lines.

All I ² C master chips and SCLs of slave chips are connected to each other, and SDA is also connected to each other. That is, all devices share SCL and SDA.

Since SCL and SDA are both open drain, SCL and SDA of all devices are connected by wired AND (Wired-AND). In wired AND connection, when any one chip outputs “0”, the state of the corresponding signal becomes logic “0”. If any chip connected to SCL or SDA outputs a logic '0', there is no way that another chip can set the signal state to a logic '1'. Therefore, each chip that is connected to the I ² C bus but is not currently participating in communication must maintain its output in a floating state.

The format of the data packet used in the I ² C bus is a 9-bit form including ACK, and becomes a basic unit of communication through the I ² C interface. The master chip changes the SDA to “0” when both the SCL and SDA are “1”, that is, notifies the start of communication while outputting the start condition. After the start condition, the logical value of SDA changes only in the section where the SCL state is “0”. In synchronization with the clock output from the master chip to the SCL, data is output from the MSB bit by bit to the SDA. The SCL is always a signal output by the master chip, but the SDA can be the output of the master chip or slave chip depending on whether the current operation is a master 'read' or 'write'.

The means for the master chip to distinguish each slave chip on the I ² C bus is a fixed chip ID of the slave chip. All I ² C slave chips have a fixed chip ID, and the master chip designates a desired slave chip by such a fixed chip ID. Since the length of the fixed chip ID is usually 7 bits, in this case, the master chip can be connected to a maximum of 128 slave chip devices. In the multi-chip system according to an embodiment of the present invention, in addition to such a fixed chip ID being assigned to each slave chip, a common chip ID is commonly assigned to all slave chips.

Hereinafter, with reference to FIG. 3, a method in which the I ² C master chip designates the chip ID of the slave chip and exchanges data will be described.

FIG. 3 is an example of a protocol for writing registers of a plurality of slave chips using the I ² C interface in the multi-chip system according to the embodiment of the present invention.

  The master chip outputs the 7-bit chip ID of the slave chip following the start condition. When the same data is written to the same address on the register for all slave chips, the master chip outputs a common chip ID. Further, when writing another address and / or other data on the register for each slave chip, the master chip outputs a fixed chip ID assigned to each slave chip.

  All slave chips connected to the bus check whether the chip ID output by the master chip matches their fixed chip ID or common chip ID while continuously monitoring the SDA line. When the chip ID output by the master chip matches the fixed chip ID of any slave chip, the slave chip outputs “0” to the ACK bit and responds to the master chip. When the chip ID output by the master chip matches the common chip ID assigned to all the slave chips, only one promised slave chip is designed to output “0” to the ACK bit. This is to prevent ACK bit collision that may occur when all slave chips output '0' to the ACK bit. If there is no slave chip having a chip ID output by the master chip, none of them outputs “0” to the ACK bit, so the state of the ACK bit is maintained at “1”, and the master chip is NACK (No Acknowledgment). To receive.

  The eighth bit (R / W Indicator) following the 7-bit chip ID indicates whether the next operation is “read” or “write” of the master chip.

  If the master chip outputs 0 at this bit, this means a “write” operation of the master chip, so the next 1-byte data of the slave chip ID is the output of the master chip. Since this data is for a slave chip whose chip ID is designated by the master chip, the slave chip (all slave chips in the case of a common chip ID) reads this value. That is, as shown in FIG. 3, in the “write” operation, the master chip outputs “CMD” including the slave chip ID and the R / W Indicator (bit value = 0), and then accesses the address of the register to be accessed ( 3 (ADDR) in FIG. 3 and data (“DATA” in FIG. 3) written to the corresponding address are sequentially output.

  On the other hand, if the 8th bit following the 7-bit chip ID is 1, this means that the next operation is a 'read' of the master chip. Therefore, the slave chip whose fixed chip ID is designated by the master chip responds to ACK, and then outputs data to be sent to the master chip. On the other hand, since the master chip 'read' operation is the work that the master chip recognizes the data of each slave chip's 'read' result, it is different from the 'write' operation and should be performed on all slave chips simultaneously. I can't. Therefore, if a common chip ID is transmitted during a 'read' operation, a process of changing the common chip ID to a single chip ID is required so that only one slave chip promised in advance is read. From the standpoint of a slave chip, it will perform a 'read' operation if this matches its fixed chip ID.

  Hereinafter, a register setting operation according to an embodiment of the present invention in a multi-chip system to which an SPI interface is applied will be described with reference to FIGS. 4 and 5. FIG.

  FIG. 4 is a diagram illustrating a multi-chip in which a master chip is connected to a plurality of slave chips through an SPI bus according to an embodiment of the present invention.

The SPI (Serial Peripheral Interconnect) interface is a synchronous communication standard developed by Motorola and capable of full-duplex communication. Similar to I ² C, it operates in a master chip-slave chip system, and the master chip outputs a clock for synchronization. Similar to the I ² C slave chip, each SPI slave chip has a fixed chip ID and a common chip ID.

  As shown in FIG. 4, the signals defined by the SPI bus are the following four signals. SCLK (Serial Clock) is a clock signal for synchronization output from the master chip. Data exchange between the master chip and the slave chip proceeds based on SCLK. MOSI (Master Output Slave Input) is an output of the master chip and is a signal for sending information to the slave chip. On the other hand, MISO (Master Input Slave Output) is an output of the slave chip and is a signal for the master chip to receive the information of the slave chip. As shown in FIG. 4, in the master chip and the slave chip, MOSIs are connected to each other and MISOs are connected to each other. SS is an output of the master chip for the master chip to activate the slave chip, and each slave chip is activated only while the / CE (Chip Enable) input is “0”.

The SCLK, MOSI, and MISO of the master chip and the plurality of slave chips are connected to each other, and / CE of the slave chip is also commonly connected to the SS terminal of the master chip. That is, it is configured in a manner similar to the case of I ² C in FIG.

  In the multi-chip system having such a configuration, when the master chip exchanges data with the slave chip, first, the SS signal is set to “0” to activate all the slave chips. Next, the master chip outputs a clock for synchronization to SLCK, and outputs data bit by bit to MOSI in accordance with this clock. Normally, SPI communication proceeds in units of 8 bits, but there are cases in which a length of 12 bits, 16 bits or more becomes one unit. The data transmission can be started from the MSB (Most Significant Byte) or can be started from the LSB (Least Significant Bit).

  FIG. 5 is an example of a protocol for writing registers of a plurality of slave chips using an SPI interface in a multi-chip system according to an embodiment of the present invention.

Similar to I ² C, in SPI, the master chip first transmits a CMD including other information such as chip ID and R / W Indicator on the MOSI, and then the address of the register to be accessed (ADDR in FIG. 5) and Data (DATA in FIG. 5) written to the corresponding address is sequentially output. Each slave chip additionally receives ADDR and DATA when the transmitted chip ID matches one of its physical chip ID (fixed chip ID) and common chip ID, and the corresponding on the register The corresponding data is written to the address.

The above example is one of various protocols that can be used in a multi-chip system to which an interface such as I ² C or SPC is applied, and a multi-chip system having an interface such as I ² C or SPC. It can be transformed into various methods depending on the application field.

  FIG. 6 is a flowchart illustrating an operation sequence of interface protocol decoding of each slave chip during a register 'write' operation according to an embodiment of the present invention.

  The master chip transmits a common chip idea when writing the same data to all the slave chips at the same address on the register, and assigns each slave chip when writing different data to a different address for each slave chip Transmit the fixed chip ID.

  First, the slave chip receives a chip ID from the master chip according to an interface protocol defined via the bus (S610). Next, the slave chip determines whether the chip ID transmitted from the master chip matches the already allocated common chip ID or its own fixed chip ID (S620). If the transmitted chip ID matches the already allocated common chip ID or the fixed chip ID of the user (Yes in S620), the address and data on the register are received (S630, S640), and the corresponding address is transferred. The “write” operation of the corresponding data is performed (S650). If the transmitted chip ID does not match either the common chip ID or the own fixed chip ID (“NO” in S620), the “write” operation is not performed.

  FIG. 7 is a flowchart illustrating a register 'read' operation sequence according to an embodiment of the present invention.

   Since the “read” operation is an operation in which the master chip recognizes the data of the “read” result of each slave chip, unlike the “write” operation, it cannot be performed simultaneously on all the slave chips. Accordingly, when a chip ID is transmitted from the master chip during the “read” operation (S710), first, it is determined whether the transmitted chip ID is a common chip ID (S720). If the common chip ID is transmitted as a result of the determination (“YES” in S720), the process of changing the common chip ID to a single chip ID so as to perform an operation of reading only one slave chip promised in advance ( S730) is necessary, and the slave chip determines whether this matches the fixed chip ID of its own (S740). If it matches (“Yes” in S740), it receives the address on the register (S750), A “read” operation is performed (S760).

  6 and 7 describe that the respective processes are sequentially executed, but this is merely an illustrative explanation of the technical idea of an embodiment of the present invention. That is, if the person has ordinary knowledge in the technical field to which the embodiment of the present invention belongs, the order shown in FIGS. 6 and 7 is changed without departing from the essential characteristics of the embodiment of the present invention. The present invention can be executed in various ways, or can be modified and modified in various ways by executing one or more processes in parallel.

  The above description is merely illustrative of the technical idea of the present embodiment. Any person having ordinary knowledge in the technical field to which the present embodiment belongs will depart from the essential characteristics of the present embodiment. Various modifications and variations are possible without departing from the scope. Therefore, the present embodiment is not intended to limit the technical idea of the present embodiment, but for explanation, and the scope of the technical idea of the present embodiment is limited by such an embodiment. There is no. The protection scope of this embodiment should be construed according to the following claims, and all technical ideas within the equivalent scope should be construed as being included in the scope of rights of this embodiment. .

Claims (7)

In a multi-chip system comprising a plurality of slave chips and a master chip for controlling the plurality of slave chips,
A common chip ID and a fixed chip ID are set in the plurality of slave chips, and the master chip simultaneously performs a 'write' command to the plurality of slave chips using the common chip ID, and the fixed chip It is configured to individually perform a 'write' command to the plurality of slave chips using an ID ,
When the chip ID output from the master chip matches the common chip ID assigned to all slave chips, only one promised slave chip outputs '0' to the ACK bit. Multi-chip system.   The common chip ID is a logical chip ID commonly assigned to the plurality of slave chips, and the fixed chip ID is a physical chip ID assigned to each of the plurality of slave chips. The multi-chip system according to claim 1, characterized in that it is.   2. The multi-chip according to claim 1, wherein the plurality of slave chips perform the “write” operation when a chip ID used for the command matches a common chip ID or a fixed chip ID of the plurality of slave chips. -Chip system. ^2. The multi-chip system according to claim 1, wherein the master chip and the plurality of slave chips are connected through an I ² C (Inter Integrated Circuit) or SPI (Serial Peripheral Interface) bus.   When connecting via the SPI bus, the plurality of slave chips are simultaneously activated, and then simultaneously output to the plurality of slave chips by outputting a common chip ID and a fixed chip ID to a MOSI (Master Output Slave Input) terminal. The multi-chip system according to claim 4, characterized in that a 'write' operation is commanded.   6. The multi-chip system according to claim 5, wherein an SS (Slave Select) terminal of the master chip is commonly connected to CE (Chip Enable) terminals of the plurality of slave chips. In an operation method of a multi-chip system comprising a plurality of slave chips in which a common chip ID and a fixed chip ID are set, and a master chip that controls the plurality of slave chips,
The master chip commands the plurality of slave chips to perform a “write” operation using the common chip ID or the fixed chip ID; and the plurality of slave chips share the chip ID used for the command. includes; process of performing the 'write' operation when matching the tip IDC or their locking tip IDC
A multi-chip system in which only one promised slave chip outputs '0' to the ACK bit when the chip ID output by the master chip matches the common chip ID assigned to all slave chips in common How it works.