JP5721501B2 - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Semiconductor device and manufacturing method of semiconductor device Download PDF

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JP5721501B2
JP5721501B2 JP2011076966A JP2011076966A JP5721501B2 JP 5721501 B2 JP5721501 B2 JP 5721501B2 JP 2011076966 A JP2011076966 A JP 2011076966A JP 2011076966 A JP2011076966 A JP 2011076966A JP 5721501 B2 JP5721501 B2 JP 5721501B2
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insulating film
metal layer
pad electrode
semiconductor device
bonding
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JP2012212743A (en
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浩之 奥芝
浩之 奥芝
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Kyocera Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78—Apparatus for connecting with wire connectors
    • H01L2224/7825—Means for applying energy, e.g. heating means
    • H01L2224/783—Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301—Capillary
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8512—Aligning
    • H01L2224/85148—Aligning involving movement of a part of the bonding apparatus
    • H01L2224/85169—Aligning involving movement of a part of the bonding apparatus being the upper part of the bonding apparatus, i.e. bonding head, e.g. capillary or wedge
    • H01L2224/8518—Translational movements
    • H01L2224/85181—Translational movements connecting first on the semiconductor or solid-state body, i.e. on-chip, regular stitch

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Description

本発明は、半導体装置および半導体装置の製造方法に関する。   The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

従来、基板の上に積層された複数の半導体層からなる機能素子を有する半導体装置が種々提案されている。半導体装置の一例として、例えばｐｎ接合領域を有する発光部が形成された発光装置が利用されている。例えば、特許文献１に記載された発光装置は、基板の上に積層された複数の半導体層を有する発光部を備え、この発光部が備える素子側電極が、基板上に絶縁膜を介して配置されたボンディング用のパッド電極と接続している。   Conventionally, various semiconductor devices having a functional element composed of a plurality of semiconductor layers stacked on a substrate have been proposed. As an example of a semiconductor device, for example, a light emitting device in which a light emitting portion having a pn junction region is formed is used. For example, a light-emitting device described in Patent Document 1 includes a light-emitting unit having a plurality of semiconductor layers stacked on a substrate, and an element-side electrode included in the light-emitting unit is disposed on the substrate via an insulating film. It is connected to the bonded pad electrode.

特開２０１０−２２６０８５号公報JP 2010-226085 A

近年、例えば発光装置による形成画像の高解像度化の要求に応じ、発光装置における発光部の配置密度が高くなってきている。これにともない、基板上に配置されたパッド電極の配置密度も高くなり、パッド電極の１つ１つの面積は小さくなってきている。   In recent years, for example, according to a demand for higher resolution of a formed image by a light emitting device, the arrangement density of light emitting units in the light emitting device has been increased. Along with this, the arrangement density of pad electrodes arranged on the substrate is also increased, and the area of each pad electrode is becoming smaller.

図６は、従来の発光装置１００のパッド電極の、周辺部分を拡大して示す概略断面図である。従来の発光装置のパッド電極は、ＧａＡｓ等の半導電性基板１０２に、絶縁膜１０４を介してパッド電極１０６が配置された構成となっている。発光装置１００では、パッド電極１０６の上面に、このパッド電極１０６の上面と接合したボンディングボール１１０を備えるボンディングワイヤ１０９が接続されている。ボンディングワイヤ１０９は、ボンディングワイヤ１０９を保持するためのキャピラリ１２０を備えた公知のボンディング装置を用いて、パッド電極１０６と接合される。図６では、ボンディングボール１１０を形成する状態、すなわちボンディング時における、パッド電極１０６とキャピラリ１２０をの位置関係を示すために、ボンディング時におけるキャピラリ１２０の先端部も模式的に示している。   FIG. 6 is a schematic cross-sectional view showing an enlarged peripheral portion of the pad electrode of the conventional light emitting device 100. A pad electrode of a conventional light emitting device has a configuration in which a pad electrode 106 is disposed on a semiconductive substrate 102 such as GaAs via an insulating film 104. In the light emitting device 100, a bonding wire 109 including a bonding ball 110 bonded to the upper surface of the pad electrode 106 is connected to the upper surface of the pad electrode 106. The bonding wire 109 is bonded to the pad electrode 106 using a known bonding apparatus including a capillary 120 for holding the bonding wire 109. In FIG. 6, in order to show the positional relationship between the pad electrode 106 and the capillary 120 when the bonding ball 110 is formed, that is, at the time of bonding, the tip of the capillary 120 at the time of bonding is also schematically shown.

絶縁膜１０４はＳｉＮｘ等からなり、弾性率が比較的高く変形し難い、一方、金属からなるパッド電極１０６は弾性率が比較的低く変形し易い。ボンディング時において、パッド電極１０６および絶縁膜１０４がキャピラリ１２０から受ける衝撃は、主にパッド電極１０６が変形することで緩和される。   The insulating film 104 is made of SiNx or the like and has a relatively high elastic modulus and is hardly deformed. On the other hand, the pad electrode 106 made of a metal has a relatively low elastic modulus and is easily deformed. During bonding, the impact that the pad electrode 106 and the insulating film 104 receive from the capillary 120 is mitigated mainly by deformation of the pad electrode 106.

しかしながら、上述のように、パッド電極１０６の配置密度が高まってパッド電極１０６の面積が小さくなると、ボンディングワイヤ１０９の接合時における、キャピラリ１２０の先端部分のパッド電極１０６に対する当接位置が、パッド電極１０６の周縁部分に近くなる。キャピラリ１２０の先端部分の当接位置が、パッド電極１０６の周縁部分に近づくほど、ボンディング時におけるキャピラリ１２０からの衝撃によって変形する、パッド電極１０６の面積が小さくなり、ボンディング時の衝撃が、ＳｉＮｘ等からなる絶縁膜に大きく伝わり易い。   However, as described above, when the arrangement density of the pad electrodes 106 is increased and the area of the pad electrodes 106 is reduced, the contact position of the tip portion of the capillary 120 with the pad electrode 106 at the time of bonding of the bonding wire 109 is changed to the pad electrode. It becomes close to the peripheral portion of 106. The closer the contact position of the tip of the capillary 120 is to the peripheral portion of the pad electrode 106, the smaller the area of the pad electrode 106 that is deformed by the impact from the capillary 120 during bonding, and the impact during bonding is SiNx or the like. It is easily transmitted to the insulating film made of

このため、近年の高密度配置のパッド電極１０６を有する半導体装置では、ボンディング時の衝撃によって絶縁膜１０６にクラック等の欠陥が生じ、電流リークによる動作不良が発生し易いといった課題があった。また、発光にともなうボンディングボール１１０の
温度変化によって、ボンディングボール１１０が膨張・収縮した場合、ボンディングボール１１０がパッド電極１０６を引き伸ばしたり、縮めたりする力が働くが、キャピラリ１２０の先端部分の当接位置が、パッド電極１０６のエッジに近くなると、この力が大きくなり、パッド電極１０６の剥がれが発生し易いといった課題もあった。 For this reason, a semiconductor device having the pad electrodes 106 arranged at a high density in recent years has a problem that defects such as cracks occur in the insulating film 106 due to an impact during bonding, and an operation failure due to current leakage is likely to occur. Further, when the bonding ball 110 expands / contracts due to a temperature change of the bonding ball 110 due to light emission, the bonding ball 110 exerts a force to expand or contract the pad electrode 106, but the tip of the capillary 120 abuts. When the position is close to the edge of the pad electrode 106, this force is increased, and there is a problem that the pad electrode 106 is easily peeled off.

本発明は、上記の課題を鑑みてなされたものである。   The present invention has been made in view of the above problems.

上記課題を解決するために、本発明は、導電性基板と、前記導電性基板の一方主面に積層された複数の半導体層からなる半導体素子部と、前記導電性基板の前記一方主面の少なくとも一部を覆う第１絶縁膜と、前記第１絶縁膜上に配置された、前記半導体素子部に電気的に接続されたパッド電極と、前記パッド電極の上面に接合したボンディングボールを備える、前記半導体素子部に電力を供給するためのボンディングワイヤとを有する半導体装置であって、前記パッド電極の周辺領域で前記第１絶縁膜を被覆する第２絶縁膜をさらに備え、前記第２絶縁膜は、前記第１絶縁膜の前記周辺領域から前記パッド電極の側面のうち前記第１絶縁膜側の一部領域にかけて連続して被覆している被覆部分と、前記被覆部分に連なって前記パッド電極の前記側面から内部に入り込んで延在している延在部分とを備え、前記延在部分の少なくとも一部が、前記ボンディングボールの下方に位置していることを特徴とする半導体装置を提供する。   In order to solve the above-described problems, the present invention provides a conductive substrate, a semiconductor element portion composed of a plurality of semiconductor layers stacked on one main surface of the conductive substrate, and the one main surface of the conductive substrate. A first insulating film covering at least a portion; a pad electrode disposed on the first insulating film and electrically connected to the semiconductor element portion; and a bonding ball bonded to the upper surface of the pad electrode. A semiconductor device having a bonding wire for supplying power to the semiconductor element portion, further comprising a second insulating film covering the first insulating film in a peripheral region of the pad electrode, and the second insulating film A covering portion continuously covering from the peripheral region of the first insulating film to a partial region of the side surface of the pad electrode on the first insulating film side, and the pad electrode connected to the covering portion. of And a extended portion extending enters the inside from the serial side, at least a portion of the extending portion, to provide a semiconductor device which is characterized in that located below the bonding ball.

また、導電性基板の一方主面に複数の半導体層を積層して半導体素子部を形成する工程と、前記導電性基板の前記一方主面の少なくとも一部を覆う第１絶縁膜を形成する工程と、
前記第１絶縁膜上に、配線導体層を介して前記半導体素子部に接続された第１金属層を形成する工程と、前記第１金属層の周辺領域の前記第１絶縁膜の上面から前記第１金属層の側面を経て前記第１金属層の上面の周縁部分にかけて延在する第２絶縁膜を形成する工程と、前記第１金属層の前記上面に、周縁部分の前記第２絶縁膜も覆うように第２金属層を形成する工程と、前記半導体素子部に電力を供給するためのボンディングワイヤを前記第２金属層の上面に、ボンディングボールの接合面の外周が前記周縁部分の前記第２絶縁膜の上方に位置するように接合する工程とを有することを特徴とする半導体装置の製造方法を、併せて提供する。 Also, a step of forming a semiconductor element portion by stacking a plurality of semiconductor layers on one main surface of the conductive substrate, and a step of forming a first insulating film covering at least a part of the one main surface of the conductive substrate When,
Forming a first metal layer connected to the semiconductor element portion via a wiring conductor layer on the first insulating film; and from an upper surface of the first insulating film in a peripheral region of the first metal layer. Forming a second insulating film extending from the side surface of the first metal layer to a peripheral portion of the upper surface of the first metal layer; and the second insulating film of the peripheral portion on the upper surface of the first metal layer. Forming a second metal layer so as to cover the surface, a bonding wire for supplying electric power to the semiconductor element portion on the upper surface of the second metal layer, and an outer periphery of the bonding surface of the bonding ball on the peripheral portion. And a step of bonding so as to be positioned above the second insulating film. A method for manufacturing a semiconductor device is also provided.

本発明によれば、パッド電極層の剥がれを抑制することができるとともに、絶縁膜の損傷にともなう絶縁破壊を低減することができる。   According to the present invention, it is possible to suppress peeling of the pad electrode layer and to reduce dielectric breakdown due to damage to the insulating film.

本発明の半導体装置の一実施形態の概略平面図である。1 is a schematic plan view of an embodiment of a semiconductor device of the present invention. 図１に示す発光装置の概略断面図である。It is a schematic sectional drawing of the light-emitting device shown in FIG. 図１に示す発光装置の概略断面図であり、図２とは異なる方向から見た図である。FIG. 3 is a schematic cross-sectional view of the light emitting device shown in FIG. 1 and is a view seen from a direction different from FIG. 図１に示す発光装置のパッド電極の周辺を拡大して示す概略断面図であり、図３と同じ方向から見た図である。FIG. 4 is a schematic cross-sectional view showing an enlarged periphery of a pad electrode of the light emitting device shown in FIG. 1 and is a view seen from the same direction as FIG. 3. 本発明の半導体装置の製造方法の一実施形態について説明する概略断面図である。It is a schematic sectional drawing explaining one Embodiment of the manufacturing method of the semiconductor device of this invention. 従来の半導体装置の一実施形態について説明する概略断面図である。It is a schematic sectional drawing explaining one Embodiment of the conventional semiconductor device.

以下、本発明に係る半導体装置の一実施形態として発光装置を例示し、図面を参照しつつ説明する。なお、図面中、同一の要素には同一の符号を付し、重複する説明を省略する
。また、図面の寸法比率は、図示の比率に限定されるものではない。また、以下の実施の形態は、本発明を説明するための例示であり、本発明をその実施の形態のみに限定する趣旨ではない。さらに、本発明は、その要旨を逸脱しない限り、さまざまな変形が可能である。 Hereinafter, a light-emitting device will be exemplified as an embodiment of a semiconductor device according to the present invention and described with reference to the drawings. In the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted. Further, the dimensional ratios in the drawings are not limited to the illustrated ratios. Further, the following embodiments are exemplifications for explaining the present invention, and are not intended to limit the present invention only to the embodiments. Furthermore, the present invention can be variously modified without departing from the gist thereof.

図１は、本実施形態の発光装置１の概略平面図である。図１に示したように、本実施形態に係る発光装置１は、基板３と、基板３の上に列をなして設けられている複数の発光部５と、各発光部５に接続されている表面電極層７と、を備えている。   FIG. 1 is a schematic plan view of a light emitting device 1 according to the present embodiment. As shown in FIG. 1, the light emitting device 1 according to the present embodiment is connected to a substrate 3, a plurality of light emitting units 5 provided in a row on the substrate 3, and each light emitting unit 5. The surface electrode layer 7 is provided.

基板３は、砒化ガリウム（ＧａＡｓ）からなっており、ｎ型の導電性を有している。この基板３には、例えばｎ型の不純物であるシリコン（Ｓｉ）が１×１０１７〜１×１０１９〔ａｔｏｍｓ／ｃｍ３〕の範囲の濃度でドーピングされている。このｎ型の不純物としては、Ｓｉの他に、例えばゲルマニウム（Ｇｅ）、セレン（Ｓｅ）、テルル（Ｔｅ）などのＩＶ族、ＶＩ族の元素が挙げられる。また、基板３は、厚さが例えば１００〜３５０〔μｍ〕の範囲とされる。 The substrate 3 is made of gallium arsenide (GaAs) and has n-type conductivity. The substrate 3 is doped with, for example, silicon (Si) as an n-type impurity at a concentration in the range of 1 × 10 17 to 1 × 10 19 [atoms / cm 3 ]. Examples of the n-type impurity include elements of Group IV and Group VI such as germanium (Ge), selenium (Se), and tellurium (Te) in addition to Si. The substrate 3 has a thickness in the range of, for example, 100 to 350 [μm].

図２および図３は、発光装置１の概略断面図であり、図２は図１に示すＩＩ−ＩＩ線に沿った断面、図３は図１に示すＩＩＩ−ＩＩＩ線に沿った断面それぞれ示している。また、図４は、パッド電極７ａの周辺を拡大して示す概略断面図であり、図１に示すＩＶ−ＩＶ線に沿った断面である、。各発光部５は、図２、３に示したように、基板３の上に設けられている第１の積層領域Ｓ１と、第１の積層領域Ｓ１の上に設けられている第２の積層領域Ｓ２と、を備えている。この第１の積層領域Ｓ１は、ｎ型クラッド層９と、活性層１１とが順次積層されている。この第２の積層領域Ｓ２は、ｐ型クラッド層１３と、コンタクト層１５とが順次積層されている。   2 and 3 are schematic cross-sectional views of the light emitting device 1. FIG. 2 is a cross-sectional view taken along line II-II shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along line III-III shown in FIG. ing. FIG. 4 is a schematic cross-sectional view showing the periphery of the pad electrode 7a in an enlarged manner, and is a cross section taken along line IV-IV shown in FIG. As shown in FIGS. 2 and 3, each light emitting unit 5 includes a first stacked region S1 provided on the substrate 3 and a second stacked region provided on the first stacked region S1. Region S2. In the first stacked region S1, an n-type cladding layer 9 and an active layer 11 are sequentially stacked. In the second stacked region S2, the p-type cladding layer 13 and the contact layer 15 are sequentially stacked.

第１の積層領域Ｓ１を構成するｎ型クラッド層９は、基板３の上面に設けられている。このｎ型クラッド層９は、アルミニウムインジウム燐（ＡｌＩｎＰ）からなっており、ｎ型の導電性を有している。このｎ型クラッド層９は、例えばｎ型の不純物であるＳｉが１×１０１７〜１×１０１９〔ａｔｏｍｓ／ｃｍ３〕の範囲の濃度でドーピングされている。このｎ型の不純物としては、Ｓｉの他に、例えばＧｅ、Ｓｎ、Ｓｅ、ＴｅなどのＩＶ族、ＶＩ族の元素が挙げられる。また、ｎ型クラッド層９は、厚さが例えば０．４〜１〔μｍ〕の範囲とされる。 The n-type cladding layer 9 constituting the first stacked region S <b> 1 is provided on the upper surface of the substrate 3. The n-type cladding layer 9 is made of aluminum indium phosphide (AlInP) and has n-type conductivity. The n-type cladding layer 9 is doped with, for example, Si, which is an n-type impurity, at a concentration in the range of 1 × 10 17 to 1 × 10 19 [atoms / cm 3 ]. Examples of the n-type impurity include elements of Group IV and Group VI such as Ge, Sn, Se, and Te in addition to Si. The n-type cladding layer 9 has a thickness in the range of 0.4 to 1 [μm], for example.

活性層１１は、ｎ型クラッド層９の上面の上に設けられている。この活性層１１は、アルミニウムガリウムインジウム燐（ＡｌＧａＩｎＰ）からなっている。この活性層１１には、不純物がドーピングされていない。この活性層１１は、厚さが例えば０．３〜１〔μｍ〕とされる。   The active layer 11 is provided on the upper surface of the n-type cladding layer 9. The active layer 11 is made of aluminum gallium indium phosphide (AlGaInP). This active layer 11 is not doped with impurities. The active layer 11 has a thickness of, for example, 0.3 to 1 [μm].

第２の積層領域Ｓ２を構成するｐ型クラッド層１３は、ＡｌＩｎＰからなっており、ｐ型の導電性を有している。このｐ型クラッド層１３は、例えばｐ型の不純物である亜鉛（Ｚｎ）が、１×１０１７〜１×１０１９〔ａｔｏｍｓ／ｃｍ３〕の範囲の濃度でドーピングされている。このｐ型の不純物としては、Ｚｎの他に、例えばベリリウム（Ｂｅ）、マグネシウム（Ｍｇ）、カルシウム（Ｃａ）、炭素（Ｃ）などの元素が挙げられる。また、ｐ型クラッド層１３は、厚さが例えば０．４〜１〔μｍ〕の範囲とされる。 The p-type cladding layer 13 constituting the second stacked region S2 is made of AlInP and has p-type conductivity. The p-type cladding layer 13 is doped with, for example, zinc (Zn), which is a p-type impurity, at a concentration in the range of 1 × 10 17 to 1 × 10 19 [atoms / cm 3 ]. Examples of the p-type impurity include elements such as beryllium (Be), magnesium (Mg), calcium (Ca), and carbon (C) in addition to Zn. The p-type cladding layer 13 has a thickness in the range of 0.4 to 1 [μm], for example.

コンタクト層１５は、燐化ガリウム（ＧａＰ）からなっており、ｐ型の導電性を有している。このコンタクト層１５には、例えばｐ型の不純物であるＺｎが、１×１０１７〜１×１０１９〔ａｔｏｍｓ／ｃｍ３〕の範囲の濃度でドーピングされている。このｐ型の不純物としては、Ｚｎの他に、例えばＢｅ、Ｍｇ、Ｃａ、Ｃなどの元素が挙げられる。また、コンタクト層１５は、厚さが例えば０．１〜５〔μｍ〕の範囲とされる。このコンタク
ト層１５は、発光部５の最上層に形成されており、表面電極層７の配線導体部７ｂが接続されている。 The contact layer 15 is made of gallium phosphide (GaP) and has p-type conductivity. The contact layer 15 is doped with, for example, Zn, which is a p-type impurity, at a concentration in the range of 1 × 10 17 to 1 × 10 19 [atoms / cm 3 ]. Examples of the p-type impurity include elements such as Be, Mg, Ca, and C in addition to Zn. The contact layer 15 has a thickness in the range of 0.1 to 5 [μm], for example. The contact layer 15 is formed on the uppermost layer of the light emitting portion 5, and is connected to the wiring conductor portion 7 b of the surface electrode layer 7.

図４に示したように、発光部５が積層された基板３の上面側は、第１絶縁膜１７と、第１絶縁膜１７の上に設けられた第２絶縁膜１９とによって被覆されている。この第１絶縁膜１７および第２絶縁膜１９はいずれも、電気絶縁性および透光性を有するＳｉＮなどからなる。第２絶縁膜１９は、表面電極７のパッド電極７ａの周辺を覆うとともに、パッド電極７ａの側面の一部を被覆している。第２絶縁膜１９を含めたパッド電極７ａの周辺部分の構成については、後に詳述する。なお、第１絶縁膜１７は、コンタクト層１５の上面に貫通孔１７ａが設けられている。この貫通孔１７ａを介し、表面電極７の配線導体部７ｂがコンタクト層１５の上面に接続されている。なお、図１では、説明の便宜上、第１絶縁膜１７および第２絶縁膜１９については図示していない。   As shown in FIG. 4, the upper surface side of the substrate 3 on which the light emitting unit 5 is stacked is covered with a first insulating film 17 and a second insulating film 19 provided on the first insulating film 17. Yes. Both the first insulating film 17 and the second insulating film 19 are made of SiN having electrical insulating properties and translucency. The second insulating film 19 covers the periphery of the pad electrode 7a of the surface electrode 7 and covers part of the side surface of the pad electrode 7a. The configuration of the peripheral portion of the pad electrode 7a including the second insulating film 19 will be described in detail later. The first insulating film 17 is provided with a through hole 17 a on the upper surface of the contact layer 15. The wiring conductor portion 7 b of the surface electrode 7 is connected to the upper surface of the contact layer 15 through the through hole 17 a. In FIG. 1, the first insulating film 17 and the second insulating film 19 are not shown for convenience of explanation.

図１に示した表面電極７は、基板３を被覆する第１絶縁膜１７（図１において不図示）の上に設けられており、パッド電極７ａと、配線導体部７ｂとを有している。このパッド電極７ａは複数設けられており、千鳥状に配置されている。この配線導体部７ｂは、発光部５とパッド電極７ａとを接続している。図２に示したように、配線導体部７ｂは、第１絶縁膜１７に形成された貫通孔１７ａを介して、発光部５のコンタクト層１５の上面に接続されている。この配線導体部７ｂは、コンタクト層１５の上面から発光部５の側面の上を介して基板３の上に引き出されている。より詳細には、この配線導体部７ｂは、コンタクト層１５の上面から、該コンタクト層１５およびｐ型クラッド層１３からなる第２の積層領域Ｓ２の側面の上を介して第１の積層領域Ｓ１の上面の上に引き出されている。さらに、この第１の積層領域Ｓ１の上面の上に引き出された配線導体部７ｂは、活性層１１およびｎ型クラッド層９からなる第１の積層領域Ｓ１の上面および側面の上を介して基板３の上面の上に引き出されている。この基板３の上面の上に引き出され配線導体部７ｂまで延在してパッド電極７ａと接続している。このパッド電極７ａおよび配線導体部７ｂによって構成される表面電極７は、例えば厚さが２５０〔Å〕程度のＣｒ層と、厚さが１〔μｍ〕程度のＡｕ層との積層体で形成することができる。   The surface electrode 7 shown in FIG. 1 is provided on a first insulating film 17 (not shown in FIG. 1) covering the substrate 3, and has a pad electrode 7a and a wiring conductor portion 7b. . A plurality of pad electrodes 7a are provided and arranged in a staggered manner. The wiring conductor portion 7b connects the light emitting portion 5 and the pad electrode 7a. As shown in FIG. 2, the wiring conductor portion 7 b is connected to the upper surface of the contact layer 15 of the light emitting portion 5 through the through hole 17 a formed in the first insulating film 17. The wiring conductor portion 7 b is drawn on the substrate 3 from the upper surface of the contact layer 15 via the side surface of the light emitting portion 5. More specifically, the wiring conductor portion 7b is connected to the first stacked region S1 from the upper surface of the contact layer 15 through the side surface of the second stacked region S2 made of the contact layer 15 and the p-type cladding layer 13. Is pulled out over the top surface. Further, the wiring conductor portion 7b drawn on the upper surface of the first laminated region S1 is formed on the substrate via the upper surface and side surfaces of the first laminated region S1 including the active layer 11 and the n-type cladding layer 9. 3 is pulled out on the top surface of 3. It is drawn on the upper surface of the substrate 3 and extends to the wiring conductor portion 7b to be connected to the pad electrode 7a. The surface electrode 7 constituted by the pad electrode 7a and the wiring conductor portion 7b is formed, for example, by a laminate of a Cr layer having a thickness of about 250 [Å] and an Au layer having a thickness of about 1 [μm]. be able to.

図２、３に示したように、基板３は、発光部５が形成されている上面と反対側の底面の上に、当該底面の全体に亘って裏面電極２９が形成されている。この裏面電極２９は、例えば厚さが２５０〔Å〕程度のＣｒ層と、厚さが５００〜１０００〔Å〕程度のＡｕおよびＧｅの合金層と、厚さが２５０〔Å〕程度のＣｒ層と、厚さが１〔μｍ〕程度のＡｕ層との積層体で形成することができる。   As shown in FIGS. 2 and 3, the substrate 3 has a back electrode 29 formed over the entire bottom surface on the bottom surface opposite to the top surface on which the light emitting unit 5 is formed. The back electrode 29 includes, for example, a Cr layer having a thickness of about 250 [Å], an Au and Ge alloy layer having a thickness of about 500 to 1000 [Å], and a Cr layer having a thickness of about 250 [Å]. And a laminated body with an Au layer having a thickness of about 1 [μm].

パッド電極７ａの上面には、パッド電極７ａの上面と接合したボンディングボール２２を備える、発光部５に電流を供給するためのボンディングワイヤ２４が接続されている。ボンディングワイヤ２４の他方は、図示しない外部の駆動回路等と接続されており、駆動回路からボンディングワイヤ２４を介して発光部５に電流が供給される。上述のように構成された発光装置１は、表面電極７と裏面電極２９との間に順方向電圧を印加することで、発光部５に電流が供給され、活性層１１が発光する。   A bonding wire 24 is connected to the upper surface of the pad electrode 7a, and includes a bonding ball 22 bonded to the upper surface of the pad electrode 7a. The other side of the bonding wire 24 is connected to an external drive circuit or the like (not shown), and current is supplied from the drive circuit to the light emitting unit 5 through the bonding wire 24. In the light emitting device 1 configured as described above, a forward voltage is applied between the front surface electrode 7 and the back surface electrode 29, whereby a current is supplied to the light emitting unit 5 and the active layer 11 emits light.

本実施形態では、パッド電極７ａは、第１金属層４１と第２金属層４２とが積層されて構成されている。図４に示すように、発光装置１は、パッド電極７ａの周辺から、パッド電極７ａの側面３１の第１絶縁膜１７側の一部領域（側面部分４５）にかけて連続した、第１絶縁膜１７上に一部が積層した第２絶縁膜１９を備えている。図４に示すように、第２絶縁膜１９は、第１絶縁膜１７のパッド電極７ａの周辺領域から、パッド電極７ａの側面部分４５にかけて連続して被覆している被覆部分３１と、被覆部分３１に連なってパッド電極７ａの側面から内部に入り込んで延在している延在部分３２とを備えている。   In the present embodiment, the pad electrode 7 a is configured by laminating a first metal layer 41 and a second metal layer 42. As shown in FIG. 4, the light emitting device 1 includes the first insulating film 17 that is continuous from the periphery of the pad electrode 7a to a partial region (side surface portion 45) on the side of the first insulating film 17 on the side surface 31 of the pad electrode 7a. A second insulating film 19 partially laminated thereon is provided. As shown in FIG. 4, the second insulating film 19 includes a covering portion 31 that continuously covers from the peripheral region of the pad electrode 7a of the first insulating film 17 to the side surface portion 45 of the pad electrode 7a, and a covering portion. 31 and an extending portion 32 extending into the inside from the side surface of the pad electrode 7a.

発光装置１では、延在部分３２の少なくとも一部が、ボンディングボール２２の下方に位置している。すなわち、基板３に垂直な方向からの平面視において、延在部分３２は、ボンディングボール２２に重なる位置まで、パッド電極７ａ内に入り込んでいる。これにより、ボンディングボール２２の下方には、パッド電極７ａを構成する第１金属層４１と、第１金属層４１に積層した第２絶縁膜１９（の延在部分３２）と、第２絶縁膜の上に積層した第２金属層４２とが積層した領域が配置された状態となっている。   In the light emitting device 1, at least a part of the extended portion 32 is located below the bonding ball 22. That is, in a plan view from a direction perpendicular to the substrate 3, the extended portion 32 enters the pad electrode 7 a up to a position overlapping the bonding ball 22. Thereby, below the bonding ball 22, the first metal layer 41 constituting the pad electrode 7 a, the second insulating film 19 (extending portion 32) laminated on the first metal layer 41, and the second insulating film A region in which the second metal layer 42 laminated on is laminated.

図１に示すように、発光装置１は、複数のパッド電極７ａが比較的高密度に配置されており、１つ１つのパッド電極７ａの上面は比較的小さくなっている。このため、発光装置１では、ボンディングボール２２の最大外接円２２Ｓの一部が、パッド電極７ａの最大外接円７Ｓに対して、パッド電極７ａよりも外側に位置する部分がある。ボンディングボール２２の最大外接円２２Ｓとは、基板３の主面に平行な仮想平面による、ボンディングボール２２の断面形状における外接円のうち、その半径が最大となるものという。同様に、パッド電極７ａの最大外接円７Ｓとは、基板３の主面に平行な仮想平面による、パッド電極７ａの断面形状における外接円のうち、その半径が最大となるものという。発光装置１は、例えば１２００ｄｐｉ規格の画像形成に用いられ、発光部５の中心位置同士の間隔（配列ピッチ）は、２１．１５μｍと非常に小さく、パッド電極７ａの最大外接円７Ｓの直径は、５０μｍ〜６０μｍとされている。   As shown in FIG. 1, in the light emitting device 1, a plurality of pad electrodes 7a are arranged at a relatively high density, and the upper surface of each pad electrode 7a is relatively small. For this reason, in the light emitting device 1, a part of the maximum circumscribed circle 22S of the bonding ball 22 is located outside the pad electrode 7a with respect to the maximum circumscribed circle 7S of the pad electrode 7a. The maximum circumscribed circle 22S of the bonding ball 22 is said to have the largest radius among the circumscribed circles in the cross-sectional shape of the bonding ball 22 by a virtual plane parallel to the main surface of the substrate 3. Similarly, the maximum circumscribed circle 7S of the pad electrode 7a is said to have the largest radius among the circumscribed circles in the cross-sectional shape of the pad electrode 7a by a virtual plane parallel to the main surface of the substrate 3. The light emitting device 1 is used for, for example, 1200 dpi standard image formation, and the distance (arrangement pitch) between the center positions of the light emitting portions 5 is as very small as 21.15 μm, and the diameter of the maximum circumscribed circle 7S of the pad electrode 7a is 50 μm to 60 μm.

ボンディングボール２２は、発光部の発熱や周辺温度の変動にともなって温度が変化することで、膨張または収縮する。発光装置１では、この膨張や収縮にともなう応力が、パッド電極７ａの側面３１の図中上側部分に直接的に作用する。例えば、ボンディングボール２２が収縮する際、パッド電極７ａを第１絶縁膜１７から引き剥がす方向の力が、パッド電極７ａの側面３１の側から働く。発光装置１では、パッド電極７ａの側面３１近傍に、パッド電極７ａを構成する第１金属層４１と、第１金属層４１に積層した第２絶縁膜１９と、第２絶縁膜の上に積層した第２金属層４２とからなる積層構造が配置されている。このため、ボンディングボール２２の温度変化にともなう応力がパッド電極７ａに働いた場合も、第２金属層４２と上記延在部分３２との境界部分に応力が集中し、第１絶縁膜１７とパッド電極７ａとの境界部分（すなわち、第１金属層４１と第１絶縁膜１７との接合部分）にかかる応力は、比較的少なくされている。たとえこの応力によって、第２金属層４２と上記延在部分３２との接合部分が剥がれたとしても、第１絶縁膜１７とパッド電極７ａとの接合部分の剥がれは抑制される。   The bonding ball 22 expands or contracts as the temperature changes in accordance with the heat generation of the light emitting part and the change in the ambient temperature. In the light emitting device 1, the stress accompanying the expansion and contraction directly acts on the upper side portion of the side surface 31 of the pad electrode 7a in the drawing. For example, when the bonding ball 22 contracts, a force in the direction of peeling the pad electrode 7a from the first insulating film 17 acts from the side surface 31 side of the pad electrode 7a. In the light emitting device 1, the first metal layer 41 constituting the pad electrode 7a, the second insulating film 19 stacked on the first metal layer 41, and the second insulating film are stacked in the vicinity of the side surface 31 of the pad electrode 7a. A laminated structure including the second metal layer 42 is disposed. For this reason, even when the stress accompanying the temperature change of the bonding ball 22 acts on the pad electrode 7a, the stress concentrates on the boundary portion between the second metal layer 42 and the extending portion 32, and the first insulating film 17 and the pad The stress applied to the boundary portion with the electrode 7a (that is, the joint portion between the first metal layer 41 and the first insulating film 17) is relatively small. Even if the joint portion between the second metal layer 42 and the extended portion 32 is peeled off due to this stress, peeling of the joint portion between the first insulating film 17 and the pad electrode 7a is suppressed.

なお、本実施形態の発光装置１では、パッド電極７ａの側面３１のうち、第２金属層４２に対応する側面部分４７は、第１金属層４１に対応する側面部分４５よりも外側に位置している。この第２金属層４２の側面部分４７を、第１金属層４１の側面部分４５よりも外側に位置させることで、第２金属層４２の上面の面積を比較的大きくとることが可能となっている。これにより、ボンディングの際の微妙な位置ずれに起因する、電極とボンディングワイヤとの接合不良の発生を抑制することができる。   In the light emitting device 1 of the present embodiment, the side surface portion 47 corresponding to the second metal layer 42 of the side surface 31 of the pad electrode 7a is located outside the side surface portion 45 corresponding to the first metal layer 41. ing. By positioning the side surface portion 47 of the second metal layer 42 outside the side surface portion 45 of the first metal layer 41, the area of the upper surface of the second metal layer 42 can be made relatively large. Yes. As a result, it is possible to suppress the occurrence of defective bonding between the electrode and the bonding wire due to a slight positional shift during bonding.

発光装置１は、以下のように作製することができる。   The light emitting device 1 can be manufactured as follows.

図５は、本発明の発光装置の製造方法の一例である、図１に示す発光装置１の製造工程について説明するための図であり、発光装置１のパッド電極７ａ近傍を拡大して示す概略断面図である。   FIG. 5 is a diagram for explaining a manufacturing process of the light-emitting device 1 shown in FIG. 1, which is an example of a method for manufacturing the light-emitting device of the present invention. It is sectional drawing.

まず、基板３の上に、例えば有機金属化学気相成長法（ＭＯＣＶＤ法）等を用いて、ｎ型クラッド層９、活性層１１、ｐ型クラッド層１３、およびコンタクト層１５となる各半導体層９Ｘ、１１Ｘ、１３Ｘ、１５Ｘを順次積層したのち、公知のフォトリソグラフィー法によるエッチング成型を行い、ｎ型クラッド層９、活性層１１、ｐ型クラッド層１３、
およびコンタクト層１５を有する発光部５を形成しておく（発光部５について、図５では図示していない）。 First, each semiconductor layer that becomes the n-type cladding layer 9, the active layer 11, the p-type cladding layer 13, and the contact layer 15 is formed on the substrate 3 using, for example, metal organic chemical vapor deposition (MOCVD). After sequentially laminating 9X, 11X, 13X, and 15X, etching molding by a known photolithography method is performed, and the n-type cladding layer 9, the active layer 11, the p-type cladding layer 13,
And the light emitting part 5 having the contact layer 15 is formed (the light emitting part 5 is not shown in FIG. 5).

続いて、図５（ａ）に示したように、発光部５が形成された基板３の上に化学蒸着法（ＣＶＤ法）などを用いて第１絶縁膜１７を形成する。この際、この第１絶縁膜１７の、発光部５上に、フォトリソグラフィー法などを用いて貫通孔１７ａを形成しておく。   Subsequently, as shown in FIG. 5A, a first insulating film 17 is formed on the substrate 3 on which the light emitting portion 5 is formed by using a chemical vapor deposition method (CVD method) or the like. At this time, a through hole 17a is formed on the light emitting portion 5 of the first insulating film 17 by using a photolithography method or the like.

次いで、第１絶縁膜１７の上にレジスト膜を塗布して、フォトリソグラフィー法によって、所望のパターンを露光、現像した後に、抵抗加熱蒸着法、電子ビーム蒸着法などを用いて、表面電極７を構成する第１金属層４１を形成するための金属層を形成する。そして、リフトオフ法によって、レジスト膜を除去して、図５（ｂ）に示したように第１金属層４１を所定の形状に形成する。   Next, after applying a resist film on the first insulating film 17 and exposing and developing a desired pattern by a photolithography method, the surface electrode 7 is formed by using a resistance heating vapor deposition method, an electron beam vapor deposition method or the like. A metal layer for forming the first metal layer 41 to be formed is formed. Then, the resist film is removed by a lift-off method, and the first metal layer 41 is formed in a predetermined shape as shown in FIG.

続いて、絶縁膜１７が形成された基板３の上に、化学蒸着法（ＣＶＤ法）などを用いて、表面電極７を構成する第２金属層４２を形成するための金属層を形成する。次いで、フォトリソグラフィー法などを用いて、成膜した第２絶縁膜１９をエッチング加工し、第１絶縁膜１７の上面、第１金属層４１の側面、および第１金属層４１の上面の周縁部分を覆う、第２絶縁膜１９を形成する。その後、第２絶縁膜１９の上にレジスト膜を塗布して、フォトリソグラフィー法によって、所望のパターンを露光、現像した後に、抵抗加熱蒸着法、電子ビーム蒸着法などを用いて、第２金属層４２を形成するための金属層を形成する。続いて、リフトオフ法によって、レジスト膜を除去して、第２絶縁膜１９の上記周縁部分に対応する領域の少なくとも一部を覆う、第２金属層４２を形成する（図５（ｃ））。   Subsequently, a metal layer for forming the second metal layer 42 constituting the surface electrode 7 is formed on the substrate 3 on which the insulating film 17 is formed by using a chemical vapor deposition method (CVD method) or the like. Next, the formed second insulating film 19 is etched using a photolithography method or the like, and the upper surface of the first insulating film 17, the side surface of the first metal layer 41, and the peripheral portion of the upper surface of the first metal layer 41. A second insulating film 19 is formed to cover the substrate. Thereafter, a resist film is applied on the second insulating film 19, and a desired pattern is exposed and developed by photolithography, and then the second metal layer is formed by resistance heating vapor deposition, electron beam vapor deposition, or the like. A metal layer for forming 42 is formed. Subsequently, the resist film is removed by a lift-off method to form a second metal layer 42 that covers at least a part of the region corresponding to the peripheral portion of the second insulating film 19 (FIG. 5C).

次に、第２金属層４２が形成されている状態で、全体を加熱処理する。この加熱処理によって、図５（ｄ）に示すように、第２金属層４２の側面部分４７は全体が丸みを帯びた形状になる。この加熱処理によって、側面部分４７の全体を丸みを帯びた形状とすることができ、側面部分４７の特定部分に応力が集中することが抑制できる。この加熱処理では、大気中で全体を３５０℃〜４００℃で、３０分〜６０分かけて加熱した後、１分間に１℃の割合で除々に温度を低減させればよい。   Next, the whole is heat-treated with the second metal layer 42 formed. By this heat treatment, as shown in FIG. 5D, the side surface portion 47 of the second metal layer 42 is entirely rounded. By this heat treatment, the entire side surface portion 47 can be formed into a rounded shape, and stress can be suppressed from concentrating on a specific portion of the side surface portion 47. In this heat treatment, the whole is heated at 350 ° C. to 400 ° C. in the air over 30 minutes to 60 minutes, and then the temperature may be gradually reduced at a rate of 1 ° C. per minute.

次いで、図５（ｅ）に示すように、キャピラリ５０を備えるボンディング装置によって、ボンディングワイヤ２４を第２金属層４２の上面に接合する。このボンディング工程によって、発光装置１では、パッド電極７ａの上面の周縁近くまで、ボンディングボール２２が拡がって配置されている。第２金属層４２の上面は比較的狭く、キャピラリ５０は第２金属層４２の側面の近傍に押圧される。発光装置１では、上述の第２絶縁膜１９の形成工程において、第１金属層４１の側面、および第１金属層４１の上面の周縁部分を覆うように第２絶縁膜１９が形成されているとともに、上述の第２金属層の形成工程において、第２絶縁膜１９の上記周縁部分に対応する領域の少なくとも一部を覆うように、第２金属層４２が形成されている。   Next, as illustrated in FIG. 5E, the bonding wire 24 is bonded to the upper surface of the second metal layer 42 by a bonding apparatus including the capillary 50. By this bonding process, in the light emitting device 1, the bonding balls 22 are arranged so as to extend to near the periphery of the upper surface of the pad electrode 7a. The upper surface of the second metal layer 42 is relatively narrow, and the capillary 50 is pressed near the side surface of the second metal layer 42. In the light emitting device 1, the second insulating film 19 is formed so as to cover the side surface of the first metal layer 41 and the peripheral portion of the upper surface of the first metal layer 41 in the step of forming the second insulating film 19 described above. At the same time, in the second metal layer forming step, the second metal layer 42 is formed so as to cover at least a part of the region corresponding to the peripheral portion of the second insulating film 19.

このため、ボンディング工程においては、キャピラリ５０による押圧力がかかる部分は、第１金属層４１と、第２絶縁膜１９と、第２金属層４２とが重なっている状態となっている。この部分では、第１金属層４１と第２絶縁膜１９と第２金属層４２とが、それぞれ応力緩和層として機能し、キャピラリ５０による応力が、各層および各層同士の接合部分に分散される。これにより、キャピラリ５０による押圧力が、第１金属層４１や第２絶縁膜１９や第２金属層４２のいずれかに集中して作用することが抑制され、各層が破壊されることが抑止されている。発光装置１は、このような工程を経て、作製することができる。   For this reason, in the bonding process, the first metal layer 41, the second insulating film 19, and the second metal layer 42 overlap each other in the portion to which the pressing force by the capillary 50 is applied. In this portion, the first metal layer 41, the second insulating film 19, and the second metal layer 42 function as stress relaxation layers, respectively, and the stress caused by the capillary 50 is distributed to each layer and the junction between the layers. Thereby, it is suppressed that the pressing force by the capillary 50 acts on any one of the first metal layer 41, the second insulating film 19, and the second metal layer 42, and each layer is prevented from being destroyed. ing. The light emitting device 1 can be manufactured through such steps.

本発明の製造方法によれば、ボンディング時における絶縁膜の損傷を抑制し、この絶縁
膜の抑制にともなう絶縁破壊を低減することができる。 According to the manufacturing method of the present invention, damage to the insulating film at the time of bonding can be suppressed, and dielectric breakdown accompanying the suppression of the insulating film can be reduced.

以上、本発明の一実施形態について説明したが、本発明は上記の実施形態に限定されるものではなく、本発明の要旨を逸脱しない限りにおいて種々の変更が可能である。例えば、上記実施形態では、ＧａＰからなるコンタクト層１５を例示しているが、これに限定されるものではない。また、上記実施形態では、パッド電極７ａを、第１金属層４１と第２金属層４２との２層構造で構成したが、電極パッド部は、例えば３層以上の金属層が積層された構造でもよく、また、１つの金属層から構成してもよい。   Although one embodiment of the present invention has been described above, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the present invention. For example, in the above embodiment, the contact layer 15 made of GaP is illustrated, but the present invention is not limited to this. Moreover, in the said embodiment, although the pad electrode 7a was comprised by the 2 layer structure of the 1st metal layer 41 and the 2nd metal layer 42, the electrode pad part is the structure where the metal layer of three or more layers was laminated | stacked, for example Alternatively, it may be composed of one metal layer.

また、上記実施形態では、半導体装置として、発光素子を備える発光装置を例に説明したが、半導体装置としては、発光素子を備える発光装置の他に、受光素子を備える受光装置や、光電変換素子を備える光電変換装置などであってもよく、特に限定されない。   Moreover, in the said embodiment, although demonstrated as an example the light-emitting device provided with a light emitting element as a semiconductor device, as a semiconductor device, in addition to the light-emitting device provided with a light-emitting element, the light-receiving device provided with a light-receiving element, or a photoelectric conversion element It may be a photoelectric conversion device provided with, and is not particularly limited.

３ 基板
５ 発光部
７ 表面電極
７ａ パッド電極
７ｂ 配線導体部
１７ 第１絶縁膜
１９ 第２絶縁膜
２２ ボンディングボール
２２Ｓ 最大外接円
２４ ボンディングワイヤ
４１ 第１金属層
４２ 第２金属層
４５、４７ 側面部分 3 Substrate 5 Light emitting portion 7 Surface electrode 7a Pad electrode 7b Wiring conductor portion 17 First insulating film 19 Second insulating film 22 Bonding ball 22S Maximum circumscribed circle 24 Bonding wire 41 First metal layer 42 Second metal layer 45, 47 Side surface portion

Claims (6)

導電性基板と、
前記導電性基板の一方主面に積層された複数の半導体層からなる半導体素子部と、
前記導電性基板の前記一方主面の少なくとも一部を覆う第１絶縁膜と、
前記第１絶縁膜上に配置された、前記半導体素子部に電気的に接続されたパッド電極と、前記パッド電極の上面に接合したボンディングボールを備える、前記半導体素子部に電力を供給するためのボンディングワイヤと
を有する半導体装置であって、
前記パッド電極の周辺領域で前記第１絶縁膜を被覆する第２絶縁膜をさらに備え、
前記第２絶縁膜は、前記第１絶縁膜の前記周辺領域から前記パッド電極の側面のうち前記第１絶縁膜側の一部領域にかけて連続して被覆している被覆部分と、前記被覆部分に連なって前記パッド電極の前記側面から、前記導電性基板に垂直な方向からの平面視において、前記ボンディングボールに重なる位置まで内部に入り込んで延在している延在部分とを備えていることを特徴とする半導体装置。 A conductive substrate;
A semiconductor element portion comprising a plurality of semiconductor layers laminated on one main surface of the conductive substrate;
A first insulating film covering at least a part of the one main surface of the conductive substrate;
A power supply for supplying power to the semiconductor element unit, comprising: a pad electrode disposed on the first insulating film and electrically connected to the semiconductor element unit; and a bonding ball bonded to the upper surface of the pad electrode. A semiconductor device having a bonding wire,
A second insulating film covering the first insulating film in a peripheral region of the pad electrode;
The second insulating film includes a covering portion continuously covering from the peripheral region of the first insulating film to a partial region of the side surface of the pad electrode on the first insulating film side, and the covering portion. An extended portion that extends from the side surface of the pad electrode to the position overlapping with the bonding ball in a plan view from a direction perpendicular to the conductive substrate. A featured semiconductor device. 前記パッド電極は、前記半導体素子部に配線導体層を介して接続された第１金属層と、前記第１金属層上に積層された第２金属層とを有しており、
前記第２絶縁膜の前記延在部分は、前記第１金属層と前記第２金属層との間に入り込んでいることを特徴とする請求項１記載の半導体装置。 The pad electrode has a first metal layer connected to the semiconductor element part via a wiring conductor layer, and a second metal layer laminated on the first metal layer,
2. The semiconductor device according to claim 1, wherein the extending portion of the second insulating film enters between the first metal layer and the second metal layer. 前記パッド電極の前記側面のうち、前記第１金属層に対応する側面部分は、前記第２金属層に対応する側面部分よりも、前記パッド電極の中央に近い側に位置していることを特徴とする請求項２記載の半導体装置。   Of the side surfaces of the pad electrode, the side surface portion corresponding to the first metal layer is located closer to the center of the pad electrode than the side surface portion corresponding to the second metal layer. The semiconductor device according to claim 2. 前記第２金属層の側面部分は、丸みを帯びている、請求項２または３に記載の半導体装置。 The semiconductor device according to claim 2, wherein a side surface portion of the second metal layer is rounded. 前記半導体素子部は、前記ボンディングワイヤを介して供給された電力によって発光する発光素子部分を備えていることを特徴とする請求項１〜４のいずれかに記載の半導体装置。   The semiconductor device according to claim 1, wherein the semiconductor element portion includes a light emitting element portion that emits light by electric power supplied via the bonding wire. 導電性基板の一方主面に複数の半導体層を積層して半導体素子部を形成する工程と、
前記導電性基板の前記一方主面の少なくとも一部を覆う第１絶縁膜を形成する工程と、
前記第１絶縁膜上に、配線導体層を介して前記半導体素子部に接続された第１金属層を形
成する工程と、
前記第１金属層の周辺領域の前記第１絶縁膜の上面から前記第１金属層の側面を経て前記第１金属層の上面の周縁部分にかけて延在する第２絶縁膜を形成する工程と、
前記第１金属層の前記上面に、周縁部分の前記第２絶縁膜も覆うように第２金属層を形成する工程と、
前記半導体素子部に電力を供給するためのボンディングワイヤを前記第２金属層の上面に、前記導電性基板に垂直な方向からの平面視において、ボンディングボールの接合面の外周が前記周縁部分に重なるように接合する工程と
を有することを特徴とする半導体装置の製造方法。 Forming a semiconductor element portion by stacking a plurality of semiconductor layers on one main surface of the conductive substrate;
Forming a first insulating film covering at least a part of the one main surface of the conductive substrate;
Forming a first metal layer connected to the semiconductor element portion via a wiring conductor layer on the first insulating film;
Forming a second insulating film extending from an upper surface of the first insulating film in a peripheral region of the first metal layer through a side surface of the first metal layer to a peripheral portion of the upper surface of the first metal layer;
Forming a second metal layer on the upper surface of the first metal layer so as to cover the second insulating film in a peripheral portion;
A bonding wire for supplying power to the semiconductor element portion is formed on the upper surface of the second metal layer, and the outer periphery of the bonding surface of the bonding ball overlaps the peripheral portion in a plan view from a direction perpendicular to the conductive substrate. A method of manufacturing a semiconductor device, characterized by comprising:
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