JP5721173B2 - Demodulator and demodulation method - Google Patents

Description

  The present invention relates to a demodulation device and a demodulation method, and more particularly, to a demodulation device and a demodulation method that compensate for a DC offset.

  In a wireless communication system using a digital modulation system, it is known that when a received signal is demodulated, the demodulation operation is greatly affected by the incorporation of a direct current component (DC component). In order to suppress this effect, DC offset removal is performed in related techniques such as Patent Document 1.

  In Patent Document 1 that demodulates an orthogonal modulation signal, an orthogonal signal is extracted from a received signal, a DC offset is cut, and then AD conversion is performed for demodulation.

JP 2007-88983 A

  In a related demodulator such as Patent Document 1, a DC component is cut before AD conversion. For this reason, the frequency component close | similar to the DC component of the signal originally received as transmission data is interrupted | blocked by cut of DC component, and DC offset will generate | occur | produce. As a result, the signal point corresponding to the DC offset is shifted from the ideal signal point of the received signal, which causes a problem that the communication quality deteriorates. In particular, in the digital modulation system, the signal point interval becomes shorter as the number of multi-values increases. Therefore, if a signal point shifts due to a DC offset, the transmission data is shifted from the signal point to be received to the adjacent signal point and erroneously transmitted. As a result, the communication quality was degraded.

  An object of the present invention is to provide a demodulation device and a demodulation method that solve the above-described problems.

  The demodulating device of the present invention includes an orthogonal signal generating unit that generates an analog orthogonal signal from an input signal, a low frequency blocking unit that blocks a low frequency component of the analog orthogonal signal, and an analog orthogonal signal from which the low frequency component is blocked. An A / D converter that converts the signal into a digital quadrature signal, a demodulator that demodulates the digital quadrature signal to generate a quadrature demodulated signal, and detects errors based on the constellation points of the generated quadrature demodulated signal And an offset correction unit that corrects the digital quadrature signal with an offset corresponding to the detected error.

  Also, the demodulation method of the present invention generates an analog quadrature signal from an input signal, blocks the low frequency component of the generated analog quadrature signal, and converts the analog quadrature signal from which the low frequency component is blocked into a digital quadrature signal. Converting, demodulating the converted digital quadrature signal to generate a quadrature demodulated signal, detecting an error based on a constellation point of the generated quadrature demodulated signal, and offset corresponding to the detected error To correct the digital quadrature signal.

  According to the present invention, it is possible to provide a demodulation device and a demodulation method capable of accurately compensating for a DC offset and preventing deterioration of communication quality.

It is the schematic which shows an example of a structure of the demodulation apparatus of this invention. It is a block diagram which shows the structure of the demodulation apparatus concerning Embodiment 1 of this invention. It is a figure which shows the constellation point by the demodulation operation of the demodulation apparatus concerning Embodiment 1 of this invention. It is a figure which shows the constellation point by the demodulation operation of the demodulation apparatus concerning Embodiment 1 of this invention. It is a figure which shows the frequency characteristic of the demodulation apparatus concerning Embodiment 1 of this invention. It is a figure which shows the constellation point by the demodulation operation of the demodulation apparatus concerning Embodiment 1 of this invention. It is a figure which shows the constellation point by the demodulation operation of the demodulation apparatus concerning Embodiment 1 of this invention. It is a figure which shows the constellation point by the demodulation operation of the demodulation apparatus concerning Embodiment 1 of this invention. It is a figure which shows the constellation point by the demodulation operation of the demodulation apparatus concerning Embodiment 1 of this invention. It is a block diagram which shows the structure of the demodulation apparatus concerning Embodiment 2 of this invention.

(Features of the present invention)
Prior to the description of the embodiments of the present invention, the features of the present invention will be outlined with reference to FIG.

  As shown in FIG. 1, the demodulation device 10 of the present invention includes an orthogonal signal generation unit 11, a low frequency cutoff unit 12, an A / D conversion unit 13, a demodulation unit 14, an error detection unit 15, and an offset correction unit 16. ing.

  Then, the quadrature signal generation unit 11 generates an analog quadrature signal from the input signal, the low frequency cut-off unit 12 cuts off the low frequency component of the analog quadrature signal, and the A / D conversion unit 13 cuts off the low frequency component. The demodulated unit 14 converts the generated analog quadrature signal into a digital quadrature signal, the demodulator 14 performs demodulation processing on the digital quadrature signal to generate a quadrature demodulated signal, and the error detector 15 generates a constellation point of the generated quadrature demodulated signal. The main feature of the present invention is that an error based on (signal point) is detected, and the offset correction unit 16 corrects the digital quadrature signal with an offset corresponding to the detected error. A constellation point is a signal point representing an Ich / Qch component of a signal on an IQ coordinate plane.

  According to the demodulating device of the present invention, offset correction is performed on a signal after AD conversion, so that DC offset mixed before AD conversion can be accurately removed. Since the offset is removed based on the constellation point shift of the orthogonal demodulated signal, the offset can be removed efficiently and at high speed to prevent deterioration in communication quality.

(Embodiment 1 of the present invention)
Next, Embodiment 1 of the present invention will be described in detail with reference to the drawings. FIG. 2 shows a configuration of demodulating apparatus 100 according to Embodiment 1 of the present invention. Demodulator 100 receives an IF (Intermediate Frequency) signal, performs quadrature demodulation, and outputs an orthogonal Ich / Qch (in-phase / orthogonal channel) signal. The input IF signal is a multilevel orthogonal modulation signal such as QPSK or QAM. Note that the Ich / Qch signal output from the demodulator 100 is further subjected to necessary demodulation and decoding processing such as deinterleaving, QPSK, and QAM demodulation, and is decoded into a data series.

As shown in FIG. 2 , the demodulator 100 includes a quadrature demodulator 110, DC cut capacitors 121 and 122, AD converters 131 and 132, ADC control units 141 and 142, a first complex multiplier 151, a second A complex multiplier 152, an error detection unit 160, a carrier regenerator 170, and an NCO 181 are included. For example, the correspondence relationship with the configuration of FIG. 1 is shown. The quadrature demodulator 110 is the quadrature signal generation unit 11, the DC cut capacitors 121 and 122 are the low-frequency cutoff unit 12, and the AD converters 131 and 132 are A / D conversion units. 13, the first complex multiplier 151 corresponds to the demodulation unit 14, the error detection unit 160 corresponds to the error detection unit 15, the ADC control units 141 and 142, and the second complex multiplier 152 corresponds to the offset correction unit 16, respectively. .

  The quadrature demodulator 110 receives an IF signal, extracts orthogonal Ich / Qch components from the IF signal, and outputs Ich1 and Qch1. That is, an IF signal obtained by frequency-converting an RF (Radio Frequency) signal received by a receiving antenna by band limitation, level adjustment, or the like is input to the quadrature demodulator 110. Then, the quadrature demodulator 110 multiplies the IF signal by the signal obtained by shifting the signal of the transmitter 113 by 90 ° by the shifter circuit 114 by the multiplier 111 to generate Ich1 of the Ich component, and converts the IF signal into the IF signal. On the other hand, the signal from the transmitter 113 is multiplied by the multiplier 112 to generate Qch1 of the Qch component.

  The Ich1 and Qch1 are input to the first complex multiplier 151 via the DC cut capacitors 121 and 122, the AD converters 131 and 132, and the ADC control units 141 and 142. That is, DC cut capacitors 121 and 122 output Ich2 and Qch2 obtained by cutting DC components from Ich1 and Qch1, and AD converters 131 and 132 output Ich2 and Qch2 obtained by cutting DC components to digital Ich3 and Qch3. Convert to

  The DC cut capacitors 121 and 122 have different electrical characteristics for each device such as a mixer, an amplifier, and a filter provided to configure a wireless communication system between the receiving antenna and the quadrature demodulator 110 and the AD converters 131 and 132. DC center voltage). As will be described later, a DC offset is generated by the DC cut capacitor.

  ADCs (Automatic DC offset Canceller) 141 and 142 remove DC offset from digital Ich3 and Qch3 based on error signals Ai2 and Aq2 from second complex multiplier 152, and output Ich4 and Qch4. .

  The first complex multiplier 151 performs complex multiplication on Ich4 and Qch4 from which the DC offset has been removed, and outputs Ich5 and Qch5 that have been subjected to phase rotation control. Ich5 and Qch5 are constellation data indicating constellation points. This complex multiplication is an example of a demodulation operation, and constellation data may be generated by other operations.

  Based on Ich5 and Qch5, feedback control, that is, control of the carrier phase and the like given to the complex multiplier, and control of the offset given to the ADC control unit are performed.

  The error detector 160 performs error calculation on the constellation data of Ich5 and Qch5 based on an error vector with the ideal signal point of the received signal, and the signal point of the signal point due to the DC offset of the constellation data of Ich5 and Qch5 is calculated. The deviation is output as error signals Ai1, Aq1. The error detector 160 also outputs an error signal C1 for carrier reproduction.

  The carrier regenerator 170 has a carrier phase detection function and a loop filter function, and a first complex multiplier 151 and an NCO (Numerical Controlled Oscillator) 181 constitute a carrier reproduction loop. The NCO 181 is a numerically controlled oscillator for the first complex multiplier 151 and the second complex multiplier 152 that changes the frequency and phase according to the input data from the carrier regenerator 170. . That is, the carrier regenerator 170 generates a carrier reproduction control signal C2 based on the error signal C1, and the NCO 181 outputs a carrier signal C3 having a frequency based on the carrier reproduction control signal C2. Based on the carrier signal C3, the first complex multiplier 151 and the second complex multiplier 152 perform complex multiplication.

  The second complex multiplier 152 returns the input error signals Ai1 and Aq1 to the phase before the phase rotation control is performed by the first complex multiplier 151. Phase rotation control in the direction opposite to that of the first complex multiplier 151 is performed, and the error signals Ai2 and Aq2 corrected to the angle before the phase rotation control of the first complex multiplier 151 are sent to the ADC control units 141 and 142. Output.

  The ADC control units 141 and 142 generate ADC control values from the error signals Ai2 and Aq2 corrected to the angle before the phase rotation control input from the second complex multiplier 152, and from the A / D converters 131 and 132. DC offset compensation calculation is performed on input Ich3 and Qch3.

  Next, the demodulation operation of the demodulation device 100 will be described with reference to FIGS. Here, an example of demodulating a QPSK signal will be described.

As shown in FIGS. 3 to 9 , in the demodulator 100, orthogonal component extraction (step 1), DC cut (step 2), complex multiplication processing (step 3), error determination (step 4), and inverse complex multiplication processing are performed. Processing is performed in the order of (Step 5) and offset correction (Step 6). After the offset correction, further complex multiplication is performed.

  First, as shown in FIG. 3, the quadrature demodulator 110 separates and extracts the received IF signal into two orthogonal I / Qch component data, and outputs Ich1 and Qch1 before DC cut ( Step 1).

  Next, as shown in FIG. 4, the DC cut capacitors 121 and 122 cut the DC component from Ich1 and Qch1, and output Ich2 and Qch2 (step 2).

  Here, FIG. 5 shows a frequency characteristic that the DC cut capacitor cuts off. Since the DC cut capacitors 121 and 122 are provided, the frequency component close to the direct current component (DC) of the signal originally received as transmission data (the hatched portion in FIG. 5A) is blocked. A DC offset is generated by the cutoff of the low frequency component. As a result, as shown in FIG. 4, the DC-cut Ich2 and Qch2 are shifted in signal points by DC offset from the ideal signal points Ich1 and Qch1 of the received signal. Therefore, Ich3 and Qch3 obtained by digitally converting Ich2 and Qch2 by the AD converters 131 and 132 are also signals including a DC offset.

  Next, as shown in FIG. 6, the first complex multiplier 151 performs complex multiplication on Ich4 and Qch4 input via the AD converters 131 and 132 and the ADC control units 141 and 142 to obtain Ich5 Qch5 is output (step 3). At this time, the first complex multiplier 151 performs rotational symmetry conversion control on Ich4 and Qch4 input from the ADC control units 141 and 142, and provides phase rotation that gives a rotation in a direction opposite to the phase rotation direction of the received signal. The phase rotation of the reception signal point is stopped by the control. That is, the first complex multiplier 151 performs complex multiplication of Ich4 and Qch4 input from the ADC control units 141 and 142 and the Sin / Cos value input, and in the phase rotation direction of the received signal from the complex multiplication result. On the other hand, phase rotation control in the opposite direction is performed, the phase rotation of the received signal is stopped, and Ich5 and Qch5 are output.

  Next, as shown in FIG. 7, the error detection unit 160 performs error determination on Ich5 and Qch5 (step 4). The error detector 160 obtains an estimated value of the received signal for each constellation data of Ich5 and Qch5 input from the first complex multiplier 151. Specifically, an ideal signal point (reference point) as a signal before AD conversion is obtained by hard-deciding Ich5 and Qch5. Then, an error is detected between the signal points of Ich5 and Qch5 and the obtained hard decision result, a difference vector of the detected errors is calculated, and an error signal Ai1 for each Ich5 and Qch5 constellation data (symbol data) , Aq1 are output to the second complex multiplier 152.

  Next, as shown in FIG. 8, the second complex multiplier 152 performs inverse complex multiplication on the error signals Ai1 and Aq1, and outputs Ai2 and Aq2 (step 5). That is, the second complex multiplier 152 performs phase rotation control in the direction opposite to that of the first complex multiplier 151. The second complex multiplier 152 performs complex multiplication of the error signals Ai1 and Aq1 input from the error detection unit 160 and the Sin / Cos value input. From this complex multiplication result, rotation control is performed to return the error signals Ai1 and Aq1 of Ich / Qch input from the error detection unit 160 to the phase before the phase control by the first complex multiplier 151, Ai2 and Aq2 are output.

  With this rotation control, the rotation phase of the signal for controlling the DC offset compensation performed by the ADC control units 141 and 142 includes the DC offset input from the AD converters 131 and 132 to the ADC control units 141 and 142. The rotation phase is the same as that of Ich3 and Qch3, and ADC control is performed correctly.

  Next, as shown in FIG. 9, the ADC control units 141 and 142 correct the DC offsets of Ich3 and Qch3 based on Ai2 and Aq2 (step 6). In other words, the ADC control units 141 and 142 compensate for the DC offset generated by providing the DC cut capacitors 121 and 122 and the DC offset depending on the transmission pattern.

  The ADC control units 141 and 142 use the error signals Ai2 and Aq2, which are input from the second complex multiplier 152 and corrected to the angle before the phase rotation control of the first complex multiplier 151, for integral control of the integrator. Then, the DC offset correction calculation is performed on Ich3 and Qch3 input from the A / D converters 131 and 132 using the integration result of the integrator as an ADC control value, and the signal point is moved to an ideal point.

  As a result, as shown in FIG. 9, the signal point shifted by the DC offset is returned to the ideal signal point of the received signal, ADC control is performed before carrier synchronization from the shift of the signal point of the received signal, and high speed DC offset compensation control is realized.

  In the present embodiment, by the above operation, ADC control is performed before carrier synchronization from the shift of the signal point of the received signal to realize high-speed DC offset compensation for each received symbol, and high-speed DC offset compensation control is performed on the received signal. This is always performed for I / Qch data, and communication quality deterioration due to DC offset is prevented, and characteristics (bit error rate) can be improved and performance can be improved.

  That is, according to the present invention, it is possible to prevent deterioration in communication quality due to a DC offset generated by blocking a low frequency component by DC cut. In particular, in the present invention, ADC control is performed before carrier synchronization from the shift of the signal point of the received signal to realize high-speed DC offset compensation.

  In the related technology, in order to generate control information of DC offset control, a signal from the AD converter is integrated to extract a DC offset component. However, since the actual DC offset amount is relatively small compared to the amplitude of the signal input to the AD converter, it has been necessary to perform integration over a sufficient time to extract the DC offset component by this method. In the present invention, since the DC offset is obtained based on the amount of deviation from the lattice point, the DC offset information can be reliably extracted when the received signal contains no noise. Even if the received signal contains noise, DC offset information can be extracted by integrating in a shorter time than the related method. Therefore, compensation control of DC offset is always performed on the received signal at a high speed, communication quality deterioration due to DC offset is prevented, and characteristics (bit error rate) can be improved and performance can be improved.

  Further, according to the present invention, it is possible to prevent deterioration of communication quality due to DC offset, and therefore, when configuring a wireless communication system, it becomes possible to easily connect general-purpose ICs having different electrical characteristics using DC cut. Therefore, it is not necessary to prepare ICs having the same electrical characteristics, and an inexpensive wireless communication system can be configured.

  Further, according to the present invention, in a wireless communication system (apparatus) using a digital modulation system, even when the number of multi-values increases and the signal point interval is shortened, deterioration of communication quality due to DC offset is prevented, and characteristics (bit error rate) are prevented. Improves performance and performance

(Embodiment 2 of the present invention)
Next, a second embodiment of the present invention will be described. FIG. 10 shows a configuration of demodulation apparatus 200 according to Embodiment 2 of the present invention.

  The demodulation apparatus 200 according to the second embodiment of the present invention is provided between the ADC control units 141 and 142 and the first complex multiplier 151 as compared with the demodulation apparatus 100 according to the first embodiment of the present invention illustrated in FIG. In addition, a first complex multiplier 153 and waveform shaping filters 191 and 192 are added, and further, an NCO 182 for controlling the first complex multiplier 153 and an NCO 182 based on the carrier reproduction signal from the carrier regenerator 170 And an AFC (Automatic Frequency Control) control unit 190 that controls the second complex multiplier 154 that performs phase rotation control opposite to the phase rotation direction controlled by the first complex multiplier 153. .

  In the configuration of the second embodiment of the present invention, the received frequency of the modulated wave is shifted for some reason (such as a frequency shift of the local signal due to a change over time or a temperature change) and deviates from the pass band of the waveform shaping filters 191 and 192. To prevent this, when the frequency shift is detected, the AFC control unit 190 adjusts the oscillation frequency to the NCO 182 and the first complex multiplier 153 adjusts the input signal to pass through the waveform shaping filter. Do.

  When the frequency of the received signal is shifted and the band of the received signal is reduced by the waveform shaping filters 191 and 192 used for shaping the waveform of the received signal, characteristics due to intersymbol interference and a decrease in the received signal level (communication quality) Deterioration occurs, but this embodiment can prevent it.

  In the case of such a configuration, in order to perform DC offset compensation of the present invention, it is necessary to place the control signal before the first complex multiplier 153. The complex multiplier 154 is used to convert to a control signal where the ADC control units 141 and 142 are arranged.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention.

DESCRIPTION OF SYMBOLS 10 Demodulator 11 Orthogonal signal production | generation part 12 Low frequency interruption | blocking part 13 A / D conversion part 14 Demodulation part 15 Error detection part 16 Offset correction part 100,200 Demodulation apparatus 110 Quadrature demodulator 111,112 Multiplier 113 Oscillator 114 Shifter circuit 121, 122 DC cut capacitors 131, 132 AD converters 141, 142 ADC control units 151, 153 First complex multipliers 152, 154 Second complex multiplier 160 Error detection unit 170 Carrier regenerator 190 AFC control unit 191, 192 Waveform shaping filter

Claims (6)

An orthogonal signal generator that generates an analog orthogonal signal from an input signal;
A low-frequency cutoff unit that cuts off a low-frequency component of the analog orthogonal signal;
An A / D converter that converts the analog quadrature signal from which the low-frequency component is blocked into a digital quadrature signal;
A demodulator that demodulates the digital quadrature signal and generates a quadrature demodulated signal;
An error detector for detecting an error based on a constellation point of the generated quadrature demodulated signal;
An offset correction unit that corrects the digital quadrature signal with an offset corresponding to the detected error, and
The error based on the constellation point is a difference between the estimated value of the constellation point of the analog quadrature signal before the low frequency component is cut off and the constellation point of the quadrature demodulated signal,
The estimate of the constellation points of the analog quadrature signal before the low-frequency components are cut off, Ri constellation points der obtained by hard decision for the quadrature demodulation signal,
The demodulation unit and the offset correction unit perform complex multiplication on the digital quadrature signal and the quadrature demodulated signal,
The demodulator includes a plurality of first complex multipliers, and generates the quadrature demodulated signal through the plurality of first complex multipliers,
The offset correction unit includes a plurality of second complex multipliers corresponding to the plurality of first complex multipliers, and corrects the digital orthogonal signal via the plurality of second complex multipliers.
Demodulator.   The demodulator according to claim 1, wherein the difference between the constellation points is a difference vector between the constellation points.   The demodulation apparatus according to claim 1, wherein the offset correction unit integrates the detected error and corrects the digital quadrature signal based on the integration result.   The demodulator according to claim 1, wherein the demodulator performs phase rotation control on the digital quadrature signal.   The demodulator according to claim 4, wherein the offset correction unit performs reverse phase rotation control that rotates a phase in a direction opposite to the phase rotation control with respect to the quadrature demodulated signal. Generate an analog quadrature signal from the input signal,
Blocking low frequency components of the generated analog quadrature signal;
Converting the analog quadrature signal from which the low-frequency component is blocked into a digital quadrature signal;
Demodulate the converted digital quadrature signal to generate a quadrature demodulated signal,
Detecting an error based on a constellation point of the generated quadrature demodulated signal;
Correcting the digital quadrature signal with an offset corresponding to the detected error;
The error based on the constellation point is a difference between the estimated value of the constellation point of the analog quadrature signal before the low frequency component is cut off and the constellation point of the quadrature demodulated signal,
The estimate of the constellation points of the analog quadrature signal before the low-frequency components are cut off, Ri constellation points der obtained by hard decision for the quadrature demodulation signal,
In the demodulation process and the correction of the digital quadrature signal, complex multiplication is performed on the digital quadrature signal and the quadrature demodulated signal,
In the demodulation process, a plurality of first complex multiplication processes are performed, and the orthogonal demodulated signal is generated through the plurality of first complex multiplication processes,
In the correction of the digital quadrature signal, a plurality of second complex multiplication processes are performed corresponding to the plurality of first complex multiplication processes, and the digital quadrature signal is corrected through the plurality of second complex multiplication processes. To
Demodulation method.

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