JP5717897B2 - Information processing apparatus or information processing method - Google Patents

Information processing apparatus or information processing method Download PDF

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JP5717897B2
JP5717897B2 JP2014052439A JP2014052439A JP5717897B2 JP 5717897 B2 JP5717897 B2 JP 5717897B2 JP 2014052439 A JP2014052439 A JP 2014052439A JP 2014052439 A JP2014052439 A JP 2014052439A JP 5717897 B2 JP5717897 B2 JP 5717897B2
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data
clock
external
information processing
cycle
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JP2014140225A (en
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昭好 桃井
昭好 桃井
浩一 森下
浩一 森下
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キヤノン株式会社
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Description

  The present invention relates to an information processing apparatus or an information processing method for capturing an external device data output by an information processing apparatus such as an external device controller supplying a clock to the external device in synchronization with the clock.

  As disclosed in Patent Document 1, for an information processing apparatus having an external device controller, when the external device is communicably connected to the information processing apparatus, the information processing apparatus operates from the external device controller to the external device. There is a technology to supply a clock. Here, it is general that the external device is set to output data in synchronization with the clock supplied by the external device controller, and the external device controller is configured to take in the data output from the external device. .

  When this method is used, the external device controller temporarily stops the supply of data from the external device to the external device controller by temporarily stopping the clock supply to the external device (corresponding to clock gating). You can stop. For example, when data is stored up to the allowable capacity of the reception buffer in the external device controller, the external device controller can stop the clock supply and stop the data supply. Overflow can be suppressed.

JP 59-173839

  When the data received from the external device of the external device controller is delayed by one cycle or more with respect to the output clock of the external device controller, a control signal for stopping the clock to the external device is sent from the external device in the external device controller. Since it is used as it is for the control for stopping the reception of data, data is lost.

  Further, if it is attempted to adjust the timing of stopping (or canceling) the data capture of the external device controller, the time required for the adjustment process becomes longer.

In order to solve the above problems, an information processing apparatus according to the present invention provides:
Supply means for supplying a clock to an external device;
Control means for transmitting a control signal for stopping the supply of the clock to the supply means;
Receiving means for receiving data output by the external device in synchronization with the clock, and stopping capturing of the data in response to the control signal;
First delay means for correcting a phase shift of data received by the receiving means ;
Second delay means for delaying the data fetching timing of the receiving means using the control signal delayed so as to correct a shift in a cycle unit of the data corrected by the first delay means ;
It is characterized by having.

  According to the present invention, even if the data received by the information processing apparatus from the external device is delayed by one cycle or more with respect to the clock of the information processing apparatus, data loss on the information processing apparatus side is suppressed.

  In addition, according to the present invention, when it is attempted to adjust the timing for stopping (or releasing the stop of) data acquisition by the external device controller, an increase in the time required for the adjustment process is suppressed.

It is a block diagram of the external device controller in one Example of this invention. The block diagram and timing chart of the skew control part of a reference example are shown. It is a block diagram and a timing chart of a cycle control part. It is the flowchart of a calibration process, and the block diagram of an output clock control part. 7 is a timing chart in which an output clock is gated based on a gating pattern during reception of a calibration pattern. It is a timing chart which shows the correlation of a cycle parameter | index and the received calibration pattern. It is a timing chart which shows the correlation of a cycle parameter | index and the received calibration pattern. It is a timing chart which shows the correlation of the number of gating cycles and the received calibration pattern. It is a timing chart which shows the correlation of the number of gating cycles and the received calibration pattern. It is a timing chart which shows the correlation of the number of gating cycles and the received calibration pattern. It is a timing chart which shows the correlation of the cycle number between gating and the received calibration pattern. It is a timing chart which shows the correlation of the cycle number between gating and the received calibration pattern. It is a timing chart which shows the correlation of the cycle number between gating and the received calibration pattern. It is a timing chart which shows the correlation of the cycle number between gating and the received calibration pattern. 6 is a timing chart showing a correlation between a gating start position / gating end position and a received calibration pattern. 6 is a timing chart showing a correlation between a gating start position / gating end position and a received calibration pattern. 6 is a timing chart showing a correlation between a gating start position / gating end position and a received calibration pattern. It is a timing chart of the signal which an external device controller and an external device handle when the correct cycle setting is used. It is the schematic of a system configuration | structure which has an external device controller. The example of the relationship of the difference of the calibration pattern actually received and the actual cycle number is shown. The timing chart which shows the structure of the external device controller of a reference example, and the format of a command and data is shown. It is a flowchart of the calibration process of a reference example. It is a timing chart of the calibration process of a reference example. It is a timing chart of the signal which the external device controller of a reference example handles.

  Embodiments of the present invention will be described below with reference to the drawings. First, an embodiment for solving a problem when data received by an external device controller from an external device is delayed by one cycle or more with respect to an output clock of the external device controller will be described below.

  FIG. 19 is a block diagram of a system including an information processing apparatus that communicates with the external device 107. The ASIC 100 that is an LSI having a function of communicating with the external device 107 includes a CPU 101, a DRAM controller 104, a DMA controller 102, an external device controller 103, and a CLOCK generator 105. (ASIC is an abbreviation for Application Specific Integrated Circuit, DMA is an abbreviation for Direct Memory Access.) Also, a CLOCK generator 105 as an oscillation means is a clock used by the CPU 101, the DMA controller 102, the external device controller 103, and the DRAM controller 104 (113_cpu_clock). dmac_clock 114, host_clock 115, dram_clock 116) are generated and supplied. The CPU 101 performs register access to the external device controller 103, the DMA controller 102, and the DRAM controller 104 via the CPU I / F 110. The DMA controller 102 performs data transfer with the DRAM controller 104 via the CPU I / F 110. The DRAM controller 104 performs data transfer with the DRAM 106 via the DRAM I / F 117. The external device controller 103 performs data transfer with the DMA controller 102 via the DMA I / F 111. Further, the external device controller 103 performs data transfer with the external device 107 via the external device I / F 112.

  Next, the external device controller will be described. FIG. 1 shows the configuration of an external device controller 103 according to an embodiment of the present invention.

  The external device controller 103 receives a host clock 115 (host_clock in the figure) from the CLOCK generator 105. The host clock 115 is connected to each block in the external device controller 103, and each block of the external device controller 103 operates in synchronization with this host clock 115.

  The CPU I / F control unit 201 receives data, commands, and register access transmitted from the CPU 101 to the card, and transmits commands and data received from the card to the CPU 101. The DMA I / F control unit 204 receives data to be transmitted to the external device 107 from the DMA controller 102, while transmitting data to be received from the external device 107 to the DMA controller 102.

  The external device controller 103 exchanges commands with the external device 107 via the transmission command parallel / serial conversion unit 125 and the reception command serial / parallel conversion unit 126. First, the CPU I / F control unit 201 transmits a transmission command 223 (s_cmd) in parallel format received from the CPU 101 to the transmission command parallel / serial conversion unit 125 (hereinafter referred to as a transmission command PS conversion unit) via the CPU I / F 110. . The transmission command PS conversion unit 125 converts the received transmission command 223 in the parallel format into a transmission command 224 (s_cmd_data) in the serial format and transmits it to the external device 107.

  The external device 107 decodes the received serial format transmission command 224 and detects the transmission command. Further, the external device 107 transmits detection information indicating the detection result of the transmission command to the external device controller 103 as a serial reception command 226 (r_cmd_data).

  The reception command serial / parallel conversion unit 126 (hereinafter, reception command SP conversion unit) receives the serial format reception command 226 output from the external device 107, converts it into a parallel format reception command 225 (r_cmd_reg), and converts it into a CPU I / F. It transmits to CPU101 via the control part 201 and CPU I / F110.

  The external device controller 103 exchanges data with the external device 107 via the transmission buffer 207, the transmission data parallel / serial conversion unit 208, the skew control unit 211, the reception data serial / parallel conversion unit 210, and the reception buffer 209. In addition, an output clock control unit 213 and an output clock gating unit 214 are provided in order to de-assert the output clock 244 and stop data from the external device 107. Further, the external device controller 103 has a gating mode setting register 605 and a gating pattern setting register 606 in order to perform effective cycle adjustment.

  In addition, the external device controller 103 includes a skew control unit 211 and a skew setting register 212 in order to perform skew adjustment (correction). Here, the skew adjustment (correction) refers to data input to the reception data serial / parallel conversion unit 210 (hereinafter referred to as reception data SP conversion unit) or data fetch timing (latch timing) of the external device controller 103 (skew control unit 211). ) (With respect to the host clock 115) is adjusted (corrected) by a delay within one cycle.

  The external device controller 103 also includes a cycle setting register 601, a cycle calculation unit 602, a cycle control unit 603, and an expected value setting register 604 in order to perform cycle adjustment (correction). Here, the cycle adjustment (correction) refers to the reception data SP conversion unit 210 by delaying the reception enable signal 250 (rcv_en), which is a control signal of the reception data SP conversion unit 210, in cycle units (relative to the host clock 115). This indicates that the data acquisition stop timing and the data acquisition restart timing are adjusted (corrected).

  The skew setting register 212 receives and holds the skew setting value 227 (skew_reg) from the CPU I / F control unit 201. The skew control unit 211 receives the skew selection value 238 (skew_sel) from the skew setting register 212, and receives the serial format received data 236 (d2h_data, hereinafter simply referred to as received data 236) from the external device 107 according to the set value. Delay).

  The cycle setting register 601 receives and holds the cycle setting value 256 (cycle_reg) from the CPU I / F control unit 201. The expected value setting register 604 receives and holds the expected value setting value 253 (exp_reg) from the CPU I / F control unit 201. An example of the expected value setting value 253 is shown in FIG. The pattern received when the difference from the actual number of cycles is 0 matches the true value (pattern output by the external device 107), but the pattern received by the external device controller 103 is the cycle when calibration is performed. It changes according to the difference between the set value and the correct cycle set value (corresponding to a cycle delay amount described later). The cycle calculation unit 602 receives the cycle setting value 255 (cycle_val) from the cycle setting register 601 and the expected value 254 (exp_pattern) from the expected value setting register 604, and calculates a desirable cycle setting value. Specifically, the received calibration pattern and the expected value are compared to determine whether they match. The difference between the cycle setting value corresponding to the expected value when the values match and the correct cycle setting value is obtained. Thereafter, the correct cycle setting value is calculated by adding the obtained difference to the cycle setting value at the time of calibration. The cycle control unit 603 receives the correct cycle selection value 249 (cycle_sel) from the cycle calculation unit 602. Further, the cycle control unit 603 receives an output clock enable signal 243 (clock control signal) from the output clock control unit 213.

[Data reception processing]
Next, processing in which the external device controller 103 receives data (external device data) from the external device 107 will be described.

  When the external device controller 103 starts data reception, the external device controller 103 first transmits a command for instructing data reception from the external device 107 to the external device 107 by the command transmission / reception process described above. Further, the external device 107 transmits a response to this transmission command to the external device controller 103 as a reception command, and further transmits data.

  Data reception is performed as follows. First, the skew control unit 211 receives serial format received data 236 (d2h_data) transmitted from the external device 107.

  The skew control unit 211 performs skew adjustment between the serial format received data 236 and the clock 115 (host_clk) of the external device controller (details will be described later). The reception data 235 after skew adjustment is input to the reception data SP conversion unit 210.

  The reception data SP conversion unit 210 is configured to receive a reception enable signal 250 (details will be described later) obtained by delaying the output clock enable signal 243 output from the output clock control unit 213 by a cycle control unit 603 described later. ing. If the reception enable signal 250 is asserted, the reception data SP converter 210 receives the received skew-adjusted reception data 235 and converts it into parallel reception data 234 (r_data_buf).

  The reception data SP conversion unit 210 has a K-stage shift register (serial input parallel output type flip-flop) (not shown), and is configured to send data received in serial format as Kbit parallel format data. Yes. Therefore, if the reception enable signal continues to be asserted, the reception data SP conversion unit 210 transmits parallel data once in K cycles. Here, the timing at which the received data SP converter 210 captures data (external device data) from the external device 107 corresponds to the latch timing of the first-stage (0 bit) flip-flop (as viewed from the external device 107 side). I can say that.

  The reception buffer 209 serving as a holding unit is configured to be able to notify that it cannot hold more data than the data currently held by the reception buffer full signal 241. Therefore, if the reception enable signal 250 is asserted and the reception buffer full signal 241 (r_buff_full) of the reception buffer 209 is deasserted, the reception data SP conversion unit 210 transmits the reception data 234 in parallel format to the reception buffer 209. On the other hand, if reception enable signal 250 is not asserted, reception data SP converter 210 stops receiving reception data 235 after skew adjustment.

  When reception data SP converter 210 starts receiving data, it asserts reception status signal 239 (rcv_status). The reception data SP conversion unit 210 continues to assert the reception status signal 239 until the final data is received from the external device 107, and deasserts it when the end bit of the reception data 235 after skew adjustment is detected. When the reception data SP converter 210 transmits the reception data 234 in parallel format to the reception buffer 209, the reception buffer 209 deasserts the reception buffer empty signal 233 (r_buff_emp).

  The reception buffer 209 receives and holds the reception data 234 (r_data_buff) converted into the parallel format from the reception data SP conversion unit 210. Here, when the reception buffer 209 becomes full, the reception buffer 209 asserts the reception buffer full signal 241 to the output clock control unit 213 and the reception data SP conversion unit 210. On the other hand, when the reception buffer 209 becomes empty, the reception buffer 209 asserts a reception buffer empty signal 233 to the DMA I / F control unit 204.

  The DMA I / F control unit 204 receives the deassertion of the reception buffer empty signal 233 of the reception buffer 209 and detects that the reception data from the external device 107 remains in the reception buffer 209. Then, the reception data 232 (r_data_dma) in parallel format held in the reception buffer 209 is received from the reception buffer 209 and transmitted to the DMA I / F 111. However, when the reception buffer 209 becomes empty, reception of data is stopped. If data reception is not stopped, a buffer underrun of the reception buffer 209 may occur. Accordingly, when the reception buffer empty signal 233 of the reception buffer 209 is asserted, the DMA I / F control unit 204 stops receiving the parallel-format reception data 232, and the data input to the DMA I / F 111 is stopped. Stop sending.

  When the reception buffer empty signal 233 of the reception buffer 209 is deasserted, the DMA I / F control unit 204 resumes reception of the parallel format reception data 232 and resumes transmission of the reception data to the DMA I / F 111.

  On the other hand, when a write to a new reception buffer occurs when the reception buffer 209 is full, a buffer overrun of the reception buffer 209 occurs, so that data reception is stopped. When the reception data SP conversion unit 210 is receiving data and the reception buffer 209 is full, the output clock control unit 213 deasserts the output clock enable signal 243.

  That the reception data SP conversion unit 210 is receiving data is detected by asserting the reception status signal 239. The reception data SP converter 210 asserts the reception status signal 239 when the first reception data is received, continues to assert until the final data is received, and deasserts when the final data is received. For this reason, the output clock enable signal 243 is not deasserted while waiting for received data (waiting for the start bit detection).

  The external device 107 receives the deassertion of the output clock 244 (dev_clk), and stops transmission of the reception data 237 (d2h_data ′). Data reception continues to stop until the reception buffer full signal 241 (r_buff_full) of the reception buffer 209 is deasserted. When the reception buffer full signal 241 (r_buff_full) of the reception buffer 209 is deasserted, the reception data SP conversion unit 210 resumes data reception. Then, the output clock gating unit 214 cancels the gating of the output clock 244, and the external device 107 resumes transmission of the reception data 237.

[Deskew configuration]
Next, details of a configuration for performing skew correction will be described.

  FIG. 2A is a block diagram of the skew control unit 211. The skew control unit 211 receives the host clock 115 (host_clk) from the CLOCK generator 105 (FIG. 19). The host clock 115 is delayed by N1 delay elements 216 (first delay means) whose inputs and outputs are connected in series. The output of each delay element 216 is input to the delay selection unit 217, and the delay element 216 used for output is selected based on the value of the skew selection value 238 (skew_sel).

  The selected delayed clock signal 246 (clk_with_skew) is input to the flip-flop 218 as a clock. On the other hand, the serial format received data 236 (d2h_data) transmitted from the external device is received by the flip-flop 218, and is synchronized with the delayed clock signal 246 (clk_with_skew) by the flip-flop 218. The synchronized serial format reception data is output to the reception data SP conversion unit 210 by the skew control unit 211 as serial format reception data 235 after skew adjustment (d2h_data_1d, hereinafter referred to as reception data 235 after skew adjustment).

  The N1 delay elements of the skew control unit 211 preferably cause a delay obtained by dividing one clock (of the host clock 115) into N1 equal parts or a little smaller than that.

  FIG. 2B is a timing chart of signals handled by the skew control unit 211 when the skew setting values are 0, 1, and 2. When each signal in FIG. 2B is associated with the codes in FIG. 1 and FIG. 2).

  In the timing chart of FIG. 2B, when the skew selection value 238 (skew_sel) is 0 and 1, d2h_data 236 is indefinite at the rise of clk_with_skew 246. Therefore, the data d2h_data_1d235 fetched into the flip-flop 218 is also undefined, and the data fetching cannot be performed normally. On the other hand, when the skew selection value 238 is 2, since d2h_data 236 outputs stable data at the rise of clk_with_skew 246, the data d2h_data_1d235 fetched into the flip-flop 218 is also normal. Adjustment of the skew selection value 238 is performed by a calibration sequence described later.

[Cycle correction configuration]
Next, details of a configuration for correcting the cycle delay will be described.

  FIG. 3A shows a schematic configuration of the cycle control unit 603. The cycle control unit 603 has N2 flip-flops 701 (second delay means) whose inputs and outputs are connected in series. The flip-flop 701 causes the output clock enable signal 243 to be delayed by one clock. The cycle control unit 603 delays the input output clock enable signal 243 by the flip-flop 701 by the number of cycles indicated by the cycle setting value 256. The delayed output clock enable signal 243 is input to the reception data SP conversion unit 210 as the reception enable signal 250.

  FIG. 3B shows waveforms of various signals handled by the cycle control unit 603. When the respective signals in FIG. 3B are described in correspondence with the reference numerals in FIG. 1, they are host_clk 115, dev_clk_en 243, and rcv_en 250 in order from the top. The cycle control unit 603 delays the input output clock enable signal 243 according to the value of the cycle selection value 249 (cycle_sel = 0, 1, 2, 3), and outputs it as a reception enable signal 250. When the value indicated by the cycle selection value 249 is 2, the cycle control unit 603 uses the selector 702 to select the output that has passed through the two flip-flops 701, thereby delaying the output clock enable signal 243 by two cycles and receiving the reception enable signal. It outputs as 250. Since there are N2 flip-flops 701 in the configuration of FIG. 3, the output clock enable signal 243 can be delayed by an integral multiple of one cycle (up to N2 cycles).

  In this embodiment, the reception data SP conversion unit 210 determines the data capture stop timing by deasserting the reception enable signal 250, and determines the data capture restart timing when the reception enable signal 250 is reasserted.

  The gating mode setting register 605 receives and holds the gating mode register setting value (247 gate_reg) from the CPU I / F control unit 201. The gating mode setting register 605 outputs the received gating mode register setting value 247 to the output clock control unit 213 as the gating mode setting value (251 gate_mode).

  Here, the gating mode of the external device controller 103 of the present embodiment includes two types of modes, a calibration mode and a normal data transfer mode. The gating pattern setting register 606 receives the gating pattern register setting value (248 pattern_reg) from the CPU I / F control unit 201 and holds it. The received gating pattern register setting value 248 is output to the output clock control unit 213 as a gating pattern setting value (252 gate_pattern).

The gating pattern register setting value 248 is information (gating information) for generating a clock gating pattern, and indicates how to perform clock gating. (Details are information indicating L, N, S, and E described later in FIG. 5.)
FIG. 4B shows the configuration of the output clock control unit 213 that functions as selection means in this embodiment. The first clock control unit 221 (first control unit) receives the reception buffer full signal 241 and the reception status signal 239, and performs clock control similar to that of Patent Document 1 and the reference example (see FIG. 21) (first operation). Three clock control mode). On the other hand, the second clock control unit 222 (second control unit) performs clock control to be described later based on the reception status signal 239 and the gating pattern 252 (first clock control mode). Further, the third clock control unit 223 (third control unit) controls to generate an output clock enable signal 243 that controls to output the host clock 115 of the external device controller without stopping (second clock). Control mode).

  First, information indicating a reception state such as how many bits of the reception data 236 the reception data SP conversion unit 210 has received is added to the reception status signal 239 and transmitted to the output clock control unit 213. Based on the reception information added to the reception status signal 239, the second clock control unit 222 determines how many bits the reception data SP conversion unit 210 has received. If the condition that the gating pattern 252 indicates to perform gating is not satisfied, the output clock enable signal 243 is generated.

  The clock control selection unit 220 is a selector, and the first clock control unit 221, the second clock control unit 222, and the third clock control according to the set value indicated by the gating mode 251 from the gating mode setting register. One of the units 223 is selectively functioned.

[Command data format]
Here, a format of a signal used for exchange of commands and data between the external device controller 103 and the external device 107 will be described.

  The external device controller 103 and the external device 107 exchange serial commands or serial data with the format shown in FIG. In the following description, it is assumed that parallel commands and parallel data have the same format.

  First, signals handled during transmission / reception of the serial transmission command 224 and the serial reception command 226 will be described with reference to FIG. The transmission command 224 includes a 1-bit start bit, an N-bit transmission command, an M-bit CRC (cyclic redundancy check signal), and a 1-bit end bit. When the transmission command PS conversion unit 125 detects reception of the transmission command 223 in parallel format, it first transmits a start bit of 1 bit. Subsequently, the N-bit parallel transmission command 223 is converted into a serial transmission command 224 and transmitted. The transmission command PS conversion unit 125 performs CRC calculation together with transmission of a serial transmission command. Then, after transmitting the serial transmission command 224, the calculated M-bit CRC is transmitted. Finally, 1 end bit is transmitted to complete the command transmission.

  The format of the serial reception command 226 is also as shown in FIG. 21B. However, since the reception command and the transmission command do not need to match, the command length and CRC length of the reception command and the transmission command are as follows. It can be different.

  The reception command SP conversion unit 126 detects a 1-bit start bit and starts receiving a command. Subsequently, an N-bit serial format reception command is received and converted into a parallel format reception command. The reception command SP conversion unit 126 performs CRC calculation together with reception of a serial reception command. After receiving the reception command in the serial format, the calculated CRC is compared with the transmitted M-bit CRC (cyclic redundancy check) to detect a CRC error. Finally, 1 end bit is received and command reception is completed.

  When the transmission data PS conversion unit 208 receives the parallel format transmission data 230 (s_data_buf) from the transmission buffer 207, the transmission data PS conversion unit 208 converts the parallel format transmission data into the serial format transmission data 231 in the same manner as the transmission command PS conversion unit 125. Transmit to the external device 107. However, the transmission data length and CRC length may be different from the transmission command.

  The format of the received data is as shown in FIG. However, the length of the received data and the length of the CRC may be different from the transmission command.

  The reception data SP converter 210 starts receiving data when it detects one start bit. Then, processing is performed in the same manner as the reception command SP conversion unit 126 to convert the reception data 235 after serial skew adjustment into parallel reception data 234 and transmit it to the reception buffer 209. The CRC calculation processing and comparison processing of the transmission data PS conversion unit 208 and the reception data SP conversion unit 210 are the same as the processing of the transmission command PS conversion unit and the reception command SP conversion unit, and therefore will be omitted.

〔Calibration〕
Next, a calibration process for adjusting various parameters (skew setting value, cycle setting value) so that the external device controller 103 can correctly capture data will be described.

  First, a calibration flow in the external device controller 103 of the reference example having the configuration shown in FIG. 21 will be described with reference to FIG.

  First, in step S <b> 101, when the external device controller 103 is instructed to start calibration by the CPU 101, the external device controller 103 transmits a transmission command for causing the external device 107 to output a calibration pattern to the external device 107. Next, the external device 107 transmits a reception command for the calibration transmission command to the external device controller 103. Further, the external device 107 transmits a predetermined calibration pattern to the external device controller 103 instead of the serial received data 237. The external device controller 103 receives the calibration pattern according to the data reception flow described above. The received calibration pattern is written into the DRAM 106 via the DMA controller 102 and the DRAM controller 104.

  After all the calibration patterns are written to the DRAM 106, the CPU 101 compares the calibration pattern stored in advance in the DRAM or the like as an expected value with the actually received calibration pattern in step S102. If the CPU 101 determines that they match, the skew setting is considered correct, and the calibration sequence is completed. On the other hand, if the two do not match, it is considered that the skew setting is incorrect. In step S103, the CPU 101 sets a different skew setting value 227 in the external device controller 103, and performs the calibration sequence (S101, S102) again. The above processing is repeated until calibration is successful.

  Here, it is assumed that the calibration pattern is stored in advance on the external device 107 side, and the external device 107 transmits the stored calibration pattern when receiving a command to start calibration.

  Here, the waveform of the signal handled in step S101 when the skew adjustment is completed will be described. FIG. 23 shows waveforms during the calibration sequence when the received data 236 has a delay of one cycle or more in the reference example. (Here, the case where the received data 236 has a delay of one cycle or more corresponds to the case where a wiring delay of ½ cycle or more occurs between the external device controller 103 and the external device 107.) 21 in correspondence with the reference numerals in FIG. 21 and FIG. Note that there is a difference between the timing of the fetched clock and the fetched data, but this indicates a delay until the data is fetched into the flip-flop when fetching with reference to the clock edge in an actual circuit. This is a delay that occurs at a location that is not directly related to the above problem, and the delay amount is also small. Therefore, this delay may be ignored (excluded) when the received data is delayed by one cycle or more. Further, in FIG. 23, a part of the waveform in the latter half of the calibration is omitted.

  In the example of FIG. 23, the clock 245 (dev_clk ′) input to the external device 107 is delayed by ½ cycle with respect to the output clock 244 (dev_clk) output from the external device controller 103. Further, the reception data 236 (d2h_data) received by the external device controller is delayed by ½ cycle with respect to the reception data 237 (d2h_data ′) transmitted by the external device.

  These delays are considered to be due to the influence of the round trip delay on the substrate between the external device 107 and the external device controller 103, the output delay in the external device 107, the delay in the external device controller 103, and the like. As a result, in the example of FIG. 23, the received data 236 that the external device controller 103 takes in the data output by the external device 107 in response to the output clock 244 of the external device controller 103 is delayed by one cycle. .

The calibration pattern is usually sufficiently smaller than the size of the reception buffer 209. For this reason, the external device controller 103 in the reference example does not stop the output clock during calibration. (Even if the calibration pattern is larger than the size of the reception buffer 209, whether the output clock stops depends on the transfer rate of the DMA controller 102. Therefore, the output clock 244 stops during calibration. It is difficult to occur.)
Referring to FIG. 23, since the contents of r_data_buff (0) 234 and the received serial format received data d2h_data 236 match, the calibration process is completed. However, when data is actually received as shown in FIG. 24, data is lost.

  The timing chart of FIG. 24 shows the waveform of a signal when the external device controller 103 is actually receiving data from the external device 107 when the received data 236 has a one-cycle delay as in FIG. Yes. The correspondence of each signal with FIG. 21 and FIG. 2 is the same as FIG.

  In FIG. 24, when “D0” of serial format received data 236 is received, a situation occurs in which the reception buffer 209 is asserted with a reception buffer full signal 241 (not shown in FIG. 24). In response to the assertion of the reception buffer full signal 241, the output clock control unit 213 deasserts the output clock enable signal 243 (dev_clk_en). The output clock gating unit 214 gates the output clock 244 in response to the deassertion of the output clock enable signal 243. Although the output clock 244 is gated by the output clock gating unit 214, the serial format received data “D 1” and “D 2” have been transmitted from the external device 107.

  Originally, the data entering the reception buffer 209 (which is a reference when issuing the reception buffer full signal 241) is delayed by a half cycle when entering the external device controller 103 from the external device 107. Then, in addition to the delay until the output clock 244 is gated after the reception buffer full signal 241 is asserted, ½ cycle until the external device 107 can recognize that the output clock 244 has been gated. There is a delay. As a result, in order for the external device 107 to recognize that the external device controller 103 is requesting to stop data transmission, it is delayed by the sum of these delays, so that “D1” and “D2” are transmitted. .

The reception data SP converter 210 receives the deassertion of the output clock enable signal 243 and immediately stops receiving the serial format reception data 236. As a result, the reception data SP conversion unit 210 cannot receive the serial reception data “D1”. (As shown in the figure, “D1” is not included in the parallel received data 234 received by the received data SP converter 210 and transmitted to the receive buffer 209.)
Further, after the reception buffer 209 deasserts the reception buffer full signal 241, the output clock enable signal 243 is asserted, and the gating of the output clock 244 is released. Since the output clock 244 is gated on the basis of the fall, the output clock 244 rises after 1/2 of the release. However, although the gating of the output clock 244 is canceled, the serial format received data “D2” continues to be transmitted from the external device 107 due to the delay between the external device 107 and the external device controller.

  On the other hand, upon receipt of the output clock enable signal 243, the reception data SP conversion unit 210 immediately resumes reception of serial format reception data. Therefore, the reception data SP converter 210 receives the serial reception data “D2” twice. Looking at the received data 234 in parallel format, it can be seen that D2 has been received twice.

  As described above, when there is a delay of one cycle or more by reciprocating between the external device controller 103 and the external device 107, even if calibration is completed in the configuration of the reference example (FIG. 23), the actual data Reception may fail (FIG. 24).

  From the above, it can be seen that the external device controller 103 of the reference example may not be able to detect the presence or absence of a delay of one cycle or more generated in the reception data 236 in the calibration sequence.

  For the sake of explanation, FIG. 24 is based on the premise that the period until the reception buffer full signal 241 is asserted and deasserted is extremely short, and the reception buffer is extremely small. is there.

  Next, the calibration flow of the present embodiment will be described with reference to FIG. In the calibration flow of this embodiment, first, skew adjustment is performed while the third clock control unit 223 is functioning, and then cycle adjustment is performed while the second clock control unit 222 is functioning. If it is known that the calibration pattern is sufficiently smaller than the size of the reception buffer and clock gating does not always occur during reception of the calibration pattern, the first clock control means instead of the third clock control means May be used.

  Here, the skew adjustment is an adjustment to correct a phase shift between the host clock 115 and the reception data 236 with the configuration shown in FIG. On the other hand, in the cycle adjustment, adjustment is performed so as to correct a shift in a cycle unit between the host clock 115 and the reception data 236 by the configuration shown in FIG. In the following description, a period shift (corresponding to a shift in data capture timing or a shift in data capture restart timing) is simply referred to as a delay cycle number (cycle delay amount).

  First, the skew adjustment flow will be described. In step S1201, the CPU 101 sets the clock gating mode to the external device controller 103 to a calibration mode (mode using the third clock control unit) that does not stop the clock. In step S1202, the CPU 101 instructs the external device controller 103 to acquire a calibration pattern. The calibration pattern acquisition process by the external device controller 103 is the same as in the reference example. When the acquisition of the calibration pattern is completed, in step S1203, the CPU 101 compares the calibration pattern read out from the ROM or RAM with the calibration pattern actually received. If the comparison results match, the skew setting is considered correct and the skew adjustment flow is completed.

  On the other hand, if the comparison results do not match, it is considered that the skew setting is incorrect. In that case, the CPU 101 changes the value of the skew setting register 212 in step S1204, changes the skew setting, and proceeds to step S1202. The skew setting is changed, and the processes in steps S1202 and S1203 are repeated until the patterns match in step S1203.

  Next, the cycle adjustment flow will be described. In step S1205, the CPU 101 sets the clock gating mode of the external device controller 103 to a calibration mode for stopping the clock based on the value indicated by the reception status signal 239 and the gating pattern 252 (a mode for causing the second clock control unit to function). ). Further, the CPU 101 sets a gating pattern register set value 248 for the external device controller 103. In step S1206, the CPU 101 instructs the external device controller 103 to acquire a calibration pattern. The outline of the calibration pattern acquisition process by the external device controller 103 is the same as in the reference example.

However, the output clock control unit 213 according to the first embodiment issues the output clock enable signal 243 according to the gating pattern 252. The output clock gating unit 214 gates the output clock 244 according to the output clock enable signal 243 during reception of the calibration pattern. When the cycle calculation unit 602 completes acquisition of the calibration pattern in step S1206, the process proceeds to step S1207. In step S <b> 1207, the cycle calculation unit 602 compares the expected value that the CPU 101 has read from the DRAM 106 and the like and stored in the expected value setting register 604 as the calibration pattern scheduled to be received with the actually received calibration pattern. I do. The actually received calibration pattern differs depending on the gating pattern, the calibration pattern (expected value), and the difference between the current cycle setting value and the actual delay cycle. (Details will be described later.)
FIG. 20 shows an example in which “01010101” is used as the calibration pattern. Although details will be described later, when the current cycle setting value matches the actual number of delay cycles, the external device controller 103 can receive the calibration pattern as “01010101”. However, when the actual number of delay cycles is one cycle greater than the current calibration pattern, the calibration pattern is received as “01011101”. In that case, the cycle calculation unit 602 compares the calibration pattern received by the above-described process with the calibration pattern (expected value) to be received, and detects the presence or absence of delay. If there is a delay, the difference from the actual number of cycles is detected based on the received pattern (see FIG. 20). In step S1208, the cycle calculation unit 602 (or the CPU 101) sets the detected actual delay cycle as a cycle set value, and completes the cycle adjustment flow. When the calibration sequence is completed, the output clock control unit 213 switches to the third clock control mode to prepare for data transmission / reception.

  As described above, if the size of the calibration pattern is made smaller than the size of the reception buffer 209, the reception buffer 209 will not become full during the calibration sequence. However, the external device controller 103 according to the first embodiment gates the output clock 244 based on the gating pattern regardless of the assertion of the reception buffer full signal 241. If the cycle setting or skew setting is incorrect, an incorrect calibration pattern is acquired as it is (so that it can be seen that the calibration is not successful). After completing the calibration using the flow shown in FIG. 4A, the CPU 101 stores “0” in the clock control selection unit in the gating mode setting register 605 in order to switch to the mode using the first clock control unit 221. To prepare for data transmission / reception.

  With the above processing, the external device controller 103 according to the present embodiment can detect the presence or absence of a delay even if a delay of one clock cycle or more occurs in the reception data 236. Therefore, various parameters for transmitting and receiving data without missing it. (Skew setting, cycle setting) can be set.

  Further, as shown in FIG. 4A, after adjusting the delay in the cycle by the skew adjustment without performing the clock gating, the delay between the cycles is performed while performing the clock gating based on the gating pattern. Calibration can be performed efficiently by making adjustments. If the skew adjustment and the cycle adjustment are not separated as described above, the calibration pattern must be received and compared (N1 × N2 times at the maximum) until the expected value matches the received data 236, and the calibration is performed. Processing takes considerable time.

  If the calibration pattern is sufficiently smaller than the size of the reception buffer 209, skew adjustment is performed by the first clock controller 221 without using the third clock controller 223 in steps S1201 to S1204 in FIG. May be. (This is because even if the first clock control unit 221 is used during reception of the calibration pattern, clock gating does not always occur.) Even in this case, the processing shown in FIG. 21A is performed by the processing of steps S1205 to S1208. Compared with the reference example, calibration is more likely to succeed (reducing the number of times).

[Calibration pattern and gating pattern]
Here, the correlation between the calibration pattern and the gating pattern will be described. When the calibration process is completed, it is assumed that the number of cycles indicated by the cycle setting value 256 matches the number of cycles actually delayed. In the example of FIG. 24, since the cycle delay is one cycle, the value indicated by the correct cycle setting value 256 to be set is “1”. (The waveform shown in FIG. 24 corresponds to the case where the cycle set value 256 is not adjusted).
If the gating pattern and the calibration pattern setting of the output clock 244 are appropriately set, the accuracy of the calibration process is increased accordingly. For example, in the example of FIG. 24, the reception data “D1” cannot be received, and instead, the reception data “D2” has been received twice. Since data replacement occurs in this way, when a comparison is made with the received data 236 using an unfavorable calibration pattern (a pattern that does not take into account the viewpoint described later), the calibration pattern is received and compared. There is a high possibility that the number of times increases or the accuracy of processing decreases. For example, for skew adjustment and cycle adjustment, it is necessary to make a brute force comparison (maximum N1 + N2 times) until the expected value matches the received data 236.

  Hereinafter, the correlation between the gating pattern of the output clock 244 and the calibration pattern will be described from four viewpoints. Comparison of calibration processes can be shortened by using a calibration pattern considering these viewpoints (maximum N1 + 1 times).

  The gating pattern is set based on the calibration pattern and the following four viewpoints. When the control signal (output clock enable signal 243) for stopping the data capture control of the reception data SP converter 210 is not delayed by the cycle delay amount by using the gating pattern for calibration, the external device controller is actually It is possible to cause duplication or omission in the data (received data 234) received by 103. FIG. 20 shows the correlation between the cycle delay amount and the pattern (received data 234) that the received data SP conversion unit 210 receives in a situation where a preferable gating pattern (for example, “01010101”) is set.

(1) Correlation between the difference between the actual delay amount and the cycle setting value (hereinafter, delay index M) and the received calibration pattern Delay index M = (actual delay amount) − (cycle setting value) The correlation between the index M and the received calibration pattern will be described. Here, the actual delay amount is the number of cycles in which the reception data 236 is delayed with respect to the output clock 244 when the cycle set value is “0” (corresponding to the cycle unadjusted after the skew adjustment). .

  6 and 7 show the waveforms of the reception data 234 in parallel format when the change timing of the reception enable signal 250 is fixed to the timing when there is no delay and the actual delay amount is changed. When the signals in FIGS. 6 and 7 are associated with the codes in FIG. 6 and 7 show four sets when the delay index M is 0, 1, 2, 3.

  6 and 7, when D3 is received, the output clock enable signal 243 is gated, and the output clock 244 is deasserted. As shown in FIGS. 6 and 7, the received calibration pattern (corresponding to dh2_data 236) differs depending on the delay index M. When the delay index is M> 1, the data received after 1 cycle to the data after M cycles are based on the data (D3 in the examples of FIGS. 6 and 7) received when gating is started. Replaced with data after M + 1 cycles. On the other hand, when M = 0, the actual delay amount matches the cycle setting value, so that the correct pattern is received.

(2) Correlation between Gating Amount (N) and Received Pattern The number of cycles in which output clock 244 continues to be gated is defined as a gating amount N (when the cycle adjustment is incorrect after skew adjustment) and N The correlation of the received calibration pattern will be described (see FIG. 5 for the definition of N).

  8, 9, and 10 show waveforms during calibration when N is 3, 2, and 1, respectively. Referring to the waveforms of r_data_buff 234 in FIGS. 8, 9, and 10, it can be seen that the data for M cycles are replaced regardless of the value of N. However, which data is replaced depends on the value of N. For example, when N = 3, D1 to D3 are replaced with D4, and when N = 2, D1 is replaced with D3, and D2 and D3 are replaced with D4. When N = 1, D1 is replaced with D2, D2 is replaced with D3, and D3 is replaced with D4.

(3) Correlation between cycle (L) between gating and received pattern When gating is performed a plurality of times, the cycle from the previous gating timing to the next gating timing is set to L (after skew adjustment) The correlation between L and the received calibration pattern will be described (when the cycle adjustment is incorrect). (Refer to FIG. 5 for the definition of L). 11, 12, 13, and 14 show waveforms during calibration when L is 1 to 4. FIG. If L> = M, multiple times of gating can be handled as independent gating. That is, replacement of data for M cycles occurs for the number of times of gating. Otherwise, multiple times of gating are correlated with each other, and M * (number of times of gating)-(ML) pieces of data are continuously replaced.

(4) Correlation between the gating start position (S) and the gating end position (E) and the received pattern. The gating start position is S and the gating end position is E. The correlation between S and E and the received calibration pattern will be described (refer to FIG. 5 for definitions of S and E).

  FIGS. 15, 16, and 17 show waveforms during calibration when the positional relationship between S and the start bit and the positional relationship between E and the end bit are changed. FIG. 15 shows a waveform when the gating start position S is after the start bit is detected and the gating end position E is before the end bit is detected. FIG. 16 shows a waveform when the gating start position S is before the start bit detection and the gating end position E is after the end bit detection. FIG. 17 shows a waveform when the gating start position S is after the start bit is detected and the gating end position E is after the end bit is detected.

  As shown in FIG. 16, when clock gating is performed periodically so as to synchronize with one cycle of the host clock 115, L> M is not satisfied, S is a position before the start bit, and E is the end. If the position is after the bit, it is not suitable for calibration. This is because data can be received correctly even though the cycle adjustment is incorrect.

  On the other hand, if S is after the start bit or E is after the end bit, data cannot be received correctly in a situation where the cycle adjustment is incorrect, and thus it can be seen that this gating pattern is suitable for calibration. . Therefore, it is necessary to consider only one of S or E during the calibration pattern reception or to consider the cycle L between gating.

  Although not directly shown in FIGS. 15, 16, and 17, the timing at which the value of the calibration pattern received by the reception data SP conversion unit 210 fluctuates (while a predetermined number of different values to be described later are input). ), The gating pattern must be set so that the gating start position S or the gating end position E comes. That is, the gating pattern is set so that the output clock 244 starts to be stopped or the stop is released at one timing at which the value of the calibration pattern fluctuates. For example, the timing at which the value fluctuates is “01” (or “10”), and the gating start position S is “1” (or “0” in “10”). The gating pattern is set so that the end position E is “0” of “01” (or “1” of “10”).

  As described above, there is a correlation shown in (1) to (4) between the calibration pattern and the gating pattern. In the example of FIGS. 6 and 7, gating is performed in the next cycle after receiving “D3” of the calibration pattern. In this example, “D4 to D6” may be replaced with “D5 to D7” because of the relationship between the cycle setting value and the actual delay. For this reason, if “D4 to D7” of the calibration pattern are all the same value, the value before the replacement and the value after the replacement are the same value, which is not preferable for detecting the delay (cycle delay). In the examples of FIGS. 6 and 7, it is preferable that “D4 to D7” of the calibration pattern be the following patterns in consideration of the correlations (1) to (4).

“D4 to D7 = 0101”
This is set based on the correlations (1) to (4). Of course, even if “1” and “0” are opposite, an expected value corresponding to that case may be set.

  Furthermore, FIG. 20 shows the relationship between the difference from the actual number of cycles and the received pattern (received data 236) when this calibration pattern (expected value) is used. The difference between the actual number of cycles can be determined based on information indicating the relationship between the received pattern and the delay amount shown in FIG. Note that it is necessary to set a pattern in which different calibration patterns are received 1: 1 depending on M. Therefore, when using a gating pattern along the correlations (1) to (4), the continuous value (bit, “1”, “0”, etc.) in the calibration pattern is first transferred to the external device controller 103. When a predetermined number of values different from the input value are continuous, a delay up to a predetermined number of cycles can be detected. That is, it is preferable that a value different from the value input immediately before (to the reception data SP conversion unit 210) continues for the number of delay cycles that can be detected. In the case of “D4 to D7 = 0101” described above, it can be assured that a value different from the value input immediately before is continuous in the portion “101”.

  Note that delay information (such as a look-up table as shown in FIG. 20 or a simple numerical sequence) indicating this relationship is tested in advance and stored in the DRAM 106 or other storage device that can be referred to by the CPU 101 to determine the cycle delay amount. The CPU 101 may refer to it when doing so.

  Next, FIG. 18 shows signals handled by the external device controller 103 and the external device 107 during data reception when the configuration of FIG. 1 is operated using correct parameters (skew setting value, cycle setting value). . Similarly to the example of FIG. 24, the example of FIG. 18 has a cycle delay of one cycle, but when the calibration is completed and the cycle selection value 249 (cycle setting value 256) corresponding to one cycle is set. The waveform is shown. (Note that when the delay occurring in the reception data 236 is one cycle, the setting indicated by the correct cycle selection value 249 (cycle setting value 256) is 1. Since the setting indicated by the cycle selection value 249 is 1, The reception enable signal 250 is delayed by one cycle by the cycle control unit 603 with respect to the output clock enable signal 243.)

  In the example of FIG. 18, when reception of “D0” is started for the reception data 236 in the serial format, the output clock enable signal 243 is deasserted and the output clock 244 is gated. Although the output clock 244 is gated, “D 1” and “D 2” are transmitted from the external device 107 for the received data 237 in the serial format. One cycle after the start of deassertion of the output clock enable signal 243, the reception enable signal 250 is also deasserted. The reception data SP conversion unit 210 receives the deassertion of the reception enable signal 250, and immediately stops receiving the serial format reception data.

  Therefore, reception of data is stopped while receiving “D1” of the reception data 235 after skew adjustment. Looking at the first bit data of the reception data 234 in parallel format, it can be seen that “D1” can be received, and that the data acquisition stop timing of the reception data SP converter 210 can be adjusted to correspond to the cycle delay.

  Further, the output clock enable signal 243 is asserted again one cycle after being deasserted, and the gating of the output clock 244 is released in response to the assertion. Here, even if the gating of the output clock 244 is cancelled, since the received data 236 has a delay of one cycle or more, “D2” of the serial format received data 236 is continuously transmitted from the external device 107.

  The reception enable signal 250 is also asserted one cycle after the assertion of the output clock enable signal 243 by the delay amount (one cycle) indicated by the cycle setting value 256. The reception data SP converter 210 immediately receives the serial reception data in response to the assertion of the reception enable signal 250. Therefore, “D2” of the received data 236 in the serial format can be correctly received. Looking at the first bit of the reception data 234 in the parallel format, it can be seen that “D2” has been correctly received, and the data acquisition restart timing of the reception data SP converter 210 can be adjusted to correspond to the cycle delay.

  As described above, in this embodiment, it is possible to prevent the calibration from being completed while the setting is not correct. Therefore, even if the received data 236 has a delay of one cycle or more, it can be correctly detected.

  Also, according to the cycle control unit 603 of the present embodiment, if the correct cycle setting value 256 is set, the received data is set so as to correspond to the amount of cycle delay that occurs between the external device controller 103 and the external device 107. The data acquisition stop timing and the data acquisition restart timing of the SP converter 210 can be delayed. This suppresses the occurrence of data loss as shown in FIG.

  In the above-described embodiment, the skew control unit 211 and the cycle control unit 603 are separately configured. However, the skew adjustment and the cycle adjustment may be combined as a single configuration or combined with the reception data SP conversion unit 210. May be. Furthermore, in skew adjustment, adjustment is performed by inputting a clock with corrected deviation. However, a delay configuration (delay element, flip-flop) for skew adjustment and cycle adjustment is directly arranged in the data supply system, and a selector, etc. The delay amount may be selected with.

  Although the above-mentioned embodiment does not mention the opportunity to execute the calibration process, the effect of the present invention can be obtained by performing calibration at the same opportunity as a known external device controller. For example, when the ASIC 100 starts up, when the external device controller 103 is initialized, every predetermined time (for example, every 10 msec at 208 MHz) or every predetermined number of cycles, or when the ASIC 100 detects a connection with the external device 107, it is performed. That's fine.

  In the above-described embodiment, the cycle calculation unit 602, the cycle setting register 601, and the expected value setting register 604 are described as hardware, but may be realized by software instead of the CPU 101. In this case, the CPU 101 reads out and executes a program for realizing the function as the cycle calculation unit 602 from the DRAM 106 or the like, and secures storage areas corresponding to various registers in the cache (or DRAM 106) of the CPU 101, as described above. The values stored in various registers are stored in the storage area.

  Regarding the wiring delay between the external device 107 and the external device controller 103 described above, it is considered that the variation in the delay amount increases when the external device 107 is configured to be detachable from the external device IF 112. Actually, in addition to the length, material, and temperature rise of the wiring, it is considered that a delay due to various factors such as poor contact is included.

  The above embodiment does not exemplify the frequency of the host clock 115, but the higher the operating frequency, the more the cycle of the received data 236 generated in the configuration shown in FIG. Delay detection becomes difficult, and calibration failure tends to occur. In order to exchange data between the external device controller 103 and the external device 107 at a higher speed, it is conceivable to increase the frequency of the host clock 115. Therefore, the present invention also contributes to the realization of high-speed and highly reliable data communication. That's right.

  In the above-described embodiment, the cycle calculation unit 602 compares the calibration pattern (received data 234) with the expected value to perform cycle adjustment. However, the CPU 101 reads the expected value and performs comparison processing in the same manner as skew adjustment. You may make it do.

  In the above-described embodiment, the data portion (D0, D1,... In FIG. 21b) of the reception data 236 is compared. However, the CRC portion (CRC0, FIG. 21b) calculated by the reception data SP conversion unit 210 as a calculation unit is compared. CRC1 ...) may be used for comparison. In that case, it is necessary to previously calculate and store the CRC received when the skew setting and the cycle setting are normal for the calibration pattern stored in advance.

  In FIG. 1, the external device controller 103 and the external device 107 are described as communicating using a 1-bit width bus, but a 4-bit width bus, an 8-bit width bus, or the like may be used. Can be applied without being limited to the bus width. However, for example, when a 4-bit (8-bit) bus is used, four flip-flops 218 and four delay selection units 217 may be arranged in the skew control unit 211 so that skew adjustment can be performed for each 1-bit width. In this case, the reception data SP conversion unit 210 only has to merge 4 bits, and the data that the external device 107 is trying to output is changed to the reception data SP conversion unit 210 or the reception buffer 209 by changing the order of the 4 bit data. A configuration that matches is required.

  In the above-described embodiment, only an example in which the operating frequency of the host clock 115 is single has been described. However, the operating frequency may be switched by identifying the external device 107. For example, a frequency dividing circuit or a multiplying circuit for dividing the host clock may be provided between the CLOCK generator 105 and the external device controller 103 to change the frequency of the host clock input to the external device controller 103. In this case, in addition to the CLOCK generator 105, a frequency division circuit and a frequency multiplication circuit are part of the oscillation means.

  At this time, when the above-described calibration is not successful, the host clock 115 input to the external device 107 may be decreased to a lower frequency to stabilize communication with the external device. The case where the calibration is unsatisfactory means that, for example, the above-described calibration occurs a predetermined number of times per unit time or the time required for calibration is a predetermined time or more (for example, the number of times required for the total number of times) May be required. In addition, when the physical connector shape of the external device IF 112 is designed to be fitted to a specific type of external device 107 defined in the standard, the frequency to be switched by a frequency divider or a multiplier circuit is determined by a specific type of standard. May be used. (For example, if it is not good at 208 MHz, switch to 100 MHz, etc.) This makes it possible to maintain the backward compatibility of the external device controller 103 in the case of an external device of the same system whose operating frequency differs depending on the version.

  Further, the transmission buffer 207 and the reception buffer 209 in the above-described embodiment may have a FIFO structure. In this case, the buffer full signal and the buffer empty signal may be created based on information (remaining amount information) indicating the FIFO free capacity, or the remaining amount information may be used as it is. In this case, if the size of the data that can be stored in the FIFO of the reception buffer 209 is equal to or larger than the size of the data of the calibration pattern, the CPU 101 may write the calibration pattern once in the FIFO and use it as it is for comparison. . However, when the data size that can be stored in the FIFO of the reception buffer is smaller than the calibration pattern, it is preferable to compare sequentially (every predetermined cycle) by the data size equal to or smaller than the FIFO capacity of the calibration pattern. Alternatively, it is possible to branch to a configuration in which comparison is performed sequentially without being taken into the FIFO of the reception buffer 209 during calibration. (It is only necessary to configure a comparator for data for a predetermined cycle, which has a configuration different from that of the CPU 101 as a comparison means, and is configured as a register that reads out the expected values of the same data size.) This is because the reception buffer 209 may overflow when the clock is not stopped by the clock control means 223.

  Further, the control signal such as the output clock enable signal 243 in the above-described embodiment may be configured to assert the disable signal at the timing when the enable signal is deasserted.

  In the above-described embodiment, the present invention has been described as the information processing apparatus having the external device controller 103. However, the present invention can be applied to the case where the configuration of the external device 107 is included in the information processing apparatus. It can be said. In addition, examples of the information processing apparatus to which the present invention is applied include various apparatuses such as an image processing apparatus and a calculation processing apparatus.

  The present invention can also be realized by executing the following processing. That is, software (program) for realizing the functions of the above-described embodiments is supplied to a system or apparatus via a network or various storage media, and a computer (or CPU, MPU, etc.) of the system or apparatus reads the program. It is a process to be executed.

Claims (17)

  1. Supply means for supplying a clock to an external device;
    Control means for transmitting a control signal for stopping the supply of the clock to the supply means;
    Receiving means for receiving data output by the external device in synchronization with the clock, and stopping capturing of the data in response to the control signal;
    First delay means for correcting a phase shift of data received by the receiving means ;
    Second delay means for delaying the data fetching timing of the receiving means using the control signal delayed so as to correct a shift in a cycle unit of the data corrected by the first delay means ;
    An information processing apparatus comprising:
  2. Further comprising an oscillating means for oscillating the clock;
    The first delay means corrects the phase shift by delaying the data received by the receiving means by an amount smaller than one cycle of the clock oscillated by the oscillating means,
    The second delay means delays the control signal by an integral multiple of one cycle of the clock oscillated by the oscillating means and inputs the delayed signal to the receiving means, thereby shifting the shift of the data fetch timing in units of cycles in the receiving means. The information processing apparatus according to claim 1, further comprising: correcting the information processing apparatus.
  3. Instruction means for instructing the external device to transmit a calibration pattern to be received by the receiving means;
    A first clock control mode for stopping the supply of the clock by the supply means and a second clock control mode for not stopping the supply of the clock are selected based on gating information indicating when the clock is stopped. Selection means for functioning automatically,
    The selecting means causes the second clock control mode to function when adjusting a phase shift of the calibration pattern, and causes the first clock control mode to function when adjusting a cycle delay of the calibration pattern. The information processing apparatus according to claim 1, wherein the information processing apparatus is characterized.
  4. Storage means for holding an expected value of a calibration pattern to be received;
    A determination unit that compares the calibration pattern received by the reception unit with the expected value held by the storage unit in a state where the control unit is caused to function by the selection unit, and determines whether or not they match. The information processing apparatus according to claim 3.
  5.   The determination unit determines that the calibration pattern received by the reception unit matches the expected value, and determines that the adjustment of the data capture timing by the reception unit is completed. The information processing apparatus described in 1.
  6.   6. The calibration pattern according to claim 3, wherein the calibration pattern includes a plurality of values, and each of a predetermined number of consecutive values among the plurality of values is different from the immediately preceding value. The information processing apparatus described.
  7.   The information processing apparatus according to claim 6, wherein the predetermined number is equal to or greater than a number of cycles corresponding to a delay amount that can occur between the information processing apparatus and the external device.
  8. Holding the data received by the receiving means, further having a holding means for notifying itself when the data cannot be held;
    The selection unit functions as a third clock control mode for receiving a notification from the holding unit and stopping the supply of the clock by the supply unit when the adjustment of the data capture timing based on the calibration pattern is completed. The information processing apparatus according to claim 3, wherein the information processing apparatus is an information processing apparatus.
  9.   The information processing apparatus according to claim 8, wherein the holding unit has a FIFO structure, and the notification is based on a signal indicating the remaining amount information of the FIFO.
  10.   And further comprising identification means for judging the type of communication with the external device, and when the external device can be judged not to be of a predetermined type, the selecting means adjusts the data fetch timing of the receiving means when the data acquisition timing is adjusted. 10. The information processing apparatus according to claim 8, wherein the three-clock control mode is made to function.
  11.   The second delay means has a plurality of flip-flops whose inputs and outputs are connected in series, and selectively outputs one of the plurality of flip-flops when the control signal is delayed by a period. The information processing apparatus according to claim 1, wherein the information processing apparatus is an information processing apparatus.
  12. The gating information, the information processing apparatus according to any one of claims 3 to 10, characterized in that it has information indicating that the supply means at periodic timing stops the clock.
  13. The gating information, claims 3 to 10, characterized in that indicating the clock stopped start timing, the timing for releasing the stopping of the clock, at least one of periodically stopping the clock by the control means , 12 information processing apparatus according to any one of.
  14.   And further comprising an identifying means for judging the type of communication with the external device, and when the external device can be judged to be of a predetermined type, the selecting means adjusts the data fetch timing of the receiving means The information processing apparatus according to claim 3, wherein the first clock control mode is made to function.
  15.   15. The control unit according to claim 1, wherein the control unit starts to stop the clock at at least one timing at which a value of the calibration pattern received by the receiving unit varies. Information processing device.
  16.   16. The control unit according to claim 1, wherein the control unit releases the stop of the clock at one of timings at which a value of the calibration pattern received by the receiving unit varies. The information processing apparatus according to item.
  17. Supplying a clock to an external device;
    A control step of transmitting a control signal for stopping the supply of the clock in the supply step;
    Receiving the data output by the external device in synchronization with the clock, and receiving the data in response to the control signal; and
    A first delay step of correcting a phase shift of data received in the reception step ;
    A second delay step of delaying the data capture timing of the receiving means by using the control signal delayed so as to correct a shift in a cycle unit of the data corrected by the first delay means ;
    An information processing method characterized by comprising:
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