JP2012124716A - Data receiver, data transmitter, control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data receiver, a data transmitter, and a control method, capable of solving a problem in which there is a possibility that a data receiver fails to acquire data supplied by a data transmitter, when there is a delay of 1 cycle or more between data the data receiver receives from the data transmitter and a clock the data receiver outputs to the data transmitter.SOLUTION: The data receiver, the data transmitter, and the control method, when transmitting a command to the data transmitter, count a cycle number between a transmission end timing of the command and a reception start timing of data corresponding to the command from the transmitter.

Description

  The present invention relates to calibration of data transfer between a data receiving device and a data transmitting device.

  As disclosed in Patent Document 1, there is a technique for supplying an operation clock from an apparatus for receiving data (data receiving apparatus) to an apparatus for supplying data (data transmitting apparatus). In such a technique, the data transmission device is set to output data in synchronization with the clock supplied from the data reception device, and the data reception device is configured to capture the data output from the data transmission device. It is common.

  When this method is used, the data receiving device temporarily stops the supply of data from the data transmitting device to the data receiving device by temporarily stopping the supply of the clock to the data transmitting device (corresponding to clock gating). Can be stopped. For example, when the data is stored up to the allowable capacity of the reception buffer in the data receiving device, the data receiving device can stop supplying the clock, and accordingly, the data transmitting device can stop supplying data. Buffer overflow can be suppressed with a small but simple configuration.

JP 59-173839

  In the technique of supplying an operation clock from the data reception device to the data transmission device, the influence of a wiring delay between the data reception device and the data transmission device increases as the clock frequency increases. When there is a delay of one cycle or more between the data received by the data receiving device from the data transmitting device and the clock output from the data receiving device to the data transmitting device, the data receiving device is supplied from the data transmitting device. Data may be lost. This includes a control system that stops the clock to the data transmission device in the data reception device, and a data transfer system that supplies the clock from the data reception device to the data transmission device and outputs data in synchronization with the clock. This is because there is a gap between them.

  In order to solve the above-mentioned problem, a data receiving apparatus according to the present invention is a data receiving apparatus connected to be communicable with a data transmitting apparatus, and a supply means for supplying a clock to the data transmitting apparatus; Receiving means for receiving data output in synchronization with the clock, transmitting means for transmitting a command to the data transmitting apparatus, transmission end timing of the command, and data corresponding to the command from the transmitting apparatus And counting means for counting the number of cycles between the reception start timing and the reception start timing.

  In order to solve the above problems, a data transmission device according to the present invention is a data transmission device connected to be communicable with a data reception device, the storage means holding predetermined data, and the data reception device Output means for outputting the predetermined data to the data receiving device in a predetermined number of cycles in synchronization with a clock supplied from the data receiving device when a calibration command related to data reception is received from the device. Features.

  Even if the influence of the wiring delay between the data transmission device and the data reception device becomes large, data loss on the data reception device side can be suppressed.

It is a block diagram of the data receiver in one Embodiment of this invention. It is the block diagram and timing chart of a skew control part. It is a block diagram and a timing chart of a cycle control part. It is the flowchart of a calibration process, and the block diagram of an output clock control part. It is a timing chart which measures the number of delay cycles. It is a block diagram of a delay cycle number counting circuit. It is a block diagram of the data transmitter in one Embodiment of this invention. It is the schematic of a system configuration | structure which has a data transmitter and a data receiver. It is a timing chart which shows the format of a command or data. It is a timing chart at the time of using a correct cycle setting. It is a timing chart at the time of using a different cycle setting.

  An embodiment of the present invention will be described below with reference to the drawings.

  FIG. 8 shows a data transmission device 107 (hereinafter referred to as an external device 107) that functions as a device that supplies data, and a data reception device (hereinafter referred to as ASIC 100) that functions as a device that receives data from the data transmission device 107. It is a block diagram which shows the state where is connected. The ASIC 100, which is an LSI having a function of communicating with the external device 107, includes a CPU 101, a DRAM controller 104, a DMA controller 102, an external device controller 103 (hereinafter abbreviated as a device control unit 103), and a CLOCK generator 105. (ASIC is an abbreviation for Application Specific Integrated Circuit, and DMA is an abbreviation for Direct Memory Access.)

  Further, the CLOCK generator 105 as an oscillating means generates and supplies clocks (cpu_clock 113, dmac_clock 114, host_clock 115, drum_clock 116) used by the CPU 101, the DMA controller 102, the device control unit 103, and the DRAM controller 104.

  The CPU 101 performs register access to the device control unit 103, the DMA controller 102, and the DRAM controller 104 via the CPU I / F 110. The DMA controller 102 performs data transfer with the DRAM controller 104 via the CPU I / F 110. The DRAM controller 104 performs data transfer with the DRAM 106 via the DRAM I / F 117. The device control unit 103 performs data transfer with the DMA controller 102 via the DMA I / F 111. Further, the device control unit 103 performs data transfer with the external device 107 via the external device I / F 112.

  FIG. 1 shows a configuration of a device control unit 103 according to an embodiment of the present invention. The details of the external device 107 that is communicably connected to the device control unit 103 will be described later, and are therefore abbreviated in FIG. The device control unit 103 receives a host clock 115 (host_clock in the figure) from the CLOCK generator 105. The host clock 115 is connected to each component in the device control unit 103, and each component of the device control unit 103 operates in synchronization with the host clock 115.

  The CPU I / F control unit 201 receives data, commands, and register access from the CPU 101, and transmits commands and data to the CPU 101. The DMA I / F control unit 111 receives data to be transmitted to the external device 107 from the DMA controller 102, while transmitting data to be received from the external device 107 to the DMA controller 102.

  The device control unit 103 exchanges commands with the external device 107 via the command parallel / serial conversion unit 125 and the reception command serial / parallel conversion unit 126. First, the CPU I / F control unit 201 transmits a transmission command 223 (s_cmd) in parallel format received from the CPU 101 to the transmission command parallel / serial conversion unit 125 (hereinafter referred to as a transmission command PS conversion unit) via the CPU I / F 110. . The transmission command PS conversion unit 125 converts the received transmission command 223 in the parallel format into a transmission command 224 (s_cmd_data) in the serial format and transmits it to the external device 107.

  The external device 107 decodes the received serial format transmission command 224 and detects the transmission command. Furthermore, the external device 107 transmits detection information indicating the detection result of the transmission command to the device control unit 103 as a serial reception command 226 (r_cmd_data).

  The reception command SP conversion unit 126 receives the serial format reception command 226 output from the external device 107, converts it into a parallel format reception command 225 (r_cmd), and passes through the CPU I / F control unit 201 and the CPU I / F 110. To the CPU 101.

  The device control unit 103 exchanges data with the external device 107 via the transmission buffer 207, the transmission data parallel / serial conversion unit 208, the skew control unit 211, the reception data serial / parallel conversion unit 210, and the reception buffer 209. In addition, an output clock control unit 213 and an output clock gating unit 214 are provided to deassert the output clock 244 and stop data supplied from the external device 107. The output clock control unit 213 outputs a clock gating signal from the state of the transmission buffer 207 / reception buffer 209 of the device control unit 103 and the serial communication state (rcv_status 239, snd_status 240). The output clock gating 214 is mounted with a clock gating cell for receiving the clock gating signal and gating the host clock 115 (host_clk).

  Further, the device control unit 103 has a circuit for a calibration (details will be described later) process including skew adjustment (correction) and cycle adjustment (correction). The device control unit 103 includes a skew control unit 211 and a skew setting register 212 in order to perform skew adjustment (correction). Here, the skew adjustment (correction) is a data acquisition timing (latch timing) of the reception data serial / parallel conversion unit 210 (hereinafter referred to as reception data SP conversion unit) (with respect to the host clock 115) by a delay within one cycle. Indicates adjustment (correction).

  The skew setting register 212 receives and holds the skew setting value 227 (skew_reg) from the CPU I / F control unit 201. The skew control unit 211 receives the skew selection value 238 (skew_sel) from the skew setting register 212, and receives the serial format received data 236 (d2h_data, hereinafter simply referred to as received data 236) from the external device 107 according to the set value. Delay).

  The device control unit 103 includes a delay cycle number counting circuit 610 and a cycle control unit 603 in order to perform cycle adjustment (correction). Here, the cycle adjustment (correction) refers to the reception data SP conversion unit 210 by delaying the reception enable signal 250 (rcv_en), which is a control signal of the reception data SP conversion unit 210, in units of cycles (relative to the host clock 115). This indicates that the data acquisition stop timing and the data acquisition restart timing are adjusted (corrected).

  The delay cycle number counting circuit 610 is a circuit that measures how many cycles the reception data 236 received by the device control unit 103 from the external device 107 is delayed with respect to the output clock 244 output by the device control unit 103. The cycle control unit 603 delays the output clock enable signal 243 (dev_clk_en) by the number of cycles corresponding to the cycle selection value 249 measured by the delay cycle number counting circuit 610, generates the reception enable signal 250 (rcv_en), and receives the received data The SP conversion unit 210 is instructed to take in data.

  Next, FIG. 7 shows the configuration of the external device 107 of this embodiment. In the present embodiment, a flash memory device is used as the external device 107. The device control unit 103 is as shown in FIG. 1, and its detailed configuration is omitted. The calibration pattern area 335 has an IO area such as a register, and data can be output to the device control unit 103 in a fixed cycle. For example, when there is no wiring delay between the data receiving apparatus and the data transmitting apparatus, a fixed cycle access time (latency) is required from the output of the command by the device control unit 103 to the reception of data from the calibration pattern area 335. . The flash memory area 334 can output data within a predetermined period. (The predetermined period is a period defined by a standard or the like. For example, when the period is determined such as min = 2 cycle, max = 1 second, the device control unit 103 outputs a command. (Waiting for data to come during this period.)

  The external device 107 receives the clock signal 245 (dev_clk ′) output from the device control unit 103. The clock signal 245 is connected to each component in the external device 107, and each component of the external device 107 operates in synchronization with this clock signal 245.

  The external device 107 parallelizes the serial-format command 324 (s_cmd_data ′) received from the device control unit 103 by a reception command serial / parallel conversion unit 325 (hereinafter simply referred to as a reception command SP conversion unit 325), and sends it to the command control unit 301. send. The command control unit 301 decodes the parallelized command, and uses the decoded result as a serial command 326 (r_cmd_data ′) by a transmission command parallel / serial conversion unit 327 (hereinafter referred to as a transmission command PS conversion unit 327). Serialized and transmitted to the device control unit 103.

  If the command decoded and interpreted from the device control unit 103 includes a data transfer command, the command control unit 301 sends data to the transmission data control unit 304 or the reception data control unit 305 based on the data transfer command. Instruct transfer.

  First, a case where the command control unit 301 receives a command (data write) indicating data transfer from the device control unit 103 to the external device 107 will be described. Serial data 331 (h2d_data ′) from the device control unit 103 is parallelized by a reception data serial / parallel conversion unit 308 (hereinafter referred to as a reception data SP conversion unit 308). Then, based on an instruction from the command control unit 301, the reception data control unit 305 adds information such as a storage address to the parallel data, and sends the data to the flash memory area 334.

  Next, a case where the command control unit 301 receives a command (data read) requesting data transfer (normal flash memory read) from the external device 107 to the device control unit 103 will be described. The transmission data control unit 304 sends an address to the flash memory area 334 through a path (not shown), extracts the data, and serializes it by the transmission data parallel serial conversion unit 310 (hereinafter referred to as the transmission data PS conversion unit 310). Then, the received data 237 (d2h_data ′) is transferred to the device control unit 103. At this time, the transmission data selection unit 333 operates to send the data from the flash memory area 334 to the transmission data control unit 304 based on the selection signal 336 (calib_sel) from the command control unit 301.

  Next, a case where the command control unit 301 receives a command instructing data transfer related to calibration from the external device 107 to the device control unit 103 will be described. First, the command control unit 301 controls the transmission data selection unit 333 to operate so as to send data from the calibration pattern region 335 to the transmission data control unit 304 by the selection signal 336. Then, the transmission data control unit 304 reads the calibration pattern from the calibration pattern area 335, serializes it by the transmission data PS conversion unit 310 in the same way as normal data, and transfers it to the device control unit 103.

[Calibration process in device controller 103]
A path in which a clock is supplied from the device control unit 103 to the external device 107 and data is transferred from the external device 107 to the device control unit 103 in synchronization with the clock is a round-trip path.

Therefore, when the clock frequency is increased, the influence of wiring delay and the like is increased. For example, even if the wiring delay is negligible with a delay equivalent to 1/2 cycle at a clock of 1, the actual time of the wiring delay does not change if the clock is doubled, but the delay equivalent to 1 cycle is Will occur. In the path that reciprocates between the external device 107 and the device control unit 103, the time constraint becomes more severe.
The calibration by the device control unit 103 that can cope with the case where the clock frequency becomes high will be described with reference to the flowchart of FIG.

  The calibration flow in FIG. 4 includes skew adjustment (correction) that means delay adjustment within one cycle and cycle adjustment (correction) that means delay adjustment in units of cycles.

  Here, the skew adjustment is an adjustment to correct a phase shift between the host clock 115 and the reception data 236 (phase shift). On the other hand, the cycle adjustment is an adjustment that corrects the shift of the host clock 115 and the received data 236 in units of periods. In the following description, a period shift (corresponding to a shift in data capture timing or a shift in data capture restart timing) is simply referred to as a delay cycle number (or cycle delay amount).

  First, in step S1202 of FIG. 4, when the device control unit 103 is instructed to start calibration by the CPU 101, the device control unit 103 transmits a transmission command for outputting a calibration pattern to the external device 107. The external device 107 outputs a predetermined calibration pattern held in the calibration pattern area 335 to the device control unit 103 in accordance with a command from the device control unit 103. The device control unit 103 receives the calibration pattern, and the received calibration pattern is written to the DRAM 106 via the DMA controller 102 and the DRAM controller 104.

  After the series of calibration patterns is written in the DRAM 106, the CPU 101, in step S1023, the calibration pattern (part of) stored in the DRAM or the like as an expected value in advance and the calibration pattern actually received. (Part of) is compared (S1203). If the CPU 101 determines that they match, the skew setting is considered correct, and the skew adjustment sequence is completed. On the other hand, if the two do not match, it is considered that the skew setting is incorrect. In step S1204, the CPU 101 sets a different skew setting value 227 in the device control unit 103, and performs a skew adjustment sequence (S1202 and S1203) again. The above processing is repeated until the calibration pattern matches the expected value.

  If the correct skew setting is made in the skew adjustment sequence and the calibration pattern matches the expected value, the process proceeds to the cycle adjustment sequence. In step S1205, the delay cycle number counting circuit 610 outputs delay cycle information 249 (cycle_sel). (Note that in the cycle control unit 603, the delay cycle information 249 is directly input to the selector 702 as the cycle selection value 249, but is the same signal.)

  This delay cycle information 249 means the number of delay cycles actually generated between the device control unit 103 and the external device 107. In S1206, based on this delay cycle information 249, the output clock control 213 sets an appropriate delay cycle for the output clock enable signal 243, and the calibration is completed.

[Calibration process in external device 107]
When the external device 107 receives a command instructing calibration from the device control unit 103 (equivalent to a command instructing to transfer the calibration pattern), the external device 107 transmits the calibration pattern to the device control unit 103 as reception data 237.

  Normally, when the external device 107 is a storage medium such as a flash memory, reading from the flash memory area 334 is not a fixed cycle, and the access time is defined by a period (minimum allowable time or cycle to maximum allowable time or cycle). Yes. The external device 107 can output data with a start bit (and end bit) at an arbitrary timing within a specified period. The device control unit 103 is controlled to wait for a start bit for a specified period. On the other hand, the calibration pattern area 335 according to the present embodiment outputs a calibration pattern in a predetermined fixed cycle after the external device 107 receives a command from the device control unit 103 instructing calibration. To do.

  For this reason, even if a calibration command is received, a calibration pattern cannot be returned in a fixed cycle depending on the state of the external device 107, so that an error response may be returned as the command 326. If the calibration pattern cannot be returned in a fixed cycle, the calibration pattern may not be output and the error may be terminated.

  Alternatively, the device control unit 103 may hold a setting related to the time range in a register (not shown) or the like and wait for a start bit. Alternatively, the external device 107 may be provided with a register holding the setting related to the time range. To the device control unit 103.

[Command data format]
The device control unit 103 and the external device 107 exchange serial commands or serial data with the format shown in FIG. In the following description, it is assumed that parallel commands and parallel data used in the device control unit 103 or the external device 107 have the same format.

  First, signals handled during transmission / reception of the serial transmission command 224 and the serial reception command 226 will be described with reference to FIG. The transmission command 224 includes a 1-bit start bit, an N-bit transmission command, an M-bit CRC (cyclic redundancy check signal), and a 1-bit end bit. The transmission command 224 and the reception command 226 may have different command lengths and CRC lengths.

  Next, processing performed by the device control unit 103 and the external device 107 in a configuration for outputting a signal having the format shown in FIG. 9 will be described.

  When the transmission command PS conversion unit 125, 326 detects the reception of the parallel transmission command, it first outputs a 1-bit start bit, and then converts the N-bit parallel transmission command into a serial transmission command. And output. The transmission command PS converters 125 and 326 perform CRC calculation together with transmission of a serial transmission command. Then, after outputting the serial transmission command, the M-bit CRC obtained by the calculation is output, and finally the 1-bit end bit is transmitted to complete the command transmission.

  The received command SP converters 126 and 325 detect 1 start bit and start receiving the command. Subsequently, an N-bit serial format reception command is received and converted into a parallel format reception command. The reception command SP conversion units 126 and 325 perform CRC calculation together with reception of a serial reception command. Then, after receiving the reception command in the serial format, a comparison between the calculated CRC and the transmitted M-bit CRC (cyclic redundancy check) is performed to detect a CRC error. Finally, 1 end bit is received and command reception is completed.

  When receiving transmission data in parallel format, transmission data PS converters 208 and 310 convert the transmission data to transmission data in serial format and transmit it. The format of the received data is as shown in FIG. However, the length of the received data and the length of the CRC may be different from the transmission command.

  The reception data SP converters 210 and 308 start receiving data when detecting one start bit. The processing itself is the same as that of the received command SP conversion units 126 and 325, and only the data is handled instead of the command, so the details are omitted.

[Data Reception Processing in Device Control Unit 103]
When starting to receive data, the device control unit 103 first transmits a transmission command for instructing data output to the external device 107 by the above-described command transmission / reception process. As a result, data is sent from the external device 107.

  Data reception from the external device 107 by the device control unit 103 is performed as follows. First, the skew control unit 211 receives serial format received data 236 (d2h_data) transmitted from the external device 107.

  The skew control unit 211 performs skew adjustment between the serial format received data 236 and the clock 115 (host_clk) of the device control unit 103. The reception data 235 after skew adjustment is input to the reception data SP conversion unit 210.

  The reception data SP conversion unit 210 is configured to receive a reception enable signal 250 obtained by delaying the output clock enable signal 243 output from the output clock control unit 213 by a cycle control unit 603 described later. If the reception enable signal 250 is asserted, the reception data SP conversion unit 210 receives the received reception data 235 after skew adjustment and converts it into parallel reception data 234 (r_data_buf).

  The reception data SP conversion unit 210 has a shift register (serial input parallel output type flip-flop) of K stages (K is 2 to the power of k) (not shown) and receives data received in serial form in kbit parallel. It is configured to send as formatted data. Therefore, if the reception enable signal continues to be asserted, the reception data SP conversion unit 210 transmits parallel format data once every K cycles.

  The reception buffer 209 as a holding unit is configured to be able to notify that it is not allowed to hold more data than the data currently held by the reception buffer full signal 241. Therefore, if the reception enable signal 250 is asserted and the reception buffer full signal 241 (r_buff_full) of the reception buffer 209 is deasserted, the reception data SP conversion unit 210 transmits the reception data 234 in parallel format to the reception buffer 209. On the other hand, if reception enable signal 250 is not asserted, reception data SP converter 210 stops receiving reception data 235 after skew adjustment.

  The reception data SP conversion unit 210 asserts a reception status signal 239 (rcv_status) when reception of the external device 107 data is started. The reception data SP conversion unit 210 continues to assert the reception status signal 239 until the final data is received from the external device 107, and deasserts it when detecting the end bit of the reception data 235 after skew adjustment. When the reception data SP converter 210 transmits the reception data 234 in parallel format to the reception buffer 209, the reception buffer 209 deasserts the reception buffer empty signal 233 (r_buff_emp).

  The reception buffer 209 receives and holds the reception data 234 (r_data_buff) converted into the parallel format from the reception data SP conversion unit 210. Here, when the reception buffer 209 becomes full, the reception buffer 209 asserts the reception buffer full signal 241 to the output clock control unit 213 and the reception data SP conversion unit 210. On the other hand, when the reception buffer 209 becomes empty, the reception buffer 209 asserts a reception buffer empty signal 233 to the DMA I / F control unit 206.

  The DMA I / F control unit 206 receives the deassertion of the reception buffer empty signal 233 of the reception buffer 209 and detects that reception data from the external device 107 remains in the reception buffer 209. Then, the reception data 232 (r_data_dma) in parallel format held in the reception buffer 209 is received from the reception buffer 209 and transmitted to the DMA I / F 111. However, when the reception buffer 209 becomes empty, reception of data is stopped. If data reception is not stopped, a buffer underrun of the reception buffer 209 may occur. Accordingly, when the reception buffer empty signal 233 of the reception buffer 209 is asserted, the DMA I / F control unit 206 stops receiving the parallel format reception data 232 and transmits the data to the DMA I / F 111. To stop.

  When the reception buffer empty signal 233 of the reception buffer 209 is deasserted, the DMA I / F control unit 206 resumes reception of the reception data 232 in the parallel format, and resumes transmission of the reception data to the DMA I / F 111.

  On the other hand, when the reception buffer 209 becomes full, a buffer overrun of the reception buffer 209 occurs, so that data reception is interrupted. When the reception data SP conversion unit 210 is receiving data and the reception buffer 209 is full, the output clock control unit 213 outputs the output clock enable signal 243 to interrupt reception of data by the reception data SP conversion unit 210. Is deasserted (interrupt processing).

  That the reception data SP conversion unit 210 is receiving data is detected by asserting the reception status signal 239. The reception data SP converter 210 asserts the reception status signal 239 when the first reception data is received, continues to assert until the final data is received, and deasserts when the final data is received. For this reason, the output clock enable signal 243 is not deasserted while waiting for received data (waiting for the start bit detection).

  When the reception buffer 209 is not full during the interruption of data reception, the output clock control unit 213 asserts (returns) the output clock enable signal 243 in order to resume data reception by the reception data SP conversion unit 210. . Note that the cycle control unit 603 performs an operation of delaying data reception interruption and recovery by the reception data SP conversion unit 210 in units of cycles.

[Data Transmission Processing in External Device 107]
When the supply of the output clock 245 (dev_clk ′) is stopped, the external device 107 temporarily stops transmission of the reception data 237 (d2h_data ′) until it is restarted. Specifically, when transmission is stopped, the signal line between the transmission data PS conversion unit 310 and the skew control unit 211 remains maintained at the signal level at the start of the stop.

[Configuration for skew correction]
Next, a detailed configuration of the device control unit 103 for performing skew correction will be described.

  FIG. 2A is a block diagram of the skew control unit 211. The skew control unit 211 receives the host clock 115 from the CLOCK generator 105 (FIG. 8). The host clock 115 is delayed by N1 delay elements 216 (first delay means) whose inputs and outputs are connected in series. The output of each delay element 216 is input to the delay selection unit 217, and the delay element 216 used for output is selected based on the value of the skew selection value 238 (skew_sel).

  The selected delayed clock signal 246 (clk_with_skew) is input to the flip-flop 218 as a clock. On the other hand, the serial format received data 236 (d2h_data) transmitted from the external device 107 is received by the flip-flop 218, and is synchronized with the delayed clock signal 246 (clk_with_skew) by the flip-flop 218. The synchronized serial format received data is output to the received data SP conversion unit 210 by the skew control unit 211 as serial format received data 235 (d2h_data_1d) after skew adjustment.

  The N1 delay elements of the skew control unit 211 preferably cause a delay obtained by dividing one clock (of the host clock 115) into N1 equal parts or a little smaller than that.

  FIG. 2B is a timing chart of signals handled by the skew control unit 211 when the skew setting values are 0, 1, and 2. When each signal in FIG. 2B is associated with the codes in FIG. 1 and FIG. 2).

  In the timing chart of FIG. 2B, when the skew selection value 238 (skew_sel) is 0 and 1, d2h_data 236 is indefinite at the rise of clk_with_skew 246. Therefore, the data d2h_data_1d235 taken into the flip-flop 218 is also undefined, and correct data cannot be received. On the other hand, when the skew selection value 238 is 2, since d2h_data 236 outputs correct data at the rise of clk_with_skew 246, correct data is also acquired in the data d2h_data_1d235 fetched into the flip-flop 218. The skew selection value 238 is adjusted by the calibration skew adjustment sequence described above.

[Configuration for delay cycle count measurement]
Next, the configuration of the device control unit 103 that measures the number of cycle delays described above will be described.

  FIG. 6 shows a schematic configuration of the delay cycle number counting circuit 610. As shown in FIG. 6, the delay cycle number counting circuit 610 includes a counter control unit 613, a counter 614, and a subtracter 615. As input information, there are information (end bit detection signal, s_cmd_ebit 611) indicating the transmission end timing of the serial format transmission command 224 and information (start bit detection signal, r_data_sbit 612) indicating the reception start timing of the serial format reception data 235. .

  The end bit detection signal 611 is a signal that is asserted when the transmission command PS conversion unit 125 detects the end bit of the transmission command 223. The start bit detection signal 612 is a signal that is asserted when the reception data SP conversion unit 210 detects the start bit of the reception data 235.

  Accordingly, the counter control 613 outputs a count-up signal 617 (count_up) to the counter 614. Specifically, the counter control unit 613 controls the counter 614 to count up after the end bit detection signal 611 is asserted until the start bit detection signal 612 is asserted.

  That is, the counter 614 is transmitted from the device control unit 103 to the external device 107 starting from the time when it passes through the command transmission command PS conversion unit 125 that instructs calibration, and the external device 107 responds and returns the calibration pattern. The number of measurement cycles 616 (acc_count) until the device control unit 103 fetches data is counted. The subtracter 615 calculates the number of delay cycles by subtracting the number of measurement cycles 616 by the number of received access cycles of the predetermined calibration pattern (the number of received access cycles is 9 in the example shown in FIG. 5).

  Specifically, if the number of measurement cycles 616 is 9, a cycle delay does not occur at 9-9, and if the number of measurement cycles 616 is 10, a cycle delay of 1 cycle occurs at 10-9. Means.

  FIG. 5 shows a timing chart of signals (reception data 235, measurement cycle number 616, count-up signal 617, cycle selection value 249) related to delay cycle number measurement for three cases with three different delay cycle numbers. Note that only one output clock 244 and one transmission command 224 are shown because they do not change even if the number of delay cycles is different.

  In “delay case 1” of FIG. 5, the received data 235 after skew adjustment and the operation clock of the received data SP conversion unit 210 (which is not clearly shown in FIG. 1 but corresponds to the host clock 115) The delay is within one cycle of the host clock 115 (that is, the number of delay cycles is 0). Similarly, “delay case 2” is a case where the delay cycle is one cycle, and “delay case 3” is a case where the delay cycle is two cycles.

  The number of measurement cycles 616 is counted up until the start bit of the reception data 235 which is a calibration pattern from the external device 107 is received from the end bit of the transmission command 224 instructing calibration. Therefore, after receiving the start bit of the calibration pattern, the cycle selection value 249 output from the subtractor 615 is a value corresponding to the cycle delay. The cycle selection value 249 is used as valid information only when the skew adjustment sequence is completed.

[Configuration for cycle correction]
Next, details of the configuration of the device control unit 103 for correcting the cycle delay based on the cycle selection value 249 determined by the above configuration will be described.

  FIG. 3A shows a schematic configuration of the cycle control unit 603. The cycle control unit 603 has N2 flip-flops 701 (second delay means) whose inputs and outputs are connected in series, and the flip-flop 701 is arranged so as to cause a delay of one clock in the output clock enable signal 243. Has been. The selector 702 of the cycle control unit 603 is configured to delay the input output clock enable signal 243 by the flip-flop 701 by the number of cycles indicated by the cycle selection value 249. The output clock enable signal 243 delayed by the cycle control unit 603 is input to the reception data SP conversion unit 210 as the reception enable signal 250.

  FIG. 3B shows waveforms of various signals handled by the cycle control unit 603. When the respective signals in FIG. 3B are described in correspondence with the reference numerals in FIG. 1, they are host_clk 115, dev_clk_en 243, and rc_en 250 in order from the top. The cycle control unit 603 delays the input output clock enable signal 243 according to the value of the cycle selection value 249 (cycle_sel = 0, 1, 2, 3), and outputs it as a reception enable signal 250. When the value indicated by the cycle selection value 249 is 2, the cycle control unit 603 uses the selector 702 to select the output that has passed through the two flip-flops 701, thereby delaying the output clock enable signal 243 by two cycles and receiving the reception enable signal. It outputs as 250. Since there are N2 flip-flops 701 in the configuration of FIG. 3, the output clock enable signal 243 can be delayed by an integral multiple of one cycle (up to N2 cycles).

  The reception data SP conversion unit 210 stops data capture when the reception enable signal 250 is deasserted, and resumes data capture when the reception enable signal 250 is reasserted.

  The output clock control unit 213 performs clock control from the reception buffer full signal 241 and the reception status signal 239. Specifically, when the buffer full signal 241 is asserted while data is being received, the output clock enable signal 243 is controlled to stop the output clock 244.

[Cycle adjustment processing]
FIG. 10 shows a timing chart of signals handled by the device control unit 103 and the external device 107 during data reception when operating with the correct cycle setting in the configuration of FIG. The example shown in this figure shows a waveform when the delay cycle is one cycle and the correct cycle selection value 249 is set. In the present embodiment, when the delay generated in the reception data 236 is one cycle, the setting indicated by the cycle selection value 249 when the calibration sequence is normally completed is 1. Since the setting indicated by the cycle selection value 249 is 1, the reception enable signal 250 is delayed by one cycle by the cycle control unit 603 with respect to the output clock enable signal 243.

  In the example of FIG. 10, when reception of “D0” is started for the reception data 236 in the serial format, the output clock enable signal 243 is deasserted and the output clock 244 is gated. Although the output clock 244 is gated, “D 1” and “D 2” are transmitted from the external device 107 for the received data 237 in the serial format. One cycle after the start of deassertion of the output clock enable signal 243, the reception enable signal 250 is also deasserted. The reception data SP conversion unit 210 receives the deassertion of the reception enable signal 250, and immediately stops receiving the serial format reception data.

  Therefore, reception of data is stopped while receiving “D1” of the reception data 235 after skew adjustment. Looking at the first bit data of the reception data 234 in the parallel format, it can be seen that “D1” has been received, and the data acquisition stop timing of the reception data SP converter 210 can be adjusted.

  Further, the output clock enable signal 243 is asserted again one cycle after being deasserted, and the gating of the output clock 244 is released in response to the assertion. Here, even if the gating of the output clock 244 is cancelled, since the received data 236 has a delay of one cycle or more, “D2” of the serial format received data 236 is continuously transmitted from the external device 107.

  The reception enable signal 250 is also asserted one cycle after the assertion of the output clock enable signal 243 by the delay amount (one cycle) indicated by the cycle selection value 249. The reception data SP converter 210 immediately receives the serial reception data in response to the assertion of the reception enable signal 250. Therefore, “D2” of the received data 236 in the serial format can be correctly received. Looking at the first bit of the reception data 234 in the parallel format, it can be seen that “D2” has been correctly received, and that the data acquisition restart timing of the reception data SP converter 210 can be adjusted.

[About data loss that occurs when the cycle is not adjusted]
FIG. 11 shows a timing chart in a state where data is lost without adjusting the cycle when a cycle delay occurs. The timing chart of FIG. 11 shows various signals in a state in which the device control unit 103 receives data from the external device 107 without adjusting the cycle when the reception data 236 is delayed by one cycle with respect to the output clock 244. The waveform is shown. Each signal is the same as in FIG. Compared to FIG. 10, rcv_en 250 is not illustrated in FIG. 11, but rcv_en 250 is substantially the same as dev_clk_en 243 in a state where cycle adjustment is not performed.

  By using dev_clk_en that is not delayed as rcv_en250, the reception data SP conversion unit 210 receives the serial reception data “D2” twice. Further, when the parallel received data 234 is viewed, D2 is received twice.

  As described above, in the present embodiment, the number of delay cycles can be acquired with a simple configuration even when a delay of one cycle or more occurs between the data receiving apparatus and the data transmitting apparatus. Therefore, even if the received data 236 has a delay of one cycle or more, it can be correctly detected or corrected.

  Further, according to the present embodiment, the data acquisition stop timing and the data acquisition restart timing of the received data SP conversion unit 210 can be delayed by the amount of delay that occurs between the device control unit 103 and the external device 107. As a result, occurrence of data loss is suppressed.

  In the above-described embodiment, the skew control unit 211 and the cycle control unit 603 are separately configured. However, the skew adjustment and the cycle adjustment may be combined as a single configuration or combined with the reception data SP conversion unit 210. May be. In addition, skew adjustment and cycle adjustment are actually performed by inputting a clock with corrected deviation, but a delay configuration (delay element, flip-flop) for skew adjustment and cycle adjustment is provided in the data supply system. The delay amount may be selected directly by a selector or the like.

  Although details are not described in the above-described embodiment, regarding the above-described wiring delay between the external device 107 and the device control unit 103, when the variation in the delay amount increases when the external device 107 can be attached to and detached from the external device 107IF112. Conceivable. Actually, in addition to the length, material, and temperature rise of the wiring, it is considered that a delay due to various factors such as poor contact is included.

  In the above-described embodiment, the data portion (D0, D1,... In FIG. 9) of the reception data 236 is compared. However, the CRC portion (CRC0, FIG. 9) calculated by the reception data SP conversion unit 210 as a calculation unit is compared. CRC1 ...) may be used for comparison. In that case, it is necessary to previously calculate and store the CRC received when the skew setting and the cycle setting are normal for the calibration pattern stored in advance.

  In FIG. 1, the device control unit 103 and the external device 107 are described as communicating using a 1-bit width bus. However, a 4-bit width bus, an 8-bit width bus, or the like may be used. Can be applied without being limited to the bus width. However, for example, when a 4-bit (8-bit) bus is used, four flip-flops 218 and four delay selection units 217 may be arranged in the skew control unit 211 so that skew adjustment can be performed for each 1-bit width. In this case, the reception data SP conversion unit 210 only needs to join 4 bits, and the external device 107 that the external device 107 is to output by changing the order of the 4 bit data to the reception data SP conversion unit 210 or the reception buffer 209 or the like. A configuration for matching with the 107 data may be provided.

  In the above-described embodiment, only an example in which the operating frequency of the host clock 115 is single is described. However, the operating frequency may be switched by identifying the external device 107. For example, a frequency dividing circuit, a multiplying circuit, or the like that divides the host clock may be provided between the CLOCK generator 105 and the device control unit 103 to change the frequency of the host clock input to the device control unit 103. In this case, in addition to the CLOCK generator 105, a frequency division circuit and a frequency multiplication circuit are part of the oscillation means.

  At this time, when the calibration is not successful, the host clock 115 input to the external device 107 may be decreased to a lower frequency to stabilize the communication with the external device 107. The case where the calibration is unsatisfactory means that, for example, the above-mentioned calibration occurs a predetermined number of times per unit time or the time required for the calibration is a predetermined time or more (for example, the number of times required for the brute force) May be required. Further, when the physical connector shape of the external device 107IF112 is designed to be fitted to a specific type of external device 107 defined in the standard, the frequency to be switched by the frequency divider or the multiplier circuit is determined by the specific type of standard. May be used. Accordingly, backward compatibility of the device control unit 103 can be maintained when the external device 107 is of the same system and the operating frequency differs depending on the version.

  On the other hand, when emphasizing the communication speed, the host clock may be amplified by a multiplier circuit if the calibration is good. The case where the calibration is favorable is when the calibration generated per unit time is less than the predetermined number of times, or when the time required for calibration is less than the predetermined number of times. By doing so, the forward compatibility of the device control unit 103 can be maintained even when the external device 107 of the same system has a different operating frequency depending on the version.

  Further, the transmission buffer 207 and the reception buffer 209 in the above-described embodiment may have a FIFO structure. In this case, the buffer full signal and the buffer empty signal may be created based on information (remaining amount information) indicating the FIFO free space, or the remaining amount information may be used as it is. In this case, when the size of data that can be stored in the FIFO of the reception buffer 209 is equal to or larger than the size of the data of the calibration pattern, the CPU 101 may write the calibration pattern once in the FIFO and use it as it is for comparison. . However, when the data size that can be stored in the FIFO of the reception buffer is smaller than the calibration pattern, it is preferable to compare sequentially (every predetermined cycle) by the data size equal to or smaller than the FIFO capacity of the calibration pattern. Alternatively, it is possible to branch to a configuration in which comparison is performed sequentially without being taken into the FIFO of the reception buffer 209 during calibration. (As a comparison means, a comparator having a configuration different from the CPU 101 and configured to be a register for reading out expected values of the same data size may be configured.) In the above-described embodiment, device control is performed. The configuration using a 1-bit bus for communication between the unit 103 and the external device 107 has been described. However, the present invention can be applied to a multi-bit bus such as a 4-bit bus or an 8-bi bus.

  Further, the control signal such as the output clock enable signal 243 in the above-described embodiment may be configured to assert the disable signal at the timing when the enable signal is deasserted.

  In the above-described embodiment, the external device is exemplified as the flash memory, but the present invention can be applied to a storage device other than the flash memory. The present invention can also be applied to an external device in which the external device 107 has a wireless LAN function or a Bluetooth function in addition to the storage device. When the ASIC 100 is provided in an information processing apparatus such as a printer or digital camera, the external device 107 is used by being connected to a slot provided in the printer or digital camera. At this time, the present invention can also be applied to the external device 107 that is inserted into the slot and expands the IO function of the information processing apparatus. More generally, the present invention can be applied to a device that supplies a clock to an external device and outputs data in synchronization with the clock.

Claims (15)

A data receiving device that is communicably connected to a data transmitting device,
Supply means for supplying a clock to the data transmission device;
Receiving means for receiving data output by the data transmitting device in synchronization with the clock;
Transmitting means for transmitting a command to the data transmitting device;
Counting means for counting the number of cycles between the transmission end timing of the command and the reception start timing of data corresponding to the command from the transmission device;
A data receiving apparatus comprising:   The data receiving apparatus according to claim 1, further comprising a control unit that interrupts reception of data by the receiving unit in response to a stop of the supply of the clock by the supplying unit.   The data receiving apparatus according to claim 2, wherein the control unit restarts reception of data by the receiving unit in response to restart of supply of the clock by the supplying unit.   4. The data receiving apparatus according to claim 2, further comprising a delay unit that delays a control timing of the receiving unit by the control unit based on the number of cycles counted by the counting unit. A calculation means for calculating the cycle deviation amount counted by the counting means;
5. The data receiving apparatus according to claim 4, wherein the delay unit delays control of the receiving unit by the control unit based on a cycle shift amount calculated by the calculating unit.   6. The data receiving apparatus according to claim 5, further comprising skew adjusting means for correcting a phase shift of data received by the receiving means. Supply means for supplying the clock;
The skew adjusting means corrects a phase shift by delaying data received by the receiving means by an amount smaller than one cycle of a clock output from the supplying means, and the delay means is the receiving means by the control means. 7. The shift of the data fetching timing in units of periods in the receiving means is corrected by delaying the control of the above by an integral multiple of one cycle of the clock output from the supplying means. The data receiving device described. A data transmission device connected to be communicable with a data reception device,
Storage means for holding predetermined data;
When a calibration command related to data reception is received from the data receiving device, the predetermined data held in the storage means is received at a predetermined number of cycles in synchronization with a clock supplied from the data receiving device. And a data transmission device comprising: output means for outputting to the device.   9. The data transmission apparatus according to claim 8, further comprising notification means for returning an error to the data reception apparatus when data output by the output means cannot be performed in the predetermined number of cycles.   9. The data transmission apparatus according to claim 8, wherein when the data output by the output means cannot be performed with the predetermined number of cycles, data is not output from the storage means.   11. The data transmission apparatus according to claim 8, wherein information indicating the predetermined number of cycles is transmitted to the data reception apparatus. A data receiving device that is communicably connected to a data transmitting device,
Supply means for supplying a clock to the data transmission device;
Receiving means for receiving data output by the data transmitting device in synchronization with the clock;
A data receiving apparatus comprising delay means for delaying interruption and return of reception of the data by the receiving means in accordance with a delay caused between the data transmitting apparatus and the data receiving apparatus. A method of controlling a data receiving device connected to be communicable with a data transmitting device,
A supplying step of supplying a clock to the data transmitting device;
A reception step of receiving data output by the data transmission device in synchronization with the clock;
A transmission step of transmitting a command to the data transmission device;
A counting step of counting the number of cycles between the transmission end timing of the command and the reception start timing of data corresponding to the command from the transmission device;
A control method characterized by comprising: A method for controlling a data transmission device connected to be communicable with a data reception device, comprising:
When a calibration command related to data reception is received from the data receiving device, the data in the storage means holding the predetermined data is received at a predetermined number of cycles in synchronization with the clock supplied from the data receiving device. A data transmission device characterized by outputting to a device. A method of controlling a data receiving device connected to be communicable with a data transmitting device,
A supplying step of supplying a clock to the data transmitting device;
A reception step of receiving data output by the data transmission device in synchronization with the clock;
A control method comprising: a delay step of delaying interruption and return of reception of the data in the reception step in accordance with a delay occurring between the data transmission device and the data reception device.

Images