JP5714156B2 - Image processing apparatus and image processing method - Google Patents

Description

  The present invention relates to an image processing apparatus and an image processing method, and more particularly to a technique for reducing circuit scale and increasing data access speed for quantizing image data by an error diffusion method.

  A process using an error diffusion method is known as a quantization process for converting multi-value image data into data having a smaller number of gradations in order to obtain print data used in the printing apparatus. In the error diffusion method, quantization processing is performed on pixels for one line arranged in a predetermined direction from a pixel at one end of the line to a pixel at the other end in order. At this time, an error caused by quantization in each pixel is diffused to a pixel on the same line as the target pixel to be quantized and a pixel adjacent to the line in a direction orthogonal to the predetermined direction. The When the quantization of the pixels for one line is completed, the quantization is similarly performed on the adjacent pixels for one line. In this way, quantization is sequentially performed on all lines constituting the image data.

  In this quantization, error data that is diffused with respect to pixels on the same line is stored, for example, in a buffer in a circuit that performs error diffusion until the pixels are quantized. Further, error data diffused to the pixels on the adjacent line is stored in a memory outside the circuit as a whole, and is read from the memory in accordance with the processing of the pixels on the adjacent line when the adjacent line is quantized. .

  By the way, in recent printing apparatuses, more types or colors of ink have been used to improve color reproducibility. In addition, the amount of image data handled by the recording apparatus tends to increase as compared with the conventional art due to the high definition of the image to be recorded and the increase in the size of the recording paper. For this reason, it is required to process a large amount of image data at a higher speed, and in particular, it is required to increase the speed of the quantization process by the error diffusion method. It is desirable that the processing speed can be increased without increasing the circuit scale, and thus without increasing the cost.

  Patent Document 1 describes a configuration for executing error diffusion processing using a line memory having a number of pixels smaller than the number of pixels for one line in a line memory in a circuit for error diffusion processing. With this configuration, the error diffusion processing circuit can be easily made ASIC, and the error diffusion processing can be speeded up.

JP-A-10-164365

  However, in the configuration of the conventional error diffusion processing as disclosed in Patent Document 1, error data for one line for diffusing to pixels of other lines is written or read in a memory outside the error diffusion circuit. Memory access takes a relatively long time. In particular, when the memory outside the error diffusion circuit is a memory having a relatively low operation speed such as a DRAM, the time for writing and reading error data is further increased. In addition, when the type or color of recording material such as ink increases, the amount of error data to be processed increases accordingly, which increases the amount of error data to be written or read, and hinders the speeding up of error diffusion processing. Will be. Further, when the data to be subjected to error diffusion processing increases as the type or color of the recording material increases, there arises a problem that the scale of the error diffusion processing circuit increases accordingly.

  The present invention has been made to solve the above-described conventional problems, and provides an image processing apparatus and an image processing method capable of performing error diffusion processing at high speed without increasing the scale of the error diffusion processing circuit. The purpose is to provide.

Therefore, according to the present invention, an image processing circuit that performs quantization processing by an error diffusion method on image data having a plurality of rasters composed of a plurality of pixels and generates recording data for each raster in an image processing apparatus. First storage means for storing error data diffused by a quantization process by the image processing circuit from a raster composed of a plurality of pixels, and a quantization process by the image processing circuit from a raster composed of a plurality of pixels A second storage means for storing error data to be diffused by the image processing circuit, reading error data to be diffused to a raster on which the image processing circuit performs a quantization process from the second storage means, and the image processing circuit The error data diffused from the raster processed by the image processing circuit is written into the second storage means, If the image processing circuit is completed quantization processing of one band formed by a predetermined number of sequences of rasters, write error data to be diffused to a raster belonging to the next band in the first storage means, the image processing circuit If but the quantization processing of the next band, and read out the error data to be diffused to a raster belonging to the next band from the first storage unit, the image processing circuit, the quantization processing of image data of the N color separation In the case of performing image processing of image data having more colors than the N colors, the quantization processing is executed in a plurality of times, and image processing of at least the first color group image data is performed. image processing, characterized by repeating Succoth per band processing order of the second image processing to the image processing of the image data of the second color group.

  According to the above configuration, error diffusion processing can be performed at high speed without increasing the scale of the error diffusion processing circuit even when the amount of recording data to be generated is as large as 12 colors.

1 is a perspective view illustrating a schematic configuration of an ink jet recording apparatus according to an embodiment of the present invention. FIG. 2 is a block diagram illustrating a configuration of control and data processing of the recording apparatus according to the present embodiment illustrated in FIG. 1. (A)-(c) is a figure explaining the pixel of the image data processed with the image processing part shown in FIG. (A) And (b) is a figure explaining the band mode of the image data processed by the image processing part shown in FIG. It is a figure explaining the structure of the functional block of the image process part shown in FIG. 2, and the format of the image data processed. (A) And (b) is a figure explaining each signal in the image processing part shown in FIG. (A) is a figure explaining the access destination of each DMAC shown in FIG. 5, (b) is a figure explaining each register part shown in FIG. (A) And (b) is a figure explaining the field of a band mode register and the field of a processing mode register in the register part shown in FIG.7 (b). It is a figure explaining the spreading | diffusion of the quantization error which generate | occur | produces by comparison with a threshold value in embodiment of this invention. (A), (b) and (c) is a figure explaining the spreading | diffusion to the adjacent raster of the said quantization error. 6 is a flowchart for explaining processing of the control circuit unit 505 shown in FIG. 5 for finally binarizing and outputting image data. 6 is a flowchart for explaining the operation of the error data read DMAC shown in FIG. 5. 6 is a flowchart for explaining the operation of the error data write DMAC shown in FIG. 5. 5 is a flowchart for explaining processing for generating recording data of 12 ink colors, particularly quantization by error diffusion, in the recording apparatus according to the embodiment of the present invention. (A) And (b) is a figure explaining the example of a register setting in the case of quantizing 12 color image data in the image processing circuit shown in FIG.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

  FIG. 1 is a perspective view showing a schematic configuration of an ink jet recording apparatus according to an embodiment of the present invention. In FIG. 1, the recording apparatus 100 includes a carriage 53. The carriage 53 is guided by the guide rails 51 and 52 and is provided so as to be movable in the scanning direction (main scanning direction) indicated by an arrow X in the drawing. The carriage 53 detachably mounts the recording head 54 and performs the above movement by transmitting a driving force of a carriage motor (not shown) by a driving force transmission mechanism (not shown) such as an endless belt. As a result, the recording head can scan the recording medium. Ink is supplied to the recording head 54 mounted on the carriage 53 from an ink tank (not shown) containing ink of each color via a tube.

  The recording head 54 of the present embodiment is provided with a nozzle row in which nozzles capable of ejecting ink are arranged in a direction crossing the scanning direction for the following 12 colors of ink. That is, the recording head 54 includes cyan (C), photocyan (light cyan; LC), magenta (M), photomagenta (light magenta; LM), yellow (Y), red (Red), green (Gr), A nozzle array for discharging ink of blue (Bl), black (K), matte black (MK), gray (Gry), and photo gray (light gray; LGry) is provided. As a mechanism for ejecting ink from each nozzle, an electrothermal transducer (heater), a piezoelectric element using a piezoelectric effect, or the like can be used. When the electrothermal transducer is used, the ink is foamed by the heat generated by the electrothermal transducer, and the ink is ejected from the ejection port using the foaming energy generated at the time of foaming.

  As a recording medium, a roll paper 55 wound in a roll shape is attached to the recording apparatus 100, and a sheet end pulled out from the roll paper 55 is inserted from an insertion port. The sheet is conveyed by the feed roller 56 in the conveyance direction (sub-scanning direction) indicated by an arrow Y in the drawing orthogonal to the scanning direction. During the scanning of the recording head 54, the recording operation for ejecting ink from each nozzle according to the recording data and the transporting operation for transporting the recording medium in the transport direction by a distance corresponding to the recording width by the scanning of the recording head 54 are repeated. Thus, images are sequentially recorded on the recording medium. In the present embodiment, recording of a maximum width of 60 inches can be performed by scanning the recording head.

  FIG. 2 is a block diagram showing a configuration of control and data processing of the recording apparatus according to the present embodiment shown in FIG. As shown in FIG. 2, the printing apparatus of this embodiment includes an image formation control unit 101 that executes control and data processing, a printer engine 128 that is a printing mechanism mainly shown in FIG. It is comprised.

  The image formation control unit 101 receives a recording instruction or recording image data from a host device such as a personal computer, converts the received image data into binary recording data used by the printer engine 122, and outputs the binary recording data. As shown in FIG. 2, the image formation control unit 101 includes a CPU 102, a communication interface unit 103, an operation unit control circuit unit 104, a display unit control circuit unit 105, a RAM controller 106, a ROM controller 107, and an expansion bus circuit unit 108. Have. The image formation control unit 101 includes an image processing unit 109 and a printer engine interface unit 110. Each of these blocks described above is connected to the system bus bridge 111 via bus lines 112a to 112i, respectively. In the present embodiment, each of these units is realized as an image forming control unit ASIC (Application Specific Integrated Circuit) 113 sealed in one package as a system LSI. Furthermore, the image formation control unit 101 includes an operation unit 114, a display unit 115, a RAM unit 116, a ROM unit 118, and an expansion slot 120 in which a function expansion unit is mounted.

  The CPU 102 controls the entire image forming control unit 101. The CPU 102 controls the communication interface unit 103 and controls the operation unit 114 and the display unit 115 by sequentially reading and executing control procedures stored in the ROM unit 118 or the RAM unit 116. Further, the CPU 102 performs control of the image processing unit 109 for converting the received image data into image formation data, control of the printer engine interface unit 110 for transferring the generated image formation data to the printer engine 122, and the like. Do.

  The communication interface unit 103 transmits / receives data to / from a host device such as a personal computer or a workstation, and stores image data received from the host device in the RAM unit 116 via the RAM controller 106. As a communication method of the communication interface unit 103, a known method such as USB (Universal Serial Bus) can be used. The operation unit control circuit unit 104 notifies the state of an electric signal output from the switch constituting the operation unit 114 as register information in response to a read command from the CPU 102. The display unit control circuit unit 105 outputs an electrical signal to the liquid crystal display device and the LED lamp that constitute the display unit 115.

  The RAM controller 106 controls the RAM unit 116 connected to the ASIC 113 of the image formation control unit via the RAM bus 117. That is, the RAM controller 106 generates necessary control signals according to read requests and write requests from the CPU 102 and each unit, and realizes writing to the RAM unit 116 and reading from the RAM unit 116. The ROM controller 107 controls the ROM unit 118 connected to the ASIC 113 of the image formation control unit via the ROM bus 119. That is, the ROM controller 107 generates necessary control signals in response to a read request from the CPU 102, reads control procedures and data stored in the ROM unit 118 in advance, and reads them to the CPU 102 via the system bus bridge 111. Send back the contents. When the ROM unit 118 is composed of an electrically rewritable device such as a flash memory, the ROM controller 107 generates necessary control signals to rewrite the contents of the ROM unit 118.

  The expansion bus circuit unit 108 controls the function expansion unit installed in the expansion slot 120 and performs control to transmit data to the function expansion unit via the expansion bus 121 and control to receive data output from the function expansion unit. The expansion slot 120 can be equipped with a hard disk drive unit that provides a large-capacity storage function, or a communication unit that communicates with a host device using a communication function compliant with IEEE1284 in addition to USB and IEEE1394.

  The image processing unit 109 performs processing for converting image data received from the host device into binary recording data that can be recorded by the printer engine 122. The detailed configuration of the image processing unit 109 will be described later with reference to FIG.

  The printer engine interface unit 110 transmits and receives data between the image formation control unit 101 and the printer engine 122. The printer engine interface unit 110 includes a DMAC (Direct Memory Access Controller). Accordingly, the printer engine interface unit 110 can sequentially read the binary recording data generated by the image processing unit 109 and stored in the RAM unit 116 via the RAM controller 106 and transfer the binary recording data to the printer engine 122. Note that the image processing unit 109, the communication interface unit 103, and the expansion bus circuit unit 108 have a DMAC function like the printer engine interface unit 110, and can issue a memory access request.

  The system bus bridge 111 has a function of connecting the components constituting the ASIC 113 of the image formation control unit, and also has a function of arbitrating a bus right when an access request is issued simultaneously from a plurality of blocks. . Each block having the CPU 102 and the DMAC may issue an access request to the RAM unit 116 almost simultaneously via the RAM controller 106, and the system bus bridge 111 may appropriately perform arbitration according to a predetermined priority. it can.

  The operation unit 114 includes switches that are linked to buttons that set the operation of the recording apparatus 100, and outputs the state of these switches as an electrical signal. The operation unit 114 includes a power button that instructs the recording apparatus 100 to turn on and off. Further, the operation unit 114 includes an online button for switching the operation mode, a menu button for instructing display of the menu screen, an up / down / left / right cross button for selecting an item from the menu screen, and an OK button for confirming the selection item. I have. In addition, the operation unit 114 includes a stop button for instructing to stop recording and a paper feed selection button for selecting a recording paper feeding method. The display unit 115 includes a liquid crystal display device, an LED lamp, and the like. The liquid crystal display device can display a menu screen by operating the menu button of the operation unit 114 in addition to displaying the operation state of the recording device 100. The LED lamp is used to display the operation state of the recording apparatus 100 and display a warning.

  The RAM unit 116 is configured by a synchronous DRAM or the like, and is a memory that provides functions such as storage of control procedures executed by the CPU 102, temporary storage of image data generated by the image processing unit 109, and work memory of the CPU 102. is there. The ROM unit 118 is configured by a flash memory or the like, and stores control procedures executed by the CPU 102 and parameters necessary for printer control.

  The printer engine 122 is a recording mechanism for recording an image on a recording medium based on binary recording data sent from the image formation control unit 101. In the present embodiment, as described above with reference to FIG. 1, the printer engine 122 forms an image on a recording medium with an ink jet recording head, and uses 12 colors of ink in a resolution of 2400 dpi in the main scanning direction. Images up to 60 inches wide can be recorded.

  3A to 3C are diagrams illustrating pixels of image data processed by the image processing unit 109. FIG. In FIG. 3A, each of the small squares represents one pixel, and the image data of each color processed by the image processing unit 109 is stored in each of the pixels arranged in the main scanning direction and the sub scanning direction. The density values are associated with each other. A row composed of a series of pixels arranged in the main scanning direction is called a raster, and a rectangular pixel group in which a predetermined number of rasters having the same number of pixels are arranged is called a band. The number of rasters constituting the band and the number of pixels constituting the raster may be one or plural.

  The image processing unit 109 performs image processing for each raster in order from the first raster in the sub-scanning direction in the band. One raster is processed pixel by pixel in order from the left end side to the right end side or from the right end side to the left end side. FIG. 3B and FIG. 3C are diagrams showing the processing direction for one raster, and the numbers in the drawings indicate the processing order for each pixel. In the case of forward processing, processing is performed in order from the left end side to the right end side as shown in FIG. 3A, and in the case of reverse processing, processing is performed in order from the right end side to the left end side as shown in FIG.

  The image processing unit of the present embodiment can select and execute bidirectional processing and unidirectional processing for band processing. In the bidirectional processing, as shown in FIG. 4A, image processing is executed while switching between forward processing and backward processing for each raster. Further, in the one-way processing, as shown in FIG. 4B, processing is performed in the same direction for all rasters constituting the band. Note that in both cases of bidirectional processing and unidirectional processing, image processing can be started from backward processing.

  In the present embodiment, as described above, the coordinates of the pixels constituting the image data are specified in correspondence with the recording area on the recording medium. In the recording apparatus of the present embodiment, the maximum recording area width in the main scanning direction is 60 inches as described above. In the case of this maximum width recording area, the recording pixel has a resolution of 2400 dpi, so the number of pixels is 144000. On the other hand, the resolution of the image data processed by the image processing unit 109 is 1200 dpi because of the relationship of 2 × 2 pixels of the dot arrangement pattern obtained by the binarization processing circuit in accordance with index data described later. Accordingly, the number of pixels of one raster of the image data is 72000 at maximum corresponding to the recording area of the above width, and the pixel coordinates are 0 to 71999 in order from the pixel on the left side of FIG. By specifying the pixel coordinates of the leftmost pixel and the rightmost pixel of the band, the recording position on the recording medium of the band to be processed can be specified. For example, if the left end pixel coordinate of the band to be processed is set to 18000 and the right end pixel coordinate is set to 35999, an image is recorded in the band from the left end side quarter on the recording sheet to the center of the sheet.

  Image data handled by the image processing unit 109 and error data in error diffusion processing are prepared by a RAM unit 116 as a first storage memory and an error buffer unit as a second storage memory in the image processing unit 109, as will be described later. And stored in these memories. The positions on the memory where the image data and the error data are stored can be calculated from the memory address where the data corresponding to the pixel coordinate 0 is to be stored, the left end pixel address, and the right end pixel address. A memory address in which data corresponding to the pixel coordinate 0 is to be stored is called an origin corresponding address.

  FIG. 5 is a diagram for explaining the functional block configuration of the image processing unit 109 and the format of image data to be processed.

  As shown in FIG. 5, the image processing unit 109 includes a color conversion processing circuit unit 501, a quantization processing circuit unit 502, a binarization processing circuit unit 503, a register unit 504, a control circuit unit 505, and an error buffer unit 510. Have. In the present embodiment, the error buffer unit 510 is configured by an SRAM. Further, the image processing unit 109 includes an image data read DMAC 506 and an error data read DMAC 508 for reading image data and error data, and an image data write DMAC 507 and an error data write DMAC 509 for writing the respective data. The image processing unit 109 according to the present embodiment having the above configuration is realized as a circuit that constitutes a part of the ASIC 113 as described above. The image processing unit 109 is a circuit that processes image data for up to six colors with respect to the ink colors used in the printer engine 122. That is, the processes of the color conversion processing circuit unit 501, the quantization processing circuit unit 502, and the binarization processing circuit unit 503 described below are executed twice for the same pixel (the target pixel to be processed). . Thereby, the scale of the circuit of the image processing unit 109 and the circuit of the ASIC 113 including the processing unit can be reduced.

  Specifically, the color conversion processing circuit unit 501 receives a color signal (any value from 0 to 255) represented by 8 bits for each of red (R), green (G), and blue (B) from the host device. Is subjected to color correction processing and color space conversion processing. In the color correction process, a gamma correction process is performed on the color signals R, G, and B by using an interpolation calculation together with a one-dimensional lookup table corresponding to each color signal. Next, in the color space conversion process, as a first process, the color signals R, G, and B are referred to a three-dimensional lookup table by these sets, and an interpolation process is used together with this reference result. The ink color signals C, LC, M, LM, Y, and Red are converted into six colors. Each of these ink color signals is represented by 8 bits and has a value of 0 to 255.

  Then, the quantization processing circuit unit 502 performs a quantization process using an error diffusion method, the details of which will be described later, on each of these six color signals, and indicates a gradation level of 0 to 4. Outputs 5-bit index data. Then, the binarization processing circuit unit 503 applies a dot arrangement pattern corresponding to the index data and outputs 1-bit binary recording data (image data).

  In the second process for the image data of the target pixel, first, color correction processing (of the color conversion processing circuit unit 501) is performed on the color signals R, G, and B that are the same image data of the target pixel. The result of this process is the same as the first time, and the color space conversion process of the color conversion processing circuit unit 501 performs conversion based on the color signals R, G, and B as the same result. That is, the color signals R, G, and B as the same color correction result are referred to the three-dimensional lookup table by the combination of these color signals, and the interpolation processing is used together with this to perform the second processing. The ink color signals Gr, Bl, K, MK, Gry, and LGry are converted. Next, the quantization processing circuit unit 502 quantizes each of the ink color signals Gr, Bl, K, MK, Gry, and LGry by error diffusion processing, the details of which will be described later, and outputs each ink color. 5 index data is output. Then, the binarization processing circuit unit 503 uses the dot arrangement pattern corresponding to the index data to output binary recording data.

  As described above, in the present embodiment, the same image processing is repeated twice in order to generate print data including 12 ink color signals. Thereby, the scale of the circuit for image processing can be reduced.

  In the present embodiment, the image data in the image processing is composed of RGB color signals. However, the present invention is not limited to this form. For example, it may be composed of four color signals of cyan (C), magenta (M), yellow (Y), and black (K). Further, the ink color signal is set to a maximum of 12 colors, and the processing of the image processing circuit corresponding to the maximum 6 colors can be executed according to this, but it goes without saying that the present invention is not limited to this form. An image processing circuit that performs processing of the number divided into two or more according to the maximum number of ink color signals to be used may be used.

  In FIG. 5, the register unit 504 includes a register group including an image processing start register that instructs the start of image processing, a command / parameter register that specifies the contents and parameters of image processing to be executed, and the like. The register unit 504 has a register for setting parameters relating to error data access when the first raster and the last raster of the band are processed. A control circuit unit 505 controls the entire image processing unit 109. For example, the control circuit unit 505 operates in response to an activation instruction from the CPU 102, and outputs necessary control signals to each functional block and the DMAC unit in the image processing unit 109 in accordance with parameters set in the register unit.

  The control circuit unit 505 outputs each control signal shown in FIG. 6A and a control signal (not shown). In FIG. 6A, the “current raster processing direction signal” is a signal indicating whether the processing direction of the raster to be processed is the forward direction or the reverse direction, “1” in the forward direction, and in the reverse direction "0" is output to. The “first raster display signal” is a signal indicating whether or not the raster to be processed is the first raster of the band, and “1” is output in the case of the first raster. The “final raster display signal” is a signal indicating whether or not the raster to be processed is the final raster of the band, and “1” is output in the case of the final raster. The “data transfer start instruction signal” is a signal instructing each DMAC (506 to 509) that reads (writes) or writes (writes) image data and error data to start data transfer, and outputs “1”. To start the transfer. Finally, the “raster processing completion response signal” is a response signal returned to the notification of completion of the raster processing output from each DMAC, and outputs “1” to return a response to the notification.

  The image data read DMAC 506 is a DMAC for reading input image data stored in the RAM unit 116. The image data write DMAC 507 is a DMAC for storing the generated binary image data (recording data) in the RAM unit 116.

  The error data read DMAC 508 is a DMAC for reading error data diffused from adjacent lines. More specifically, the error data read DMAC 508 selects either the RAM unit 116 or the error buffer unit 510 in accordance with a signal from the control circuit unit 505 and processes it from the error data for one line stored therein. The error data corresponding to the pixel related to is read out. On the other hand, the error data write DMAC 509 is a DMAC for writing error data for diffusion to adjacent lines. That is, the error data write DMAC 509 selects either the RAM unit 116 or the error buffer unit 510 in accordance with a signal from the control circuit unit 505, and writes (stores) error data for one line therein. it can.

  More specifically, as shown in FIG. 7A, the error data read DMAC 508 and the error data write DMAC 509 control to access the RAM unit 116 when the address of the memory to be accessed is in the range of 0x00000000 to 0x03FFFFFF. . When the address of the memory to be accessed is in the range of 0xA0000000 to 0xA009FFFF, control is performed so as to access the error buffer unit 510. Each DMAC (506 to 509) outputs a “raster processing completion notification signal” shown in FIG. 6B to the control circuit unit 505 when the data transfer for one raster is completed.

  As shown in FIG. 7B, the register unit 504 includes an image processing activation register 801 that instructs the start of image processing, and registers for setting parameters that define the operation mode of the quantization processing circuit unit 502. It is configured. The register unit 504 includes a register group (not shown) that sets an operation mode for color conversion processing and binarization processing. Parameters relating to the operation mode of the quantization processing circuit unit 502 are set in each of the band mode register 802, the processing mode register 803, and the raster number register 804. The register unit 504 further includes a left end pixel address register 805, a right end pixel address register 806, a common origin corresponding address register 807, a first raster origin corresponding address register 808, and a final raster origin corresponding address register 809.

  As shown in FIG. 8A, the band mode register 802 includes a field for designating a band processing mode and a field for designating the processing direction of the first raster. Further, as shown in FIG. 8B, the processing mode register 803 for performing access setting stores a field for designating an address from which error data diffused to the first raster is read and error data diffused from the last raster. It has a field for specifying an address. The processing mode register 803 has a field for setting other operation modes. The contents set in each register are supplied to each unit in the image processing unit 109 as a register set value signal so that each unit can be referred to.

  A quantization process mainly using the error diffusion method by the image processing unit 109 having the above configuration will be described below. First, the quantization processing circuit unit 502 of the image processing unit 109 reads error data diffused from a raster before the raster including the pixel of interest (hereinafter also referred to as “previous raster”). Then, the read error data is added to the image data of the target pixel output from the color conversion processing circuit unit 501. That is, the error value represented by the error data is added to the gradation value of the image data of the target pixel. The error data to be diffused from the previous raster is stored in the error buffer unit 510 or the RAM unit 116 capable of storing this data. Then, as will be described later, based on the control of the error data read DMAC 508 that performs access control, error data is read from the error buffer unit 510 or the RAM unit 116 according to which raster the target pixel belongs to. In addition, the quantization processing circuit unit 502 diffuses an error diffused from a pixel that has been subjected to quantization processing of the same raster (hereinafter, also referred to as “same raster”) including the pixel of the image data of the pixel of interest. Data is also added. Error data to be diffused from pixels of the same raster is temporarily stored in a buffer (not shown) in the quantization processing circuit unit 502.

  The quantization processing circuit unit 502 quantizes the image data of the pixel of interest added with the error data from the pixels of the same raster and the previous raster as described above by comparing with the threshold value for each color signal. Get index data. The index data is sent to the binarization processing circuit unit 503, converted into binary recording data, and stored in the RAM unit 116 by the image data write DMAC 507. Further, an error that occurs during quantization is diffused to predetermined pixels of the same raster and adjacent rasters.

  FIG. 9 is a diagram for explaining the diffusion of the quantization error generated by the comparison with the above-described threshold value. In FIG. 9, the error generated by the quantization process of the target pixel “P” is diffused to the unprocessed peripheral pixels according to the diffusion coefficient shown in FIG. Specifically, the error data diffused to the pixels A and B of the same raster L1 as the target pixel P is stored in a buffer (not shown) in the quantization processing circuit unit 502. The error data diffused to the pixels C, D, and E of the adjacent raster L2 is temporarily stored in the buffer in the quantization processing circuit unit 502, and then all error data diffused to the same pixel is added. The The summed error data is stored in the error buffer unit 510 or the RAM unit 116 via the error data write DMAC 509 according to which raster the target pixel belongs to, as will be described in detail later.

  Specifically, as shown in FIG. 10A, the error data diffused from the target pixel P to the pixel X of the adjacent raster L2 is the sum of the following first, second, and third error data. It will be a thing. The first error data is error data diffused from the target pixel “P” shown in FIG. 10A according to the diffusion coefficient (1/16) of the pixel E shown in FIG. The second error data is error data diffused from the target pixel “Q” of FIG. 10B according to the diffusion coefficient (1/4) of the pixel D shown in FIG. The third error data is error data diffused from the target pixel “R” in FIG. 10C according to the diffusion coefficient (1/8) of the pixel C shown in FIG.

  When the CPU 102 is instructed to start image processing by the CPU 102 writing a control parameter to the register unit 501, the image processing unit 109 converts the input image data stored in the RAM unit 116 from one end pixel of the raster to the other end pixel. The pixels are sequentially read out, and color conversion processing, quantization processing, and binarization processing are performed. The image processing unit 109 repeats these series of processes (also referred to as “raster processing”), and when the processing for the set number of rasters is completed, the image processing unit 109 issues an interrupt to the CPU 102 to notify the completion of the band processing. In accordance with an instruction from the CPU 102, the same processing is performed on an unprocessed band that exists in the sub-scanning direction, thereby performing binarization processing on the entire image data. The binarized image data (recording data) is sequentially stored in the RAM unit 116 and sent to the printer engine 122 by the printer engine interface unit 110, whereby an image is recorded on the recording medium based on the recording data. The

  FIG. 11 is a flowchart for explaining the processing of the control circuit unit 505 when performing the above-described image processing, in which input image data is finally binarized and output. When the CPU 102 writes “1” in the image processing activation register 801 of the register unit 504 and instructs the start of image processing, the register unit 504 outputs an image processing activation signal to each unit of the image processing unit 109. Upon receiving the image processing activation signal from the register unit 504, the control circuit unit 505 executes an image processing operation according to the flowchart of FIG.

  First, in step S1201, initialization processing and the like necessary before starting image processing are performed. In the initialization process, an internal counter (not shown) for counting the number of processed rasters is cleared, an image processing start signal is output to each part in the image processing unit 109, and the like. In step S1202, the image processing parameters for each raster are updated. Specifically, according to the value of the counter for counting the processing raster and the value of the band mode register 802 set in the register unit, the “current raster processing direction signal” and the “first raster display signal” shown in FIG. "And" last raster display signal "are updated and output. These signals are supplied to each unit in the image processing unit 109.

  In step S1203, the image data read DMAC 506, the image data write DMAC 507, the error data read DMAC 508, and the error data write DMAC 509 are instructed to start data transfer related to raster processing. That is, the control circuit unit 505 outputs “1” as the “data transfer start instruction signal” shown in FIG. 6A to instruct the start of data transfer of each DMAC (506 to 509).

  Next, in step S1204, it is determined whether or not a raster processing end notification has been received from each DMAC (506 to 509). If it is determined that a raster processing end notification has been received from all DMACs, the process advances to step S1205. If it is determined that there is a DMAC that has not received the raster processing end notification, the process returns to step S1204 again. Whether or not the raster processing end notification of each DMAC (506 to 509) is received is determined by whether or not the raster processing completion notification signal output by each DMAC is “1”.

  In step S1205, a response to the raster processing completion notification is returned to each DMAC (506 to 509), and the process proceeds to step S1206. That is, the control circuit unit 505 outputs “1” as a raster processing completion response signal and responds to the raster processing completion notification.

  Next, in step S1206, the content of the internal counter for counting the number of processed rasters is incremented by 1, and the process proceeds to step S1207. In step S1207, the number of processing rasters counted by the internal counter for counting the number of rasters is compared with the number of rasters set in the raster number register 804 for specifying the number of rasters in the register unit 504 (first determination). . If the counted number of rasters matches the set number of rasters, it is determined that the band processing is completed, and the process proceeds to step S1208. If the counted number of rasters has not reached the set number of rasters, the process returns to step S1202 and the raster is again set. Repeat the process. When all the raster processes are completed, a band process end process is performed in step S1208, and the present process operation ends. In this step, an interrupt signal to the CPU 102 is activated.

  In the present embodiment, the processing according to the flowchart of FIG. 11 is described in a hardware description language (HDL), and a logic circuit capable of executing the image processing operation by performing logic synthesis based on the description. Is generated. The logic circuit generated by this logic synthesis constitutes the control circuit unit.

  Next, processing procedures of the error data read DMAC 508 and the error data write DMAC 509 will be described with reference to FIGS. These processes are started by the process of step S1203 in FIG.

  First, the error data read DMAC 508 determines whether or not the start of data transfer is instructed from the control circuit unit 505 in step S1301 of FIG. 12, and proceeds to step S1302 if instructed to start data transfer. . On the other hand, if the start of data transfer is not instructed, the process returns to step S1301 again. Whether or not the start of data transfer is instructed from the control circuit unit 505 is determined by whether or not the data transfer start instruction signal is “1”.

  Next, in step S1302, the error data read DMAC 508 determines whether the processing raster is the first raster and the address for the first raster is used (second determination). If the condition is met, the process proceeds to step S1303. If not, the process proceeds to step S1304. When the head raster current signal output from the control circuit unit 505 is “1” and the head raster use address signal output from the register unit 504 is “1”, it is determined that the condition is met. That is, when the leading raster use address signal is “1”, “use leading raster origin corresponding address” shown in FIG. 8B is “1”, and “use common origin corresponding address” indicates “0”. Is the case. This is a setting for enabling reading of error data in the RAM 116. On the other hand, there is a case where the first raster current signal is “1” and the first raster use address signal is “0” as a case where the above condition is not met. In this case, “Use first raster origin corresponding address” is “0”, and “Use common origin corresponding address” is “1”. This is a setting for invalidating the reading of error data in the RAM 116 in spite of the processing of the first raster, unlike the processing in the case where the above-described conditions are met. For example, in a mode in which recording is performed using four colors of ink, in the circuit capable of processing up to six colors according to the present embodiment, a series of image processing is performed in one process, and binary recording data is generated. Can be obtained. Therefore, the error data for one line of the leading raster and the leading raster can be stored in the error buffer 510 in the circuit as four colors. For this reason, error data is not read in the RAM 116, but is read out in the error buffer 510 in spite of the processing of the leading raster. The same applies to the case of writing error data in the final raster processing, which will be described later with reference to FIG.

  Referring to FIG. 12 again, next, in step S1303, the error data read DMAC 508 calculates the read source address using the head raster origin corresponding address, and proceeds to step S1305. At this time, when the processing direction is the forward direction, the memory address is calculated from the left end pixel address set in the register unit 504, and when the processing direction is the reverse direction, the memory address is calculated from the right end pixel address set in the register unit 504. calculate. Further, the processing direction of the processing raster is acquired based on the current raster processing direction signal output from the control circuit unit 505.

  On the other hand, in step S1304, the error data read DMAC 508 calculates a read source address using the common origin corresponding address, and proceeds to step S1305. At this time, similarly to step S1303, the memory address is calculated using the left end pixel address or the right end pixel address according to the processing direction.

  Next, in step S1305, the error data read DMAC 508 performs other initialization processing related to raster processing, and specifies parameters other than the read source memory address. The error data read DMAC 508 clears a counter (not shown) in the error data read DMAC 508 that counts the number of processed pixels.

  In step S1306, the error data read DMAC 508 reads error data from the read memory address, stores it in a buffer (not shown) in the error data read DMAC 508, and updates the read memory address. Here, when the processing raster is in the forward direction, the address is updated in the increasing direction, and when the processing raster is in the reverse direction, the address is updated in the decreasing direction.

  In step S1307, the error data read DMAC 508 outputs the error data stored in the buffer in step S1306 to the quantization processing circuit unit 502 for each pixel. Further, the content of the internal counter that counts the number of processed pixels is incremented by 1, and the process proceeds to step S1308.

  In step S1308, it is determined whether or not the number of processed pixels counted by the internal counter has reached the number of pixels of one raster. If reached, the process proceeds to step S1309, and if not, step S1306 is determined. Return to, and continue reading error data. The number of pixels in one raster is calculated as a value obtained by adding 1 to the difference between the right end pixel address and the left end pixel address.

  When the error data corresponding to the number of pixels for one raster is read, the error data read DMAC 508 notifies the control circuit unit 505 of the completion of the raster processing in step S1309, and proceeds to step S1310. That is, the error data read DMAC 508 outputs “1” as a raster processing completion notification signal to notify the completion of the raster processing.

  In step S1310, the error data read DMAC 508 determines whether or not a response to the raster processing completion notification is returned from the control circuit unit 505. If there is a response, the process proceeds to step S1311. The process returns to step S1310. Whether or not a response from the control circuit unit 505 is returned is determined by whether or not the raster processing completion response signal is “1”.

  In step S1311, the error data read DMAC 508 determines whether or not the processed raster is the final raster of the band. If the final raster, the error data read DMAC 508 ends this processing operation, and if not, returns to step S1301 and returns to the subsequent raster. Continue processing.

  On the other hand, the error data write DMAC 509 determines in step S1401 in FIG. 13 whether or not the control circuit unit 505 has instructed the start of data transfer. If instructed to start the data transfer, the error data write DMAC 509 proceeds to step S1402. If the start of data transfer is not instructed, the process returns to step S1401. Whether or not the start of data transfer is instructed from the control circuit unit 505 is determined by whether or not the data transfer start instruction signal is “1”. Next, in step S1402, the error data write DMAC 509 determines whether or not the processing raster is the final raster and the address for the final raster is used. If the condition is met, the process proceeds to step S1403. The process proceeds to step S1404. When the final raster current signal output from the control circuit unit 505 is “1” and the final raster use address signal output from the register unit 504 is “1”, it is determined that the condition is met.

  In step S1403, the error data write DMAC 509 calculates a write destination address using the address corresponding to the last raster origin, and proceeds to step S1405. At this time, when the processing direction is the forward direction, the memory address is calculated from the left end pixel address set in the register unit 504, and when the processing direction is the reverse direction, the memory address is calculated from the right end pixel address set in the register unit 504. calculate. Further, the processing direction of the processing raster is acquired based on the current raster processing direction signal output from the control circuit unit 505.

  On the other hand, in step S1404, the error data write DMAC 509 calculates the write left address using the common origin corresponding address, and proceeds to step S1405. At this time, similarly to step S1403, the memory address is calculated using the left end pixel address or the right end pixel address according to the processing direction.

  Next, in step S1405, the error data write DMAC 509 performs other initialization processing relating to raster processing, and specifies parameters other than the write destination memory address. The error data write DMAC 509 clears a counter (not shown) in the error data write DMAC 509 that counts the number of processed pixels. In step S1406, the error data write DMAC 509 writes (stores) the error data for one pixel output from the quantization processing circuit unit in a buffer (not shown) in the error data write DMAC 509. Further, an internal counter (not shown) that counts the number of processed pixels is incremented by 1, and the process proceeds to step S1407.

  In step S1407, the error data write DMAC 509 writes the error data stored in the buffer in step S1406 to the write memory address and updates the write memory address. If the processing raster is in the forward direction, the address is updated in the increasing direction, and if the processing raster is in the reverse direction, the address is updated in the decreasing direction.

  In step S1408, it is determined whether or not the number of processed pixels counted by the internal counter has reached the number of pixels of one raster. If reached, the process proceeds to step S1409, and if not, step S1406 is determined. Go back to and continue writing error data. The number of pixels in one raster is calculated as a value obtained by adding 1 to the difference between the right end pixel address and the left end pixel address.

  When the error data for the number of pixels of one raster is written, the error data write DMAC 509 notifies the control circuit unit 505 of the completion of the raster processing in step S1409, and proceeds to step S1410. That is, the error data write DMAC 509 outputs “1” to the raster processing completion notification signal to notify the completion of the raster processing.

  In step S1410, the error data write DMAC 509 determines whether a response to the raster processing completion notification is returned from the control circuit unit 505. If there is a response, the process proceeds to step S1411. The process returns to step S1410. Whether or not a response from the control circuit unit 505 is returned is determined by whether or not the raster processing completion response signal is “1”. In step S1411, the error data write DMAC 509 determines whether or not the processed raster is the final raster of the band. If the final raster, the error data write DMAC 509 ends this processing operation, and if not, returns to step S1401 to perform the subsequent raster processing. Continue.

  In this embodiment, error data read DMAC and error data that can execute each image processing operation by describing the processing according to the flowcharts shown in FIGS. 12 and 13 in the hardware description language and performing logic synthesis. A write DMAC is generated. That is, the logic circuits generated by this logic synthesis constitute an error data read DMAC unit and an error data write DMAC unit, respectively.

  FIG. 14 is a flowchart for explaining processing for generating print data of 12 ink colors, particularly quantization by error diffusion, in the printing apparatus according to the present embodiment described above. In this process, as described above, the same input image data is subjected to image processing twice to obtain recording data for 12 colors.

  In FIG. 14, first, in step S1501, the CPU 102 sets registers corresponding to image processing for six colors to be processed in the first half. That is, each set value shown in FIG. 15A is set in the register unit 504 of the image processing unit 109.

  Next, in step S1502, the CPU 102 writes the value “1” in the image processing activation register 801 of the register unit 504, and activates image processing. Through the processing in this step, the image processing unit 109 executes image processing of one band for the first six colors and generates binary recording data as described above with reference to FIG. 5 and the subsequent drawings. .

  In step S1503, the process waits for completion of image processing for the six colors processed in the first half. The end of the image processing can be determined by an interrupt notification issued by the image processing unit 109 in the process of step S1208 in FIG.

  When the image processing for the first six colors is completed and an interrupt notification is received, the CPU 102 sets a register corresponding to the image processing for the six colors processed in the second half in step S1504. That is, each set value shown in FIG. 15B is set in the register unit 504 of the image processing unit 109.

  In step S1505, the value “1” is written in the image processing activation register 801 of the register unit 504 to activate the image processing in the same manner as the processing in step S1502. Through the processing in this step, the image processing unit executes image processing for one band for the latter six colors to generate binary recording data. In step S1506, the CPU 102 waits for the end of image processing for six colors to be processed in the second half. The end of the image processing is determined by an interrupt notification issued by the image processing unit 109 in the processing of step S1208.

  When the processing for the last six colors is completed, in step S1507, the CPU 102 determines whether or not processing of all image data has been completed. If unprocessed image data remains, the process returns to step S1501 to continue the process. If all the image data has been processed, the process ends.

  In the above recording data generation, by setting each set value shown in FIG. 15A in the register unit 504, in the processing of the leading raster, the RAM portion indicated by the address 0x01200000 set in the leading raster origin corresponding address 808 Error data is read from 116. Here, error data for the first six colors among the error data diffused from the final raster of the previously processed band is stored. The 64th raster is the final raster. In this raster, error data is written to the RAM unit 116 indicated by the address 0x12000000 set in the final raster origin corresponding address register 809. This error data is used as error data diffused to the head raster of the subsequent band when the first six colors of the subsequent band are processed. On the other hand, in the intermediate raster from the second raster to the 63rd raster, error data is read from and written to the error buffer unit 510 indicated by the address 0xA0000000 set in the common origin corresponding address register 807.

  Further, in the latter half of the six-color image processing in which the setting values shown in FIG. 15B are set in the register unit 504, the error data reading of the first raster and the error data writing of the last raster are similarly executed to the RAM unit 116. Is done. In an intermediate raster other than the first and last rasters, as in the case of the first six colors, the error buffer unit 510 of the image processing unit is used as a storage area for error data.

  As described above, in quantization by error diffusion according to the present embodiment, binarized image data for 12 colors is obtained by operating an image processing circuit that executes quantization processing for 6 colors twice. At this time, the error data diffused from the first raster and the error data diffused from the final raster are accessed to the RAM unit 116 constituted by a DRAM having a relatively low operation speed. On the other hand, for other error data, an error buffer unit 510 configured by an SRAM having a high operating speed in the image processing circuit, that is, a short access time is accessed.

  As a result, when the error data for one line of each raster is read or written, the raster that accesses the RAM unit 116 having a relatively low operation speed can be the first and last rasters only. As a result, the memory access speed for reading and writing error data can be improved as a whole. That is, when the same image processing is executed multiple times and the scale of the processing circuit is reduced, the memory in the circuit such as the error buffer unit is also divided into multiple times as in the above six colors. The capacity is commensurate with the amount of data processed. For this reason, for example, when the process shifts from the first six colors to the latter six colors, error data for a total of 12 colors before and after that cannot be stored in the error buffer unit at the same time, and is outside the processing circuit such as the RAM unit 116. Use other memory. At this time, in the present embodiment, by making only the first and last raster accesses to other memories, it is possible to suppress a decrease in speed due to accessing this memory as much as possible.

  As a result, even when a large amount of recording data is generated, such as 12 colors, the error diffusion processing can be performed at high speed without increasing the scale of the error diffusion processing circuit.

(Other embodiments)
In the above-described embodiment, a case has been described in which binary print data is generated by combining image data quantization with a multi-value error diffusion method and a dot arrangement pattern. However, the present invention is not limited to this, and it is needless to say that the present invention can also be configured in a recording apparatus that employs a binary error diffusion system that directly binarizes by quantization processing.

  In the above-described embodiment, the case where the CPU and each circuit block are configured as a system LSI sealed in one package has been described. However, the present invention is not limited to this, and some or all of the circuit blocks can be configured by individual ICs or the like.

  In the above-described embodiment, the case has been described in which the logic circuit is generated by logically synthesizing the contents described in the hardware description language, and the quantization process is performed by the logic circuit, but the present invention is limited to this. It is not a thing. The storage medium storing the software program for realizing the functions of the above-described embodiments is supplied to the apparatus, and the CPU of the apparatus or computer reads out and executes the program stored in the storage medium, thereby performing the quantization process. This is also included in the present invention. In this case, the program itself read from the storage medium realizes the functions of the above-described embodiments, and the storage medium storing the program constitutes the present invention. Further, based on the instruction of the program code of the program read by the computer, the OS running on the computer performs part or all of the actual processing, and the functions of the above-described embodiments are realized by the processing. Cases are also included in the present invention.

(Still another embodiment)
The present invention relates to an image processing apparatus that uses an error diffusion method in which error data of a pixel of interest is distributed to peripheral pixels around the pixel of interest, as a method for quantizing image data representing the gradation of each pixel, It can also be applied as an image processing method. The image processing apparatus can be configured in the host apparatus in addition to being integrated into the recording apparatus 100 as in the above-described embodiment.

  Further, the present invention does not limit the recording method for recording an image based on the quantized image data. Therefore, the recording method may be a recording method other than the ink jet recording method described above, and the configuration of the recording apparatus that realizes the recording method is not limited.

100 recording apparatus 102 CPU
109 Image processing unit 113 Image formation control unit ASIC
116 RAM section 118 ROM section 501 Color conversion processing circuit section 502 Quantization processing circuit section 503 Binary processing circuit section 504 Register section 505 Control circuit section 508 Error data read DMAC
509 Error data write DMAC
510 Error buffer

Claims (13)

An image processing circuit for generating recording data for each raster by performing a quantization process by an error diffusion method on image data having a plurality of rasters composed of a plurality of pixels;
First storage means for storing error data diffused by a quantization process by the image processing circuit from a raster composed of a plurality of pixels;
Second storage means for storing error data diffused by a quantization process by the image processing circuit from a raster composed of a plurality of pixels;
Have
The error processing diffused to the raster for the quantization processing by the image processing circuit is read from the second storage means, the quantization processing is performed by the image processing circuit,
Write error data diffused from the raster processed by the image processing circuit to the second storage means,
When the image processing circuit finishes the quantization processing of one band configured by arranging a predetermined number of rasters, error data diffused to the raster belonging to the next band is written to the first storage means,
If the image processing circuit to the quantization processing of the next band, and read out the error data to be diffused to a raster belonging to the next band from the first storage means,
The image processing circuit is capable of quantizing image data for N colors, and when performing image processing of image data with more colors than the N colors, the quantization processing is performed in a plurality of times, and wherein at least a first of the first image processing for the image processing of the image data of the color group, Succoth repeated every band in processing order of the second image processing to the image processing of the image data of the second color group An image processing apparatus. The image processing circuit performs image processing of a number obtained by dividing the number of colors larger than the N colors into two or more when performing image processing of image data of colors larger than the N colors. The image processing apparatus according to claim 1.   When the image processing circuit performs image processing of image data of more than N colors, when the image processing circuit finishes the quantization processing of one band, error data diffused to a raster belonging to the next band is The error data diffused to a raster belonging to the next band is read from the first storage means when the image processing circuit writes to the first storage means and the image processing circuit performs quantization processing of the next band. 2. The image processing apparatus according to 2. When the image processing circuit performs image processing of image data of N colors or less, when the image processing circuit finishes the quantization process of one band, error data diffused to a raster belonging to the next band is stored in the first band. 3. The error data diffused to a raster belonging to the next band is not read from the first storage means when the image processing circuit performs quantization processing of the next band without writing to the storage means. Or the image processing apparatus of 3.   The image processing apparatus according to claim 1, wherein the first storage unit has an access speed slower than that of the second storage unit.   The image processing according to claim 1, wherein the first storage unit is provided outside the image processing circuit, and the second storage unit is provided in the image processing circuit. apparatus.   7. The image processing circuit according to claim 1, further comprising a control circuit that instructs writing of error data to the first storage unit and reading of error data from the first storage unit. The image processing apparatus according to item. The image processing circuit further comprises first determination means for determining whether the raster on which quantization processing is performed is the final raster of each band,
When it is determined by the first determination means that the raster to which the pixel to be quantized belongs is the final raster, error data diffused to the raster belonging to the next band is written to the first storage means. The image processing apparatus according to claim 1. The image processing circuit further comprises second determination means for determining whether the raster on which the quantization processing is performed is a leading raster of each band;
When the second determination means determines that the raster to which the pixel to be quantized belongs is the first raster, the error data diffused to the raster belonging to the next band is read from the first storage means. The image processing apparatus according to claim 1. The image processing circuit further comprises third determination means for determining a processing direction of a raster for performing quantization processing,
The image processing apparatus according to claim 1, wherein the image processing circuit performs quantization processing of each raster according to a processing direction determined by the third determination unit. .   The image processing apparatus according to claim 1, further comprising a recording head that performs recording based on the recording data. From the image processing circuit that generates the recording data for each raster by performing the quantization process by the error diffusion method on the image data having a plurality of rasters composed of a plurality of pixels, and the raster composed of a plurality of pixels First storage means for storing error data diffused by quantization processing by the image processing circuit; and second storage for storing error data diffused by quantization processing by the image processing circuit from a raster composed of a plurality of pixels. An image processing method in an image processing apparatus having storage means,
Writing error data diffused from the raster processed by the image processing circuit into the second storage means;
A step of reading from the second storage means error data that is diffused to a raster on which the image processing circuit performs quantization processing, and performing the quantization processing by the image processing circuit;
When the image processing circuit finishes the quantization processing of one band configured by arranging a predetermined number of rasters, writing error data diffused to the raster belonging to the next band to the first storage means;
When the image processing circuit performs quantization processing of the next band, reading error data that diffuses to a raster belonging to the next band from the first storage unit;
With
The image processing circuit is capable of quantizing image data for N colors, and when performing image processing of image data with more colors than the N colors, the quantization processing is performed in a plurality of times, An image characterized by being repeated for each band in a processing order of at least a first image processing for image processing of image data of the first color group and a second image processing for image processing of image data of the second color group. Processing method.   A program for executing the image processing method according to claim 12 by a computer.

Images