JP5706689B2 - アーキテクチャー上の物理的合成 - Google Patents

アーキテクチャー上の物理的合成 Download PDF

Info

Publication number
JP5706689B2
JP5706689B2 JP2010518222A JP2010518222A JP5706689B2 JP 5706689 B2 JP5706689 B2 JP 5706689B2 JP 2010518222 A JP2010518222 A JP 2010518222A JP 2010518222 A JP2010518222 A JP 2010518222A JP 5706689 B2 JP5706689 B2 JP 5706689B2
Authority
JP
Japan
Prior art keywords
placement
design
transformation
resource
synthesis
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010518222A
Other languages
English (en)
Japanese (ja)
Other versions
JP2010534374A5 (cg-RX-API-DMAC7.html
JP2010534374A (ja
Inventor
ケニス エス マケルヴェイン
ケニス エス マケルヴェイン
ベノワ ルモニエ
ベノワ ルモニエ
ビル ハルピン
ビル ハルピン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Synopsys Inc
Original Assignee
Synopsys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synopsys Inc filed Critical Synopsys Inc
Publication of JP2010534374A publication Critical patent/JP2010534374A/ja
Publication of JP2010534374A5 publication Critical patent/JP2010534374A5/ja
Application granted granted Critical
Publication of JP5706689B2 publication Critical patent/JP5706689B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
    • G06F2119/12—Timing analysis or timing optimisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2010518222A 2007-07-23 2008-07-23 アーキテクチャー上の物理的合成 Active JP5706689B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US95143607P 2007-07-23 2007-07-23
US60/951,436 2007-07-23
US12/177,867 2008-07-22
US12/177,867 US8819608B2 (en) 2007-07-23 2008-07-22 Architectural physical synthesis
PCT/US2008/008998 WO2009014731A2 (en) 2007-07-23 2008-07-23 Architectural physical synthesis

Publications (3)

Publication Number Publication Date
JP2010534374A JP2010534374A (ja) 2010-11-04
JP2010534374A5 JP2010534374A5 (cg-RX-API-DMAC7.html) 2012-11-29
JP5706689B2 true JP5706689B2 (ja) 2015-04-22

Family

ID=40139171

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010518222A Active JP5706689B2 (ja) 2007-07-23 2008-07-23 アーキテクチャー上の物理的合成

Country Status (5)

Country Link
US (2) US8819608B2 (cg-RX-API-DMAC7.html)
EP (1) EP2171623A2 (cg-RX-API-DMAC7.html)
JP (1) JP5706689B2 (cg-RX-API-DMAC7.html)
CN (1) CN101821737A (cg-RX-API-DMAC7.html)
WO (1) WO2009014731A2 (cg-RX-API-DMAC7.html)

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8595674B2 (en) 2007-07-23 2013-11-26 Synopsys, Inc. Architectural physical synthesis
JP5239597B2 (ja) * 2008-07-31 2013-07-17 ソニー株式会社 データ処理装置およびその方法、並びにプログラム
US8307315B2 (en) 2009-01-30 2012-11-06 Synopsys, Inc. Methods and apparatuses for circuit design and optimization
US9576092B2 (en) * 2009-02-24 2017-02-21 Mentor Graphics Corporation Synthesis using multiple synthesis engine configurations
US8656332B2 (en) * 2009-02-26 2014-02-18 International Business Machines Corporation Automated critical area allocation in a physical synthesized hierarchical design
US8255847B1 (en) * 2009-10-01 2012-08-28 Altera Corporation Method and apparatus for automatic hierarchical design partitioning
US10185594B2 (en) * 2009-10-29 2019-01-22 International Business Machines Corporation System and method for resource identification
US8261220B2 (en) * 2009-11-30 2012-09-04 Synopsys, Inc. Path preserving design partitioning with redundancy
US8276107B2 (en) * 2010-10-18 2012-09-25 Algotochip Corporation Integrated data model based framework for driving design convergence from architecture optimization to physical design closure
US8336017B2 (en) * 2011-01-19 2012-12-18 Algotochip Corporation Architecture optimizer
US9381013B2 (en) * 2011-11-10 2016-07-05 Biomet Sports Medicine, Llc Method for coupling soft tissue to a bone
US9524363B2 (en) * 2012-05-31 2016-12-20 Globalfoundries Inc. Element placement in circuit design based on preferred location
CN102768506B (zh) * 2012-07-18 2015-01-07 复旦大学 带时序约束的fpga时序驱动布局方法
US9836567B2 (en) 2012-09-14 2017-12-05 Nxp Usa, Inc. Method of simulating a semiconductor integrated circuit, computer program product, and device for simulating a semiconductor integrated circuit
US8914759B2 (en) * 2012-12-31 2014-12-16 Synopsys, Inc. Abstract creation
US9087168B2 (en) * 2013-06-19 2015-07-21 International Business Machines Corporation Optimizing operating range of an electronic circuit
CN104376138B (zh) * 2013-08-15 2017-11-21 龙芯中科技术有限公司 集成电路芯片的时序确定方法和装置
US20150178436A1 (en) * 2013-12-20 2015-06-25 Lattice Semiconductor Corporation Clock assignments for programmable logic device
US10783292B1 (en) 2015-05-21 2020-09-22 Pulsic Limited Automated analog layout
CN105005638B (zh) * 2015-06-04 2018-06-26 广东顺德中山大学卡内基梅隆大学国际联合研究院 一种基于线性延时模型的高层次综合调度方法
US9613173B1 (en) * 2015-10-01 2017-04-04 Xilinx, Inc. Interactive multi-step physical synthesis
US9852254B2 (en) * 2015-11-10 2017-12-26 Arteris, Inc. Automatic architecture placement guidance
US9852259B2 (en) 2016-01-21 2017-12-26 Globalfoundries Inc. Area and/or power optimization through post-layout modification of integrated circuit (IC) design blocks
US9495501B1 (en) 2016-01-29 2016-11-15 International Business Machines Corporation Large cluster persistence during placement optimization of integrated circuit designs
US10120970B2 (en) 2016-06-14 2018-11-06 International Business Machines Corporation Global routing framework of integrated circuit based on localized routing optimization
US10586005B1 (en) 2018-03-21 2020-03-10 Xilinx, Inc. Incremental synthesis for changes to a circuit design
CN109670268B (zh) * 2018-12-29 2022-11-25 京微齐力(北京)科技有限公司 一种多个ip与efpga端口连接方法
JP2022536648A (ja) 2019-06-10 2022-08-18 バテル メモリアル インスティチュート 平坦化されたネットリストからの挙動設計回復
CN110765710B (zh) * 2019-10-22 2021-11-30 清华大学 基于非易失器件的通用逻辑综合方法及装置
CN111027267B (zh) * 2019-11-13 2021-01-19 广东高云半导体科技股份有限公司 Fpga逻辑综合中加法器优化的实现方法及装置、系统
CN111143274B (zh) * 2019-11-13 2022-07-12 广东高云半导体科技股份有限公司 以逻辑综合结果为导向的层级结构优化方法及装置、系统
US10891413B1 (en) * 2019-12-05 2021-01-12 Xilinx, Inc. Incremental initialization by parent and child placer processes in processing a circuit design
US11121933B2 (en) 2019-12-27 2021-09-14 Arteris, Inc. Physically aware topology synthesis of a network
CN111198523A (zh) * 2019-12-27 2020-05-26 广东高云半导体科技股份有限公司 基于结果导向的逻辑推理控制方法及装置、系统
US11665776B2 (en) 2019-12-27 2023-05-30 Arteris, Inc. System and method for synthesis of a network-on-chip for deadlock-free transformation
US11657203B2 (en) 2019-12-27 2023-05-23 Arteris, Inc. Multi-phase topology synthesis of a network-on-chip (NoC)
US11558259B2 (en) 2019-12-27 2023-01-17 Arteris, Inc. System and method for generating and using physical roadmaps in network synthesis
US10990724B1 (en) 2019-12-27 2021-04-27 Arteris, Inc. System and method for incremental topology synthesis of a network-on-chip
US11418448B2 (en) 2020-04-09 2022-08-16 Arteris, Inc. System and method for synthesis of a network-on-chip to determine optimal path with load balancing
CN113642280B (zh) * 2020-04-27 2024-06-14 中国科学院上海微系统与信息技术研究所 超导集成电路的布局方法
CN112270148A (zh) * 2020-10-16 2021-01-26 山东云海国创云计算装备产业创新中心有限公司 一种门级网表生成方法及相关装置
US11601357B2 (en) 2020-12-22 2023-03-07 Arteris, Inc. System and method for generation of quality metrics for optimization tasks in topology synthesis of a network
US11281827B1 (en) 2020-12-26 2022-03-22 Arteris, Inc. Optimization of parameters for synthesis of a topology using a discriminant function module
US11449655B2 (en) 2020-12-30 2022-09-20 Arteris, Inc. Synthesis of a network-on-chip (NoC) using performance constraints and objectives
US12289384B2 (en) 2021-02-12 2025-04-29 Arteris, Inc. System and method for synthesis of connectivity to an interconnect in a multi-protocol system-on-chip (SoC)
US11956127B2 (en) 2021-03-10 2024-04-09 Arteris, Inc. Incremental topology modification of a network-on-chip
US12184499B2 (en) 2021-09-29 2024-12-31 Arteris, Inc. System and method for editing a network-on-chip (NOC)
US12438829B2 (en) 2021-09-29 2025-10-07 Arteris, Inc. System and method for deadlock detection in network-on-chip (NoC) having external dependencies
US12067335B2 (en) 2022-04-11 2024-08-20 Arteris, Inc. Automatic configuration of pipeline modules in an electronics system
CN115952759B (zh) * 2023-02-20 2025-10-24 京微齐力(北京)科技股份有限公司 Fpga布局方法、装置、电子设备和存储介质

Family Cites Families (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01142922A (ja) 1987-11-30 1989-06-05 Omron Tateisi Electron Co プリンタ用アダプタ
JPH0659686B2 (ja) 1990-10-29 1994-08-10 ダイアホイルヘキスト株式会社 コンデンサー用二軸配向ポリエステルフィルム
JPH05342290A (ja) 1992-06-08 1993-12-24 Nec Corp 要素配置方法および装置
JPH06266801A (ja) 1993-03-15 1994-09-22 Nec Corp フロアプランを考慮した論理合成方法
JP3424997B2 (ja) 1995-01-31 2003-07-07 富士通株式会社 回路設計装置
US5712793A (en) 1995-11-20 1998-01-27 Lsi Logic Corporation Physical design automation system and process for designing integrated circuit chips using fuzzy cell clusterization
JP2954894B2 (ja) 1996-12-13 1999-09-27 株式会社半導体理工学研究センター 集積回路設計方法、集積回路設計のためのデータベース装置および集積回路設計支援装置
JPH1185819A (ja) 1997-09-02 1999-03-30 Matsushita Electric Ind Co Ltd 部品配置装置
US6249902B1 (en) 1998-01-09 2001-06-19 Silicon Perspective Corporation Design hierarchy-based placement
US6145117A (en) 1998-01-30 2000-11-07 Tera Systems Incorporated Creating optimized physical implementations from high-level descriptions of electronic design using placement based information
US6519754B1 (en) 1999-05-17 2003-02-11 Synplicity, Inc. Methods and apparatuses for designing integrated circuits
JP2001142922A (ja) 1999-11-15 2001-05-25 Matsushita Electric Ind Co Ltd 半導体集積回路装置の設計方法
US6618839B1 (en) * 1999-11-30 2003-09-09 Synplicity, Inc. Method and system for providing an electronic system design with enhanced debugging capabilities
US7047163B1 (en) * 2000-03-13 2006-05-16 International Business Machines Corporation Method and apparatus for applying fine-grained transforms during placement synthesis interaction
US6415426B1 (en) 2000-06-02 2002-07-02 Incentia Design Systems, Inc. Dynamic weighting and/or target zone analysis in timing driven placement of cells of an integrated circuit design
JP2002123563A (ja) * 2000-10-13 2002-04-26 Nec Corp コンパイル方法および合成装置ならびに記録媒体
US6711729B1 (en) 2000-12-05 2004-03-23 Synplicity, Inc. Methods and apparatuses for designing integrated circuits using automatic reallocation techniques
US6480991B1 (en) 2001-04-11 2002-11-12 International Business Machines Corporation Timing-driven global placement based on geometry-aware timing budgets
JP2005517223A (ja) 2001-06-08 2005-06-09 マグマ・デザイン・オートメーション・インコーポレイテッド 階層的な集積回路設計システムのモジュールに対する設計制約の生成方法
JP2005527045A (ja) 2002-05-23 2005-09-08 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 集積回路設計方法
US7827510B1 (en) * 2002-06-07 2010-11-02 Synopsys, Inc. Enhanced hardware debugging with embedded FPGAS in a hardware description language
JP2004164627A (ja) 2002-10-22 2004-06-10 Matsushita Electric Ind Co Ltd 高位合成方法
US6925628B2 (en) 2002-10-22 2005-08-02 Matsushita Electric Industrial Co., Ltd. High-level synthesis method
JP3811133B2 (ja) * 2003-03-03 2006-08-16 三菱電機株式会社 半導体集積回路設計方法および設計支援装置
US7003747B2 (en) 2003-05-12 2006-02-21 International Business Machines Corporation Method of achieving timing closure in digital integrated circuits by optimizing individual macros
US7337100B1 (en) * 2003-06-12 2008-02-26 Altera Corporation Physical resynthesis of a logic design
US8095903B2 (en) 2004-06-01 2012-01-10 Pulsic Limited Automatically routing nets with variable spacing
US7788625B1 (en) * 2005-04-14 2010-08-31 Xilinx, Inc. Method and apparatus for precharacterizing systems for use in system level design of integrated circuits
CN100347710C (zh) 2005-05-13 2007-11-07 清华大学 多端线网插入缓冲器优化时延的标准单元总体布线方法
WO2007002799A1 (en) 2005-06-29 2007-01-04 Lightspeed Logic, Inc. Methods and systems for placement
GB0516634D0 (en) 2005-08-12 2005-09-21 Univ Sussex Electronic circuit design
CN100362520C (zh) 2005-09-09 2008-01-16 深圳市海思半导体有限公司 一种专用集成电路综合系统及方法
US7451416B2 (en) 2006-03-17 2008-11-11 International Business Machines Corporation Method and system for designing an electronic circuit
US8332793B2 (en) 2006-05-18 2012-12-11 Otrsotech, Llc Methods and systems for placement and routing
US8595674B2 (en) 2007-07-23 2013-11-26 Synopsys, Inc. Architectural physical synthesis

Also Published As

Publication number Publication date
US20140053120A1 (en) 2014-02-20
EP2171623A2 (en) 2010-04-07
CN101821737A (zh) 2010-09-01
JP2010534374A (ja) 2010-11-04
US20090031277A1 (en) 2009-01-29
WO2009014731A2 (en) 2009-01-29
WO2009014731A9 (en) 2009-04-09
US8966415B2 (en) 2015-02-24
US8819608B2 (en) 2014-08-26

Similar Documents

Publication Publication Date Title
JP5706689B2 (ja) アーキテクチャー上の物理的合成
JP5608079B2 (ja) アーキテクチャー上の物理的合成
US7669160B2 (en) Methods and systems for placement
US7275233B2 (en) Methods and apparatuses for designing integrated circuits
US7752588B2 (en) Timing driven force directed placement flow
CN104239595B (zh) 用于实现用于设计规划和架构探索的系统级设计工具的方法和装置
Hutton et al. FPGA synthesis and physical design
Chen et al. Simultaneous timing driven clustering and placement for FPGAs
Pandini et al. Congestion-aware logic synthesis
TWI475415B (zh) 架構之實體合成
Reis et al. Physical awareness starting at technology-independent logic synthesis
WO2007146966A2 (en) Methods and systems for placement
Murgai Technology-dependent logic optimization
Iida Design Methodology
Sayal EDA design for Microscale Modular Assembled ASIC (M2A2) circuits
Choi Performance driven optimization of VLSI layout

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20110722

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20110722

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20120921

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20121011

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20130314

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20130614

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20130621

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20130716

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131017

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140117

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140124

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20140217

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20140224

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140317

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140702

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141104

A911 Transfer to examiner for re-examination before appeal (zenchi)

Free format text: JAPANESE INTERMEDIATE CODE: A911

Effective date: 20141217

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20150128

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20150227

R150 Certificate of patent or registration of utility model

Ref document number: 5706689

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250