JP5678418B2 - Semiconductor device - Google Patents

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JP5678418B2
JP5678418B2 JP2009195243A JP2009195243A JP5678418B2 JP 5678418 B2 JP5678418 B2 JP 5678418B2 JP 2009195243 A JP2009195243 A JP 2009195243A JP 2009195243 A JP2009195243 A JP 2009195243A JP 5678418 B2 JP5678418 B2 JP 5678418B2
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temperature
semiconductor substrate
region
detection element
temperature detection
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JP2011049272A (en
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亀山　悟
悟 亀山
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Toyota Motor Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601—Structure
    • H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths

Description

本発明は、温度検知素子を備えた半導体装置に関する。   The present invention relates to a semiconductor device provided with a temperature detection element.

半導体装置が動作することによって、半導体装置が発熱する場合がある。特に、大電流が流れるＩＧＢＴ等のパワー半導体装置では、この発熱量が大きくなる傾向がある。半導体装置による発熱を検知するために、半導体装置に温度センサが設置されることがある。例えば、特許文献１では、半導体基板の表面の中央部と端部に、温度検知素子としてダイオードを設置している。この半導体装置は、２箇所に設置したダイオードの温度を検知して、半導体装置の表面温度をより均一化するように、ゲート電圧等を制御する。   When the semiconductor device operates, the semiconductor device may generate heat. In particular, in a power semiconductor device such as an IGBT through which a large current flows, the amount of generated heat tends to increase. In order to detect heat generated by the semiconductor device, a temperature sensor may be installed in the semiconductor device. For example, in Patent Document 1, diodes are installed as temperature detection elements at the center and the end of the surface of a semiconductor substrate. This semiconductor device detects the temperature of diodes installed at two locations, and controls the gate voltage and the like so as to make the surface temperature of the semiconductor device more uniform.

特開２００７−２３４８５０号公報JP 2007-234850 A

特許文献１の技術では、半導体装置の表面温度を均一化することのみを目的に温度検知素子を設置しているため、２つの温度検知素子は、ともに半導体基板の表面上に設置されている。しかしながら、半導体基板の内部で発熱が発生する場合（例えば、半導体基板を縦方向に電流が流れる縦型の半導体装置等の場合）には、半導体基板の表面よりも半導体基板の内部において温度上昇が起こり易い。特許文献１の技術では、半導体基板の発熱によって半導体基板の内部が高温となっていても、半導体基板の表面温度が上昇しないと、この発熱を検知することができない。また、半導体基板の表面上に設置された温度検知素子によって半導体装置の発熱を検知しても、半導体基板の深さ方向のどの位置で発熱しているかを判断することはできない。発熱の原因となった箇所の位置を知るためには、さらに断面観察等を行う必要がある。   In the technique of Patent Document 1, since the temperature detection element is installed only for the purpose of uniformizing the surface temperature of the semiconductor device, the two temperature detection elements are both installed on the surface of the semiconductor substrate. However, when heat is generated inside the semiconductor substrate (for example, in the case of a vertical semiconductor device in which a current flows through the semiconductor substrate in the vertical direction), the temperature rises inside the semiconductor substrate rather than the surface of the semiconductor substrate. It is easy to happen. In the technique of Patent Document 1, even if the inside of the semiconductor substrate is heated due to heat generation of the semiconductor substrate, this heat generation cannot be detected unless the surface temperature of the semiconductor substrate rises. Further, even if heat generation of the semiconductor device is detected by a temperature detection element installed on the surface of the semiconductor substrate, it cannot be determined at which position in the depth direction of the semiconductor substrate the heat generation. In order to know the position of the location that caused the heat generation, it is necessary to further observe the cross section.

本発明では、主活性領域が形成された半導体基板と、半導体基板の温度を検知する第１温度検知素子と、第１温度検知素子よりも半導体基板の深い位置の温度を検知する第２温度検知素子とを備える半導体装置を提供する。この半導体装置では、第１温度検知素子と第２温度検知素子は、半導体基板の表面の等温度領域に設けられている。 In the present invention, the semiconductor substrate in which the main active region is formed, the first temperature detection element for detecting the temperature of the semiconductor substrate, and the second temperature detection for detecting the temperature at a position deeper than the first temperature detection element. A semiconductor device including the element is provided. In this semiconductor device, the first temperature detection element and the second temperature detection element are provided in an isothermal region on the surface of the semiconductor substrate.

本発明によれば、第１温度検知素子と第２温度検知素子によって、半導体基板の深さが異なる２つの位置の温度を検知することができる。半導体基板の内部で発熱が発生した場合により温度が上昇し易い、半導体基板の内部での温度を検知することができるため、半導体基板内部での発熱を検知し易くなる。半導体基板の内部と表面側の温度が検知できるため、半導体基板において発熱している箇所の深さ方向の位置を推定することができる。   According to the present invention, the first temperature detection element and the second temperature detection element can detect the temperatures at two positions where the depth of the semiconductor substrate is different. When heat is generated inside the semiconductor substrate, it is possible to detect the temperature inside the semiconductor substrate, which is likely to increase the temperature. Therefore, it is easy to detect the heat generation inside the semiconductor substrate. Since the temperature inside and on the surface side of the semiconductor substrate can be detected, it is possible to estimate the position in the depth direction of the location where heat is generated in the semiconductor substrate.

また、第２温度検知素子を配置する深さを発熱が予想される位置に配置することで、半導体基板の深さ方向の温度分布を検知することができるため、深さ方向の温度分布を知ることができる。   In addition, since the temperature distribution in the depth direction of the semiconductor substrate can be detected by arranging the depth at which the second temperature detection element is arranged at a position where heat generation is expected, the temperature distribution in the depth direction is known. be able to.

さらに、第１温度検知素子と第２温度検知素子は、半導体基板の表面の等温度領域に設けられているため、半導体基板の平面方向の温度分布による影響を小さくした状態で、半導体基板の深さ方向の温度分布を検知することができる。 Further, the first temperature sensing element and the second temperature sensing element, because it is provided in the constant temperature region of the semiconductor substrate surface, while reducing the influence of the temperature distribution in the planar direction of the semiconductor substrate, a semiconductor substrate depth The temperature distribution in the vertical direction can be detected.

第１温度検知素子と第２温度検知素子は、半導体基板の平面方向の位置が隣接していることが好ましい。このようにしても、半導体基板の平面方向の温度分布による影響を小さくした状態で、半導体基板の深さ方向の温度分布を検知することができる。   The first temperature detection element and the second temperature detection element are preferably adjacent to each other in the planar direction of the semiconductor substrate. Even in this case, the temperature distribution in the depth direction of the semiconductor substrate can be detected in a state where the influence of the temperature distribution in the planar direction of the semiconductor substrate is reduced.

第１温度検知素子と第２温度検知素子は、半導体基板の平面方向の中央部となる位置に設置されていることが好ましい。半導体基板の平面方向の中央部は、端部に比べて半導体基板の発熱による温度上昇が発生し易い。このため、この中央部において、半導体基板の深さ方向の温度分布を測定すれば、検知感度が向上する。   It is preferable that the first temperature detection element and the second temperature detection element are installed at a position that is a central portion in the planar direction of the semiconductor substrate. A temperature rise due to heat generation of the semiconductor substrate is more likely to occur in the central portion in the planar direction of the semiconductor substrate than in the end portion. For this reason, if the temperature distribution in the depth direction of the semiconductor substrate is measured at this central portion, the detection sensitivity is improved.

第２温度検知素子は、半導体基板の表面から内部に向けて形成されており、その内壁面に絶縁膜が形成されているトレンチと、トレンチ内の底部に形成された第１導電型の第１半導体領域と、トレンチ内の底部に形成され、第１半導体領域と接する第２導電型の第２半導体領域と、第１半導体領域に接し、第２半導体領域に接しない第１電極と、第２半導体領域に接し、第１半導体領域に接しない第２電極と、第１電極と第２電極とを隔離する絶縁体とを備えることが好ましい。   The second temperature detection element is formed from the surface of the semiconductor substrate toward the inside, and has a trench in which an insulating film is formed on the inner wall surface, and a first conductivity type first formed at the bottom of the trench. A semiconductor region, a second conductivity type second semiconductor region formed at the bottom of the trench and in contact with the first semiconductor region; a first electrode in contact with the first semiconductor region but not in contact with the second semiconductor region; It is preferable to include a second electrode that is in contact with the semiconductor region and not in contact with the first semiconductor region, and an insulator that separates the first electrode and the second electrode.

本発明によれば、半導体基板の深さ方向の温度分布を検知することができるため、半導体装置の発熱を検知し易くなる。半導体基板の内部と表面側の温度が検知できるため、半導体基板において発熱している箇所の深さ方向の位置を推定することができる。   According to the present invention, since the temperature distribution in the depth direction of the semiconductor substrate can be detected, it becomes easy to detect the heat generation of the semiconductor device. Since the temperature inside and on the surface side of the semiconductor substrate can be detected, it is possible to estimate the position in the depth direction of the location where heat is generated in the semiconductor substrate.

実施例１の半導体装置の平面図。FIG. 3 is a plan view of the semiconductor device of Example 1; 図１のＩＩ−ＩＩ線断面の拡大図。The enlarged view of the II-II line cross section of FIG. 図１のＩＩＩ−ＩＩＩ線断面におけるトレンチ底部の拡大図。The enlarged view of the trench bottom part in the III-III line cross section of FIG. 実施例１の半導体装置の通常動作時における半導体基板の深さ方向の温度分布の概念図。3 is a conceptual diagram of a temperature distribution in the depth direction of a semiconductor substrate during normal operation of the semiconductor device of Example 1. FIG. 実施例１の半導体装置の短絡発生時における半導体基板の深さ方向の温度分布の概念図。2 is a conceptual diagram of a temperature distribution in the depth direction of a semiconductor substrate when a short circuit occurs in the semiconductor device of Example 1. FIG. 実施例１の半導体装置の通常動作時と短絡発生時の深さ方向の温度差を比較する概念図。The conceptual diagram which compares the temperature difference of the depth direction at the time of normal operation of the semiconductor device of Example 1, and the time of a short circuit occurrence. 変形例の半導体装置の平面図。The top view of the semiconductor device of a modification. 半導体基板の表面温度分布の概念図。The conceptual diagram of the surface temperature distribution of a semiconductor substrate. 変形例の半導体装置の断面図。Sectional drawing of the semiconductor device of a modification. 変形例の半導体装置の断面図。Sectional drawing of the semiconductor device of a modification. 変形例の半導体装置の断面図。Sectional drawing of the semiconductor device of a modification. 変形例の半導体装置の断面図。Sectional drawing of the semiconductor device of a modification. 変形例の半導体装置の断面図。Sectional drawing of the semiconductor device of a modification. 変形例の温度検知素子の断面図。Sectional drawing of the temperature detection element of a modification. 変形例の温度検知素子の断面図。Sectional drawing of the temperature detection element of a modification. 変形例の温度検知素子の断面図。Sectional drawing of the temperature detection element of a modification.

以下に説明する実施例の主要な特徴を以下に列記する。
（特徴１）主活性領域には、縦型のＩＧＢＴが形成されている。
（特徴２）温度検知素子の少なくとも１つは、ＩＧＢＴのボディ領域近傍のドリフト領域の深さの温度を検知する位置に設けられている。 The main features of the embodiments described below are listed below.
(Feature 1) A vertical IGBT is formed in the main active region.
(Feature 2) At least one of the temperature detection elements is provided at a position for detecting the temperature of the depth of the drift region near the body region of the IGBT.

以下、本発明の実施例１について、図面を参照しながら説明する。図１は本実施例に係る半導体装置１００の平面図であり、図２は図１に示す半導体装置１００のＩＩ−ＩＩ線断面の拡大図であり、図３は図１に示す半導体装置１００のＩＩＩ−ＩＩＩ線断面におけるトレンチ底部の拡大図である。   Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of a semiconductor device 100 according to the present embodiment, FIG. 2 is an enlarged view of a cross section taken along line II-II of the semiconductor device 100 shown in FIG. 1, and FIG. It is an enlarged view of the trench bottom part in the III-III line cross section.

図１に示すように、半導体装置１００は、主活性領域１と温度検知領域２とを含む半導体基板１０を備えている。温度検知領域２においては、第１温度検知素子３と、第２温度検知素子５が形成されている。半導体基板１０の主活性領域１には、縦型のＩＧＢＴが形成されている。   As shown in FIG. 1, the semiconductor device 100 includes a semiconductor substrate 10 including a main active region 1 and a temperature detection region 2. In the temperature detection region 2, a first temperature detection element 3 and a second temperature detection element 5 are formed. A vertical IGBT is formed in the main active region 1 of the semiconductor substrate 10.

図１に示すように、第１温度検知素子３と第２温度検知素子５とは、半導体基板１０を平面視したときの中央部（平面方向の中央部）に設けられており、互いに隣接している。本実施例においては、第１温度検知素子３および第２温度検知素子５は、ともにダイオードである。半導体基板１０の表面の周縁部には、カソードパッド３２、５２、アノードパッド３４、５４が形成されている。   As shown in FIG. 1, the first temperature detection element 3 and the second temperature detection element 5 are provided in a central portion (a central portion in the planar direction) when the semiconductor substrate 10 is viewed in plan, and are adjacent to each other. ing. In the present embodiment, the first temperature detection element 3 and the second temperature detection element 5 are both diodes. Cathode pads 32 and 52 and anode pads 34 and 54 are formed on the periphery of the surface of the semiconductor substrate 10.

図２に示すように、半導体基板１０は、裏面側から順に、Ｐ＋型のコレクタ領域１０１、Ｎ型のバッファ領域１０２、Ｎ−型のドリフト領域１０３、Ｐ型のボディ領域１０４が積層されている。 As shown in FIG. 2, the semiconductor substrate 10 has a P + -type collector region 101, an N-type buffer region 102, an N − -type drift region 103, and a P-type body region 104 stacked in order from the back surface side. Yes.

主活性領域１においては、ボディ領域１０４の表面に、Ｎ＋型のエミッタ領域１０５と、Ｐ＋型のボディコンタクト領域１０６とが形成されている。エミッタ領域１０５およびボディコンタクト領域１０６は、ボディ領域１０４によってドリフト領域１０３と隔離されている。半導体基板１０の表面側から、ボディ領域１０４を貫通し、ドリフト領域１０３に至るトレンチゲート１３０が設けられている。エミッタ領域１０５は、トレンチゲート１３０の側面と接している。トレンチゲート１３０のトレンチの内壁面にはゲート絶縁膜が形成されており、ゲート絶縁膜の内部にゲート電極が充填されている。トレンチゲート１３０の上面は、半導体基板１０の表面に形成された絶縁膜４１によって被覆されている。 In main active region 1, N + -type emitter region 105 and P + -type body contact region 106 are formed on the surface of body region 104. Emitter region 105 and body contact region 106 are isolated from drift region 103 by body region 104. A trench gate 130 that penetrates through the body region 104 and reaches the drift region 103 from the surface side of the semiconductor substrate 10 is provided. The emitter region 105 is in contact with the side surface of the trench gate 130. A gate insulating film is formed on the inner wall surface of the trench of the trench gate 130, and the gate electrode is filled in the gate insulating film. The upper surface of the trench gate 130 is covered with an insulating film 41 formed on the surface of the semiconductor substrate 10.

図２に示すように、第１温度検知素子３は、その内壁面に絶縁膜が形成されているトレンチ３０１と、トレンチ３０１内の底部に形成されたＮ型の第１半導体領域３０３と、トレンチ３０１内の底部に形成され、第１半導体領域３０３と接するＰ型の第２半導体領域３０５とを備えている。第１半導体領域３０３はダイオードのカソード領域となり、第２半導体領域３０３はダイオードのアノード領域となる。   As shown in FIG. 2, the first temperature sensing element 3 includes a trench 301 in which an insulating film is formed on the inner wall surface, an N-type first semiconductor region 303 formed at the bottom of the trench 301, and a trench A P-type second semiconductor region 305 that is formed at the bottom of 301 and is in contact with the first semiconductor region 303 is provided. The first semiconductor region 303 becomes a cathode region of the diode, and the second semiconductor region 303 becomes an anode region of the diode.

トレンチ３０１は、半導体基板１０の表面側からボディ領域１０４内にまで設けられており、ドリフト領域１０３には到達していない。トレンチ３０１内の第１半導体領域３０３および第２半導体領域３０５は、ボディ領域１０４内に位置している。これによって、第１温度検知素子３は、半導体基板１０の主活性領域１のボディ領域１０４の位置の温度を検知できる。   The trench 301 is provided from the surface side of the semiconductor substrate 10 to the body region 104, and does not reach the drift region 103. The first semiconductor region 303 and the second semiconductor region 305 in the trench 301 are located in the body region 104. Thereby, the first temperature detection element 3 can detect the temperature at the position of the body region 104 of the main active region 1 of the semiconductor substrate 10.

図２に示すように、第２温度検知素子５は、第１温度検知素子３よりも半導体基板１０の深い位置に形成されている。第２温度検知素子５は、半導体基板１０のボディ領域１０４側の表面から内部に向けて形成されている。第２温度検知素子５は、その内壁面に絶縁膜が形成されているトレンチ５０１と、トレンチ５０１内の底部に形成されたＮ型の第１半導体領域５０３と、トレンチ５０１内の底部に形成され、第１半導体領域５０３と接するＰ型の第２半導体領域５０５とを備えている。第１半導体領域５０３はダイオードのカソード領域となり、第２半導体領域５０３はダイオードのアノード領域となる。   As shown in FIG. 2, the second temperature detection element 5 is formed at a deeper position on the semiconductor substrate 10 than the first temperature detection element 3. The second temperature detection element 5 is formed from the surface on the body region 104 side of the semiconductor substrate 10 toward the inside. The second temperature detection element 5 is formed at a trench 501 having an insulating film formed on its inner wall surface, an N-type first semiconductor region 503 formed at the bottom of the trench 501, and a bottom of the trench 501. And a P-type second semiconductor region 505 in contact with the first semiconductor region 503. The first semiconductor region 503 becomes a cathode region of the diode, and the second semiconductor region 503 becomes an anode region of the diode.

トレンチ５０１は、半導体基板１０の表面側からボディ領域１０４を貫通し、ドリフト領域１０３に到達している。トレンチ５０１の底部は、主活性領域１のトレンチゲート１３０の底部と同じ深さであり、ボディ領域１０４近傍のドリフト領域１０３内に第１半導体領域５０３および第２半導体領域５０５が位置している。これによって、第２温度検知素子５は、半導体基板１０の主活性領域１の、ボディ領域１０４近傍のドリフト領域１０３の位置の温度を検知できる。すなわち、第２温度検知素子５は、第１温度検知素子３よりも、半導体基板１０の深い位置の温度を検知する。   The trench 501 penetrates the body region 104 from the surface side of the semiconductor substrate 10 and reaches the drift region 103. The bottom of the trench 501 has the same depth as the bottom of the trench gate 130 in the main active region 1, and the first semiconductor region 503 and the second semiconductor region 505 are located in the drift region 103 near the body region 104. Thereby, the second temperature detection element 5 can detect the temperature at the position of the drift region 103 in the vicinity of the body region 104 in the main active region 1 of the semiconductor substrate 10. That is, the second temperature detection element 5 detects the temperature at a position deeper in the semiconductor substrate 10 than the first temperature detection element 3.

第１温度検知素子３が設けられた半導体基板１０の表面には、絶縁膜４３が形成されており、第２温度検知素子５が設けられた半導体基板１０の表面には、絶縁膜４５が形成されている。   An insulating film 43 is formed on the surface of the semiconductor substrate 10 provided with the first temperature detecting element 3, and an insulating film 45 is formed on the surface of the semiconductor substrate 10 provided with the second temperature detecting element 5. Has been.

第２温度検知素子５のトレンチ５０１の底部の拡大図である図３を用いて、ダイオードを構成する第１半導体領域と第２半導体領域の構成について説明する。図３は、図２に示す断面と垂直な方向の断面の一部を示している。尚、第１温度検知素子３のトレンチ３０１の底部も、第２温度検知素子５と同様の構成である。   A configuration of the first semiconductor region and the second semiconductor region constituting the diode will be described with reference to FIG. 3 which is an enlarged view of the bottom of the trench 501 of the second temperature detection element 5. FIG. 3 shows a part of a cross section in a direction perpendicular to the cross section shown in FIG. The bottom of the trench 301 of the first temperature detection element 3 has the same configuration as that of the second temperature detection element 5.

図３に示すように、トレンチ５０１の底部にはＮ型の第１半導体領域５０３、Ｐ型の第２半導体領域５０５が積層されており、その表面側には、第１電極５２３、第２電極５２５、絶縁体５０７が設けられている。第１半導体領域５０３はその一部が上方（第２半導体領域５０５側）に突出しており、その突出部において第１電極５２３と接している。第２半導体領域５０５は、第２電極５２５と接している。絶縁体５０７は、第１電極５２３と第２電極５２５とを隔離しており、第１電極５２３と第２半導体領域５２５とを隔離している。これによって、第１電極５２３は、第１半導体領域５０３にのみ接し、第２半導体領域５０５に接しない状態となる。第２電極５２５は、第２半導体領域５０５にのみ接し、第１半導体領域５０３に接しない状態となる。   As shown in FIG. 3, an N-type first semiconductor region 503 and a P-type second semiconductor region 505 are stacked at the bottom of the trench 501, and a first electrode 523 and a second electrode are formed on the surface side thereof. 525 and an insulator 507 are provided. A portion of the first semiconductor region 503 protrudes upward (on the second semiconductor region 505 side), and is in contact with the first electrode 523 at the protruding portion. The second semiconductor region 505 is in contact with the second electrode 525. The insulator 507 isolates the first electrode 523 and the second electrode 525 and isolates the first electrode 523 and the second semiconductor region 525. Accordingly, the first electrode 523 is in contact with only the first semiconductor region 503 and is not in contact with the second semiconductor region 505. The second electrode 525 is in contact with only the second semiconductor region 505 and is not in contact with the first semiconductor region 503.

第１電極５２３は、ダイオードのカソード領域となる第１半導体領域５０３と接するカソード電極である。図３に示す第１電極５２３と図１に示すカソードパッド５２は、図１に示す半導体基板１０の表面に形成された配線によって接続されている。第２電極５２５は、ダイオードのアノード領域となる第２半導体領域５０５と接するアノード電極である。図３に示す第２電極５２５と図１に示すアノードパッド５４は、図１に示す半導体基板１０の表面に形成された配線によって接続されている。   The first electrode 523 is a cathode electrode in contact with the first semiconductor region 503 that becomes the cathode region of the diode. The first electrode 523 shown in FIG. 3 and the cathode pad 52 shown in FIG. 1 are connected by wiring formed on the surface of the semiconductor substrate 10 shown in FIG. The second electrode 525 is an anode electrode in contact with the second semiconductor region 505 serving as the anode region of the diode. The second electrode 525 shown in FIG. 3 and the anode pad 54 shown in FIG. 1 are connected by a wiring formed on the surface of the semiconductor substrate 10 shown in FIG.

上記のとおり、本実施例では、半導体装置１００は、主活性領域１が形成された半導体基板１０と、半導体基板１０の温度を検知する第１温度検知素子３と、第１温度検知素子３よりも半導体基板１０の深い位置の温度を検知する第２温度検知素子５とを備えている。第１温度検知素子３と第２温度検知素子５によって、半導体基板１０の深さ方向に異なる２つの位置の温度を検知することができ、深さ方向の温度分布を把握することができる。   As described above, in this embodiment, the semiconductor device 100 includes the semiconductor substrate 10 in which the main active region 1 is formed, the first temperature detection element 3 that detects the temperature of the semiconductor substrate 10, and the first temperature detection element 3. And a second temperature detecting element 5 for detecting the temperature at a deep position of the semiconductor substrate 10. The first temperature detection element 3 and the second temperature detection element 5 can detect temperatures at two different positions in the depth direction of the semiconductor substrate 10 and can grasp the temperature distribution in the depth direction.

また、第１温度検知素子３と第２温度検知素子５は、半導体基板１０の表面上の位置が隣接している。すなわち、第１温度検知素子３と第２温度検知素子５は、平面方向に隣接した位置にある。このため、半導体基板１０の平面方向の温度分布による影響が殆ど無い状態で、半導体基板１０の深さ方向の温度分布を検知することができる。   Further, the first temperature detection element 3 and the second temperature detection element 5 are adjacent to each other on the surface of the semiconductor substrate 10. That is, the first temperature detection element 3 and the second temperature detection element 5 are located adjacent to each other in the planar direction. Therefore, the temperature distribution in the depth direction of the semiconductor substrate 10 can be detected in a state where there is almost no influence from the temperature distribution in the planar direction of the semiconductor substrate 10.

また、第１温度検知素子３と第２温度検知素子５は、半導体基板１０を平面視したときの中央部（平面方向の中央部）となる位置に設置されている。半導体基板１０の平面方向の中央部は、端部に比べて半導体基板１０の発熱による温度上昇が発生し易い。このような温度上昇が発生し易い位置に第１温度検知素子３および第２温度検知素子５を設置すれば、検知感度が向上する。   In addition, the first temperature detection element 3 and the second temperature detection element 5 are installed at a position that is a central portion (a central portion in the planar direction) when the semiconductor substrate 10 is viewed in plan. The central portion of the semiconductor substrate 10 in the planar direction is more likely to increase in temperature due to heat generation of the semiconductor substrate 10 than the end portion. If the 1st temperature detection element 3 and the 2nd temperature detection element 5 are installed in the position where such a temperature rise is easy to generate | occur | produce, detection sensitivity will improve.

また、第２温度検知素子５のトレンチ５０１の底部は、主活性領域１のトレンチゲート１３０の底部と同じ深さであるため、製造工程において、主活性領域１のトレンチゲート１３０と第２温度検知素子のトレンチ５０１を同時に形成することができる。半導体装置１００の製造工程を簡素化することが可能である。   In addition, since the bottom of the trench 501 of the second temperature detection element 5 has the same depth as the bottom of the trench gate 130 in the main active region 1, the second temperature detection and the trench gate 130 in the main active region 1 in the manufacturing process. An element trench 501 can be formed simultaneously. The manufacturing process of the semiconductor device 100 can be simplified.

図４は、通常動作時の半導体基板１０の平面方向の中央部における深さ方向の温度分布の一例を概念的に示す図である。図４に示すように、通常動作時には、半導体基板１０の温度は、その表面または裏面から深くなるにしたがって全体的に緩やかに上昇した状態となっている。半導体基板１０の深さ方向においては、ボディ領域１０４とドリフト領域１０３との境界近傍のドリフト領域１０３が最も温度が上昇し、この境界近傍において、深さ方向の温度が最高温度であるＴｍａｘ１となる。 FIG. 4 is a diagram conceptually showing an example of the temperature distribution in the depth direction at the center in the planar direction of the semiconductor substrate 10 during normal operation. As shown in FIG. 4, at the time of normal operation, the temperature of the semiconductor substrate 10 is in a state of gradually rising as a whole from the front surface or the back surface thereof. In the depth direction of the semiconductor substrate 10, the temperature of the drift region 103 in the vicinity of the boundary between the body region 104 and the drift region 103 rises most, and in the vicinity of this boundary, the temperature in the depth direction is T max1 , which is the maximum temperature. Become.

本実施例では、第１温度検知素子３は、半導体基板１０のボディ領域１０４内の温度を検知できる位置に設置されており、第２温度検知素子５は、半導体基板１０のボディ領域１０４とドリフト領域１０３との境界近傍のドリフト領域１０３の温度を検知できる位置に設置されている。半導体装置１００の製造時の検査工程において、半導体基板１０が発熱した場合に、第１温度検知素子３と第２温度検知素子５の検知値を知ることによって、その発熱が発生した位置を推定することができる。   In the present embodiment, the first temperature detection element 3 is installed at a position where the temperature in the body region 104 of the semiconductor substrate 10 can be detected, and the second temperature detection element 5 drifts with the body region 104 of the semiconductor substrate 10. It is installed at a position where the temperature of the drift region 103 in the vicinity of the boundary with the region 103 can be detected. In the inspection process at the time of manufacturing the semiconductor device 100, when the semiconductor substrate 10 generates heat, by knowing the detection values of the first temperature detection element 3 and the second temperature detection element 5, the position where the heat generation has occurred is estimated. be able to.

例えば、第１温度検知素子３が検知する半導体基板１０の表面側の温度が通常よりも高く、第２温度検知素子５が検知する半導体基板１０の内部の温度が通常の状態であれば、半導体基板１０の表面側で異常な発熱が発生していると推定できる。また、第１温度検知素子３が検知する半導体基板１０の表面側の温度が通常の状態であり、第２温度検知素子５が検知する半導体基板１０の内部の温度が高い場合には、半導体基板１０の内部もしくは裏面側で異常な発熱が発生していると推定できる。   For example, if the temperature on the surface side of the semiconductor substrate 10 detected by the first temperature detection element 3 is higher than normal and the temperature inside the semiconductor substrate 10 detected by the second temperature detection element 5 is normal, the semiconductor It can be estimated that abnormal heat is generated on the surface side of the substrate 10. Further, when the temperature on the front surface side of the semiconductor substrate 10 detected by the first temperature detection element 3 is normal and the temperature inside the semiconductor substrate 10 detected by the second temperature detection element 5 is high, the semiconductor substrate It can be estimated that abnormal heat is generated inside 10 or on the back side.

半導体装置１００の製造時の検査工程においても、第１温度検知素子３と第２温度検知素子５の検知値を知ることによって、その発熱が発生した位置を簡易に推定又は把握することができる。そして、この発熱が異常な発熱と認められる場合には、その後に製造される製品の製造工程にフィードバックすることができる。半導体装置１００の製造工程の効率向上、歩留まり向上に寄与することができる。   Also in the inspection process at the time of manufacturing the semiconductor device 100, by knowing the detection values of the first temperature detection element 3 and the second temperature detection element 5, it is possible to easily estimate or grasp the position where the heat generation has occurred. And when this heat generation is recognized as an abnormal heat generation, it can be fed back to the manufacturing process of a product manufactured thereafter. This can contribute to improving the efficiency of the manufacturing process of the semiconductor device 100 and improving the yield.

また、本実施例によれば、半導体装置１００の短絡の発生を簡易に調べることも可能である。図５は、短絡発生時の半導体基板１０の平面方向の中央部における深さ方向の温度分布の一例を概念的に示す図である。短絡発生時は、通常動作時と比較して、半導体基板１０に印加されるエネルギー密度が高い状態となる。このため、図５に示すように、半導体基板１０の深さ方向の温度分布は、局所的に急激な温度上昇が発生する状態となる。半導体基板１０の深さ方向においては、通常運転時と同様にボディ領域１０４とドリフト領域１０３の境界近傍のドリフト領域１０３の温度が最高温度となり、この温度はＴｍａｘ２である。最高温度Ｔｍａｘ２＞最高温度Ｔｍａｘ１であり、最高温度Ｔｍａｘ２となる位置の近傍において急激に温度が上昇する一方、半導体基板１０の表面側近傍、裏面側近傍では、通常動作時と同様の温度分布となる（図４、図５参照）。 Further, according to the present embodiment, it is possible to easily check the occurrence of a short circuit in the semiconductor device 100. FIG. 5 is a diagram conceptually illustrating an example of the temperature distribution in the depth direction at the center in the planar direction of the semiconductor substrate 10 when a short circuit occurs. When a short circuit occurs, the energy density applied to the semiconductor substrate 10 is higher than that during normal operation. For this reason, as shown in FIG. 5, the temperature distribution in the depth direction of the semiconductor substrate 10 is in a state where a sudden rapid temperature rise occurs locally. In the depth direction of the semiconductor substrate 10, the temperature of the drift region 103 in the vicinity of the boundary between the body region 104 and the drift region 103 is the highest temperature as in normal operation, and this temperature is T max2 . The maximum temperature T max2 > the maximum temperature T max1 , and the temperature rises rapidly in the vicinity of the position where the maximum temperature T max2 is reached, while the temperature near the front surface side and the back surface side of the semiconductor substrate 10 is the same as that during normal operation. Distribution (see FIGS. 4 and 5).

本実施例では、通常動作時および短絡発生時に半導体基板１０の深さ方向の最高温度となる位置の温度を検知するために、ボディ領域１０４とドリフト領域１０３との境界近傍のドリフト領域１０３の位置に第２温度検知素子５を設置している。半導体基板１０の深さ方向の最高温度となる位置は、短絡発生時においても、温度上昇が起こり易い位置である。短絡時に温度上昇が起こり易い位置の温度を検知できるため、短絡時の温度上昇の検知感度を向上させることができる。尚、実験又はシミュレーションによって、最高温度となる位置を調べて、その位置に第２温度検知素子５を設置するようにしてもよい。   In the present embodiment, the position of the drift region 103 in the vicinity of the boundary between the body region 104 and the drift region 103 is detected in order to detect the temperature at the maximum temperature in the depth direction of the semiconductor substrate 10 during normal operation and when a short circuit occurs. The second temperature detecting element 5 is installed in the. The position where the maximum temperature in the depth direction of the semiconductor substrate 10 is a position where the temperature rises easily even when a short circuit occurs. Since the temperature at a position where a temperature rise is likely to occur at the time of a short circuit can be detected, the detection sensitivity of the temperature rise at the time of a short circuit can be improved. Note that the position where the maximum temperature is reached may be examined by experiment or simulation, and the second temperature detection element 5 may be installed at that position.

また、本実施例では、第２温度検知素子５よりも半導体基板１０の表面側の浅い位置の温度を検知できるように、第１温度検知素子３を設置している。図６は、図４に示す通常動作時と、図５に示す短絡発生時の第１温度検知素子３と第２温度検知素子５の検知値を概念的に示す図である。図６に示すように、通常動作時と比較して、短絡発生時には、第１温度検知素子３の検知値Ｔ１と第２温度検知素子５の検知値Ｔ２との差が大きくなる。このため、検知値Ｔ１と検知値Ｔ２との差を調べることによって、半導体装置１００の短絡発生を検知することができる。   In the present embodiment, the first temperature detection element 3 is installed so that the temperature at a shallower position on the surface side of the semiconductor substrate 10 than the second temperature detection element 5 can be detected. 6 is a diagram conceptually showing detection values of the first temperature detection element 3 and the second temperature detection element 5 at the time of normal operation shown in FIG. 4 and at the time of occurrence of a short circuit shown in FIG. As shown in FIG. 6, the difference between the detection value T1 of the first temperature detection element 3 and the detection value T2 of the second temperature detection element 5 is larger when a short circuit occurs than in the normal operation. Therefore, the occurrence of a short circuit in the semiconductor device 100 can be detected by examining the difference between the detection value T1 and the detection value T2.

従来、半導体装置には、温度検知素子とは別に、半導体装置の短絡を検知するための電流検知素子が設置されていた。本実施例の温度検知素子によれば、半導体装置の短絡を検知することもできるため、短絡を検知するために電流検知素子を設置する必要がなくなる。その結果、半導体装置の構造の簡素化、製造工程の簡素化に寄与することができる。   Conventionally, in a semiconductor device, a current detection element for detecting a short circuit of the semiconductor device has been installed separately from the temperature detection element. According to the temperature detection element of the present embodiment, it is possible to detect a short circuit of the semiconductor device, so that it is not necessary to install a current detection element to detect the short circuit. As a result, the structure of the semiconductor device can be simplified and the manufacturing process can be simplified.

上記のとおり、本実施例によれば、半導体基板の内部で発熱が発生した場合に、この発熱を検知し易くなる。また、半導体基板の深さ方向の温度分布を検知することができるため、深さ方向の温度分布に基づいて、半導体基板において発熱している位置を推定することができる。断面観察等を行うことなく、発熱している位置を推定できるため、製造時の検査工程において発熱している位置を簡易に検知し、その後に製造される製品の製造工程にフィードバックすることが可能である。   As described above, according to the present embodiment, when heat is generated inside the semiconductor substrate, it becomes easy to detect this heat. Further, since the temperature distribution in the depth direction of the semiconductor substrate can be detected, the position where heat is generated in the semiconductor substrate can be estimated based on the temperature distribution in the depth direction. Since the position where heat is generated can be estimated without performing cross-sectional observation, etc., it is possible to easily detect the position where heat is generated in the inspection process during manufacturing, and to feed back to the manufacturing process of the product to be manufactured thereafter It is.

尚、半導体装置に複数組の第１温度検知素子と第２温度検知素子が設けられていてもよい。例えば、図７に示すように、図１に示した一組の第１温度検知素子３と第２温度検知素子５以外に、一組の第１温度検知素子３ａと第２温度検知素子５ａ、一組の第１温度検知素子３ｂと第２温度検知素子５ｂが設けられていても良い。図７において、第１温度検知素子３、３ａ、３ｂは半導体基板の浅い位置の温度を検知し、第２温度検知素子５、５ａ，５ｂは、は半導体基板の深い位置の温度を検知する。第１電極３２、５２、３２ａ、５２ａ、３２ｂ、５２ｂはカソードパッドであり、第２電極３４、５４、３４ａ、５４ａ、３４ｂ、５４ｂはアノードパッドである。   Note that a plurality of sets of first temperature detection elements and second temperature detection elements may be provided in the semiconductor device. For example, as shown in FIG. 7, in addition to the set of first temperature detection element 3 and second temperature detection element 5 shown in FIG. 1, a set of first temperature detection element 3a and second temperature detection element 5a, A set of first temperature detection element 3b and second temperature detection element 5b may be provided. In FIG. 7, the first temperature detection elements 3, 3a, 3b detect the temperature at a shallow position of the semiconductor substrate, and the second temperature detection elements 5, 5a, 5b detect the temperature at a deep position of the semiconductor substrate. The first electrodes 32, 52, 32a, 52a, 32b, and 52b are cathode pads, and the second electrodes 34, 54, 34a, 54a, 34b, and 54b are anode pads.

また、一組の第１温度検知素子３と第２温度検知素子５は、半導体基板の平面方向の中央部以外に設置することもできる。この場合は、半導体基板の平面方向の温度分布が同じとなる位置に一組の第１温度検知素子３と第２温度検知素子５とを設置することが好ましい。例えば、図８に示すように、半導体基板の表面上の温度分布が中央部を中心とする楕円形状の等温線によって表される場合、同一の等温線（例えば等温線８）上に一組の第１温度検知素子３と第２温度検知素子５を設置することが好ましい。半導体基板１０の表面の等温度領域に一組の第１温度検知素子３と第２温度検知素子５を設置することによって、平面方向の温度分布による影響を小さくした状態で、半導体基板１０の深さ方向の温度分布を検知することができる。   Further, the pair of the first temperature detection element 3 and the second temperature detection element 5 can be installed in a region other than the central portion in the planar direction of the semiconductor substrate. In this case, it is preferable to install a pair of first temperature detection element 3 and second temperature detection element 5 at a position where the temperature distribution in the planar direction of the semiconductor substrate is the same. For example, as shown in FIG. 8, when the temperature distribution on the surface of the semiconductor substrate is represented by an elliptical isotherm centered on the center, a set of the same isotherm (for example, isotherm 8). It is preferable to install the first temperature detection element 3 and the second temperature detection element 5. By installing a pair of the first temperature detecting element 3 and the second temperature detecting element 5 in the isothermal region on the surface of the semiconductor substrate 10, the influence of the temperature distribution in the planar direction is reduced, and the depth of the semiconductor substrate 10 is increased. The temperature distribution in the vertical direction can be detected.

また、図９に示すように、第１温度検知素子３が、主活性領域１に囲まれた状態で深いＰ＋層６１の内部に設けられていてもよいし、図１０に示すように、第１温度検知素子３が半導体基板１０の周辺耐圧構造（ＦＬＲ）としての深いＰ＋層６３の内部に形成されていてもよい。また、図１１に示すように、第１温度検知素子９３のトレンチの深さが主活性領域１のトレンチゲート１３０と同じ深さで、第２温度検知素子９５のトレンチの深さが主活性領域１のトレンチゲート１３０よりも深い位置まで形成されていてもよい。さらに、第２温度検知素子９５が、第２温度検知素子９５よりもさらに深いＰ＋層６５の内部に形成されていてもよい。温度検知素子を深いＰ＋層の内部に設置することによって、半導体装置の耐圧低下を抑制することができる。 Further, as shown in FIG. 9, the first temperature sensing element 3 may be provided inside the deep P + layer 61 in a state surrounded by the main active region 1, or as shown in FIG. The first temperature detection element 3 may be formed inside a deep P + layer 63 as a peripheral breakdown voltage structure (FLR) of the semiconductor substrate 10. Further, as shown in FIG. 11, the trench depth of the first temperature sensing element 93 is the same depth as the trench gate 130 of the main active region 1, and the trench depth of the second temperature sensing element 95 is the main active region. It may be formed to a position deeper than one trench gate 130. Further, the second temperature detection element 95 may be formed inside the P + layer 65 that is deeper than the second temperature detection element 95. By installing the temperature detection element inside the deep P + layer, it is possible to suppress a decrease in the breakdown voltage of the semiconductor device.

また、温度検知素子は、上記の実施例１で説明したトレンチ型の温度検知素子でなくともよい。例えば、図１２に示すように、半導体基板１０の表面上に絶縁膜４７を設け、さらにその表面上に第１温度検知素子７を設置してもよい。また、図１３に示すように、深いＰ＋層６１の表面に第１温度検知素子７を設置してもよい。温度検知素子を半導体基板の表面に設ける場合、温度検知素子の設置位置は半導体装置の耐圧低下に影響しない。 Further, the temperature detecting element may not be the trench type temperature detecting element described in the first embodiment. For example, as shown in FIG. 12, an insulating film 47 may be provided on the surface of the semiconductor substrate 10, and the first temperature detection element 7 may be further provided on the surface. Further, as shown in FIG. 13, the first temperature detection element 7 may be installed on the surface of the deep P + layer 61. When the temperature detection element is provided on the surface of the semiconductor substrate, the installation position of the temperature detection element does not affect the decrease in the breakdown voltage of the semiconductor device.

さらには、上述した各実施例では、半導体基板の深さが異なる２つの位置に温度検知素子を配置した例であったが、半導体基板の深さが異なる３つの位置又は３以上の位置に温度検知素子を配置するようにしてもよい。このように多段階に温度検知素子を配置することで、半導体基板の深さ方向の温度分布を精度よく推定することができる。   Further, in each of the above-described embodiments, the temperature detecting elements are arranged at two positions where the depth of the semiconductor substrate is different. However, the temperature is detected at three positions or three or more positions where the depth of the semiconductor substrate is different. You may make it arrange | position a detection element. By arranging the temperature detection elements in multiple stages in this way, the temperature distribution in the depth direction of the semiconductor substrate can be accurately estimated.

トレンチ型の温度検知素子のトレンチ底部の構成は、図３に示す構成に限定されない。例えば、図１４に示すように、Ｎ型の第１半導体領域５０３とＰ型の第２半導体領域５０５が隣接しており、同じ高さに形成されていてもよい。また、図１５、図１６に示すように、２組以上のダイオードが接続されていてもよい。図１５、図１６においては、第１電極５２３と接続するＮ型の第１半導体領域５０３は、Ｐ型の第４半導体領域５１５と第１のＰＮ接合を形成しており、第２電極５２５と接続するＰ型の第２半導体領域５０５は、Ｎ型の第３半導体領域５１３と第２のＰＮ接合を形成している。第３半導体領域５１５と第４半導体領域５１３は、第３電極５２７によって接続されている。絶縁膜５０７ａ、５０７ｂは、第１電極５２３、第２電極５２５、第３電極５２７を互いに隔離している。絶縁膜５５７は、第１のＰＮ接合と第２のＰＮ接合とを隔離している。これによって、第１のＰＮ接合による第１のダイオードと、第２のＰＮ接合による第２のダイオードとが第３電極５２７によって直列に接続された状態となる。   The configuration of the trench bottom of the trench-type temperature detection element is not limited to the configuration shown in FIG. For example, as shown in FIG. 14, the N-type first semiconductor region 503 and the P-type second semiconductor region 505 may be adjacent to each other and formed at the same height. Further, as shown in FIGS. 15 and 16, two or more sets of diodes may be connected. 15 and 16, the N-type first semiconductor region 503 connected to the first electrode 523 forms a first PN junction with the P-type fourth semiconductor region 515, and the second electrode 525 The P-type second semiconductor region 505 to be connected forms a second PN junction with the N-type third semiconductor region 513. The third semiconductor region 515 and the fourth semiconductor region 513 are connected by a third electrode 527. The insulating films 507a and 507b isolate the first electrode 523, the second electrode 525, and the third electrode 527 from each other. The insulating film 557 isolates the first PN junction and the second PN junction. As a result, the first diode by the first PN junction and the second diode by the second PN junction are connected in series by the third electrode 527.

以上、本発明の実施例について詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。   As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.

本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。   The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

１ 主活性領域
２ 温度検知領域
３、３ａ、３ｂ、７、９３ 第１温度検知素子
５、５ａ、５ｂ、９５ 第２温度検知素子
８ 等温線
１０ 半導体基板
３２、３２ａ、３２ｂ、５２、５２ａ、５２ｂ カソードパッド
３４、３４ａ、３４ｂ、５４、５４ａ、５４ｂ アノードパッド
４１、４３、４５、４７ 絶縁膜
６１、６３、６５ Ｐ＋層
１００ 半導体装置
１０１ コレクタ領域
１０２ バッファ領域
１０３ ドリフト領域
１０４ ボディ領域
１０５ エミッタ領域
１０６ ボディコンタクト領域
１３０ トレンチゲート
３０１、５０１ トレンチ
３０３、５０３ 第１半導体領域
３０５、５０５ 第２半導体領域
５０７、５０７ａ、５０７ｂ、５５７ 絶縁体
５１３ 第４半導体領域
５１５ 第３半導体領域
５２３ 第１電極
５２５ 第２電極
５２７ 第３電極 DESCRIPTION OF SYMBOLS 1 Main active area 2 Temperature detection area 3, 3a, 3b, 7, 93 1st temperature detection element 5, 5a, 5b, 95 2nd temperature detection element 8 Isotherm 10 Semiconductor substrate 32, 32a, 32b, 52, 52a, 52b Cathode pads 34, 34a, 34b, 54, 54a, 54b Anode pads 41, 43, 45, 47 Insulating films 61, 63, 65 P + layer 100 Semiconductor device 101 Collector region 102 Buffer region 103 Drift region 104 Body region 105 Emitter Region 106 body contact region 130 trench gate 301, 501 trench 303, 503 first semiconductor region 305, 505 second semiconductor region 507, 507a, 507b, 557 insulator 513 fourth semiconductor region 515 third semiconductor region 523 first electrode 525 Second electrode 527 Third electrode

Claims (4)

主活性領域が形成された半導体基板と、
半導体基板の温度を検知する第１温度検知素子と、
第１温度検知素子よりも半導体基板の深い位置の温度を検知する第２温度検知素子とを備え、
第１温度検知素子と第２温度検知素子は、半導体基板の表面の等温度領域に設けられていることを特徴とする半導体装置。 A semiconductor substrate on which a main active region is formed;
A first temperature sensing element for sensing the temperature of the semiconductor substrate;
A second temperature detection element that detects a temperature at a position deeper in the semiconductor substrate than the first temperature detection element ;
First temperature sensing element and the second temperature sensing element is a semiconductor device which is characterized that you have provided an isothermal region of the semiconductor substrate surface. 第１温度検知素子と第２温度検知素子は、半導体基板の平面方向の位置が隣接していることを特徴とする請求項１に記載の半導体装置。 First temperature sensing element and the second temperature sensing element, the semiconductor device according to claim 1, wherein the planar direction of the position of the semiconductor substrate is adjacent. 第１温度検知素子と第２温度検知素子は、半導体基板の平面方向の中央部となる位置に設置されていることを特徴とする請求項１または２に記載の半導体装置。 3. The semiconductor device according to claim 1, wherein the first temperature detection element and the second temperature detection element are installed at a position that is a central portion in a planar direction of the semiconductor substrate. 第２温度検知素子は、
半導体基板の表面から内部に向けて形成されており、その内壁面に絶縁膜が形成されているトレンチと、
トレンチ内の底部に形成された第１導電型の第１半導体領域と、
トレンチ内の底部に形成され、第１半導体領域と接する第２導電型の第２半導体領域と、
第１半導体領域に接し、第２半導体領域に接しない第１電極と、
第２半導体領域に接し、第１半導体領域に接しない第２電極と、
第１電極と第２電極とを隔離する絶縁体と、
を備えることを特徴とする請求項１〜３のいずれか一項に記載の半導体装置。
The second temperature sensing element is
A trench that is formed from the surface of the semiconductor substrate toward the inside, and an insulating film is formed on the inner wall surface thereof;
A first semiconductor region of a first conductivity type formed at the bottom of the trench;
A second semiconductor region of a second conductivity type formed at the bottom of the trench and in contact with the first semiconductor region;
A first electrode in contact with the first semiconductor region and not in contact with the second semiconductor region;
A second electrode in contact with the second semiconductor region and not in contact with the first semiconductor region;
An insulator separating the first electrode and the second electrode;
The semiconductor device according to any one of claims 1 to 3, characterized in that it comprises.
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