JP5672068B2 - Noise estimation method and noise estimation device - Google Patents

Description

  The present invention relates to estimating noise of a circuit block mounted on an LSI.

  In recent years, in LSI (Large Scale Integration) development, so-called analog circuits such as AD (Analog to Digital) converters, DA (Digital to Analog) converters, and RF (Radio Frequency) circuits, and digital circuits are integrated on one chip. Mixed signal SOC (System On Chip) has been developed.

  In a mixed signal SOC, an analog circuit (Victim) that operates with a smaller amplitude than a digital circuit is less resistant to noise, and is susceptible to the noise that is generated in the digital circuit (Aggressor) and propagates through the silicon substrate. Therefore, the magnitude of the received noise is analyzed by simulation.

  For example, the amount of noise is estimated by extracting the contact closest to the analog circuit (Victim) affected by noise from the layout data and creating a power supply noise analysis model that excludes other contacts from the calculation target and performing simulation. In addition, in order to speed up power supply noise analysis, it has been proposed to model a power supply wiring layer using layout data.

JP 2008-108783 A JP 2008-112233 A

  The above-described prior art reduces the processing load of power supply noise analysis using layout data including information related to the placement and routing of each element, and the relationship between the digital circuit (Aggressor) and the analog circuit (Victim) is One-to-one is assumed. In other words, the noise propagation path only has to be a path through the silicon substrate between the digital circuit (Aggressor) and the analog circuit (Victim).

  When only one pair of digital circuit (Aggressor) and analog circuit (Victim) are integrated on one chip, it is possible to estimate the amount of noise with high accuracy even with the above-described conventional technology. However, in recent SOCs, a plurality of power supply separated circuits are integrated on one chip. In that case, in addition to the above, the noise propagation path has a plurality of digital circuits and a plurality of paths that are propagated via the silicon substrate between the Aggressor and Victim because the power supply region is normally separated. Must be considered.

  For example, the above conventional technology based on a pair of a digital circuit (Aggressor) and an analog circuit (Victim) cannot cope with such a recent SOC configuration, and therefore the noise propagation amount is estimated to be smaller than the original. There was a problem that it was lost.

  Furthermore, it is desirable that the amount of noise in the analog circuit (Victim) can be predicted in the initial design stage from the placement and routing stage of each element. However, since the layout data cannot be used in the initial design stage, the above-described multiple noise propagations are possible. The route and the amount of noise caused by these routes could not be estimated effectively.

The disclosed technique is a noise estimation method executed by a computer, and the computer is configured to include a plurality of circuits arranged in the LSI based on process parameters relating to electrical characteristics of the LSI substrate stored in the storage area. a calculation procedure for calculating the substrate resistance between the blocks, the calculated and generation procedure that generates an equivalent circuit of the substrate of the LSI having a substrate resistance was, the plurality of circuit blocks respectively in the equivalent circuit of the substrate generated the LSI And a circuit simulation procedure for estimating noise for each circuit block based on the simulation result of the circuit to which the time-dependent current consumption data is added.

  In the disclosed technique, an in-chip netlist is generated using an equivalent circuit having substrate resistance between a plurality of circuit blocks. Therefore, power supply wiring of a neighboring circuit block in an LSI mounting a plurality of circuit blocks is obtained by circuit simulation. It is possible to accurately estimate the noise that propagates via.

It is a figure for demonstrating the principle of a present Example. It is a figure which shows the example which represented the noise which propagates via a circuit with an equivalent circuit. It is a figure which shows the hardware constitutions of a noise estimation apparatus. It is a figure which shows the function structural example which concerns on a present Example. It is a figure which shows an example of floor plan data. It is a figure which shows an example of the consumption current data for every module. It is a figure which shows an example of a PKG net list. It is a figure for demonstrating the process in a net list production | generation part in a chip | tip. It is a figure for demonstrating the process in a whole net list production | generation part. It is a figure which shows an example of the analysis model which concerns on a present Example. It is a figure which shows an example of the noise distribution by the circuit simulation using the analysis model illustrated in FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the present embodiment, in an SOC in which a plurality of digital circuits and at least one analog circuit are integrated on one chip at an initial design stage where information relating to arrangement and wiring of elements in the module is not obtained, a noise source The noise amount can be estimated in consideration of a plurality of noise propagation paths from the digital circuit (Aggressor) to the analog circuit (Victim) that receives noise.

  FIG. 1 is a diagram for explaining the principle of this embodiment. In FIG. 1, the LSI 5 includes a circuit (Aggressor) 1, a circuit (Victim) 2, a circuit 10, and a circuit 11. Circuits 1, 10, and 11 are digital circuits, and circuit 2 is an analog circuit. In this embodiment, in the same figure, the circuit 1 is described as an Aggressor that is a noise source, and the circuit 2 is described as Victim that receives noise from the noise source.

  In this embodiment, first, the impedance of a silicon substrate (hereinafter simply referred to as a substrate) is obtained from the circuit (Aggressor) 1 to all the other circuits 2, 10 and 11. Substrate resistance 3 between circuit (Aggressor) 1 and circuit (Victim) 2, substrate resistance 20 between circuit (Aggressor) 1 and circuit 10, and substrate resistance 21 between circuit (Aggressor) 1 and circuit 11 calculate.

  Second, the impedance of the silicon substrate is obtained from the circuit (Victim) 2 for all the other circuits 1, 10 and 11. Substrate resistance 3 between circuit (Victim) 2 and circuit (Aggressor) 1, substrate resistance 22 between circuit (Victim) 2 and circuit 10, and substrate resistance 23 between circuit (Victim) 2 and circuit 11 calculate.

  Each substrate resistance is obtained by calculating all the rectangular areas obtained by dividing the mesh between the circuits using the following calculation formula (1) using process parameters prepared in advance (see Patent Document 1). .

ρ × X / Y · Z (1)
ρ is low efficiency, X is the length in the row direction that defines the mesh size, Y is the length in the column direction that defines the mesh size, and Z is the effective depth related to noise propagation from the surface of the silicon substrate .

Third, the resistance value in each of the circuits 10 and 11 on the noise propagation path from the circuit (Aggressor) 1 to the circuit (Victim) 2 is set to zero, and an equivalent circuit is assembled. The noise propagation path in the configuration of the LSI 5 shown in FIG. 1 includes three paths K1, K2, and K3.

  The path K1 is a path that propagates from the circuit (Aggressor) 1 to the circuit (Victim) 2 through the substrate. The path K3 is a path that propagates from the circuit (Aggressor) 1 through the substrate 12 to the circuit 12 and further propagates through the substrate to the circuit (Victim) 2. The path K3 is a path that propagates from the circuit (Aggressor) 1 through the board 11 to the circuit 11 and further through the board to the circuit (Victim) 2. The resistance values of the circuit 10 in the path K2 and the circuit 11 in the path K3 are set to zero, and an equivalent circuit is assembled.

  Fourth, the amount of noise propagated is estimated by simulating the created equivalent circuit.

  The impedance of noise that propagates through the power supply wiring in the circuit in the paths K2 and K3 described above will be described with reference to FIG. FIG. 2 is a diagram illustrating an example in which noise propagating through a circuit is represented by an equivalent circuit.

  In the propagation of noise from the circuit (Aggressor) 1 to the circuit 10 in the path K2, the circuit resistance 20 may be calculated because the circuit (Aggressor) 1 and the circuit 10 are separated from each other. Similarly, the substrate resistance 22 may be calculated for noise propagation from the circuit 10 to the circuit (Victim) 2.

  Next, the propagation (from the top to the bottom in the figure) from the circuit (Aggressor) 1 side in the circuit 10 to the circuit (Victim) 2 side will be considered. In this case, there are two propagation paths. A path that travels through the power supply wiring in the circuit 10 and a path that travels through the substrate directly below the circuit 10. Generally, since the impedance of the power supply wiring is two digits or more smaller than the substrate, the impedance of the power supply wiring becomes the dominant factor. However, it is known that the impedance of the power supply wiring is generally about two orders of magnitude smaller than the substrate resistances 20 and 22 described above and is a negligible value. Therefore, the in-circuit resistance 25a can be set to 0Ω.

  The noise that passes through the circuit 11 can be similarly calculated. That is, the in-circuit resistance 25b of the circuit 11 may be 0Ω.

  Therefore, originally, an equivalent circuit (FIG. 2) corresponding to the substrate resistors 3, 20, 21, 22, and 23 and the in-circuit resistors 25a and 25b is created and simulated. Then, only an equivalent circuit (FIG. 1) corresponding to the substrate resistors 3, 20, 21, 22, and 23 is created and simulation is performed.

  The noise estimation apparatus for estimating the noise propagating through the silicon substrate as described above has a hardware configuration as shown in FIG. FIG. 3 is a diagram illustrating a hardware configuration of the noise estimation device.

  In FIG. 3, a noise estimation device 100 is a device controlled by a computer, and is a device or the like on which CAD (Computer Aided Design) is mounted. The noise estimation device 100 includes a CPU (Central Processing Unit) 11, a memory unit 12, a display unit 13, an output unit 14, an input unit 15, a communication unit 16, a storage device 17, and a driver 18. And connected to the system bus B.

  The CPU 11 controls the noise estimation device 100 according to a program stored in the memory unit 12. The memory unit 12 uses a RAM (Random Access Memory), a ROM (Read-Only Memory), or the like, and is obtained by a program executed by the CPU 11, data necessary for processing by the CPU 11, and processing by the CPU 11. Stored data. A part of the memory unit 12 is allocated as a work area used for processing by the CPU 11.

  The display unit 13 displays various information required under the control of the CPU 11. The output unit 14 has a printer or the like, and is used for outputting various types of information in accordance with instructions from the user. The input unit 15 includes a mouse, a keyboard, and the like, and is used by a user to input various information necessary for the noise estimation apparatus 100 to perform processing. The communication unit 16 is a device that is connected to, for example, the Internet, a LAN (Local Area Network), and the like and controls communication with an external device. For example, a hard disk unit is used as the storage device 17 and stores data such as programs for executing various processes.

  A program for realizing the processing performed by the noise estimation apparatus 100 is provided to the noise estimation apparatus 100 by a storage medium 19 such as a CD-ROM (Compact Disc Read-Only Memory). That is, when the storage medium 19 storing the program is set in the driver 18, the driver 18 reads the program from the storage medium 19, and the read program is installed in the storage device 17 via the system bus B. . When the program is activated, the CPU 11 starts its processing according to the program installed in the storage device 17. The medium for storing the program is not limited to a CD-ROM, and any medium that can be read by a computer may be used. As a computer-readable storage medium, in addition to a CD-ROM, a portable recording medium such as a DVD disk or a USB memory, or a semiconductor memory such as a flash memory may be used.

  In addition, a program that realizes processing performed by the noise estimation device 100 may be provided from an external device via the communication unit 16.

  FIG. 4 is a diagram illustrating a functional configuration example according to the present embodiment. In FIG. 4, the noise estimation apparatus 100 includes, as processing units, a floor plan creation unit 31, an in-chip netlist generation unit 32, an overall netlist generation unit 33, a circuit simulation unit 34, and a noise distribution display unit 35. Have Each processing unit 31 to 35 is realized by the CPU 11 being a processor executing a corresponding program.

  Further, the noise estimation apparatus 100 includes floor plan data 41, edge information 42, representative node name assignment information 42-2, processed edge information 43, an in-chip netlist 44, and current consumption data 45 per module. The PKG net list 46, the entire net list 47, and the process parameter 49 are stored in the memory unit 12 or the storage area 40 of the storage device 17.

  The floor plan creation unit 31 is a processing unit that supports the layout of the modules mounted on the LSI by the user. The floor plan data 41 created by the floor plan creation unit 31 is stored in the storage area 40. The module is a functional unit circuit block such as the circuits 1, 2, 10 and 11 shown in FIGS.

  The floor plan data 41 includes the outline of each module arranged in the LSI, the arrangement information indicating the arrangement position of the module, and the position information of the power supply GND terminal. The floor plan data 41 may be data created in advance.

  The in-chip netlist generation unit 32 refers to the floor plan data 41 created by the floor plan creation unit 31 or previously created and stored, and generates impedance coupling between the modules in the chip and is equivalent. This is a processing unit that creates an in-chip netlist 44 represented by a circuit. The on-chip netlist 44 is output to the storage area 40. The edge information 42, the representative node name allocation information 42-2, and the processed edge information 43 are information that is temporarily generated in the course of processing by the in-chip netlist generation unit 32 and stored in the storage area 40, which will be described later. The processing flow will be described.

  The in-chip netlist generation unit 32 is a processing unit for obtaining the substrate resistances 20 to 23 as shown in FIG. However, Aggressor and Victim cannot be comprehensively recognized with only the floor plan data 41 information. Therefore, in this embodiment, all substrate impedances between adjacent modules are calculated using the process parameter 49 without distinguishing between Aggressor and Victim.

  The process parameter 49 has a parameter for representing an electrical characteristic in a rectangular area obtained by dividing the LSI substrate into meshes, and is used in the above formula (1) as a parameter for calculating the substrate resistance. Parameters such as a length X in the row direction that defines the mesh size, a length Y in the column direction that defines the mesh size, and an effective depth Z related to noise propagation from the surface of the silicon substrate are included.

  As described above, the impedance of the power supply wiring (the circuit resistors 25a and 25b in FIGS. 1 and 2) in each module (the circuits 10 and 11 in FIGS. 1 and 2) is a negligible value. Therefore, in this embodiment, the calculation process is unnecessary. Therefore, it is possible to simply calculate the impedance in the LSI necessary for noise estimation.

  The entire net list generation unit 33 is a processing unit that connects the module current consumption data 45 and the PKG (package) net list 37 to the in-chip net list 44. The entire net list 47 in which the module current consumption data 45 and the PKG (package) net list 37 are connected to the in-chip net list 44 is output to the storage area 40.

  The module-based current consumption data 45 includes time-dependent current consumption data for each module, and is data indicating an operation waveform, a frequency characteristic, and the like for each module created using SPICE (Simulation Program with Integrated Circuit Emphasis).

  The PKG netlist 37 includes chip level connection information. The connection destination of the LSI package unit is originally the position of the power supply GND generated by the floor plan creation unit 31, but in this embodiment, the connection is made to the representative node of the module closest to the position of the power supply GND.

  The circuit simulation unit 34 executes circuit simulation using the entire netlist 47.

  The noise distribution display unit 35 displays the result of the circuit simulation by the circuit simulation unit 34 on the display unit 13. The noise distribution display unit 35 may display the peak value of the noise amount for each module. Or a general equivoltage line display etc. may be sufficient.

  Data examples referred to in the noise estimation process according to the present embodiment will be described with reference to FIGS. 5, 6, and 7.

  FIG. 5 is a diagram illustrating an example of floor plan data. The floor plan data 41 includes library data 41a and chip data 41b. The library data 41a is stored in a data file such as LEF (Library Exchange Format), for example. The chip data 41b is stored in a data file such as DEF (Design Exchange Format).

  An example of the library data 41a is shown in FIG. The library data 41a mainly includes information such as a module name, a module size, and a pin name attached to the module for each module including an IO arranged in the LSI.

  In the library data 41a shown in FIG. 5A, for example, regarding the module name “module_name1”, the module size is indicated by (size_x1, size_y1), and the attached pin name is indicated by “pin_name1”. . The same applies to other module names “module_name2” and “IO_name1”.

  An example of the chip data 41b is shown in FIG. The chip data 41b mainly includes information such as a chip name, a chip size, a module name arranged on the chip, an instance name corresponding to the module, an arrangement coordinate of the instance, and a net name of the instance.

  In the chip data 41b shown in FIG. 5B, for example, regarding the chip name “Chip_name”, the chip size is indicated by (chipsize_x, chipsize_y), and one or more instances are defined. Each instance has information such as an instance name, a module name arranged on a chip represented by the instance, an arrangement coordinate of the instance, and a net name of the instance.

  Regarding the instance name “Inst_name1”, the module name is “module_name1”, and the arrangement coordinates are (pos_x1, pos_y1). The same applies to the instance name “Inst_name2”. Regarding the instance name “Inst_IO_name1”, the module name is “IO_name1”, the arrangement coordinates are (pos_x3, pos_y3), and the net name is “net_name3”.

  FIG. 6 is a diagram illustrating an example of current consumption data for each module. The module-based current consumption data 45 illustrated in FIG. 6 is associated with current data represented by a set of time and current value vectors for each module. For example, regarding the module name “Module_name1”, (t0, i10) , (t1, i11), (t2, i12),... (tn, i1n), etc., the waveform is represented by a vector of time t and current value i. The same applies to other modules.

  FIG. 7 is a diagram illustrating an example of the PKG netlist. The PKG netlist 46 illustrated in FIG. 7 shows connection information for each element. For example, regarding the inductance “L01”, the value is “1 nH”, which indicates that it is connected to the ground GND1 and the node 0. ing. The same applies to other elements.

  Next, processing in the in-chip net list generation unit 32 will be described with reference to FIG. 8, and processing in the entire net list generation unit 33 will be described with reference to FIG.

  FIG. 8 is a diagram for explaining processing in the in-chip netlist generation unit. The processes in steps S71 to S85 shown in FIG. 8 are processes executed by the CPU 11 as the in-chip netlist generation unit 32.

  In FIG. 8, the intra-chip netlist generation unit 32 reads one instance name from the chip data 41a, and obtains the module name associated with the instance name and the arrangement coordinates of the instance (step S71).

  The in-chip netlist generation unit 32 acquires the module size and pin name specified from the module name from the library data 41a using the module name acquired in step S71 (step S72).

  Then, the in-chip netlist generation unit 32 uses the information obtained from the processing of steps S71 and S72, assumes that the module shape is a rectangle, and on the chip of four lines serving as module sides (module edges). The edge information 42 including the coordinates of each edge calculated together with the module name is stored in the storage area 40 (step S73). Hereinafter, the coordinates of the edge are simply referred to as an edge.

  The intra-chip netlist generation unit 32 determines whether or not processing has been completed for all modules indicated by the chip data 41b (step S74). If the processing has not been completed for all the modules, the in-chip netlist generation unit 32 returns to step S71 and repeats the same processing as described above for the next module.

  In step S74, when the processing is completed for all modules, the in-chip netlist generation unit 32 acquires the chip size from the chip data 41b, calculates the coordinates of the four line segments of the chip side, and the edge information 42. The chip name and the calculated coordinates are added to (Step S75).

  Then, the intra-chip netlist generation unit 32 reads all the instance names from the chip data 41b, and arbitrarily assigns a representative node name corresponding to the module name associated with each instance (step S76). Only in the case of IO, the in-chip net list generation unit 32 assigns a net name indicated in the chip data 41b. Representative node name assignment information 42-2 in which the module name is associated with the representative node name or net name is stored in the storage area 40.

  Next, the intra-chip netlist generation unit 32 reads one instance name from the chip data 41b (step S77), and selects one edge corresponding to the instance name from the edge information 42 (step S78).

  The distances from all edges belonging to other instances are calculated from the edge information 42, and the nearest edge is searched (step S79). The edge having the shortest value among the distance values to all edges is acquired as the closest edge. The closest edge is specified by the instance name and the coordinates of the edge.

  The intra-chip netlist generation unit 32 determines whether or not the acquired closest edge is an edge associated with the chip name (step S80). What is necessary is just to judge whether the instance name of the nearest edge corresponds with the chip name of the chip data 41b. If the closest edge is an edge associated with the chip name, the intra-chip netlist generation unit 32 returns to Step S78 and repeats the same processing as described above from the coordinates of the next edge corresponding to the instance name.

  On the other hand, if it is determined in step S80 that the closest edge is not an edge associated with the chip name, the intra-chip netlist generation unit 32 further determines whether or not the closest edge is included in the processed edge information 43. Is determined (step S81). If the closest edge is included in the processed edge information 43, the in-chip netlist generation unit 32 returns to Step S78 and repeats the same processing as described above from the coordinates of the next edge corresponding to the instance name.

  On the other hand, if it is determined in step S81 that the closest edge is not included in the processed edge information 43, the intra-chip netlist generation unit 32 associates the edge selected in step S78 with the closest edge. The processed edge information 43 is stored in the storage area 40 (step S82).

  Next, the intra-chip netlist generation unit 32 generates an equivalent circuit between the edge selected in step S78 and its closest edge, and the connection information relating to the generated equivalent circuit is stored in the intra-chip netlist 44 in the storage area 40. (Step S83). The in-chip netlist generation unit 32 calculates the substrate resistance of the rectangular area corresponding to the mesh division using the above-described calculation formula (1), and according to the distance between the edge selected in step S78 and its nearest edge. Determine the substrate resistance. The equivalent circuit is generated as a resistance element having the substrate resistance.

  The intra-chip netlist generation unit 32 refers to the representative node name assignment information 42-2 to acquire each representative node name from the instance name of the edge selected in step S78 and the instance name of the nearest edge. The connection information is created and added to the in-chip netlist 44 and stored.

  Then, the intra-chip netlist generation unit 32 determines whether or not all edges of the selected instance have been processed (step S84). If all the edges of the selected instance have not been processed, the intra-chip netlist generation unit 32 returns to step S78 and performs the same processing as described above for the next edge.

  On the other hand, if it is determined in step S84 that all edges of the selected instance have been processed, the intra-chip netlist generation unit 32 further determines whether or not the processing of all modules has been completed (step S85). If the processing of all modules has not been completed, the in-chip netlist generation unit 32 returns to step S77 and performs the same processing as described above for the next module.

  On the other hand, when the processing of all the modules is completed in step S85, the CPU 11 ends the processing in the in-chip netlist generation unit 32 and performs the processing by the entire netlist generation unit 33. Therefore, the process proceeds to step S91 in FIG. move on.

  FIG. 9 is a diagram for explaining processing in the entire netlist generation unit. The processes in steps S91 to S94 shown in FIG. 9 are processes executed by the CPU 11 as the entire netlist generation unit 33.

  In FIG. 9, the entire netlist generation unit 33 reads current data represented by a set of time and current value vectors corresponding to the module name from the module current consumption data 45 (step S91).

  The entire netlist generation unit 33 adds connection node information indicating the representative node and the 0 node as connection destinations to the current data read in step S91, and adds the connection destination node information to the in-chip netlist 44 (step S92). . The overall netlist generation unit 33 acquires a representative node from the representative node name assignment information 42-2 using a module name corresponding to the instance name.

  Then, the overall netlist generation unit 33 determines whether or not the processing of all modules has been completed (step S93). If the processing of all modules has not been completed, the entire netlist generation unit 33 returns to step S91 and performs the same processing as described above for the next module.

  On the other hand, if it is determined in step S93 that the processing of all modules has been completed, the entire net list generation unit 33 reads the PKG net list 46 and adds it to the in-chip net list 44, thereby creating the entire net list 47. Create (step S94). The overall netlist generation unit 33 adds connection information for connecting to the representative node of the module closest to the power supply GND, and adds the PKG netlist 46 to the in-chip netlist 44. Then, the CPU 11 ends the process by the entire net list generation unit 33.

  An example of an analysis model for performing noise estimation based on the entire netlist 47 including the equivalent circuit generated by the above-described processing and its connection information will be described with reference to FIG. FIG. 10 is a diagram illustrating an example of the analysis model according to the present embodiment. The analysis model shown in FIG. 10 is based on the circuit configuration of the LSI 5 shown in FIG. The circuit (Aggressor) 1, the circuit (Victim) 2, the circuit 10, and the circuit 11 shown in FIG. 1 are simply referred to as modules 1m, 2m, 10m, and 11m in this case. The shapes of the modules 1m, 2m, 10m, and 11m (step S73 in FIG. 8) are indicated by dotted lines.

  In the analysis model illustrated in FIG. 10, the representative nodes 50, 51, 52, and 53 are the representatives assigned to the modules 10m, 11m, 2m, and 1m by the process in step S76 of FIG. It is a node.

  The substrate resistances 24a, 24b, 24c, 24d, 24e, and 24f between the modules are equivalent circuits that represent the impedance between the modules, generated by the processing in step S83 in FIG. 8, and are connected to the representative node of the target module. Is done.

  In the example of this analysis model, the current consumption 69 is connected to the representative node 53 by the processing in step S92 in FIG.

  The PKG equivalent circuits 60, 62, and 63 are connected to the representative nodes 50, 52, and 53 of the corresponding module by the processing in step S94 in FIG. 9 according to the connection information defined in advance in the PKG netlist 46. Is done.

  The junction capacitor 26 is created by the in-chip netlist generation unit 32 when the module 2m is a circuit block that is triple-well separated (see Patent Document 1). This model is not generated unless the circuit block is a triple well separated circuit block.

  A circuit simulation is performed by the circuit simulation unit 34 using such an analysis model, whereby noise is estimated. Then, the noise distribution display unit 35 displays the noise distribution on the display unit 13.

  FIG. 11 is a diagram illustrating an example of noise distribution by circuit simulation using the analysis model illustrated in FIG. In FIG. 11, the estimated amount of noise (mV) received by each circuit is shown corresponding to the areas of modules 1m, 2m, 10m, and 11m.

  For example, in the noise distribution example of FIG. 11, the noise amount of the module 1 m corresponding to the circuit (Aggressor) 1 is 112 mV, the noise amount of the module 2 m corresponding to the circuit (Victim) 2 is 12 mV, and the module 10 m corresponding to the circuit 10 The noise amount is 50 mV, and the noise amount of the module 11 m corresponding to the circuit 11 is 40 mV. These values are, for example, noise amount peak values.

  The noise amount of the module 2m corresponding to the circuit (Victim) 2 is determined by the generated equivalent circuit, in addition to the path K1 shown in FIG. 1, at least the power supply in the proximity circuit 10 and the circuit 11 from the path K2 and the path K3. A value that takes into account the noise propagating through the wiring.

  As described above, in the present embodiment, in the initial design stage, a plurality of circuit blocks separated from the power source are mounted using design information such as the floor plan data 41, the module current consumption data 45, and the PKG netlist 46. It is possible to estimate the noise propagated through the power supply wiring of the adjacent circuit block of the LSI to be operated.

  Therefore, the noise estimation can be realized even if the relationship between Aggressor and Victim is not limited to one-to-one, but many-to-one or many-to-many.

  Further, when the relationship between Aggressor and Victim is estimated on a one-to-one basis, the problem that the amount of noise is underestimated can be solved, and more accurate noise estimation can be realized.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and changes can be made without departing from the scope of the claims.

The following additional notes are further disclosed with respect to the embodiment including the above examples.
(Appendix 1)
A noise estimation method performed by a computer comprising:
A calculation procedure for calculating a substrate resistance between a plurality of circuit blocks arranged in the LSI, using process parameters relating to electrical characteristics of the LSI substrate stored in the storage area;
A generation procedure for generating an equivalent circuit having the calculated substrate resistance and generating an in-chip netlist in a storage area;
For each circuit block, a circuit simulation is performed using an entire net list in which connection information between electrical elements and circuit blocks related to the operation of the LSI is added to the intra-chip net list stored in the storage area. And a circuit simulation procedure for estimating the noise of the circuit.
(Appendix 2)
The noise estimation method according to appendix 1, wherein a resistance value in each circuit block is set to zero.
(Appendix 3)
The noise estimation method according to appendix 1 or 2, wherein the plurality of circuit blocks include at least two or more digital circuits and at least one analog circuit.
(Appendix 4)
The computer is
4. The noise distribution display procedure for displaying a noise amount obtained by the circuit simulation on a display unit corresponding to a circuit block area is performed for each circuit block. Noise estimation method.
(Appendix 5)
The noise estimation method according to any one of appendices 1 to 4, wherein the plurality of circuit blocks are circuits that are mounted on the LSI with a power supply region separated.
(Appendix 6)
A storage area for storing process parameters related to the electrical characteristics of the LSI substrate;
Using the process parameters, calculation means for calculating substrate resistance between a plurality of circuit blocks arranged in the LSI,
Generating means for generating an equivalent circuit having the calculated substrate resistance and generating an in-chip netlist in the storage area;
For each circuit block, a circuit simulation is performed using an entire net list in which connection information between electrical elements and circuit blocks related to the operation of the LSI is added to the intra-chip net list stored in the storage area. And a circuit simulation means for estimating the noise.
(Appendix 7)
Using the process parameters related to the electrical characteristics of the LSI substrate stored in the storage area, calculate the substrate resistance between a plurality of circuit blocks arranged in the LSI,
Generating an equivalent circuit having the calculated substrate resistance, and generating an in-chip netlist in a storage area;
For each circuit block, a circuit simulation is performed using an entire net list in which connection information between electrical elements and circuit blocks related to the operation of the LSI is added to the intra-chip net list stored in the storage area. Estimate the noise of the
A computer-readable storage medium storing a program for causing a computer to execute processing.

1 Circuit (Aggressor)
2 Circuit (Victim)
5 LSI
10, 11 circuit 11 CPU
DESCRIPTION OF SYMBOLS 12 Memory unit 13 Display unit 14 Output unit 15 Input unit 16 Communication unit 17 Storage device 18 Driver 19 Storage medium 20, 21, 22, 23 Substrate resistance 24a, 24b, 24c, 24d, 24e Substrate resistance 25a, 25b In-circuit resistance 26 Junction capacity 31 Floor plan creation unit 32 In-chip net list generation unit 33 Overall net list generation unit 34 Circuit simulation unit 35 Noise distribution display unit 40 Storage area 41 Floor plan data 42 Edge information 42-2 Representative node name allocation information 43 Processed Edge information 44 In-chip netlist 45 Current consumption data per module 46 PKG netlist 47 Overall netlist 49 Process parameters 50, 51, 52, 53 Representative nodes 60, 62, 63 PKG equivalent Road 69 Current consumption 1m, 2m, 10m, 11m module K1, K2, K3 noise propagation path 100 noise estimation device

Claims (5)

A noise estimation method performed by a computer comprising:
A calculation procedure for calculating a substrate resistance between a plurality of circuit blocks arranged in the LSI based on process parameters related to electrical characteristics of the LSI substrate stored in the storage area;
A generation step that generates an equivalent circuit of the substrate of the LSI having a substrate resistance that the calculated,
Executing a circuit simulation procedure for estimating noise for each circuit block based on a simulation result of a circuit in which time-dependent consumption current data in each of the plurality of circuit blocks is added to the generated equivalent circuit of the LSI substrate. How to estimate noise.   The noise estimation method according to claim 1, wherein a resistance value in each circuit block is set to zero.   The noise estimation method according to claim 1, wherein the plurality of circuit blocks include at least two or more digital circuits and at least one analog circuit. The computer is
For each circuit block, according to any one of claims 1 to 3, characterized in that to perform the noise distribution display procedure for displaying on the display unit in correspondence to the noise amount obtained by the circuit simulation in the area of the circuit blocks Noise estimation method. A storage area for storing process parameters related to the electrical characteristics of the LSI substrate;
Calculation means for calculating substrate resistance between a plurality of circuit blocks arranged in the LSI based on the process parameters;
A generation unit that generates an equivalent circuit of the substrate of the LSI having a substrate resistance that the calculated,
Circuit simulation means for estimating noise for each circuit block based on a simulation result of a circuit in which time-dependent consumption current data in each of the plurality of circuit blocks is added to the generated equivalent circuit of the LSI substrate. Noise estimation device.

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