JP5671050B2 - ランダムアクセスメモリの動的管理 - Google Patents

ランダムアクセスメモリの動的管理 Download PDF

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Publication number
JP5671050B2
JP5671050B2 JP2012537394A JP2012537394A JP5671050B2 JP 5671050 B2 JP5671050 B2 JP 5671050B2 JP 2012537394 A JP2012537394 A JP 2012537394A JP 2012537394 A JP2012537394 A JP 2012537394A JP 5671050 B2 JP5671050 B2 JP 5671050B2
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JP
Japan
Prior art keywords
instruction
memory
processor
priority
execution
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Expired - Fee Related
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JP2012537394A
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English (en)
Japanese (ja)
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JP2013510355A (ja
JP2013510355A5 (enExample
Inventor
ミッシェル カトルイエ，
ミッシェル カトルイエ，
ロイック パラルディ，
ロイック パラルディ，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grand Ouest SAS
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ST Ericsson France SAS
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Publication of JP2013510355A5 publication Critical patent/JP2013510355A5/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/24—Loading of the microprogram
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Executing Machine-Instructions (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2012537394A 2009-11-04 2010-11-03 ランダムアクセスメモリの動的管理 Expired - Fee Related JP5671050B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0957809 2009-11-04
FR0957809 2009-11-04
PCT/EP2010/066760 WO2011054884A1 (en) 2009-11-04 2010-11-03 Dynamic management of random access memory

Publications (3)

Publication Number Publication Date
JP2013510355A JP2013510355A (ja) 2013-03-21
JP2013510355A5 JP2013510355A5 (enExample) 2013-12-19
JP5671050B2 true JP5671050B2 (ja) 2015-02-18

Family

ID=42357885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012537394A Expired - Fee Related JP5671050B2 (ja) 2009-11-04 2010-11-03 ランダムアクセスメモリの動的管理

Country Status (4)

Country Link
US (1) US9390029B2 (enExample)
EP (1) EP2497025A1 (enExample)
JP (1) JP5671050B2 (enExample)
WO (1) WO2011054884A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
HUE031778T2 (en) 2010-05-14 2017-07-28 Univ Leland Stanford Junior Humanized and chimeric monoclonal antibodies against CD47
JP2012242877A (ja) * 2011-05-16 2012-12-10 Sony Corp メモリ管理装置、メモリ管理方法、および、制御プログラム
US9224452B2 (en) * 2013-01-17 2015-12-29 Qualcomm Incorporated Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems
GB2516435A (en) * 2013-04-05 2015-01-28 Continental Automotive Systems Embedded memory management scheme for real-time applications
US11077364B2 (en) 2018-04-02 2021-08-03 Google Llc Resolution-based scaling of real-time interactive graphics
CN112074330B (zh) 2018-04-02 2022-07-08 谷歌有限责任公司 交互式云游戏的方法、设备和系统

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719602A (en) * 1985-02-07 1988-01-12 Visic, Inc. Memory with improved column access
US4839796A (en) * 1987-07-16 1989-06-13 Icon International, Inc. Static frame digital memory
US5634135A (en) 1991-12-13 1997-05-27 Texas Instruments Incorporated Microprocessor with priority determination and priority based instruction selection
JPH08137513A (ja) 1994-11-10 1996-05-31 Fanuc Ltd メモリ管理方式
SE0000533D0 (sv) * 2000-02-18 2000-02-18 Ericsson Telefon Ab L M Static cache
US7657706B2 (en) * 2003-12-18 2010-02-02 Cisco Technology, Inc. High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory
US7395385B2 (en) * 2005-02-12 2008-07-01 Broadcom Corporation Memory management for a mobile multimedia processor
JP2007026094A (ja) 2005-07-15 2007-02-01 Matsushita Electric Ind Co Ltd 実行装置およびアプリケーションプログラム
US7502890B2 (en) * 2006-07-07 2009-03-10 International Business Machines Corporation Method and apparatus for dynamic priority-based cache replacement
US7496711B2 (en) * 2006-07-13 2009-02-24 International Business Machines Corporation Multi-level memory architecture with data prioritization
US7584335B2 (en) * 2006-11-02 2009-09-01 International Business Machines Corporation Methods and arrangements for hybrid data storage
US7769955B2 (en) 2007-04-27 2010-08-03 Arm Limited Multiple thread instruction fetch from different cache levels
BRPI0721953A2 (pt) 2007-08-31 2014-03-18 Panasonic Corp Aparelho de processamento de informações
US20090138683A1 (en) 2007-11-28 2009-05-28 Capps Jr Louis B Dynamic instruction execution using distributed transaction priority registers
JP5414305B2 (ja) * 2009-02-25 2014-02-12 キヤノン株式会社 情報処理装置、仮想記憶管理方法及びプログラム

Also Published As

Publication number Publication date
WO2011054884A1 (en) 2011-05-12
US20120215975A1 (en) 2012-08-23
EP2497025A1 (en) 2012-09-12
JP2013510355A (ja) 2013-03-21
US9390029B2 (en) 2016-07-12

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