JP5671050B2 - ランダムアクセスメモリの動的管理 - Google Patents

ランダムアクセスメモリの動的管理 Download PDF

Info

Publication number
JP5671050B2
JP5671050B2 JP2012537394A JP2012537394A JP5671050B2 JP 5671050 B2 JP5671050 B2 JP 5671050B2 JP 2012537394 A JP2012537394 A JP 2012537394A JP 2012537394 A JP2012537394 A JP 2012537394A JP 5671050 B2 JP5671050 B2 JP 5671050B2
Authority
JP
Japan
Prior art keywords
instruction
memory
processor
priority
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012537394A
Other languages
English (en)
Japanese (ja)
Other versions
JP2013510355A5 (enExample
JP2013510355A (ja
Inventor
ミッシェル カトルイエ，
ミッシェル カトルイエ，
ロイック パラルディ，
ロイック パラルディ，
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Grand Ouest SAS
Original Assignee
ST Ericsson France SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ST Ericsson France SAS filed Critical ST Ericsson France SAS
Publication of JP2013510355A publication Critical patent/JP2013510355A/ja
Publication of JP2013510355A5 publication Critical patent/JP2013510355A5/ja
Application granted granted Critical
Publication of JP5671050B2 publication Critical patent/JP5671050B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12—Replacement control
    • G06F12/121—Replacement control using replacement algorithms
    • G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/24—Loading of the microprogram
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Executing Machine-Instructions (AREA)
JP2012537394A 2009-11-04 2010-11-03 ランダムアクセスメモリの動的管理 Expired - Fee Related JP5671050B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0957809 2009-11-04
FR0957809 2009-11-04
PCT/EP2010/066760 WO2011054884A1 (en) 2009-11-04 2010-11-03 Dynamic management of random access memory

Publications (3)

Publication Number Publication Date
JP2013510355A JP2013510355A (ja) 2013-03-21
JP2013510355A5 JP2013510355A5 (enExample) 2013-12-19
JP5671050B2 true JP5671050B2 (ja) 2015-02-18

Family

ID=42357885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012537394A Expired - Fee Related JP5671050B2 (ja) 2009-11-04 2010-11-03 ランダムアクセスメモリの動的管理

Country Status (4)

Country Link
US (1) US9390029B2 (enExample)
EP (1) EP2497025A1 (enExample)
JP (1) JP5671050B2 (enExample)
WO (1) WO2011054884A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2569013B1 (en) 2010-05-14 2016-11-23 The Board of Trustees of the Leland Stanford Junior University Humanized and chimeric monoclonal antibodies to cd47
JP2012242877A (ja) * 2011-05-16 2012-12-10 Sony Corp メモリ管理装置、メモリ管理方法、および、制御プログラム
US9224452B2 (en) * 2013-01-17 2015-12-29 Qualcomm Incorporated Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems
GB2516435A (en) * 2013-04-05 2015-01-28 Continental Automotive Systems Embedded memory management scheme for real-time applications
KR102694451B1 (ko) 2018-04-02 2024-08-13 구글 엘엘씨 대화형 클라우드 게임용 방법, 디바이스 및 시스템
US11077364B2 (en) 2018-04-02 2021-08-03 Google Llc Resolution-based scaling of real-time interactive graphics

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719602A (en) * 1985-02-07 1988-01-12 Visic, Inc. Memory with improved column access
US4839796A (en) * 1987-07-16 1989-06-13 Icon International, Inc. Static frame digital memory
US5634135A (en) * 1991-12-13 1997-05-27 Texas Instruments Incorporated Microprocessor with priority determination and priority based instruction selection
JPH08137513A (ja) * 1994-11-10 1996-05-31 Fanuc Ltd メモリ管理方式
SE0000533D0 (sv) * 2000-02-18 2000-02-18 Ericsson Telefon Ab L M Static cache
US7657706B2 (en) * 2003-12-18 2010-02-02 Cisco Technology, Inc. High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory
US7395385B2 (en) * 2005-02-12 2008-07-01 Broadcom Corporation Memory management for a mobile multimedia processor
JP2007026094A (ja) 2005-07-15 2007-02-01 Matsushita Electric Ind Co Ltd 実行装置およびアプリケーションプログラム
US7502890B2 (en) * 2006-07-07 2009-03-10 International Business Machines Corporation Method and apparatus for dynamic priority-based cache replacement
US7496711B2 (en) * 2006-07-13 2009-02-24 International Business Machines Corporation Multi-level memory architecture with data prioritization
US7584335B2 (en) * 2006-11-02 2009-09-01 International Business Machines Corporation Methods and arrangements for hybrid data storage
US7769955B2 (en) 2007-04-27 2010-08-03 Arm Limited Multiple thread instruction fetch from different cache levels
US20110113216A1 (en) * 2007-08-31 2011-05-12 Panasonic Corporation Information processing apparatus
US20090138683A1 (en) * 2007-11-28 2009-05-28 Capps Jr Louis B Dynamic instruction execution using distributed transaction priority registers
JP5414305B2 (ja) * 2009-02-25 2014-02-12 キヤノン株式会社 情報処理装置、仮想記憶管理方法及びプログラム

Also Published As

Publication number Publication date
EP2497025A1 (en) 2012-09-12
US20120215975A1 (en) 2012-08-23
US9390029B2 (en) 2016-07-12
JP2013510355A (ja) 2013-03-21
WO2011054884A1 (en) 2011-05-12

Similar Documents

Publication Publication Date Title
CN105074666B (zh) 执行在具有不同指令集架构的处理器上的操作系统
JP5671050B2 (ja) ランダムアクセスメモリの動的管理
KR20120123127A (ko) 이종 플랫폼에서 포인터를 공유시키는 방법 및 장치
KR20230041593A (ko) 프로그래밍가능한 인터리브 입도를 갖는 cxl 타입-2 디바이스들을 위한 확장가능한 주소 디코딩 체계
US9632958B2 (en) System for migrating stash transactions
US20140344602A1 (en) Apparatus and method managing power based on data
CN117271136A (zh) 数据处理方法、装置、设备和存储介质
CN116010299A (zh) 一种数据处理方法、装置、设备及可读存储介质
KR20220049294A (ko) 스케줄러, 스케줄러의 동작 방법 및 이를 포함한 전자 장치
CN118519768A (zh) 向共享缓存进行数据溢出的方法、装置、设备和存储介质
JP7410186B2 (ja) Ｇｐｕにおける明示的な個別マスクレジスタのマスク操作方法
US11226798B2 (en) Information processing device and information processing method
CN104216684A (zh) 一种多核并行系统及其数据处理方法
JP5278538B2 (ja) コンパイルシステム、コンパイル方法およびコンパイルプログラム
TW202107408A (zh) 波槽管理之方法及裝置
CN105103138B (zh) 用于实时应用的嵌入式存储器管理方案
CN103197918A (zh) 多通道时间片组
CN112230931B (zh) 适用于图形处理器的二次卸载的编译方法、装置和介质
CN116301874A (zh) 代码编译方法、电子设备及存储介质
KR102757653B1 (ko) 확장 메모리 인터페이스
US20220067872A1 (en) Graphics processing unit including delegator and operating method thereof
CN118035131B (zh) 数据预取方法及装置、处理器和计算机可读存储介质
CN112015751A (zh) 数据查询方法及相关设备
CN110990151A (zh) 一种基于异构计算平台的业务处理方法
CN113110879B (zh) 指令处理方法及装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20131031

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20131031

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20140312

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140411

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140707

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140929

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20141120

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20141215

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141218

R150 Certificate of patent or registration of utility model

Ref document number: 5671050

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

LAPS Cancellation because of no payment of annual fees