JP2013510355A5 - - Google Patents

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Publication number
JP2013510355A5
JP2013510355A5 JP2012537394A JP2012537394A JP2013510355A5 JP 2013510355 A5 JP2013510355 A5 JP 2013510355A5 JP 2012537394 A JP2012537394 A JP 2012537394A JP 2012537394 A JP2012537394 A JP 2012537394A JP 2013510355 A5 JP2013510355 A5 JP 2013510355A5
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JP
Japan
Prior art keywords
instruction
item
memory
compromising
storage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2012537394A
Other languages
English (en)
Japanese (ja)
Other versions
JP5671050B2 (ja
JP2013510355A (ja
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Publication date
Application filed filed Critical
Priority claimed from PCT/EP2010/066760 external-priority patent/WO2011054884A1/en
Publication of JP2013510355A publication Critical patent/JP2013510355A/ja
Publication of JP2013510355A5 publication Critical patent/JP2013510355A5/ja
Application granted granted Critical
Publication of JP5671050B2 publication Critical patent/JP5671050B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2012537394A 2009-11-04 2010-11-03 ランダムアクセスメモリの動的管理 Expired - Fee Related JP5671050B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR0957809 2009-11-04
FR0957809 2009-11-04
PCT/EP2010/066760 WO2011054884A1 (en) 2009-11-04 2010-11-03 Dynamic management of random access memory

Publications (3)

Publication Number Publication Date
JP2013510355A JP2013510355A (ja) 2013-03-21
JP2013510355A5 true JP2013510355A5 (enExample) 2013-12-19
JP5671050B2 JP5671050B2 (ja) 2015-02-18

Family

ID=42357885

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012537394A Expired - Fee Related JP5671050B2 (ja) 2009-11-04 2010-11-03 ランダムアクセスメモリの動的管理

Country Status (4)

Country Link
US (1) US9390029B2 (enExample)
EP (1) EP2497025A1 (enExample)
JP (1) JP5671050B2 (enExample)
WO (1) WO2011054884A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2569013B1 (en) 2010-05-14 2016-11-23 The Board of Trustees of the Leland Stanford Junior University Humanized and chimeric monoclonal antibodies to cd47
JP2012242877A (ja) * 2011-05-16 2012-12-10 Sony Corp メモリ管理装置、メモリ管理方法、および、制御プログラム
US9224452B2 (en) * 2013-01-17 2015-12-29 Qualcomm Incorporated Heterogeneous memory systems, and related methods and computer-readable media for supporting heterogeneous memory access requests in processor-based systems
GB2516435A (en) * 2013-04-05 2015-01-28 Continental Automotive Systems Embedded memory management scheme for real-time applications
KR102694451B1 (ko) 2018-04-02 2024-08-13 구글 엘엘씨 대화형 클라우드 게임용 방법, 디바이스 및 시스템
US11077364B2 (en) 2018-04-02 2021-08-03 Google Llc Resolution-based scaling of real-time interactive graphics

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4719602A (en) * 1985-02-07 1988-01-12 Visic, Inc. Memory with improved column access
US4839796A (en) * 1987-07-16 1989-06-13 Icon International, Inc. Static frame digital memory
US5634135A (en) * 1991-12-13 1997-05-27 Texas Instruments Incorporated Microprocessor with priority determination and priority based instruction selection
JPH08137513A (ja) * 1994-11-10 1996-05-31 Fanuc Ltd メモリ管理方式
SE0000533D0 (sv) * 2000-02-18 2000-02-18 Ericsson Telefon Ab L M Static cache
US7657706B2 (en) * 2003-12-18 2010-02-02 Cisco Technology, Inc. High speed memory and input/output processor subsystem for efficiently allocating and using high-speed memory and slower-speed memory
US7395385B2 (en) * 2005-02-12 2008-07-01 Broadcom Corporation Memory management for a mobile multimedia processor
JP2007026094A (ja) 2005-07-15 2007-02-01 Matsushita Electric Ind Co Ltd 実行装置およびアプリケーションプログラム
US7502890B2 (en) * 2006-07-07 2009-03-10 International Business Machines Corporation Method and apparatus for dynamic priority-based cache replacement
US7496711B2 (en) * 2006-07-13 2009-02-24 International Business Machines Corporation Multi-level memory architecture with data prioritization
US7584335B2 (en) * 2006-11-02 2009-09-01 International Business Machines Corporation Methods and arrangements for hybrid data storage
US7769955B2 (en) 2007-04-27 2010-08-03 Arm Limited Multiple thread instruction fetch from different cache levels
US20110113216A1 (en) * 2007-08-31 2011-05-12 Panasonic Corporation Information processing apparatus
US20090138683A1 (en) * 2007-11-28 2009-05-28 Capps Jr Louis B Dynamic instruction execution using distributed transaction priority registers
JP5414305B2 (ja) * 2009-02-25 2014-02-12 キヤノン株式会社 情報処理装置、仮想記憶管理方法及びプログラム

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