JP5669674B2 - Drive control device for semiconductor optical modulator - Google Patents

Description

  The present invention relates to a drive control device for an optical modulator used for optical communication, and more particularly to a drive control device that can stably drive and control a semiconductor Mach-Zehnder type optical modulator.

  As a modulation method of an optical communication system, a direct modulation method has been used in which a laser diode is modulated with a drive current to obtain a light intensity signal proportional to an electrical signal. This direct modulation method has an advantage that the device configuration is very simple.

  However, in an ultrahigh-speed / broadband optical communication system in which the transmission speed exceeds several Gbit / s, a wavelength fluctuation (chirping) phenomenon in which the wavelength of light changes during direct modulation has become a factor limiting transmission capacity.

For this reason, the direct modulation method is used in a relatively low-speed optical communication system.
On the other hand, in order to suppress chirping during modulation, an optical modulator method for ultra-high-speed transmission uses an external modulator method in which a semiconductor laser is continuously emitted and this light is turned on / off by an external modulator. ing. The most common external modulator is a Mach-Zehnder type optical modulator (hereinafter referred to as an MZ type modulator).

  FIG. 19 is a diagram illustrating an example of an optical output characteristic with respect to a drive signal of the MZ type optical modulator. Referring to FIG. 19, in the conventional non-return to zero (NRZ) modulation code, the high level and low level of the drive signal whose level changes in period T are set to the light emission vertex A and the light extinction vertex B, respectively. By combining them, on / off modulation of the optical output is performed.

  In the following description, the difference in bias voltage corresponding to the vertices A and B of light emission / extinction with periodically changing light output characteristics will be expressed as Vπ. According to this, the amplitude of the drive signal in the NRZ modulation method is Vπ.

  This MZ type optical modulator has an advantage that the chirping phenomenon is small. However, there has been a problem that the optical output characteristic with respect to the drive signal drifts with time due to temperature change, change with time, etc., and intersymbol interference occurs in the on / off level of the optical output.

  In order to solve such a problem and to stably control the operating point of the MZ type modulator, when the curve a indicating the optical output characteristic with respect to the driving voltage shown in FIG. It is necessary to control the operating point to reduce the bias voltage by the signal in accordance with the change. On the other hand, when the curve a changes to the curve c, it is necessary to similarly control the operating point such that the bias voltage is increased in accordance with the change.

  In the modulation method using the NRZ code or the RZ (return to zero) code, for example, in the technique disclosed in Japanese Patent Laid-Open No. 4-140712 (Patent Document 1), a low frequency signal is superimposed on the drive signal. The purpose is to compensate for the bias voltage using a compensation technique that detects the amount and direction of fluctuation of the point, controls the bias voltage by feedback, and keeps the operating point normal.

  The technique disclosed in Japanese Patent Laid-Open No. 10-048582 (Patent Document 2) aims to optimize both the bias and the drive amplitude. A first synchronous detection circuit and a second synchronous detection circuit are arranged, and the first dither signal generator and the second dither signal generator are added by an adder and connected to a DC bias terminal. In the first synchronous detection circuit, the dither signal is superimposed on the DC bias, and the dither signal component is detected by the peak detector. The detected signal is multiplied with the original dither signal to obtain an error signal corresponding to the difference from the optimum bias value. By feeding back this value to the DC bias, the bias of the modulator can be optimized. The second synchronous detection circuit has the same configuration, and an error signal corresponding to a deviation from the optimum value of the modulator drive amplitude is output from the synchronous detection circuit. By feeding back the error signal to the variable gain amplifier, The drive signal amplitude to the optical modulator can be optimized.

Japanese Patent Laid-Open No. 4-140712 Japanese Patent Laid-Open No. 10-048582

  By using the technique disclosed in Japanese Patent Laid-Open No. 4-140712 (Patent Document 1), it becomes possible to compensate for the bias drift due to a temperature change or a change with time. An LN modulator using a general LiNbO3 substrate as an MZ type optical modulator can be used stably.

  Furthermore, in recent years, a semiconductor MZ modulator that constitutes an MZ modulator using a semiconductor waveguide has been realized. The semiconductor MZ modulator can be significantly reduced in size. The semiconductor MZ modulator also has a small drive amplitude. Therefore, by using the semiconductor MZ modulator, the optical transmitter can be significantly reduced in size, and is expected as a promising device in the future.

  However, this semiconductor MZ modulator has a problem that Vπ (amplitude of the drive signal) also changes depending on temperature and wavelength, in addition to bias drift due to temperature and aging.

  In the technique disclosed in Japanese Patent Laid-Open No. 10-048582 (Patent Document 2), it is assumed that there are a plurality of optimum bias voltages. Therefore, when there is only one optimum bias voltage, it may not converge to the optimum point. There is also a problem that there is.

  The present invention has been made to solve the above-described problems, and provides a drive control device that controls both the bias drift and the amplitude of the drive signal at the same time and stably operates the semiconductor MZ modulator. The purpose is to do.

  A drive control device for a semiconductor light modulator according to the present invention is a drive control device for a semiconductor light modulator that receives light from a light source that emits continuous light and whose light output characteristics with respect to a drive voltage periodically change, Synchronous detection based on a peak detector that detects an electrical signal that changes according to the output light output from the semiconductor optical modulator, an oscillation circuit, and the output of the oscillation circuit and the peak detection output signal of the peak detector A detection circuit; a bias control unit that controls a phase bias of the semiconductor optical modulator according to the output of the synchronous detection circuit; an amplifier that amplifies the data signal; and an amplifier that is output from the amplifier according to the output of the synchronous detection circuit. An amplitude controller that controls the amplitude of the data signal, a power supply circuit that supplies a reference voltage to the output of the amplifier, and an adder that receives the output of the amplifier and the reference voltage to generate a drive voltage. Obtain.

  According to the drive control apparatus of the present invention, in the control of the semiconductor MZ modulator, the bias and the drive amplitude can be controlled to optimum values, and the semiconductor MZ modulator can be stably operated.

1 is a block diagram showing a drive control apparatus 100 according to Embodiment 1. FIG. 2 is a diagram showing a configuration of a semiconductor MZ modulator 2. FIG. FIG. 6 is a diagram illustrating a modification of the configuration of the semiconductor MZ modulator illustrated in FIG. 2. It is a figure for demonstrating operation | movement of the semiconductor MZ modulator 2 when P bias voltage is set appropriately. It is a figure for demonstrating operation | movement of the semiconductor MZ modulator 2 when P bias voltage is set higher than an appropriate value. It is a figure for demonstrating operation | movement of the semiconductor MZ modulator 2 when P bias voltage is set lower than an appropriate value. It is a figure for demonstrating operation | movement of the semiconductor MZ modulator 2 when a drive amplitude is set appropriately. It is a figure for demonstrating operation | movement of the semiconductor MZ modulator 2 when a drive amplitude is set larger than an appropriate value. It is a figure for demonstrating operation | movement of the semiconductor MZ modulator 2 when a drive amplitude is set smaller than an appropriate value. FIG. 6 is a block diagram showing a drive control apparatus 200 of a second embodiment. FIG. 3 is a diagram showing the relationship between the S bias voltage and the drive amplitude of the semiconductor MZ modulator 2. FIG. 10 is a block diagram for explaining an example of a connection relationship of a drive control apparatus 300 according to a third embodiment. FIG. 10 is a block diagram for explaining another example of the connection relationship of the drive control device 300 according to the third embodiment. FIG. 10 is a block diagram showing a drive control device 300A that is a modification of the drive control device 300 of the third embodiment. FIG. 10 is a block diagram showing a drive control apparatus 400 according to a fourth embodiment. It is a figure for demonstrating the relationship between P bias in two different wavelengths, and an optical output. FIG. 10 is a block diagram showing a drive control apparatus 500 of a fifth embodiment. FIG. 10 is a block diagram showing a drive control device 600 of a sixth embodiment. It is a figure which shows an example of the optical output characteristic with respect to the drive signal of an MZ type | mold optical modulator.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

[Embodiment 1]
FIG. 1 is a block diagram showing a drive control apparatus 100 according to the first embodiment. Referring to FIG. 1, a drive control apparatus 100 includes a light source 1 that emits continuous light, a semiconductor MZ modulator 2, a duplexer 3 that demultiplexes an output signal, and a photo that converts an optical signal into an electrical signal. A diode 4, a peak detector 5 that amplifies the output electric signal of the photodiode 4 and detects an envelope, an oscillation circuit 6 that generates a dither signal (low frequency signal), and a dither signal and a peak detection signal are multiplied. And a synchronous detection circuit 7 for synchronous detection. The oscillation circuit 6 includes dither signal generation units 6a and 6b, and the synchronous detection circuit 7 includes synchronous detection units 7a and 7b.

  Furthermore, the drive control apparatus 100 includes a bias control unit 8 that controls the bias based on the output signal from the synchronous detection unit 7a, and an amplitude control unit 9 that controls the amplitude of the data signal based on the output signal from the synchronous detection unit 7b. The amplifier 10 that amplifies the data signal and drives the semiconductor MZ modulator, the adders 11a and 11b that respectively add the control signals from the bias control unit 8 and the amplitude control unit 9 to the dither signal, and the data signal by the amplifier 10 A DC power supply 12 that supplies a bias (reference voltage) to be superimposed on the amplified signal and an adder 11c that adds the data signal and the output voltage of the DC power supply 12 are included.

  Various forms of the synchronous detection circuit 7 are realized. For example, a circuit composed of a band-pass filter, a mixer, and a low-pass filter is generally used. Further, it can be realized by digital signal processing. Further, the peak detector 5 is usually configured easily using a diode and a capacitor, and can be easily obtained on the market as a peak detector.

  FIG. 2 is a diagram showing a configuration of the semiconductor MZ modulator 2. Referring to FIG. 2, a semiconductor MZ modulator 2 includes two symmetrical arms 20A and 20B, a waveguide 15 for optical input / output, a signal electrode 13 for modulating with a data signal, And a phase adjusting electrode 14 for adjusting the phase.

  The signal electrode 13 applies a data signal and a bias (S bias) to change the phase of each arm at high speed. The phase adjustment electrode 14 applies a phase adjustment bias (P bias) to adjust the phase of each arm. The reason why the signal electrode 13 and the phase adjustment electrode 14 are separated is that light absorption occurs due to the bias and that the half-wave voltage (Vπ) varies depending on the bias value. However, the electrodes do not necessarily have to be separated as described above, and it is possible to control with one electrode.

  Next, the semiconductor MZ modulator 2A will be described in comparison with the semiconductor MZ modulator 2. FIG. 3 is a diagram illustrating a semiconductor MZ modulator 2 </ b> A that is a modification of the semiconductor MZ modulator 2. Referring to FIG. 3, in addition to the configuration of semiconductor MZ modulator 2 in FIG. 2, semiconductor MZ modulator 2 </ b> A is replaced with signal electrode 13 and phase adjustment electrode 14 in the one-electrode configuration of semiconductor MZ modulator 2. It includes signal electrodes 13a and 13b and two phase adjustment electrodes 14a and 14b, which are two electrodes, each having an electrode disposed immediately above the waveguide.

  However, although the configuration of the semiconductor MZ modulators 2 and 2A has been described, the present invention is not limited to this.

  Next, the operation of the first embodiment will be described. The light source 1 emitted from the light source 1 is input to the semiconductor MZ modulator 2. The data signal is amplified by the amplifier 10. The output signal of the DC power source 12 is added to the amplified signal amplified by the amplifier 10 by the adder 11c and input to the signal electrode 13 of the semiconductor MZ modulator 2 as an S bias.

  At this time, the dither signal from the dither signal generator 6a is input to the amplitude adjustment terminal of the amplifier 10 that amplifies the data signal. That is, the data signal is intensity-modulated by the dither signal generator 6a.

  The output optical signal of the semiconductor MZ modulator 2 is demultiplexed by the demultiplexer 3, converted into an electric signal by the photodiode 4, and input to the peak detector 5. In order to detect the envelope of the input signal, the peak detection unit 5 extracts only the intensity modulation component modulated by the dither signal.

  One of the peak detection output signals from the peak detection unit 5 is input to the synchronous detection unit 7a. The dither signal generated from the dither signal generator 6a is further input to the synchronous detector 7a. Using the dither signal generated from the dither signal generator 6a and the peak detection output signal from the peak detector 5, the synchronous detector 7a performs synchronous detection.

  In response to the synchronous detection, an error signal from the target value is output and input to the bias control unit 8. The bias controller 8 outputs a control signal for controlling the bias based on the error signal. In the adder 11b, this control signal is added to the dither signal generated from the dither signal generator 6b, and this added output signal is input as the P bias voltage of the semiconductor MZ modulator 2.

  By performing the above control, the P bias voltage can be controlled to an optimum value. Specifically, the above control will be described with reference to FIGS. Here, each drawing further includes (a) to (d).

  In (a), a signal at the S bias voltage input as the P bias voltage to the semiconductor MZ modulator 2 is shown. (B) shows an operating characteristic curve (extinction curve) given by the semiconductor MZ modulator 2.

  (C) shows an optical signal waveform output from the semiconductor MZ modulator 2. In (d), the optical signal waveform output from the semiconductor MZ modulator 2 is received by the photodiode 4, converted into an electrical signal, and output from the peak detection unit 5 when the peak detection unit 5 performs peak detection. Is shown.

  FIG. 4 is a diagram for explaining the operation of the semiconductor MZ modulator 2 when the P bias voltage is appropriately set. 4A to 4D, the dither signal added to the data signal in the adder 11a is not observed, and the frequency component that is twice the frequency of the dither signal is output as the output of the peak detector 5. Is generated. For this reason, when the peak detection output signal from the peak detection unit 5 and the dither signal output from the dither signal generation unit 6a are synchronously detected, the output of the synchronous detection unit 7a becomes zero. Therefore, the bias controller 8 determines that the P bias at this time is appropriately controlled and set.

  FIG. 5 is a diagram for explaining the operation of the semiconductor MZ modulator 2 when the P bias voltage is set higher than an appropriate value. Referring to FIGS. 5A to 5D, the dither signal added to the data signal in adder 11a is output from the peak detection output signal from peak detection unit 5 and dither signal generation unit 6a. It can be seen that the dither signal has the same frequency and the phase is inverted. For this reason, the output of the synchronous detection is negative, and the bias control unit controls to increase the P bias voltage.

  FIG. 6 is a diagram for explaining the operation of the semiconductor MZ modulator 2 when the P bias voltage is set lower than an appropriate value. With reference to FIGS. 6A to 6D, the dither signal added to the data signal in the adder 11a is output from the peak detection output signal from the peak detection unit 5 and the dither signal generation unit 6a. It can be seen that the dither signal has the same frequency and the same phase. For this reason, the output of the synchronous detection is positive, and the bias control unit controls the P bias voltage to decrease.

  As described with reference to FIGS. 4 to 6, if the above control is performed, the P bias voltage can be controlled to an optimum value.

  The output optical signal from the semiconductor MZ modulator 2 is demultiplexed by the demultiplexer 3, converted into an electric signal by the photodiode 4, and input to the peak detector 5. The peak detector 5 extracts only the intensity modulation component modulated by the dither signal in order to detect the envelope of the input signal.

  Another peak detection output signal from the peak detector 5 is input to the synchronous detector 7b. The dither signal generated from the dither signal generator 6b is also input to the synchronous detector 7b. Using the dither signal and the peak detection output signal from the peak detection unit 5, synchronous detection is performed in the synchronous detection unit 7b.

  In response to the synchronous detection, an error signal from the target value is output, and an amplitude control voltage is generated by the amplitude control unit 9. In the adder 11a, the dither signal generated from the dither signal generator 6a is added to the output waveform of the amplitude control voltage. The output signal of the adder 11a is input to the amplitude control terminal of the amplifier 10.

  By performing the above control, the drive amplitude of the data signal can be controlled to an optimum value. The above control will be specifically described with reference to FIGS. Here, each drawing further includes (a) to (d).

  In (a), a signal at the S bias voltage input as the P bias voltage to the semiconductor MZ modulator 2 is shown. (B) shows an operating characteristic curve (extinction curve) given by the semiconductor MZ modulator 2.

  (C) shows an optical signal waveform output from the semiconductor MZ modulator 2. In (d), the optical signal waveform output from the semiconductor MZ modulator 2 is received by the photodiode 4, converted into an electrical signal, and output from the peak detection unit 5 when the peak detection unit 5 performs peak detection. Is shown.

  FIG. 7 is a diagram for explaining the operation of the semiconductor MZ modulator 2 when the drive amplitude is appropriately set. 7A to 7D, the dither signal added to the P bias voltage in the adder 11b is not observed, and the frequency of the dither signal frequency twice as the output of the peak detector 5 is not observed. A signal having a component is generated. For this reason, when the peak detection output signal from the peak detection unit 5 and the dither signal output from the dither signal generation unit 6b are synchronously detected, the output of the synchronous detection unit 7b becomes zero. Therefore, the amplitude control unit 9 determines that the drive amplitude at this time is the optimum value.

  FIG. 8 is a diagram for explaining the operation of the semiconductor MZ modulator 2 when the drive amplitude is set larger than an appropriate value. Referring to FIGS. 8A to 8D, the dither signal added to the P bias voltage in the adder 11b is output from the peak detection output signal from the peak detection unit 5 and the dither signal generation unit 6b. It can be seen that the dither signal has the same frequency as the dither signal and the phase is inverted. For this reason, the output of the synchronous detection is negative, and the amplitude control unit 9 performs control so as to decrease the drive amplitude.

  FIG. 9 is a diagram for explaining the operation of the semiconductor MZ modulator 2 when the drive amplitude is set smaller than an appropriate value. With reference to FIGS. 9A to 9D, the dither signal added to the P bias voltage in the adder 11b is output from the peak detection output signal from the peak detection unit 5 and the dither signal generation unit 6b. It can be seen that the dither signal has the same frequency and the same phase. For this reason, the output of the synchronous detection is positive, and the amplitude control unit 9 controls to increase the drive amplitude.

  As described with reference to FIGS. 7 to 9, if the above control is performed, the drive amplitude can be controlled to an optimal value.

  Therefore, as described with reference to FIGS. 4 to 9, by implementing the drive control apparatus 100 of the first embodiment, the P bias voltage control and the drive amplitude control are performed simultaneously, thereby realizing the P bias. Both voltage and drive amplitude can always be optimally controlled.

  Since the P bias voltage and the drive amplitude are controlled simultaneously, it is necessary to determine the dither signal used in these controls. For this reason, the frequencies of the dither signal generators 6a and 6b are set to different frequencies.

  As described above, in the drive control apparatus 100 according to the first embodiment, by using dither signals having two different frequencies, the P bias voltage and the drive amplitude whose optimum values vary depending on temperature change, secular change, and wavelength. Can be controlled to an appropriate value.

[Embodiment 2]
The drive control device 200 will be described in comparison with the drive control device 100 of the first embodiment. FIG. 10 is a block diagram illustrating the drive control apparatus 200 according to the second embodiment. Referring to FIG. 10, drive control apparatus 200 includes a DC power supply 12A in place of DC power supply 12 of drive control apparatus 100 in addition to the configuration of drive control apparatus 100 of FIG. The adder 11a of the device 100 is not included. The other configuration of drive control device 200 is similar to that of drive control device 100, and therefore description thereof will not be repeated.

  In the drive control apparatus 100 of FIG. 1, the value of the drive amplitude is controlled to an appropriate value by inputting the output signal of the amplitude control unit 9 to the amplitude control terminal of the amplifier 10.

  On the other hand, in the drive control apparatus 200, the output signal of the amplitude control unit 9 is input to the DC power source 12A that applies the S bias.

  FIG. 11 is a diagram showing the relationship between the S bias voltage and the drive amplitude of the semiconductor MZ modulator 2. Referring to FIG. 11, the vertical axis indicates the optical output signal, and the horizontal axis indicates the S bias voltage. In the semiconductor MZ modulator 2, the required drive amplitude (Vπ) decreases as the depth of the S bias voltage increases. That is, Vπ when the bias is −3 V is 1.7 Vp-p, and Vπ when the bias is −6 V is 0.7 Vp-p. Note that Vp-p is an amplitude value between peaks of a normal modulation waveform.

  That is, changing the amplitude of the data signal and changing the depth of the bias have the same effect. Therefore, the drive amplitude can be set to an appropriate value by fixing the amplitude of the data signal, controlling the output voltage of the DC power supply 12A, and changing the S bias.

  As described above, the drive control apparatus 200 according to Embodiment 2 can control the drive amplitude to an optimal value without changing the output amplitude of the amplifier 10.

[Embodiment 3]
The drive control device 300 according to the third embodiment will be described in comparison with the drive control device 100 according to the first embodiment. FIG. 12 is a block diagram for explaining an example of the connection relationship of the drive control apparatus 300 according to the third embodiment.

  Referring to FIG. 12, drive control apparatus 300 includes an oscillation circuit 106 instead of oscillation circuit 6 of drive control apparatus 100 in addition to the configuration of drive control apparatus 100 of FIG. Instead of the synchronous detection circuit 7, a synchronous detection circuit 107 is included.

  The oscillation circuit 106 further includes a dither signal generation unit 306 and a switching unit 16a that switches a connection destination of the output signal of the dither signal.

  The synchronous detection circuit 107 further includes a synchronous detection unit 307 and a switching unit 16b that switches the connection destination of the output signal of the synchronous detection unit.

  In addition, a control unit 21 that controls the switching units 16a and 16b in synchronization, a bias storage unit 17T that holds output values of the bias control unit 8 and the amplitude control unit 9 immediately before the switching units 16a and 16b are switched, and And an amplitude storage unit 18T.

  The bias storage unit 17T and the amplitude storage unit 18T can be realized by volatile storage elements such as SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory), for example.

  The switching unit 16a includes a terminal 16a1 to which an output signal from the dither signal generation unit 306 is connected, a terminal 16a2 that is connected to an input signal to the adder 11b, and a terminal 16a3 that is connected to an amplitude adjustment terminal of the amplifier 10. including.

  On the other hand, the switching unit 16b includes a terminal 16b1 connected to the output signal from the synchronous detection unit 307, a terminal 16b2 connected to the bias control unit 8, and a terminal 16b3 connected to the amplitude control unit 9.

  The switching unit 16a, 16b is switched by the control unit 21 between the output destination of the dither signal generated by the dither signal generation unit 306 and the output destination of the synchronous detection unit, and the control of the P bias and the control of the drive amplitude are performed in a time division manner.

  An operation of drive control apparatus 300 according to Embodiment 3 will be described. In the switching units 16a and 16b, the control unit 21 selects the following two connection relationships.

  On the other hand, when the switching unit 16a selects that the terminal 16a1 and the a terminal 16a3 are connected, the switching unit 16b selects that the terminal 16b1 and the terminal 16b2 are connected. is there.

  The other connection relationship is that when the switching unit 16a is selected to connect the terminal 16a1 and the a terminal 16a2, the switching unit 16b is selected to connect the terminal 16b1 and the terminal 16b3. is there.

  In this connection relationship, the operations of the switching units 16 a and 16 b are switched in synchronization with the operation signal of the control unit 21.

  Either the bias control unit 8 or the amplitude control unit 9 is not connected to the dither signal from the dither signal generation unit 306 or the output signal from the synchronous detection unit 307 by the switching units 16a and 16b. Accordingly, the bias control output signal or the amplitude control output signal data immediately before switching from the bias storage unit 17T and the amplitude storage unit 18T corresponding to the bias control unit 8 and the amplitude control unit 9 not connected to each other is used. And control of the drive amplitude.

  For example, when the switching units 16a and 16b are connected as shown in FIG. 12 at the start of control, the dither signal generated by the dither signal generation unit 306 is input to the amplitude adjustment terminal of the amplifier 10 via the adder 11a. Is done. This dither signal is also input to the synchronous detector 307. Since the dither signal is input to the amplitude adjustment terminal of the amplifier 10, the output signal of the amplifier 10 is amplitude-modulated by the dither signal. The amplitude storage unit 18T holds a control value immediately before the start of control of the amplitude control unit 9, and the control value is used as an output signal of the amplitude control unit.

  A voltage from a DC power supply is added to this output signal and input to the semiconductor MZ modulator 2 as an S bias voltage. The output signal of the semiconductor MZ modulator 2 is converted into an electric signal by the photodiode 4, the envelope is detected by the peak detector 5, and is input to the synchronous detector 307.

  The synchronous detection unit 307 performs synchronous detection using the dither signal and the peak detection output signal from the peak detection unit 5 and outputs an error signal. The error signal is input to the bias control unit 8 by the switching unit 16b. The bias controller 8 generates a P bias voltage from the error signal and inputs it to the semiconductor MZ modulator 2. Since the control of the P bias is the same as the control shown in FIGS. 4 to 6, description thereof will not be repeated.

  FIG. 13 is a block diagram for explaining another example of the connection relationship of the drive control apparatus 300 according to the third embodiment. Referring to FIG. 13, the P bias control is repeated for a predetermined time while maintaining the connection relationship between the switching units 16 a and 16 b in FIG. 12, and then the connection relationship between the switching units 16 a and 16 b in FIG. Switch to.

  At this time, the bias storage unit 17T holds a control value immediately before the switching of the bias control unit 8, and this control value is used as an output signal of the bias control unit 8 in the subsequent control. The dither signal is input to the P bias via the adder 11b. This dither signal is also input to the synchronous detector 307. The dither signal applied to the P bias is processed by the photodiode 4 and the peak detector 5 and input to the synchronous detector 307.

  The synchronous detection unit 307 performs synchronous detection using the dither signal and the peak detection output signal from the peak detection unit 5 and outputs an error signal. The error signal is input to the amplitude control unit by the switching unit 16b. The amplitude control unit generates an amplitude control voltage from the error signal and inputs it to the amplitude control terminal of the amplifier. The control of the drive amplitude is similar to the control shown in FIGS. 7 to 9, and therefore the description will not be repeated.

  After this drive amplitude control is repeated for a certain time, the switching units 16a and 16b are switched again to the connection relationship of FIG. At this time, the amplitude storage unit 18T holds a control value immediately before the switching of the amplitude control unit 9, and this control knowledge is used as an output signal of the amplitude control unit 9 in the subsequent control. Thereafter, the connection relationship between FIGS. 12 and 13 is repeated by the control unit 21.

  As described above, in the drive control apparatus 300 according to the third embodiment, the P bias and the drive are switched by switching the connection relationship by the switching units 16a and 16b using the single dither signal generation unit 306 and the synchronous detection unit 307. The amplitude can be controlled to an optimum value, and the circuit can be simplified and the S / N ratio of the dither signal can be improved.

  Also in the third embodiment, by combining the second embodiment, the signal of the amplitude control unit can be connected to the DC power source and controlled.

  The drive control apparatus 300 according to Embodiment 3 may be a single dither signal generation unit as a signal after peak detection, and the S / N ratio of the peak detection signal is deteriorated as compared with the case where a plurality of dither signal generation units are used. There is no.

  In addition, the drive control apparatus 300 according to the third embodiment does not require a more accurate synchronous detection unit, thereby reducing the cost. Furthermore, since the drive control apparatus 300 according to the third embodiment does not need to be provided with this highly accurate synchronous detection unit, the chip size can be reduced.

  The drive control apparatus 300 according to the third embodiment does not need to increase the amplitude of the dither signal, and can maintain the main signal without degrading the quality.

[Modification of Embodiment 3]
The drive control device 300A according to the third embodiment will be described in comparison with the drive control device 300 according to the third embodiment. FIG. 14 is a block diagram illustrating a drive control apparatus 300A that is a modification of the drive control apparatus 300 according to the third embodiment.

  Referring to FIG. 14, drive control apparatus 300A includes a DC power supply 12A in place of DC power supply 12 of drive control apparatus 300 in addition to the configuration of drive control apparatus 300 of FIG. The adder 11a of the device 300 is not included. The other configuration of drive control device 300A is similar to that of drive control device 300, and therefore description thereof will not be repeated.

  This drive control device 300A is an embodiment in which the drive control device 300 of the third embodiment and the drive control device 200 of the second embodiment are combined.

  Therefore, the drive control device 300A fixes the amplitude of the data signal, controls the output voltage of the DC power supply 12A, and changes the S bias in the same manner as the drive control device 200 of the second embodiment, thereby changing the drive amplitude to an appropriate value. Can be. Since the operation of the modification of the third embodiment is the same as that of the second and third embodiments, description thereof will not be repeated.

[Embodiment 4]
The drive control device 400 according to the fourth embodiment will be described while comparing with the drive control device 100 according to the first embodiment. FIG. 15 is a block diagram showing a drive control apparatus 400 according to the fourth embodiment. Referring to FIG. 15, drive control device 400 further includes a bias storage unit 17 and an amplitude storage unit 18 in which different initial values are stored in advance, in addition to the configuration of drive control device 100 in FIG. 1.

  In the drive control device 100 of FIG. 1, the control is started without any initial value such as the control voltage being determined. However, in the case of the semiconductor MZ modulator 2, the controllable range varies depending on the wavelength and temperature. Therefore, the drive control device 400 stores different values for each wavelength or temperature in the bias storage unit 17 and the amplitude storage unit 18 and starts control using the values as initial values.

  The bias storage unit 17 and the amplitude storage unit 18 store information on the wavelength of the light source 1. For example, if the light source 1 is a wavelength tunable light source, the wavelength information can be easily obtained. If the light source 1 is not a wavelength tunable laser, the wavelength information can be obtained in advance by using a wavelength meter or the like.

  Each of the bias storage unit 17 and the amplitude storage unit 18 has a plurality of initial values. As these initial values, different values for each wavelength are prepared and stored in advance. When control is started based on the obtained wavelength information, the initial values stored in the bias storage unit 17 and the amplitude storage unit 18 are read into the bias control unit 8 and the amplitude control unit 9, respectively, and the drive control device 400 is Start control. Since subsequent operations are the same as those described in the first embodiment, description thereof will not be repeated.

  FIG. 16 is a diagram for explaining the relationship between the P bias and the optical output at two different wavelengths. Referring to FIG. 16, the vertical axis indicates the optical output [dBm], and the horizontal axis indicates the P bias voltage.

  For example, when the wavelength of a certain light source is 1550 nm, the voltage with an S bias of P1 (about 1.03 V) is the optimum point, and when the wavelength of another light source is 1590 nm, the voltage with an S bias of Q1 (0.99 V). Degree) is the optimum point.

  In the synchronous detection control, since the S bias is controlled so as to be the minimum point, the S bias is controlled near the voltage P1 when the wavelength is 1550 nm and near the voltage Q1 when the wavelength is 1590 nm. It is desirable.

  However, it is difficult to control from all the initial values to the voltages of P1 and Q1, which are the minimum points. For example, when a light source having a wavelength of 1550 nm is used and the control is started by setting the initial voltage to a voltage lower than the voltage P2 (0.81 V), the minimum point is set to a voltage lower than the potential P2. There is a possibility that it is erroneously recognized as being present, and it is controlled at a voltage lower than the voltage of P2.

  When the wavelength is 1590 nm, if control is started with an S bias voltage lower than the voltage of Q2 (0.77V) as an initial value, control is not performed to the voltage of Q1, but control is performed toward a voltage lower than the voltage of Q1. Will be.

  Thus, in the case of the semiconductor MZ modulator 2, it is difficult to control from all initial values. Therefore, first, a certain controllable range is set in advance. Therefore, by storing the initial value of which S bias voltage to start control in the bias storage unit 17 and the amplitude storage unit 18, it is possible to reliably control to the optimum point.

  Further, as shown in FIG. 16, since the controllable range differs for each wavelength, the bias storage unit 17 and the amplitude storage unit 18 can store a plurality of different values for each wavelength.

  The bias storage unit 17 and the amplitude storage unit 18 can be realized by using a nonvolatile storage element such as a flash memory.

  As described above, in the drive control device 400 according to the fourth embodiment, the bias storage unit 17 and the amplitude storage unit 18 are provided, and a plurality of initial values different for each wavelength are stored in the bias storage unit 17 and the amplitude storage unit 18 as initial values. Can be stored in advance, and the synchronous detection control is started based on the stored initial value, so that the optimum point can be controlled.

  Although the above has described the control when the wavelengths are different, it is not limited to only the wavelengths. For example, it is possible to arrange a temperature sensor and start from an initial value that varies depending on the temperature.

[Embodiment 5]
The drive control device 500 according to the fifth embodiment will be described in comparison with the drive control device 400 according to the fourth embodiment. FIG. 17 is a block diagram showing drive control apparatus 500 of the fifth embodiment. Referring to FIG. 17, in addition to drive control device 400 of FIG. 15, drive control device 500 replaces different initial values included in drive control device 400 with bias storage unit 17 and amplitude storage unit 18 stored in advance. An initial value search unit 19a for searching for an initial value for controlling the semiconductor MZ modulator 2 by the bias control unit 8 and an initial value for searching for an initial value for controlling the semiconductor MZ modulator 2 by the amplitude control unit 9 A search unit 19b is further included.

  In the drive control apparatus 400 of Embodiment 4, it is necessary to store the initial value for each wavelength in advance. On the other hand, in the drive control apparatus 500 of the fifth embodiment, the initial value is not automatically stored in advance, but the initial value is automatically searched by the initial value search units 19a and 19b, and the searched initial value is used. Start synchronous detection control.

  The operation of the drive control apparatus 500 according to the fifth embodiment will be described. The initial value search units 19a and 19b search the initial values of the bias control unit 8 and the amplitude control unit 9, respectively.

  At the start of the control operation of the drive control device 500, the initial value search units 19a and 19b sweep the voltage in the entire output range from 0 V to the maximum output possible voltage. After the sweep, the initial value search units 19a and 19b detect a range where the light output is decreasing, and set the minimum voltage (control start voltage) in the range as the initial value.

  Specifically, referring to FIG. 16 again, at the start of the control operation of drive control device 500, the initial value search units 19a and 19b have a constant voltage range from 0V to the maximum output possible voltage. Perform sweeps at intervals. P1 which is the minimum value is detected from the sweep result at this time, and control is started with the voltage of P1 (1.03V) as an initial value. Further, it is possible to further sweep the vicinity of the voltage of P1 partially at an interval narrower than the above-mentioned fixed interval by using the voltage of P1 (1.03V), and to select a minimum value again.

  As described above, by providing the initial value search units 19a and 19b in the drive control device 500 of the fifth embodiment, the initial values are stored in advance in the bias storage unit 17 and the amplitude storage as in the drive control device 400 of the fourth embodiment. The initial value is automatically searched by the initial value search units 19a and 19b without being stored in the unit 18, the initial value of the optimum point is set, and the synchronous detection control is started, so that the P bias and driving are performed. It is possible to control the amplitude to an optimum value.

[Embodiment 6]
The drive control device 600 according to the sixth embodiment will be described in comparison with the drive control device 100 according to the first embodiment. FIG. 18 is a block diagram illustrating a drive control apparatus 600 according to the sixth embodiment. Referring to FIG. 18, drive control apparatus 600 includes power supply circuit 12B instead of DC power supply 12 of drive control apparatus 100 of FIG. And the photodiode 4 are not included. The power supply circuit 12 </ b> B includes a DC power supply 312 in which a current flowing in accordance with the amount of output optical signal absorbed, and a current detection unit 22 that detects a current flowing in the DC power supply 312.

  In the drive control apparatus 100 of the first embodiment, the output light of the semiconductor MZ modulator 2 is demultiplexed by the demultiplexer 3 and the photoelectric conversion is performed by the photodiode 4.

  On the other hand, in the drive control device 600 of the sixth embodiment, the current detection unit 22 monitors the current flowing through the DC power supply 312 and detects the amount of current instead of the photodiode 4 included in the drive control device 100. The peak detection unit 5 detects an electrical signal based on this amount of current. This feedback improves the intensity of the output optical signal. That is, the DC power supply 312 is used as the S bias voltage.

  Here, the DC power supply 312 applies a voltage to the S bias that controls the drive amplitude. When a voltage is applied to the S bias, not only the phase of the semiconductor MZ modulator 2 changes, but also light absorption by the semiconductor MZ modulator 2 occurs. This is the same as the principle of the photodiode.

  The amount of light absorption also changes depending on the intensity of light passing through the semiconductor MZ modulator 2. Therefore, the DC power supply 312 detects the amount of light absorption, applies a voltage accordingly, and inputs the current amount from the DC power supply 312 detected by the current detection unit 22 to the peak detection unit 5, so that the intensity of the output optical signal is increased. Can be improved.

  Although the DC power supply 312 and the current detection unit 22 have been described individually, the DC power supply 312 can also be realized by providing the function of the current detection unit 22 inside.

  As described above, in the drive control apparatus 600 according to the sixth embodiment, the optical / electrical conversion is performed based on the light absorption amount of the semiconductor MZ modulator 2, and therefore the branching filter according to the first embodiment is used by using the power supply circuit 12B. 3 and the photodiode 4 can be omitted, and the mounting area can be further reduced. Furthermore, since the modulation signal output from the semiconductor MZ modulator 2 is not demultiplexed or the optical output intensity does not decrease, the modulation efficiency can be improved.

  As described above, by implementing each embodiment, the bias and the drive amplitude can be controlled to optimum values, and the semiconductor MZ modulator can be stably operated.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  DESCRIPTION OF SYMBOLS 1 Light source, 2A 2 modulator, 3 splitter, 4 photodiode, 5 peak detection part, 6,106 oscillation circuit, 6a, 6b, 306 dither signal generation part, 7, 107 synchronous detection circuit, 7a, 7b, 107,307 Synchronous detection unit, 8 bias control unit, 9 amplitude control unit, 10 amplifier, 11a, 11b, 11c adder, 12, 12A, 312 DC power supply, 12B power supply circuit, 13 signal electrode, 14 phase adjustment electrode, 15 Waveguide, 16a, 16b switching unit, 16a1, 16a2, 16a3, 16b1, 16b2, 16b3 terminal, 17, 17T bias storage unit, 18, 18T amplitude storage unit, 19a, 19b initial value search unit, 20A, 20B arm, 21 Control unit, 22 Current detection unit, 100, 200, 300, 300A, 400, 500, 600 Apparatus.

Claims (6)

A drive control device for a semiconductor optical modulator that receives light from a light source that emits continuous light and whose light output characteristics with respect to a drive voltage change periodically,
A peak detector that detects an electrical signal that changes in accordance with output light output from the semiconductor optical modulator;
An oscillation circuit;
A synchronous detection circuit that performs synchronous detection based on the output of the oscillation circuit and the peak detection output signal of the peak detection unit;
A bias control unit for controlling a phase bias of the semiconductor optical modulator according to an output of the synchronous detection circuit;
An amplifier for amplifying the data signal;
And it amplified the data signal that controls the control part output from said amplifier according to an output of the synchronous detection circuit,
A power supply circuit for supplying a reference voltage corresponding to the output of the control unit to the output of the amplifier;
A drive control apparatus for a semiconductor optical modulator, comprising: an adder that receives the output of the amplifier and the reference voltage and generates the drive voltage. A drive control device for a semiconductor optical modulator that receives light from a light source that emits continuous light and whose light output characteristics with respect to a drive voltage change periodically,
A peak detector that detects an electrical signal that changes in accordance with output light output from the semiconductor optical modulator;
An oscillation circuit;
A synchronous detection circuit that performs synchronous detection based on the output of the oscillation circuit and the peak detection output signal of the peak detection unit;
A bias control unit for controlling a phase bias of the semiconductor optical modulator according to an output of the synchronous detection circuit;
An amplifier for amplifying the data signal;
An amplitude control unit for controlling the amplitude of the amplified data signal output from the amplifier according to the output of the synchronous detection circuit;
A power supply circuit for supplying a reference voltage to the output of the amplifier;
An adder for receiving the output of the amplifier and the reference voltage and generating the drive voltage;
The oscillation circuit is
An oscillation unit;
A first switching unit that switches a connection destination of an output of the oscillation unit to either the amplifier or the semiconductor optical modulator;
The synchronous detection circuit is
A synchronous detector;
A second switching unit that switches a connection destination of an output of the synchronous detection unit to either the bias control unit or the amplitude control unit;
A controller for synchronously controlling the first and second switching units;
When the control unit causes the first switching unit to select the amplifier, the control unit causes the second switching unit to select the bias control unit, and the first switching unit selects the semiconductor optical modulator. When it is made to do, the drive control apparatus of the semiconductor optical modulator which makes the said 2nd switching part select the said amplitude control part. Further comprising a bias storage unit and amplitude storage unit that holds the bias control unit and each of the output values of the amplitude control section immediately before the connection of the first and the second switching unit is switched, according to claim 2 Drive control device for semiconductor optical modulator. A drive control device for a semiconductor optical modulator that receives light from a light source that emits continuous light and whose light output characteristics with respect to a drive voltage change periodically,
A peak detector that detects an electrical signal that changes in accordance with output light output from the semiconductor optical modulator;
An oscillation circuit;
A synchronous detection circuit that performs synchronous detection based on the output of the oscillation circuit and the peak detection output signal of the peak detection unit;
A bias control unit for controlling a phase bias of the semiconductor optical modulator according to an output of the synchronous detection circuit;
An amplifier for amplifying the data signal;
An amplitude control unit for controlling the amplitude of the amplified data signal output from the amplifier according to the output of the synchronous detection circuit;
A power supply circuit for supplying a reference voltage to the output of the amplifier;
An adder for receiving the output of the amplifier and the reference voltage to generate the drive voltage;
The bias control unit El Bei a first initial value search unit for searching an initial value for controlling the semiconductor optical modulator, a semiconductor optical modulator of the drive control device. 5. The drive control apparatus for a semiconductor optical modulator according to claim 4 , further comprising a second initial value search unit that searches for an initial value for the amplitude control unit to control the semiconductor optical modulator. 6. 6. The drive control of a semiconductor optical modulator according to claim 5, wherein the first and second initial value search units sweep a voltage range that can be output and set a voltage at which the optical output is minimum to an initial value. apparatus.

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