JP5659747B2 - Reset device for peak hold circuit - Google Patents

Description

  The present invention relates to a reset device for discharging a hold capacitor of a peak hold circuit.

  The peak hold circuit that holds the peak value of the input signal discharges the charge corresponding to the peak value stored in the hold capacitor and resets the held peak value by inputting the reset signal when the reset condition is satisfied. I am doing so.

  By the way, when the input signal is a pulse signal, if the pulse width (ON period) is short, the response performance of an element used in a circuit such as an operational amplifier provided in the input stage of the peak hold circuit may not catch up. In such a case, the hold capacitor cannot be sufficiently charged according to the signal level of the input signal.

  Regarding the reset of the peak hold circuit, until the difference between the voltage level of the input signal and the hold voltage of the hold capacitor falls within a predetermined range, charging is repeated without resetting the hold capacitor, and when the voltage falls within the predetermined range. Proposals for inputting a reset signal have been made in the past (for example, Patent Document 1).

JP 2002-288990 A

  However, in the conventional proposal described above, the voltage level of the input signal is used to determine the input timing of the reset signal.

  First, if the pulse width of the pulse signal is so short that the response performance of the operational amplifier cannot catch up, the hold voltage may not reach a difference within a predetermined range from the voltage level of the input signal even if the number of charges of the hold capacitor is increased. As a result, the hold capacitor continues to be not reset by the input of the reset signal, and as a result, the hold capacitor may fall into a freeze state.

  In addition, the voltage level of the input signal may not be stable and may fluctuate. In such a case, the logic for determining whether the reset signal is appropriate based on the comparison with the hold voltage of the hold capacitor becomes unstable. End up. Therefore, when the voltage level of the input signal fluctuates, the above-described conventional proposal cannot function properly.

In addition, when the input period of the input signal is short, such as a pulse signal with a short pulse width, a high-performance comparator that has a short response period and can be compared with the voltage level of the input signal is excellent. If not used, it may not be possible to compare the two.

  The present invention has been made in view of the above circumstances, and the object of the present invention is to determine whether the input signal whose peak value is to be held is a pulse signal with a short pulse width or a signal whose voltage level varies. An object of the present invention is to provide a reset device for a peak hold circuit that can output a reset signal at an appropriate timing with an inexpensive configuration that does not use a high-performance element.

In order to achieve the above object, a peak hold circuit reset device of the present invention described in claim 1 comprises:
Connects to the peak hold circuit that outputs the hold voltage of the hold capacitor until the peak value of the input signal with periodicity is held by the hold capacitor and the hold capacitor is discharged by the input of the reset signal to the reset switch element. In the reset device that outputs the reset signal to the reset switch element,
Every time the input signal is input, and means output increase amount detection which detects the increase amount before Symbol hold voltage obtained from the output of the hold capacitor,
When the pressurized volume before Symbol increased to the boosted pressure quantity detecting means has detected is equal to or less than a predetermined threshold, the reset signal output means for outputting the reset signal to the reset switch element,
It is characterized by providing.

  According to the reset device of the peak hold circuit of the present invention described in claim 1, since the input signal has periodicity, the hold voltage of the hold capacitor can be set to the period of the input signal even if the pulse width of the input signal is short. Gradually increases according to Therefore, as long as the hold capacitor is repeatedly charged every time an input signal is input, the hold voltage of the hold capacitor eventually approaches the voltage level of the input voltage. The amount of increase in the hold voltage of the hold capacitor detected each time an input signal is input decreases as the input signal is repeatedly input.

  For this reason, the increase amount of the hold voltage detected each time an input signal is input can be reliably made to reach a predetermined threshold value or less, and the reset signal can be reliably output to the reset switch element.

  Moreover, since the voltage level of the input signal is not used as a criterion for determining the output of the reset signal to the reset switch element, the hold voltage of the hold capacitor approaches the voltage level of the input signal even when the voltage level of the input signal varies greatly. A reset signal can be output at an appropriate timing.

  Further, since it is the hold voltage before and after the increase accompanying the input of the input signal that is compared when the reset signal is output, a sufficient comparison time can be ensured regardless of the input signal input period. Therefore, it is possible to use an inexpensive comparator, and therefore, it is possible to output a reset signal with an inexpensive configuration without particularly using a high-performance comparator.

  As described above, if the input signal has periodicity, even if the signal has a short pulse width or an unstable voltage level, the reset signal can be sent at an appropriate timing with an inexpensive configuration that does not use high-performance elements. Can be output.

A peak hold circuit reset device according to a second aspect of the present invention is the peak hold circuit reset device according to the first aspect of the present invention, wherein the reset signal output means is detected by the increase amount detection means. when the increment was becomes less than the predetermined threshold value with the number series continues predetermined times, and outputs the reset signal to the reset switch element.

  According to the reset device for the peak hold circuit of the present invention described in claim 2, in the reset device of the peak hold circuit of the present invention described in claim 1, the increase amount of the hold voltage accompanying the input of the input signal is a predetermined value. By satisfying the following conditions continuously a predetermined number of times, the reset signal output condition is satisfied for the first time. For this reason, after confirming that the hold voltage of the hold capacitor is more reliably saturated, the reset signal can be output at a more appropriate timing.

  According to the reset device of the peak hold circuit of the present invention, even if the input signal to hold the peak value is a periodic signal with a short pulse width or a signal whose voltage level is not stable, A reset signal can be output at an appropriate timing with an inexpensive configuration that does not use an element.

It is a circuit diagram which shows the peak hold circuit which connected the reset apparatus which concerns on one Embodiment of this invention. 2 is a graph showing a relationship between an input signal input to the peak hold circuit of FIG. 1 and a hold voltage of a hold capacitor. 3 is a flowchart illustrating an example of an operation flow by the FPGA circuit of FIG. 1. 6 is a flowchart showing another example of the operation flow by the FPGA circuit of FIG. 1.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing a peak hold circuit to which a reset device according to an embodiment of the present invention is connected, and FIG. 2 shows a relationship between an input signal inputted to the peak hold circuit of FIG. 1 and a hold voltage of a hold capacitor. It is a graph.

  In the peak hold circuit 1 of the present embodiment shown in FIG. 1, an operational amplifier OP1 to which an input signal Vin is input is connected to the anode side of the diode D, and a hold capacitor C is connected between the cathode of the diode D and the ground (earth). Is connected to the collector-emitter of an NPN transistor T1 (corresponding to the reset switch element in the claims), and the operational amplifier outputs the hold voltage of the hold capacitor C at a low impedance at the connection point between them and the cathode of the diode D It has a general configuration with OP2 connected.

  When the voltage level of the inverted signal of the input signal Vin input to the operational amplifier OP1 is higher than the hold voltage of the hold capacitor C, the output of the operational amplifier OP1 becomes + (plus), and the diode D is biased in the forward direction. Therefore, the operational amplifier OP1 serves as a buffer having a gain of 1, and the hold capacitor is charged by the inverted signal of the input signal Vin.

  On the other hand, when the voltage level of the inverted signal of the input signal Vin becomes smaller than the hold voltage of the hold capacitor C, the output of the operational amplifier OP1 becomes-(minus), and the diode D is biased in the reverse direction. Therefore, the hold capacitor C is disconnected from the operational amplifier OP1 and is in an open state. As a result, the hold capacitor C is held at the hold voltage up to that time.

  Incidentally, the input signal Vin input to the operational amplifier OP1 is a low-active pulse signal having periodicity as shown in the upper half of FIG. 2, and has a pulse width (on period) of 10 ns or less. .

  Thus, since the pulse width (ON period) of the input signal Vin is extremely short, even if the input signal Vin is input to the operational amplifier OP1 once (one pulse), as shown in the lower half of FIG. The hold voltage of C does not reach the voltage level of the inverted signal of the input signal Vin at once.

  Therefore, in the present embodiment, as shown in FIG. 1, the hold is performed by an FPGA (Field Programmable Gate Array) circuit 5 (corresponding to the reset device in the claims) connected to the operational amplifier OP2 through the A / D conversion circuit 3. The reset signal is output to the base of the reset NPN transistor T1 after the hold voltage of the capacitor C approaches the voltage level of the inverted signal of the input signal Vin.

  The FPGA circuit 5 is configured by connecting a large number of logic cells each having a look-up table (LUT) and a flip-flop (FF) to each other or an I / O interface circuit through internal wiring.

  The FPGA circuit 5 is configured to perform a desired process defined by the bit stream data by loading the bit stream data, which is a program file, into the configuration memory and operating the logic cell according to the load. In the case of the SRAM type FPGA circuit 5, the bit stream data is read from the external nonvolatile memory 7 (flash memory, EEPROM, etc.) and loaded into the configuration memory.

  Then, in the FPGA circuit 5, the voltage level of the hold voltage of the hold capacitor C input as a digital signal from the A / D conversion circuit 3 is changed in accordance with the input of the input signal Vin (shift from the off period to the on period). It is designed to obtain the difference between the voltage levels before and after the increase by the internal comparator 5a each time it increases.

  The FPGA circuit 5 is designed to output a reset signal to the base of the NPN transistor T1 when the difference obtained by the comparator 5a is equal to or less than a predetermined threshold value.

  Note that the predetermined threshold value is set to a value close to “0” suitable for determining that the hold voltage of the hold capacitor C is saturated.

  Next, the flow of operations performed by the FPGA circuit 5 having the above-described configuration will be described with reference to the flowchart of FIG. First, the FPGA circuit 5 executes an initialization process with the start-up when the power is turned on (step S1). After execution of the initialization process, the FPGA circuit 5 executes the operations after step S5 while the power is on (YES in step S3).

  First, in the FPGA circuit 5, when an increase in the voltage level of the hold voltage of the hold capacitor C input as a digital signal from the A / D conversion circuit 3 is detected (YES in step S5), the difference in voltage level before and after the increase is detected. Is obtained by the comparator 5a (step S7).

  If the obtained difference is not less than the predetermined threshold value (NO in step S9), the process returns to step S3. On the other hand, if the obtained difference is equal to or smaller than the predetermined threshold value (YES in step S9), a reset signal is output (step S11), and the process returns to step S3.

  As apparent from the above description, in the present embodiment, the increase detection means in the claims is constituted by the FPGA circuit 5 when performing the operation of step S5 in the flowchart of FIG. Further, in the present embodiment, the reset signal output means in the claims is constituted by the FPGA circuit 5 when performing the operations of steps S7 to S11 in FIG.

  When the FPGA circuit 5 of this embodiment configured as described above is used for outputting a reset signal to the peak hold circuit 1, the amount of increase in the hold voltage of the hold capacitor C accompanying the input of the input signal Vin is saturated with the hold voltage. The hold capacitor C is reset for the first time and the hold voltage is discharged when the value falls below a predetermined threshold suitable for determination.

  For example, in the lower half of the graph of FIG. 2, when the hold capacitor C is continuously charged six times by the periodic input of the input signal Vin, the difference between the hold voltages before and after the increase becomes less than a predetermined threshold value. The hold capacitor C is reset by the reset signal. The hold voltage at the time of reset of the hold capacitor C is far more than the hold voltage at the time of the first charge of the hold capacitor C, for example, and is the inverted signal of the input signal Vin shown at the left end of the lower half graph of FIG. The value is close to the peak value of the voltage level.

  That is, when the input signal is periodically input, the hold voltage of the hold capacitor C gradually increases even if the input period of the input signal Vin is short. Therefore, as long as the charging of the hold capacitor C is repeated every time the input signal Vin is input, the hold voltage of the hold capacitor C eventually approaches the voltage level of the input signal Vin. The increase amount of the hold voltage of the hold capacitor C detected each time the input signal Vin is input decreases as the input of the input signal Vin is repeated.

  For this reason, every time the input signal Vin is input to the operational amplifier OP1, the increase amount of the hold voltage detected by the FPGA circuit 5 can be surely reached below a predetermined threshold value. As a result, the hold capacitor C is charged until the hold voltage reaches a value that is much closer to the peak value of the voltage level of the inverted signal of the input signal Vin than the hold voltage at the first charging time of the hold capacitor C. At this point, the reset signal can be reliably output to the reset NPN transistor T1.

  In addition, since the voltage level of the input signal Vin is not used as a criterion for determining the output of the reset signal for the NPN transistor T1, the hold voltage of the hold capacitor C is the voltage of the input signal Vin even if the voltage level of the input signal Vin varies greatly. A reset signal can be output at an appropriate timing approaching the level.

  Further, since the comparator 5a of the FPGA circuit 5 compares the reset signal output with the hold voltage before and after the increase accompanying the input of the input signal Vin to the operational amplifier OP1, the input period of the input signal Vin (ON period) Regardless of the length, it is possible to ensure sufficient time for comparison. Therefore, it is possible to use an inexpensive comparator as the comparator 5a. Therefore, it is possible to output a reset signal with an inexpensive configuration without particularly using a high-performance comparator.

  As described above, even if the input signal Vin is a signal with a short pulse width or a voltage level that is not stable, the reset signal can be output at an appropriate timing with an inexpensive configuration that does not use a high-performance element. Can do.

  In the above-described embodiment, the FPGA circuit 5 is configured to output a reset signal immediately when the increase in the voltage level of the hold voltage of the hold capacitor C due to the input of the input signal Vin falls below a predetermined threshold value. The case where was configured was explained. However, the FPGA circuit 5 may be configured so that the reset signal is output only when the increase amount of the voltage level of the hold voltage is continuously equal to or less than a predetermined threshold value a predetermined number of times.

  The flow of operations performed by the FPGA circuit 5 in such a configuration will be described with reference to the flowchart of FIG.

  First, the FPGA circuit 5 performs a process of resetting the count value of the internal counter to zero in the initialization process of step S1. After execution of the initialization process, the FPGA circuit 5 executes the operations after step S5 while the power is on (YES in step S3).

  Then, after performing the operations of step S5 and step S7 in FIG. 3, if the difference in voltage level of the hold voltage before and after the increase obtained by the comparator 5a is not less than a predetermined threshold value (NO in step S9), After resetting the count value of the internal counter to zero (step S10a), the process returns to step S3. On the other hand, when the obtained difference is equal to or smaller than the predetermined threshold value (YES in step S9), the count value of the internal counter is incremented by “1” (step S10b).

  Furthermore, if the count value has not reached the specified value (the value specifying the predetermined number of times in the claims) (NO in step S10c), the process returns to step S3, and if the count value has reached the specified value (step In step S10c, a reset signal is output (step S11). After the count value of the internal counter is reset to zero (step S13), the process returns to step S3.

  As is clear from the above description, in this case, the reset signal output means in the claims is constituted by the FPGA circuit 5 when performing a series of operations from step S7 to step S13 in FIG. Become.

  If the FPGA circuit 5 is configured in this way, the reset signal output condition is satisfied for the first time by continuously satisfying the condition that the increase amount of the hold voltage accompanying the input of the input signal Vin is a predetermined value or less continuously. become. For this reason, after confirming that the hold voltage of the hold capacitor C is more reliably saturated, the reset signal can be output at a more appropriate timing.

  In the above-described embodiment, the reset device is configured by the FPGA circuit 5. However, the reset device is configured by a combination of a programmable device other than the FPGA circuit 5 such as a microcomputer and a comparator (comparator). Also good.

DESCRIPTION OF SYMBOLS 1 Peak hold circuit 3 A / D conversion circuit 5 FPGA circuit 5a Comparator 7 Non-volatile memory C Hold capacitor D Diode OP1 Operational amplifier OP2 Operational amplifier T1 NPN type transistor Vin Input signal

Claims (2)

Connects to the peak hold circuit that outputs the hold voltage of the hold capacitor until the peak value of the input signal with periodicity is held by the hold capacitor and the hold capacitor is discharged by the input of the reset signal to the reset switch element. In the reset device that outputs the reset signal to the reset switch element,
Every time the input signal is input, an increase amount detecting means for detecting an increase amount before Symbol hold voltage obtained from the output of the hold capacitor,
Reset signal output means for outputting the reset signal to the reset switch element when the increase amount detected by the increase amount detection means is less than or equal to a predetermined threshold;
A reset device for a peak hold circuit, comprising:   The reset signal output means outputs the reset signal to the reset switch element when the increase amount detected by the increase amount detection means continuously falls below the predetermined threshold value a predetermined number of times. The peak hold circuit resetting device according to claim 1, wherein:

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