JP5656462B2 - Surface mount semiconductor package - Google Patents

Surface mount semiconductor package Download PDF

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JP5656462B2
JP5656462B2 JP2010135238A JP2010135238A JP5656462B2 JP 5656462 B2 JP5656462 B2 JP 5656462B2 JP 2010135238 A JP2010135238 A JP 2010135238A JP 2010135238 A JP2010135238 A JP 2010135238A JP 5656462 B2 JP5656462 B2 JP 5656462B2
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terminal
connection
semiconductor package
lead
surface mount
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JP2012004177A (en
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山田　博之
博之 山田
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Panasonic Corp
Panasonic Holdings Corp
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Panasonic Corp
Matsushita Electric Industrial Co Ltd
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Description

本発明は、半導体パッケージの端子形状に関し、特にプリント基板へ表面実装される多端子半導体パッケージの多端子化及び端子ピッチを狭くする技術に関する。   The present invention relates to a terminal shape of a semiconductor package, and more particularly to a technique for increasing the number of terminals of a multi-terminal semiconductor package surface-mounted on a printed circuit board and narrowing a terminal pitch.

現在、プリント基板へ表面実装される多端子半導体パッケージ（以下表面実装型半導体パッケージという）として、例えば、図１に示すようなＬＧＡ（Ｌａｎｄ Ｇｒｉｄ Ａｒｒａｙ）と呼ばれる半導体パッケージの形態があり、接続端子１０は、多数配置する為に、格子状に配列されている。   At present, as a multi-terminal semiconductor package (hereinafter referred to as a surface-mount semiconductor package) that is surface-mounted on a printed circuit board, for example, there is a semiconductor package called LGA (Land Grid Array) as shown in FIG. Are arranged in a lattice pattern so as to be arranged in large numbers.

特開平０６−２６０５６６号公報JP-A-06-260566

図４は、ＬＧＡの接続端子の形状を示す図である。１０ｋ、１０ｌ、１０ｍ、１０ｎ、１０ｏは接続端子である。２０は実効的な接続端子面積、３０はレジスト開口である。接続端子１０ｌ〜１０ｏは、半導体パッケージ内部の半導体チップへの接続用引き出し配線４０が引き出しされている形状を有している。   FIG. 4 is a diagram showing the shape of the connection terminal of the LGA. 10k, 10l, 10m, 10n, 10o are connection terminals. 20 is an effective connection terminal area, and 30 is a resist opening. Each of the connection terminals 10l to 10o has a shape in which a connection lead wire 40 for connection to a semiconductor chip inside the semiconductor package is drawn out.

接続端子の形状は、半導体チップへの電気的接続内容によって、接続用引き出し線４０を有しない接続端子１０ｋ、１本の接続用引き出し線４０を有する端子１０ｌ、２本の接続用引き出し線４０を有する端子１０ｍ、３本の接続用引き出し線４０を有する端子１０ｎ、４本の接続用引き出し線４０を有する端子１０ｏが存在し、レジスト開口３０により、面積制限を受けた状態での実効的な接続端子面積２０は、端子毎に異なっている。   The shape of the connection terminal is such that the connection terminal 10k having no connection lead wire 40, the terminal 10l having one connection lead wire 40, and the two connection lead wires 40 depending on the electrical connection contents to the semiconductor chip. 10m having a terminal 10n having three connection lead wires 40 and a terminal 10o having four connection lead wires 40, and effective connection in a state where the area is limited by the resist opening 30. The terminal area 20 is different for each terminal.

このように構成された従来の表面実装型半導体においては、端子毎引き出し形状が異なり、実効的な接続端子面積２０が端子毎に異なっている。その為、端子毎に最適なはんだ量が異なり、供給するはんだ量を調整する必要がある。   In the conventional surface-mount type semiconductor configured as described above, the lead-out shape for each terminal is different, and the effective connection terminal area 20 is different for each terminal. Therefore, the optimal amount of solder differs for each terminal, and the amount of solder to be supplied needs to be adjusted.

本発明は、プリント基板へ表面実装される表面実装型半導体パッケージにおいて、接続信頼性の高い端子形状を提供するものである。本発明の表面実装型半導体パッケージは、基板上に複数の接続端子を有する。複数の接続端子は、レジスト開口により制限された実効的な接続端子面積が同一面積となり且つ接続用引き出し線の本数が互いに異なる複数の接続端子を含む。例えば、表面実装型半導体パッケージは、半導体パッケージ内部の半導体チップへの接続用引き出し配線４０とは別に、擬似的な引き出し配線５０を設け、端子毎の実効的な接続端子面積２０を均一とする。複数の接続端子１０には、接続用引き出し線の本数が互いに異なる複数の接続端子１０ａ〜１０ｅが存在する。 The present invention provides a terminal shape with high connection reliability in a surface-mount semiconductor package that is surface-mounted on a printed circuit board . The surface mount semiconductor package of the present invention has a plurality of connection terminals on a substrate. The plurality of connection terminals include a plurality of connection terminals having the same effective connection terminal area limited by the resist opening and having different numbers of connection lead lines. For example, in the surface-mount type semiconductor package, a pseudo lead wire 50 is provided separately from the lead wire 40 for connection to the semiconductor chip inside the semiconductor package, and the effective connection terminal area 20 for each terminal is made uniform. The plurality of connection terminals 10 include a plurality of connection terminals 10a to 10e having different numbers of connection lead lines.

端子毎の実効的な接続端子面積２０が均一となり、端子毎の最適なはんだ量が一定となる。その結果として、接続信頼性が向上する。   The effective connection terminal area 20 for each terminal becomes uniform, and the optimum amount of solder for each terminal becomes constant. As a result, connection reliability is improved.

表面実装型半導体パッケージの端子が設けられた面を正面とする正面図Front view of the surface-mounted semiconductor package with the terminals provided on the front 実施の形態１の端子形状を示す図The figure which shows the terminal shape of Embodiment 1. 実施の形態２の端子形状を示す図The figure which shows the terminal shape of Embodiment 2. 従来の表面実装型半導体パッケージの端子形状Terminal shape of conventional surface mount semiconductor package

以下に、本発明の実施の形態について、図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

（実施の形態１）
図１は本実施形態における表面実装型半導体パッケージを示しており、表面実装型半導体パッケージの接続端子を設けた側を正面とする正面図を示している。 (Embodiment 1)
FIG. 1 shows a surface-mounted semiconductor package according to the present embodiment, and shows a front view with the side provided with connection terminals of the surface-mounted semiconductor package as the front.

図２は本実施形態における端子形状を示している。   FIG. 2 shows the terminal shape in the present embodiment.

図においては、１は接続端子１０を設けた表面実装型半導体パッケージであり、１つの面にはプリント基板へ表面実装する際、はんだ等により接続を行なう為の接続端子１０が設けられている。   In the figure, reference numeral 1 denotes a surface mount type semiconductor package provided with a connection terminal 10, and one surface is provided with a connection terminal 10 for connection by soldering or the like when surface mounting is performed on a printed circuit board.

接続端子１０には、その電気的な機能により、接続用引き出し線４０を有しない端子１０ａ、１本の接続用引き出し線４０を有する端子１０ｂ、２本の接続用引き出し線４０を有する端子１０ｃ、３本の接続用引き出し線４０を有する端子１０ｄ、４本の接続用引き出し線４０を有する端子１０ｅが存在し、実効的な接続端子面積２０はレジスト開口３０によって、制限される。   The connection terminal 10 has a terminal 10a having no connection lead wire 40, a terminal 10b having one connection lead wire 40, a terminal 10c having two connection lead wires 40, due to its electrical function. There are a terminal 10 d having three connection lead lines 40 and a terminal 10 e having four connection lead lines 40, and an effective connection terminal area 20 is limited by the resist opening 30.

端子１０ａには４箇所の擬似的な引き出し線５０が、端子ｂには３箇所の擬似的な引き出し線５０が、端子ｃには２箇所の擬似的な引き出し線５０が、端子ｄには１箇所の擬似的な引き出し線５０が設けられており、レジスト開口３０により制限を受ける実効的な接続端子面積２０は全て同一面積を有している。   The terminal 10a has four pseudo lead lines 50, the terminal b has three pseudo lead lines 50, the terminal c has two pseudo lead lines 50, and the terminal d has one pseudo lead line 50. Pseudo lead lines 50 are provided at locations, and the effective connection terminal areas 20 limited by the resist openings 30 have the same area.

なお、擬似的な引き出し線５０の形状は、実効的な接続端子面積２０が同一となるのであれば、線状の形状である必要は無い。   Note that the shape of the pseudo lead wire 50 is not necessarily a linear shape as long as the effective connection terminal area 20 is the same.

（実施の形態２）
図３は本実施形態における端子形状を示している。接続端子１０はレジスト開口３０より大きな形状を有しており、接続用引き出し線４０を有しない端子１０ｆ、１本の接続用引き出し線４０を有する端子１０ｇ、２本の接続用引き出し線４０を有する端子１０ｈ、３本の接続用引き出し線４０を有する端子１０ｉ、４本の接続用引き出し線４０を有する端子１０ｊいずれも実効的な接続端子面積２０は全て同一面積を有している。 (Embodiment 2)
FIG. 3 shows the terminal shape in the present embodiment. The connection terminal 10 has a shape larger than that of the resist opening 30, and has a terminal 10f having no connection lead line 40, a terminal 10g having one connection lead line 40, and two connection lead lines 40. The terminal 10h, the terminal 10i having three connection lead lines 40, and the terminal 10j having four connection lead lines 40 all have the same effective connection terminal area 20.

本発明は、半導体パッケージの端子形状に関し、特にプリント基板へ表面実装される表面実装型半導体パッケージの多端子化及び端子ピッチを狭くする技術に関する。   The present invention relates to a terminal shape of a semiconductor package, and more particularly to a technique for increasing the number of terminals and reducing a terminal pitch of a surface-mount semiconductor package that is surface-mounted on a printed circuit board.

１ 表面実装型半導体パッケージ
１０ 接続端子
１０ａ〜e 本発明の実施形態１による接続端子
１０ａ 半導体パッケージ内部の半導体チップへの接続用引き出し線を有しない端子
１０ｂ 半導体パッケージ内部の半導体チップへの接続用引き出し線を１本有する端子
１０ｃ 半導体パッケージ内部の半導体チップへの接続用引き出し線を２本有する端子
１０ｄ 半導体パッケージ内部の半導体チップへの接続用引き出し線を３本有する端子
１０ｅ 半導体パッケージ内部の半導体チップへの接続用引き出し線を４本有する端子
１０ｆ〜ｊ 本発明の実施形態２による接続端子
１０ｆ 半導体パッケージ内部の半導体チップへの接続用引き出し線を有しない端子
１０ｇ 半導体パッケージ内部の半導体チップへの接続用引き出し線を１本有する端子
１０ｈ 半導体パッケージ内部の半導体チップへの接続用引き出し線を２本有する端子
１０ｉ 半導体パッケージ内部の半導体チップへの接続用引き出し線を３本有する端子
１０ｊ 半導体パッケージ内部の半導体チップへの接続用引き出し線を４本有する端子
１０ｋ〜ｏ 従来の実施形態による接続端子
１０ｋ 半導体パッケージ内部の半導体チップへの接続用引き出し線を有しない端子
１０ｌ 半導体パッケージ内部の半導体チップへの接続用引き出し線を１本有する端子
１０ｍ 半導体パッケージ内部の半導体チップへの接続用引き出し線を２本有する端子
１０ｎ 半導体パッケージ内部の半導体チップへの接続用引き出し線を３本有する端子
１０ｏ 半導体パッケージ内部の半導体チップへの接続用引き出し線を４本有する端子
２０ 実効的な接続端子面積
３０ レジスト開口
４０ 半導体パッケージ内部の半導体チップへの接続用引き出し線
５０ 擬似的な引き出し線 DESCRIPTION OF SYMBOLS 1 Surface mount type semiconductor package 10 Connection terminal 10a-e Connection terminal by Embodiment 1 of this invention 10a Terminal which does not have a lead-out line for connection to semiconductor chip inside semiconductor package 10b Lead-out for connection to semiconductor chip inside semiconductor package Terminal having one line 10c Terminal having two lead wires for connection to a semiconductor chip inside the semiconductor package 10d Terminal having three lead wires for connecting to the semiconductor chip inside the semiconductor package 10e To the semiconductor chip inside the semiconductor package Terminals 10f to j having four lead wires for connection 10f to j Connection terminals 10f according to the second embodiment of the present invention 10f Terminals having no lead wire for connection to the semiconductor chip inside the semiconductor package 10g For connection to the semiconductor chip inside the semiconductor package Terminal with one lead wire 0h Terminal having two lead wires for connection to a semiconductor chip inside the semiconductor package 10i Terminal having three lead wires for connecting to the semiconductor chip inside the semiconductor package 10j Lead wire for connecting to the semiconductor chip inside the semiconductor package Four terminals 10k to o Connection terminal 10k according to the conventional embodiment 10k Terminal that does not have a lead wire for connection to a semiconductor chip inside a semiconductor package 10l Terminal 10m that has one lead wire for connection to a semiconductor chip inside a semiconductor package 10m 10n terminal having two lead wires for connection to the semiconductor chip inside the semiconductor package 10n terminal having three lead wires for connecting to the semiconductor chip inside the semiconductor package 10o 4 lead wires for connecting to the semiconductor chip inside the semiconductor package This terminal has 20 effective Connecting terminal area 30 resist opening 40 connecting a lead wire for the semiconductor package inside of the semiconductor chip 50 pseudo lead wire

Claims (2)

基板上に複数の接続端子を有する表面実装型半導体パッケージであって、
前記複数の接続端子が、レジスト開口により制限された実効的な接続端子面積が同一面積となり且つ接続用引き出し線の本数が互いに異なる複数の接続端子を含むように構成され、
擬似的な引き出し線を設けることにより、実効的な接続端子面積を全て同一面積もしくは同一面積となるように設計された表面実装型半導体パッケージ。 A surface mount semiconductor package having a plurality of connection terminals on a substrate,
The plurality of connection terminals are configured to include a plurality of connection terminals in which the effective connection terminal area limited by the resist opening is the same area and the number of connection lead lines is different from each other,
By providing a pseudo-lead line, surface mount semiconductor package designed so that all the effective connection terminal area the same area or the same area. 基板上に複数の接続端子を有する表面実装型半導体パッケージであって、
前記複数の接続端子が、レジスト開口により制限された実効的な接続端子面積が同一面積となり且つ接続用引き出し線の本数が互いに異なる複数の接続端子を含むように構成され、
接続端子をレジスト開口より大きくすることにより、実効的な接続端子面積を全て同一面積もしくは同一面積となるように設計された表面実装型半導体パッケージ。 A surface mount semiconductor package having a plurality of connection terminals on a substrate,
The plurality of connection terminals are configured to include a plurality of connection terminals in which the effective connection terminal area limited by the resist opening is the same area and the number of connection lead lines is different from each other,
By larger than resist opening the connection terminals, surface mount semiconductor package designed so that all the effective connection terminal area the same area or the same area.
JP2010135238A 2010-06-14 2010-06-14 Surface mount semiconductor package Active JP5656462B2 (en)

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JPH08340170A (en) * 1995-06-12 1996-12-24 Ibiden Co Ltd Printed-wiring board
KR100216839B1 (en) * 1996-04-01 1999-09-01 김규현 Solder ball land structure of bga semiconductor package
JPH10313167A (en) * 1997-05-12 1998-11-24 Canon Inc Wiring board
JPH11354680A (en) * 1998-06-11 1999-12-24 Sony Corp Printed wiring board and semiconductor package using the same
KR100368025B1 (en) * 2000-09-26 2003-01-15 삼성전자 주식회사 Ciruict board having center-directional package land types and ball grid array package using the circuit board
JP2003324168A (en) * 2002-04-26 2003-11-14 Mitsui Chemicals Inc Printed wiring board for mounting semiconductor integrated circuit
JP3856130B2 (en) * 2002-10-11 2006-12-13 セイコーエプソン株式会社 Semiconductor device
JP4639964B2 (en) * 2005-05-31 2011-02-23 凸版印刷株式会社 Wiring board manufacturing method
JP4956173B2 (en) * 2006-12-19 2012-06-20 新光電気工業株式会社 Flip chip mounting board

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