JP5650497B2 - Refresh control device, radio receiver, and semiconductor integrated circuit - Google Patents

Description

  The present invention relates to a refresh control device, a wireless receiver, and a semiconductor integrated circuit that generate a refresh trigger for requesting execution of a refresh operation for a volatile memory that needs a refresh operation to hold data.

  In recent years, multi-functionalization of wireless receivers equipped with a radio tuner is progressing. In particular, in consumer audio and car audio product fields, CD and DVD playback functions, USB memory and SD memory card connection functions in addition to radio tuners, and in-vehicle navigation functions have been greatly expanded compared to conventional products. The range of products is expanding. Many of these extended functions are realized by highly integrated semiconductor digital circuits.

  In such a background, there is a problem that harmonic components of various digital signals become EMI noise and affect the radio frequency band. There are cases where EMI noise propagates via a power supply, a GND line, and the like, and cases where the EMI noise propagates from space due to electrostatic coupling and electromagnetic coupling to the antenna input line.

  Methods for avoiding these EMI noises that interfere with radio reception by using noise countermeasure parts such as capacitors and ferrite beads and circuit countermeasures for noise generation sources have been studied.

  As a representative example, Patent Document 1 discloses a technique for spectrum-spreading a clock signal of a digital circuit and reducing a peak value of a noise spectrum. Patent Document 2 discloses a technique for shifting the clock frequency in accordance with the reception frequency. These techniques are effective techniques for noise suppression.

  On the other hand, digital processing of radio tuners has also progressed, and integration of a tuner unit into a system LSI (Large Scale Integration) has been realized using a complementary metal oxide semiconductor (CMOS) circuit.

  Conventionally, a structure in which a small pack module of an analog circuit is configured and external noise can be blocked by surrounding the pack module with an iron plate has been the mainstream.

  However, by realizing integration of the tuner unit in the system LSI, it is possible to mount the digital high-performance LSI and the wireless receiving unit on the same substrate with high density. Therefore, the problem of noise in radio reception cannot be further separated.

  In LSI digital processing circuits that realize high functions, as the speed and integration increase, many of the memories used require a large capacity. Therefore, DRAM (Dynamic Random Access Memory) is used in many systems. The DRAM is mounted in the system by a configuration in which the DRAM is arranged in the vicinity of the LSI or a configuration in which the DRAM is built in the LSI.

  A DRAM stores information by storing electric charge in a capacitive element in a memory cell. In the DRAM, in order to hold the information stored in the memory cell, a refresh operation is required to read and rewrite the stored information at regular time intervals.

  In a general DRAM, data is held by performing refresh access a predetermined number of times within a certain period. Specifically, a refresh operation is performed by selecting a word line while circulating in the DRAM.

  Patent Document 3 discloses a technique related to a refresh operation for effectively using a memory that requires refresh. Specifically, a refresh request is made at a predetermined time interval, and when an access request from a device using the memory overlaps with a refresh request, processing for the access request is given priority in principle. In this process, when the number of unprocessed requests for a refresh request reaches a predetermined value, the refresh process is prioritized.

Japanese Patent No. 2756739 Japanese Patent No. 3122102 Japanese Patent Publication No. 7-40432

  However, the conventional refresh control method has the following problems.

  During the refresh operation of the DRAM, it is necessary to precharge the internal data lines and set the threshold voltage of the sense amplifier (the threshold voltage for distinguishing the voltage between 1 and 0). At this time, a large current flows when the internal data line is precharged, and EMI noise occurs due to power supply fluctuations of the power supply line and the GND line.

  FIG. 19 is a block diagram showing a configuration of a general wireless receiver 5000. As shown in FIG.

  Referring to FIG. 19, wireless receiver 5000 includes a memory controller 10, a DRAM 20, an antenna 30, a tuner unit 31, and a CPU (Central Processing Unit) 32.

  The tuner unit 31 receives a radio signal via the antenna 30. The CPU 32 controls the tuner unit 31 and the memory controller 10.

  The memory controller 10 makes either a refresh operation request or a memory access request to the DRAM 20. Here, it is assumed that memory access to the DRAM 20 is stopped and the DRAM 20 is performing a refresh operation.

  In this case, the cycle of the refresh request generated in the memory controller 10 in order to request memory access to the DRAM 20 is as shown in FIG.

In FIG. 20, one refresh request corresponds to one trigger (pulse). That is, the refresh request cycle is a fixed cycle. Here, a refresh request cycle as a trigger (pulse) is T _ref . Further, it is assumed that T _ref = 1 / F _ref . In this case, the frequency spectrum of the signal having the period T _ref is as shown in FIG.

In this case, the signal of the period T _{ref is} a signal indicating a fundamental wave of the frequency F _ref and a harmonic that is an integral multiple of F _ref .

  When the generation period of the refresh request as a trigger (pulse) is a constant period, the level of noise due to the refresh request is large. As a result, the level of the EMI noise is also increased.

  In this case, when each component in the wireless receiver 5000 is arranged on a common substrate or in one semiconductor integrated circuit, a large level of EMI noise generated in the DRAM 20 is caused by a common GND line or air path. Is transmitted to the tuner unit 31. For this reason, the reception quality of the tuner unit 31 deteriorates.

  That is, if the trigger cycle is a constant cycle to request a refresh operation of the memory, there is a problem that a problem due to a large level of noise caused by the trigger occurs. An example of the problem is deterioration of reception quality of the tuner unit 31.

  The present invention has been made to solve the above-described problems, and provides a refresh control device and the like that can reduce the level of noise caused by a trigger cycle for requesting a memory refresh operation. The purpose is to do.

  In order to solve the above-described problem, a refresh control device according to an aspect of the present invention requests a memory access request to a volatile memory that requires a refresh operation to hold data, and performs the refresh operation. An arbitration function unit that arbitrates a refresh trigger for the data, and a regulation for holding data in the volatile memory so as to satisfy a refresh rate regulation that defines a necessary number of executions of the refresh operation per predetermined time And a trigger generation unit for generating the refresh trigger at a non-constant period.

  That is, the refresh control device arbitrates a memory access request to the volatile memory and a refresh trigger for requesting execution of the refresh operation, and the refresh trigger is set so as to satisfy a refresh rate regulation. A trigger generation unit that generates at a non-constant period.

  That is, the trigger generation unit generates a refresh trigger for requesting execution of the refresh operation at a non-constant period.

  Here, the level of noise caused by the trigger generated at a non-constant period is lower than the level of noise caused by the trigger generated at a constant period.

  For this reason, the refresh control device according to one aspect of the present invention is caused by a trigger that generates a noise level caused by a trigger cycle for requesting a memory refresh operation at a constant cycle while satisfying a refresh rate rule. The noise level can be reduced.

  Preferably, the arbitration function unit includes a refresh request unit that outputs a refresh request for requesting execution of the refresh operation based on the refresh trigger generated by the trigger generation unit, and the refresh request unit includes: An arbitration unit that arbitrates the output refresh request and the access request;

  Preferably, the trigger generation unit is a base period counter that sequentially indicates from a first value to a second value larger than the first value in a base period that satisfies the refresh rate rule, and A base period counter that shows the same value for each base period, and any value from the first value to the second value that is different for each base period, for each base period A coincidence timing that is a timing at which a comparison value generation unit output as a comparison value, a value indicated by the base period counter coincides with a latest comparison value output from the comparison value generation unit, and the coincidence timing is detected. And a coincidence detection unit that generates the refresh trigger.

  Preferably, the comparison value generation unit holds the comparison value and outputs the held comparison value, and the comparison value holding unit holds the comparison value holding unit for each base period. An addition unit that performs an addition process for adding an addition value to the comparison value, and a first calculation value calculated by the addition process is greater than the second value each time the addition unit performs the addition process. A limit processing unit that determines whether or not the value is larger, and the limit processing unit further determines the second value from the first value when the first calculated value is larger than the second value. Limit processing is performed to subtract the number up to the first calculated value, and the second calculated value calculated by the limit processing is transmitted as the latest comparison value to the comparison value holding unit, If the calculated value of 1 is less than or equal to the second value, the first value The output value is transmitted as the latest comparison value to the comparison value holding unit, and the comparison value holding unit is transmitted from the limit processing unit instead of the held comparison value for each base period. The latest comparison value is retained.

  Preferably, the comparison value generation unit holds the comparison value, outputs a comparison value holding unit that holds the comparison value, holds an addition value, and holds it for each base period. An added value holding unit that outputs the latest added value, and the latest added value held by the added value holding unit to the comparison value held in the comparison value holding unit for each base period An addition unit that performs addition processing for adding values, and each time the addition unit performs the addition processing, it is determined whether or not the first calculated value calculated by the addition processing is greater than the second value. A first determination unit; a second determination unit that determines whether the latest addition value output by the addition value holding unit is the first value or the second value; and the addition value holding. Each time the latest addition value is output from the unit, the addition value is used. An arithmetic unit for calculating, and when the addition value held in the addition value holding unit is the first value, the second determination unit further sets the addition value to the second value. A process of incrementing the addition value by 1 for each base period until the time period elapses, and a process of transmitting the latest addition value to the addition value holding unit each time the addition value is incremented by 1, When the addition value held in the addition value holding unit is the second value, the addition value is decremented by one for each base period until the addition value becomes the first value. Each time the addition value is decremented by 1, the processing unit transmits the latest addition value to the addition value holding unit, and the addition value holding unit , Send from the calculation unit instead of the stored addition value Holding the latest of the adding value.

  Preferably, the first determination unit further calculates a number from the first value to the second value when the first calculated value is larger than the second value. Limit processing for subtracting from the calculated value is performed, and the second calculated value calculated by the limit processing is transmitted as the latest comparison value to the comparison value holding unit, and the first calculated value is the second calculated value. If the value is less than or equal to the value, the first calculated value is transmitted as the latest comparison value to the comparison value holding unit, and the comparison value holding unit replaces the holding comparison value for each base period. The latest comparison value transmitted from the first determination unit is held.

  Preferably, the trigger generation unit has a third frequency larger than the first value from a first value in a frequency dividing period equal to or greater than M (an integer greater than or equal to 2) times a base period satisfying the refresh rate rule. A reference counter sequentially indicating up to a value, the reference counter indicating the same value for each frequency division period, and M counters that hold any value from the first value to the third value as a comparison value The M detection values held by the M match detection units are different from each other, and each of the match detection units holds the value indicated by the reference counter and the match detection unit. Detecting a coincidence timing that is a coincidence timing with the comparison value, and generating a trigger at the coincidence timing, and further, the trigger generation unit further generates the trigger generated by each of the M coincidence detection units at different timing , Including generator for generating as said refresh trigger.

  Preferably, the trigger generation unit performs a count process of counting only a variable cycle setting value for determining the generation timing of the refresh trigger, and a variable that generates a trigger every time the count process ends. A period counter and a period setting value generation unit that outputs a different value to the variable period counter as the period setting value that the variable period counter counts each time the variable period counter generates the trigger. The variable period counter also generates the trigger that is generated every time the counting process ends as the refresh trigger.

  Preferably, the cycle setting value output by the cycle setting value generation unit is any value from a fourth value to a fifth value greater than the fourth value, and the fourth value Is a value obtained by subtracting a value of 1 / u (an integer equal to or greater than 2) of the specified value from a specified value corresponding to a base period that satisfies the refresh rate specification, and the fifth value is It is a value obtained by adding a value of 1 / u of a specified value, and the cycle setting value generation unit holds the cycle setting value, and each time the variable cycle counter generates a trigger, A cycle setting value holding unit that outputs at least a cycle setting value to the variable cycle counter, and whether the latest cycle setting value output by the cycle setting value holding unit is the fourth value or the fifth value. A determination unit for determining whether or not the cycle setting value holding unit Each time the latest cycle setting value is output, the calculation unit calculates using the cycle setting value, and the determination unit further includes the cycle setting value held in the cycle setting value holding unit Is the fourth value, a process of incrementing the period setting value by 1 until the period setting value becomes the fifth value, and every time the period setting value is incremented by 1, the latest period Processing for transmitting a set value to the cycle set value holding unit is executed by the calculation unit, and when the cycle set value held in the cycle set value holding unit is the fifth value, the cycle setting is performed. Processing for decrementing the cycle setting value by 1 until the value reaches the fourth value, and processing for transmitting the latest cycle setting value to the cycle setting value holding unit every time the cycle setting value is decremented by 1 Is executed by the calculation unit, and the cycle setting is performed. Holding unit, every time the variable period counter for generating a trigger, instead of the period setting value held, to retain the most recent of the cycle setting value transmitted from the computing unit.

  Preferably, the period setting value generation unit uses the M-sequence cyclic code having a different value as the period setting value to be counted by the variable period counter every time the variable period counter generates a trigger. It has a code generator for outputting to the variable period counter.

  Preferably, the refresh control device has a function of generating the refresh trigger at a constant period and a function of generating the refresh trigger at a non-constant period.

  A wireless receiver according to an aspect of the present invention includes the refresh control device, a tuner that receives a wireless signal, and a volatile memory for holding data, and the refresh control device includes the volatile memory. A refresh trigger for requesting execution of the refresh operation is generated at a non-constant period.

  Preferably, the frequency at which the tuner unit receives the radio signal is different from each frequency indicated by a signal composed of a plurality of refresh triggers having a non-constant period.

  Preferably, the tuner unit, the volatile memory, and the refresh control device are arranged on the same substrate.

  A semiconductor integrated circuit according to an aspect of the present invention includes the refresh control device and a tuner unit that receives a radio signal.

  According to the present invention, it is possible to reduce the level of noise caused by a trigger cycle for requesting a memory refresh operation.

It is a block diagram which shows the structure of the radio | wireless receiver which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the trigger generation part which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the comparison value generation part which concerns on Embodiment 1 of this invention. It is an example of the timing chart for demonstrating operation | movement of the trigger generation part which concerns on Embodiment 1 of this invention. It is a figure for demonstrating the refresh trigger which concerns on Embodiment 1 of this invention. It is a block diagram which shows the structure of the trigger generation part which concerns on Embodiment 2 of this invention. It is an example of the timing chart for demonstrating operation | movement of the trigger generation part which concerns on Embodiment 2 of this invention. It is a figure for demonstrating the refresh trigger which concerns on Embodiment 2 of this invention. It is a block diagram which shows the structure of the trigger generation part which concerns on Embodiment 3 of this invention. It is an example of the timing chart for demonstrating operation | movement of the trigger generation part which concerns on Embodiment 3 of this invention. It is a block diagram which shows the structure of the trigger generation part which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the period setting value production | generation part which concerns on Embodiment 4 of this invention. It is an example of the timing chart for demonstrating operation | movement of the trigger generation part which concerns on Embodiment 4 of this invention. It is a block diagram which shows the structure of the trigger generation part which concerns on Embodiment 5 of this invention. It is a block diagram which shows an example of a structure of the M series cyclic code generation part which concerns on Embodiment 5 of this invention. FIG. 10 is an example of a timing chart for explaining an operation of a trigger generation unit according to Embodiment 5. It is a figure which shows the structure of the radio | wireless receiver which concerns on Embodiment 6 of this invention. It is a figure which shows the structure of the semiconductor integrated circuit which concerns on Embodiment 7 of this invention. It is a block diagram which shows the structure of a common radio receiver. It is a wave form diagram of a refresh request. It is a figure which shows the frequency spectrum of a signal.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following description, the same components are denoted by the same reference numerals. Their names and functions are also the same. Therefore, detailed description thereof may be omitted.

  A configuration for generating a refresh trigger for suppressing or preventing deterioration of a reception state of a wireless receiver in an apparatus for generating a refresh trigger for executing a refresh operation on a volatile memory that requires the refresh operation Etc. will be described.

<Embodiment 1>
FIG. 1 is a block diagram showing a configuration of radio receiver 1000 according to Embodiment 1 of the present invention. As an example, the wireless receiver 1000 is a radio receiver. Note that the wireless receiver 1000 is not limited to a radio receiver, and may be another device (for example, a communication device) that receives a wireless signal.

  Referring to FIG. 1, wireless receiver 1000 includes memory controller 100, DRAM 200, antenna 310, tuner unit 311, and CPU 320.

  The tuner unit 311 receives a radio signal via the antenna 310. The radio signal is, for example, an AM (Amplitude Modulation) wave signal or an FM (Frequency Modulation) wave signal.

  The CPU 320 controls the tuner unit 311 and the memory controller 100.

  The DRAM 200 is a volatile memory that needs a refresh operation to hold data.

  The memory controller 100 transmits a control signal for controlling the DRAM 200 to the DRAM 200. The control signal is a signal for controlling access to the DRAM 200 or a signal for causing the DRAM 200 to perform a refresh operation.

  The memory controller 100 includes a refresh control device 400 and a driver unit 500.

  The refresh control device 400 transmits an access signal based on various instructions from the components in the refresh control device 400 to the driver unit 500.

  The driver unit 500 performs address output processing, data input / output processing, and the like in accordance with the access signal. The processing performed by the driver unit 500 is the same as that of a general DRAM driver, and therefore will not be described in detail.

  Refresh control device 400 includes a trigger generation unit 600 and an arbitration function unit 700.

  The trigger generation unit 600 generates a refresh trigger for requesting execution of the refresh operation, as will be described in detail later.

  The arbitration function unit 700 conceptually arbitrates a memory access request to the DRAM 200 and a refresh trigger. Specifically, the arbitration function unit 700 arbitrates a memory access request and a refresh request based on a refresh trigger.

  The arbitration function unit 700 includes a refresh request unit 710 and an arbitration unit 720.

  Each time the refresh request unit 710 receives a refresh trigger, it increments (counts up) the value of the refresh request counter. The refresh request counter is a counter indicating the acceptance status of the refresh trigger.

  Each time the refresh request unit 710 receives a refresh trigger, the refresh request unit 710 transmits (outputs) a refresh request to the arbitration unit 720 as necessary. The refresh request is a request for requesting execution of the refresh operation.

  That is, the refresh request unit 710 outputs a refresh request based on the refresh trigger generated by the trigger generation unit.

  The arbitration unit 720 arbitrates between the memory access request and the refresh request when the memory access request and the refresh request conflict. Then, the arbitrating unit 720 permits either a memory access request or a refresh request as a result of the arbitration, and transmits an access signal according to the permission to the driver unit 500.

  When the arbitration unit 720 receives the refresh request, the arbitration unit 720 transmits a refresh request reception signal indicating that the refresh request has been received to the refresh request unit 710. Each time the refresh request unit 710 receives a refresh request acceptance signal, the refresh request counter 710 decrements (counts down) the value of the refresh request counter.

  When the arbitration unit 720 receives the memory access request and the refresh request at the same time, the arbitration unit 720 gives priority to the processing for the memory access request in principle. This priority processing is performed based on an instruction from the refresh request unit 710 for switching the priority order.

  In the process, the arbitrating unit 720 gives priority to the refresh process when the number of unprocessed refresh operations for the refresh request reaches a predetermined value.

  When there is no memory access request, the refresh request is accepted at the fastest speed. On the other hand, during a period in which memory access to the DRAM 200 is being executed, reception of a refresh request is awaited.

  The value of the refresh request counter is incremented during a period when access to the DRAM 200 is occupied by a burst operation due to a memory access request. At the end of memory access, the refresh operation is continuously performed for the value indicated by the refresh request counter.

  FIG. 2 is a block diagram showing a configuration of trigger generation unit 600 according to Embodiment 1 of the present invention.

  Referring to FIG. 2, trigger generation unit 600 includes a base period counter 610, a comparison value generation unit 620, and a coincidence detection unit 630.

  The base period counter 610 is a counter that sequentially indicates (counts) 0 to 15 as counter values, for example, in the base period that satisfies the refresh rate specification. That is, the base period counter 610 sequentially indicates (counts) 0 to 15 over the base period.

  Here, the refresh rate rule is a rule related to refresh of the DRAM 200. The refresh rate rule is a rule for the DRAM 200 to hold data, and is a rule that defines the required number of executions N of the refresh operation per predetermined time t1. That is, the required number N of refresh operations per predetermined time t1 is the number of required refresh operations per predetermined time necessary for the DRAM 200 to hold data.

  The base period satisfying the refresh rate rule is a value obtained by multiplying the value obtained by dividing the predetermined time t1 by the required number of executions N by the number counted in the base period.

  Here, as an example, it is assumed that the predetermined time t1 is 64 ms and the necessary number of executions N is 4096. In this case, the base period satisfying the refresh rate rule is a period calculated by 64 m / 4096 × 16. In this case, the refresh rate rule is a rule indicating that, for example, it is necessary to execute 4096 refresh operations per 64 ms.

  That is, the base period counter 610 is a counter that sequentially indicates a first value (0) to a second value (15) that is larger than the first value in a base period that satisfies the refresh rate specification, and It is a counter which shows the same value for every base period.

  Note that the required number of executions of the refresh operation per predetermined time varies depending on conditions such as the capacity and temperature of an element that holds charges in the DRAM 200. If the refresh operation is performed at a constant period, a refresh operation on the order of several tens of kHz to several MHz is necessary.

  Here, it is assumed that the wireless receiver 1000 is a radio receiver and the wireless signal received by the tuner unit 311 is an AM wave signal. In this case, the frequency band of the radio signal is 530 kHz to 1710 kHz.

  Further, it is assumed that the wireless receiver 1000 is a radio receiver and the wireless signal received by the tuner unit 311 is an FM wave signal. In this case, the frequency band of the radio signal is 76 MHz to 109 MHz.

  The base cycle counter 610 transmits the latest counter value to the coincidence detection unit 630 every time the counter value indicated by the base cycle counter 610 changes. Thereby, the coincidence detection unit 630 sequentially receives counter values from 0 to 15 in the base period.

  For example, the base period counter 610 transmits a period signal as a trigger (pulse) to the comparison value generation unit 620 at a timing when the base period counter 610 indicates “0”. That is, the base cycle counter 610 transmits a cycle signal to the comparison value generation unit 620 for each base cycle.

  Although the details will be described later, the comparison value generation unit 620 transmits an arbitrary different comparison value to the coincidence detection unit 630 every time a periodic signal is received. Here, the comparison value is a value used by the coincidence detection unit 630 for comparison with the counter value. The comparison value is one of a plurality of counter values indicated by the base period counter 610.

  That is, the comparison value generation unit 620 outputs a value that is any value from the first value to the second value and that differs for each base period as a comparison value for each base period. Here, for example, the first value and the second value are “0” and “15”, respectively.

  The coincidence detection unit 630 detects coincidence timing that is a timing at which the counter value transmitted from the base period counter 610 coincides with the latest comparison value output from the comparison value generation unit 620. Then, the comparison value generator 620 generates a trigger as a refresh trigger at the detected coincidence timing.

  That is, the coincidence detection unit 630 detects a coincidence timing that is a timing at which the value indicated by the base period counter 610 coincides with the latest comparison value output from the comparison value generation unit 620, and sets a refresh trigger at the coincidence timing. Occur.

  That is, the trigger generation unit 600 generates a refresh request trigger as a refresh trigger at the timing at which the value indicated by the base cycle counter 610 matches the comparison value output from the comparison value generation unit 620 for each base cycle. To 710.

  Thereby, it is possible to prevent the generation period of the refresh request from satisfying the refresh rate rule and not to be a constant period. That is, the trigger generation unit 600 generates a refresh trigger at a non-constant period so as to satisfy the refresh rate rule. Here, the non-constant period is a period that changes with time. In the following, a non-constant period is also referred to as a variable period.

  FIG. 3 is a block diagram showing a configuration of comparison value generation unit 620 according to Embodiment 1 of the present invention.

  Referring to FIG. 3, comparison value generation unit 620 includes comparison value holding unit 621, addition unit 622, addition value holding unit 623, and limit processing unit 624.

  The aforementioned base period counter 610 transmits the aforementioned periodic signal to the comparison value holding unit 621 for each base period.

  The comparison value holding unit 621 holds one comparison value. The comparison value holding unit 621 continues to transmit the held comparison value to the match detection unit 630 and the addition unit 622. That is, the comparison value holding unit 621 holds the comparison value and outputs the held comparison value.

  It is assumed that the comparison value holding unit 621 holds “0” as the initial comparison value.

  The added value holding unit 623 holds an added value set to an arbitrary value from the outside. For example, the CPU 320 sets the addition value held by the addition value holding unit 623. The added value is smaller than the maximum counter value indicated by the base period counter 610. The added value is, for example, “7”.

  The added value holding unit 623 continues to send the held added value to the adding unit 622.

  The addition unit 622 performs addition processing for adding the addition value transmitted from the addition value holding unit 623 to the comparison value transmitted from the comparison value holding unit 621. Although details will be described later, the comparison value holding unit 621 updates the comparison value for each base period and transmits the updated comparison value to the match detection unit 630 and the addition unit 622.

  That is, the addition unit 622 performs addition processing for adding the addition value to the comparison value held in the comparison value holding unit 621 for each base period.

  Hereinafter, the value calculated by the addition process is referred to as a first calculated value. Further, each time the addition process is performed, the addition unit 622 transmits the first calculated value calculated by the addition process to the limit processing unit 624.

  Each time the limit processing unit 624 receives the first calculated value, the limit processing unit 624 determines whether the first calculated value is larger than the maximum value of the counter value. In other words, the limit processing unit 624 determines whether the first calculation value calculated by the addition process is greater than the second value (the maximum value “15” of the counter value) each time the addition unit 622 performs the addition process. Determine whether.

  The limit processing unit 624 further performs limit processing for subtracting the number (number) from the first value to the second value from the first calculated value when the first calculated value is larger than the second value. Do. Here, the number from the first value to the second value is a value of “(maximum value of counter value) +1”. When the first value and the second value are “0” and “15”, respectively, the number (number) from the first value to the second value is 16.

  Then, the limit processing unit 624 continues to transmit the second calculated value calculated by the limit processing to the comparison value holding unit 621 as the latest comparison value.

  Further, when the first calculated value is equal to or smaller than the second value, the limit processing unit 624 continues to transmit the first calculated value to the comparison value holding unit 621 as the latest comparison value.

  Each time the comparison value holding unit 621 receives a periodic signal, the comparison value holding unit 621 receives the latest comparison value transmitted from the limit processing unit 624 and holds the latest comparison value instead of the held comparison value. That is, the comparison value holding unit 621 holds the latest comparison value transmitted from the limit processing unit 624 instead of the held comparison value for each base period.

  Then, the comparison value holding unit 621 continues to transmit the latest comparison value held to the match detection unit 630 and the addition unit 622. That is, the comparison value holding unit 621 updates the comparison value for each base period, and transmits the updated comparison value to the match detection unit 630 and the addition unit 622.

  As described above, the match detection unit 630 detects the match timing and generates a refresh trigger at the match timing.

  Through the above processing, the trigger generation unit 600 generates a refresh trigger at a variable period so as to satisfy the refresh rate rule.

  FIG. 4 is an example of a timing chart for explaining the operation of trigger generation unit 600 according to Embodiment 1 of the present invention. The horizontal axis in FIG. 4 indicates time.

  FIG. 4A is an enlarged view of a part of the timing chart shown in FIG.

  FIG. 4B is a timing chart of the comparison value and the refresh trigger.

  With reference to FIG. 4A and FIG. 4B, the “counter value” is a counter value indicated by the base period counter 610 at each timing. As described above, as an example, the base cycle counter 610 transmits a cycle signal as a trigger (pulse) to the comparison value generation unit 620 at a timing when the base cycle counter 610 indicates “0”. In FIG. 4A, one periodic signal corresponds to one trigger (pulse).

  The comparison values shown in FIGS. 4A and 4B are comparison values at each timing when the addition value held in the addition value holding unit 623 is “7”. In FIG. 4A and FIG. 4B, one refresh trigger corresponds to one trigger (pulse).

  As shown in FIG. 4A and FIG. 4B, each time the base period counter 610 outputs a periodic signal, the adding unit 622 adds the added value to the comparison value held in the comparison value holding unit 621. Add “7”. 4A and 4B, limit processing is performed at the timing when the comparison value held in the comparison value holding unit 621 is updated from 14 to 5.

  This is due to the following processing. First, the first calculated value “21” calculated by 14 + 7 = 21 by the above-described addition processing is larger than the maximum value 15 of the counter value of the base period counter. Therefore, in the limit process, the value (16) of “(the maximum value of the counter value) +1” is subtracted from the first calculated value “21”.

  As a result, the second calculated value “5” calculated by the limit process becomes the latest comparison value held in the comparison value holding unit 621.

  In this manner, the comparison value held in the comparison value holding unit 621 is updated while the limit process is generated for each base period. Thereby, the cycle of the timing at which the counter value of the base cycle counter 610 matches the value held in the comparison value holding unit 621 is not a fixed cycle.

  Therefore, in this case, the frequency component of the refresh trigger includes two types of frequency components, the interval “23” and the interval “7”. The interval “23” is an interval of one frequency component calculated by the equation 16 + 7 = 23 when the limit process is not performed. The interval “7” is the interval of the other frequency component when the limit process occurs (is performed).

  FIG. 5 is a diagram for explaining a refresh trigger according to Embodiment 1 of the present invention.

  FIG. 5A is a diagram showing a frequency spectrum of a signal composed of a plurality of refresh triggers (hereinafter referred to as a constant cycle signal N) when the refresh trigger generation cycle is a fixed cycle. That is, the fixed period signal N is a signal as noise during the refresh operation of the DRAM 200.

  The vertical axis | shaft of Fig.5 (a) shows the noise level (dB) as a signal level. The horizontal axis indicates the frequency (Hz).

  As shown in FIG. 5A, the constant period signal N is a signal indicating a fundamental wave or a harmonic having a peak at a frequency that is n (n is a natural number) times T / 16.

  FIG. 5B is a diagram illustrating a frequency spectrum of a signal (hereinafter, referred to as a variable period signal SA) that is generated by the trigger generation unit 600 according to Embodiment 1 and includes a plurality of refresh triggers having a variable period. is there. That is, the variable period signal SA is a signal as noise during the refresh operation of the DRAM 200.

  The vertical and horizontal axes in FIG. 5B are the same as the vertical and horizontal axes in FIG. 5A, respectively. In FIG. 5B, for comparison, the constant period signal N in FIG. 5A is indicated by a dotted line.

  As shown in FIG. 5B, the variable period signal SA composed of a plurality of refresh triggers generated by the trigger generation unit 600 includes two signals (hereinafter referred to as signals S1, S2) each having two types of frequency components. It is composed of. In this case, the signal S1 is a signal indicating a fundamental wave or a harmonic wave having a peak at a frequency n times T / 23. The signal S2 is a signal indicating a fundamental wave or a harmonic wave having a peak at a frequency n times T / 7.

  Further, as shown in FIG. 5B, the maximum noise level of the variable periodic signal SA is lower than the maximum noise level of the constant periodic signal N. Here, the variable period signal SA is a signal for requesting the refresh operation of the DRAM 200.

  That is, according to the refresh control device 400 including the trigger generation unit 600 according to the first embodiment, the level of noise (for example, the maximum level) caused by the periods of the plurality of refresh triggers constituting the variable period signal SA is constant. It can be reduced from the level of noise caused by the refresh trigger that occurs in a cycle. That is, the noise level caused by the trigger cycle for requesting the memory refresh operation can be reduced from the noise level caused by the trigger generated at a constant cycle.

  The frequency of each peak included in the variable periodic signal SA is a frequency obtained by shifting the frequency of each peak included in the constant periodic signal N.

  Using this, for example, by setting the added value held in the added value holding unit 623 to an arbitrary value by the CPU 320, the frequency peak of the variable period signal SA can be shifted to an arbitrary position. Become. As a result, even if the frequency band of the radio signal exists in the low-order (second-order, third-order, etc.) harmonic region of the variable periodic signal SA, the tuner unit 311 can prevent the reception of the radio signal. The peak can be shifted to a position where it does not become necessary. That is, it is possible to suppress degradation of the reception state of radio signals (reception interference). The said radio signal is a signal used with a radio, for example.

  Therefore, the frequency at which the tuner unit 311 receives the radio signal is different from the frequency indicated by the signal composed of a plurality of refresh triggers having a non-constant period (variable period).

  Thereby, the refresh control device 400 including the trigger generation unit 600 and the trigger generation unit 600 according to the first embodiment satisfies the refresh rate regulation of the volatile memory (DRAM 200) and performs radio based on the frequency of the signal for the refresh operation. The influence on reception can be prevented.

  In addition, the wireless receiver 1000 according to the first embodiment does not use an analog configuration such as a VCO (Voltage Controlled Oscillator) and shifts the frequency or frequency with a digitally simple circuit configuration based on the system operation clock. Modulation can be realized.

  Further, without changing the configuration of a conventional arbitration circuit or the like, the effect of refresh is almost the same as that of a conventional wireless receiver, and memory access to the DRAM becomes possible.

  The trigger generation unit 600 is not limited to a configuration that generates a refresh trigger with a variable period. For example, the trigger generation unit 600 may have a function of generating a refresh trigger at a constant cycle and a function of generating the refresh trigger at a variable cycle (non-fixed cycle).

  In this case, the refresh control device 400 has a function of generating a refresh trigger at a constant period and a function of generating a refresh trigger at a variable period (non-constant period).

  Here, in order to cause the trigger generation unit 600 to generate a refresh trigger at a constant cycle, for example, the CPU 320 sets the value of the addition value held by the addition value holding unit 623 to “0”. This makes it possible to cause the DRAM 200 to perform a refresh operation at the conventional timing under conditions that do not affect the reception state of the radio signal.

  In the first embodiment, one refresh trigger is generated at the coincidence detection timing detected by the coincidence detection unit 630. However, the present invention is not limited to this. The coincidence detection unit 630 may generate a plurality of continuous refresh triggers at the detected coincidence detection timing.

  However, in consideration of the case where memory access is performed in the DRAM 200, one refresh trigger is generated per one base period. As a result, refresh timings are equalized and there are few adverse effects on memory access.

  The reference clock counted by the base period counter 610 is not particularly limited. For example, the reference clock may be a system clock in the memory controller that serves as a reference for access timing with the DRAM. In some cases, a frequency-divided clock may be used as the reference clock in view of the effect of the radio signal reception state.

<Embodiment 2>
Next, a trigger generation unit 600A according to Embodiment 2 of the present invention will be described.

  Hereinafter, the refresh control device according to the second embodiment is referred to as a refresh control device A2. The refresh control device A2 differs from the refresh control device 400 of FIG. 1 only in that a trigger generation unit 600A is provided instead of the trigger generation unit 600. The rest of the configuration of refresh control device A2 is the same as that of refresh control device 400, and therefore detailed description will not be repeated.

  FIG. 6 is a block diagram showing a configuration of trigger generation unit 600A according to Embodiment 2 of the present invention. The trigger generation unit 600A is different from the trigger generation unit 600 of FIG. 3 mainly in that the addition value is variable.

  Referring to FIG. 6, trigger generation unit 600 </ b> A is different from trigger generation unit 600 of FIG. 3 in that it includes a comparison value generation unit 620 </ b> A instead of comparison value generation unit 620. Since the other configuration of trigger generation unit 600A is the same as that of trigger generation unit 600, detailed description will not be repeated.

  Compared to comparison value generation unit 620 in FIG. 3, comparison value generation unit 620 </ b> A has addition value holding unit 623 </ b> A instead of addition value holding unit 623, and further includes calculation control unit 625, calculation unit 626, and It differs from the point which has. Since the other configuration of comparison value generation unit 620A is the same as that of comparison value generation unit 620, detailed description will not be repeated.

  The base cycle counter 610 of the trigger generation unit 600A transmits the above-described cycle signal to the comparison value holding unit 621, the addition value holding unit 623A, and the calculation control unit 625 for each base cycle.

  The added value holding unit 623A holds one added value. The addition value is a value used by the above-described addition processing. Further, every time the addition value holding unit 623A receives a periodic signal, the addition value holding unit 623A continues to transmit the latest addition value held to the addition unit 622, the calculation control unit 625, and the calculation unit 626.

  That is, the addition value holding unit 623A holds the addition value and outputs the latest addition value held for each base period.

  The calculation control unit 625 determines whether the latest addition value output from the addition value holding unit 623A is the first value or the second value every time a periodic signal is received. Part. Here, the first value and the second value are the minimum value and the maximum value of the base period counter, respectively. Here, as an example, it is assumed that the first value and the second value are “0” and “15”, respectively.

  Although the details will be described later, the added value is updated by adding +1 for each base period until the added value reaches the maximum value of the counter value. Further, when the added value reaches the maximum value of the counter value, the added value is updated by adding −1 for each base period until the added value reaches the minimum value.

  Although the details will be described later, the calculation unit 626 performs calculation using the addition value every time the latest addition value is output from the addition value holding unit 623A.

  Then, when the latest addition value output from the addition value holding unit 623A is the first value, the arithmetic control unit 625 performs the base period until the addition value becomes the second value. A process for incrementing the addition value by 1 and a process for transmitting the latest addition value to the addition value holding unit 623A and an instruction for executing the process are issued to the calculation unit 626 each time the addition value is incremented by one.

  That is, the arithmetic control unit 625 serving as a second determination unit further sets the addition value to the second value when the addition value held in the addition value holding unit 623A is the first value. A process of incrementing the addition value by 1 every base period and a process of transmitting the latest addition value to the addition value holding unit 623A each time the addition value is incremented by 1. To run.

  In this case, the calculation unit 626 performs calculation processing to increment the addition value by 1 for each base period until the addition value becomes the second value, and every time the addition value is incremented by 1, The added value is transmitted to the added value holding unit 623A.

  In addition, when the latest addition value output from the addition value holding unit 623A is the second value, the arithmetic control unit 625 performs the base cycle every time the base value is changed until the addition value becomes the first value. An instruction to execute the process of decrementing the added value by 1 and the process of transmitting the latest added value to the added value holding unit 623A and the instruction to execute each time the added value is decremented by 1 are issued to the arithmetic unit 626.

  That is, when the addition value held in the addition value holding unit 623A is the second value, the arithmetic control unit 625 serving as the second determination unit determines that the addition value becomes the first value. A process of decrementing the addition value by 1 every base period and a process of transmitting the latest addition value to the addition value holding unit 623A every time the addition value is decremented by 1 are executed in the arithmetic unit 626. Let

  In this case, the calculation unit 626 performs a calculation process of decrementing the addition value by 1 for each base period until the addition value becomes the first value, and every time the addition value is decremented by 1, Is sent to the added value holding unit 623A.

  Each time the addition value holding unit 623A receives the periodic signal, the addition value holding unit 623A receives the latest addition value transmitted from the calculation unit 626 and holds the latest addition value instead of the held addition value. That is, the addition value holding unit 623A holds the latest addition value transmitted from the calculation unit 626 instead of the held addition value for each base period.

  As described above, the addition value holding unit 623A continues to transmit the latest addition value held for each base period to the addition unit 622, the calculation control unit 625, and the calculation unit 626.

  Each time the addition unit 622 receives the addition value, the addition unit 622 performs addition processing A in which the addition value transmitted from the addition value holding unit 623A is added to the comparison value transmitted from the comparison value holding unit 621. That is, the addition unit 622 performs addition processing A for adding the latest addition value held by the addition value holding unit 623A to the comparison value held by the comparison value holding unit 621 for each base period. .

  Hereinafter, the value calculated by the addition process A is referred to as a first calculated value. Further, each time the addition process A is performed, the addition unit 622 transmits the first calculated value calculated by the addition process A to the limit processing unit 624.

  Since the processing performed by limit processing unit 624 and comparison value holding unit 621 is the same as the processing of the first embodiment, detailed description will not be repeated. A brief description is given below.

  That is, the limit processing unit 624 serving as a first determination unit is configured such that each time the addition unit 622 performs the addition processing A, the first calculated value calculated by the addition processing A is the second value (the counter value). It is determined whether it is larger than the maximum value (15)).

  Further, the limit processing unit 624 as the first determination unit further calculates the number (number) from the first value to the second value when the first calculated value is larger than the second value. Limit processing for subtracting from the first calculated value is performed.

  Then, the limit processing unit 624 continues to transmit the second calculated value calculated by the limit processing to the comparison value holding unit as the latest comparison value.

  Further, the limit processing unit 624 as the first determination unit, when the first calculated value is equal to or less than the second value, sets the first calculated value as the latest comparison value to the comparison value holding unit. Keep sending.

  Each time the comparison value holding unit 621 receives a periodic signal, the comparison value holding unit 621 receives the latest comparison value transmitted from the limit processing unit 624 and holds the latest comparison value instead of the held comparison value. That is, the comparison value holding unit 621 holds the latest comparison value transmitted from the limit processing unit 624 serving as the first determination unit instead of the held comparison value for each base period.

  Then, the comparison value holding unit 621 continues to transmit the latest comparison value held to the match detection unit 630 and the addition unit 622. That is, the comparison value holding unit 621 updates the comparison value for each base period, and transmits the updated comparison value to the match detection unit 630 and the addition unit 622.

  As described above, the match detection unit 630 detects the match timing and generates a refresh trigger at the match timing.

  Through the above processing, the trigger generation unit 600A generates a refresh trigger at a variable period so as to satisfy the refresh rate rule.

  FIG. 7 is an example of a timing chart for explaining the operation of trigger generation unit 600A according to Embodiment 2 of the present invention. The horizontal axis in FIG. 7 indicates time.

  Referring to FIG. 7, the timing chart associated with the character string “arithmetic unit” shows processing performed by arithmetic unit 626. The period in which “+1” is indicated is a period during which the calculation unit 626 performs calculation processing to increment the addition value by one. The period in which “−1” is indicated is a period during which the calculation unit 626 performs a calculation process of decrementing the added value by one.

  The “added value” is an added value at each timing. The “comparison value” is a comparison value at each timing. In FIG. 7, one refresh trigger corresponds to one trigger (pulse).

  Although not shown in FIG. 7, the base period counter 610 outputs the counter value and period signal shown in FIG. As an example, the counter value is a value from 0 to 15.

  For example, the base period counter 610 outputs a period signal as a trigger (pulse) at a timing when the base period counter 610 indicates “0”.

  The calculation unit 626 performs calculation processing for incrementing the addition value by one for each base period until the addition value reaches the maximum value (15) during the period indicated by “+1”. On the other hand, the calculation unit 626 performs a calculation process of decrementing the added value by 1 for each base period until the added value reaches the minimum value (0) during the period indicated by “−1”. That is, the added value is updated in a sweep form.

  Although not shown in the figure, when the added value reaches the minimum value (0), that is, when the period in which “+1” is indicated ends, the period in which “−1” is indicated again becomes.

  By repeatedly performing these processes, the added value updated for each base period is added to the comparison value held in the comparison value holding unit 621. The comparison value is updated.

  Through the above processing, the trigger generation unit 600A generates a refresh trigger at a variable period so as to satisfy the refresh rate rule.

  FIG. 8 is a diagram for explaining a refresh trigger according to Embodiment 2 of the present invention. FIG. 8 is a diagram illustrating a frequency spectrum of a signal (hereinafter, referred to as a variable period signal SA2) composed of a plurality of variable period refresh triggers generated by the trigger generation unit 600A according to the second embodiment. That is, the variable period signal SA2 is a signal as noise during the refresh operation of the DRAM 200.

  The vertical axis and the horizontal axis in FIG. 8 are the same as the vertical axis and the horizontal axis in FIG.

  In FIG. 8, the constant period signal N of FIG. 5A is indicated by a dotted line for comparison.

  As shown in FIG. 8, the variable period signal SA2 composed of a plurality of refresh triggers generated by the trigger generator 600A is a signal indicating a fundamental wave or a harmonic having a peak at a frequency n times T / 16. It is.

  As described above, in the second embodiment, the addition value is updated in a sweep form. As a result, the refresh trigger generation cycle becomes an irregular cycle.

  Further, as shown in FIG. 8, the maximum noise level of the variable periodic signal SA2 is significantly lower than the maximum noise level of the constant periodic signal N. That is, with the configuration according to the second embodiment, the variable periodic signal SA2 is a signal in which the peak level of the fixed periodic signal N is averagely dispersed, and the fundamental and harmonic noise levels of the fixed periodic signal N Is a signal that is greatly reduced (attenuated).

  That is, according to the refresh control device A2 including the trigger generation unit 600A according to the second embodiment, the refresh trigger that generates the noise level caused by the cycles of the plurality of refresh triggers constituting the variable cycle signal SA2 at a constant cycle. It can be greatly reduced from the level of noise caused by. That is, the noise level caused by the trigger cycle for requesting the refresh operation of the memory can be significantly reduced from the noise level caused by the trigger generated at a constant cycle.

  Therefore, the radio receiver having the trigger generation unit 600A deteriorates the reception state (reception of the radio signal received by the tuner unit 311) even if the frequency band of the radio signal exists in the relatively high-order harmonic region. Interference) can be greatly suppressed. That is, the wireless receiver having the trigger generation unit 600A according to Embodiment 2 can significantly suppress the deterioration of the reception state (reception interference) of the wireless signal.

  The trigger generation unit 600A is not limited to a configuration that generates a refresh trigger with a variable period. For example, the trigger generation unit 600A may have a function of generating a refresh trigger at a constant cycle and a function of generating the refresh trigger at a variable cycle.

  In this case, the refresh control device A2 has a function of generating a refresh trigger at a constant period and a function of generating a refresh trigger at a variable period.

  Here, in order for trigger generation unit 600 to generate a refresh trigger at a constant cycle, for example, CPU 320 controls addition value holding unit 623A so that the addition value output from addition value holding unit 623A is a fixed value. To do. This makes it possible to cause the DRAM 200 to perform a refresh operation at the conventional timing under conditions that do not affect the reception state of the radio signal.

<Embodiment 3>
Next, the trigger generation unit 600B according to Embodiment 3 of the present invention will be described. Hereinafter, the refresh control device according to the third embodiment is referred to as a refresh control device A3. The refresh control device A3 is different from the refresh control device 400 of FIG. 1 only in that a trigger generation unit 600B is provided instead of the trigger generation unit 600. The rest of the configuration of refresh control device A3 is the same as that of refresh control device 400, and therefore detailed description will not be repeated.

  FIG. 9 is a block diagram showing a configuration of trigger generation unit 600B according to Embodiment 3 of the present invention.

  The trigger generation unit 600B mainly differs from the trigger generation unit 600 of FIG. 3 in the counter cycle.

  Referring to FIG. 9, trigger generation unit 600B includes a reference counter 610B, a detection unit 620B, and an OR operation unit 640.

  The above-described base period counter 610 is a counter for outputting one refresh trigger in the circulation period of the base period counter 610. On the other hand, the reference counter 610B is a counter for outputting M (an integer of 2 or more) refresh triggers in the circulation cycle of the reference counter 610B.

  As an example, the reference counter 610B sequentially indicates from the first value to the third value as a counter value in a frequency dividing period equal to or greater than M (an integer greater than or equal to 2) times the base period that satisfies the refresh rate specification ( Counter). That is, the base period counter 610B sequentially indicates (counts) the first value to the third value over the frequency dividing period. The first value and the third value are the minimum value and the maximum value of the values indicated by the reference counter 610B, respectively. Here, as an example, it is assumed that the first value and the third value are “0” and “47”, respectively.

  That is, the reference counter 610B sequentially indicates from the first value to the third value greater than the first value in a frequency dividing period that is M (an integer greater than or equal to 2) times the base period that satisfies the refresh rate specification. It is a counter which is the counter and shows the same value for each frequency division period.

  The detection unit 620B includes M (an integer greater than or equal to 2) coincidence detection units 631. That is, the trigger generation unit 600B includes M coincidence detection units 631.

  Each time the counter value indicated by the reference counter 610B changes, the reference counter 610B transmits the latest counter value to each of the M coincidence detection units 631.

  Each of the M number of coincidence detection units 631 holds different comparison values. The comparison value held by each of the M coincidence detection units 631 is a value set by an external CPU, for example.

  That is, each of the M coincidence detection units 631 holds any value from the first value to the third value as a comparison value. The M comparison values held by the M coincidence detection units 631 are different from each other.

  Each of the coincidence detection units 631 detects a coincidence timing that is a timing at which the latest counter value received from the reference counter 610B coincides with the comparison value held by the coincidence detection unit 631. Then, the coincidence detection unit 631 generates a trigger as a refresh trigger at the detected coincidence timing.

  That is, each of the coincidence detection units 631 detects a coincidence timing that is a timing at which the value indicated by the reference counter 610B coincides with the comparison value held by the coincidence detection unit, and generates a trigger at the coincidence timing. Each of the coincidence detection units 631 transmits a trigger (pulse) to the logical sum operation unit 640 at the detected coincidence timing.

  Each of the M coincidence detection units 631 transmits a trigger (pulse) to the logical sum operation unit 640 at a different timing.

  The OR operation unit 640 performs an OR operation on the trigger (pulse) received from each of the M coincidence detection units 631. That is, the OR operation unit 640 is a generation unit that generates the trigger that is generated at a different timing by each of the M coincidence detection units as the refresh trigger.

  When the M comparison values held by the M match detection units 631 are arranged in order from the smallest value, the absolute value of the difference between the two consecutive comparison values is different from each other. As a result, the trigger generation unit 600B generates a refresh trigger at a variable period.

  Thereby, it is possible to prevent the generation period of the refresh request from satisfying the refresh rate rule and not to be a constant period.

  Through the above processing, the trigger generation unit 600B generates a refresh trigger at a variable period so as to satisfy the refresh rate rule.

  Here, the base period that satisfies the refresh rate specification in the reference counter 610B is set to a period within N clocks. Further, it is assumed that the frequency dividing period of the reference counter 610B is N × M. In this case, the detection unit 620B outputs M refresh triggers per at least one frequency division period.

  FIG. 10 shows an example of a timing chart for explaining the operation of trigger generation unit 600B according to Embodiment 3 of the present invention. The horizontal axis in FIG. 10 indicates time.

  Here, it is assumed that the base period N = 16 of the reference counter 610B and M = 3. In this case, the detection unit 620B has three match detection units 631. The three comparison values held by the three match detection units 631 are “0”, “19”, and “24”, respectively.

  In this case, the reference counter 610B sequentially indicates values from “0” to “47”. That is, the period of counting from “0” to “47” is one period of the reference counter 610B.

  FIG. 10A is an enlarged view of a part of the timing chart shown in FIG.

  In FIG. 10A, the counter value is a counter value indicated by the reference counter 610B at each timing.

  FIG. 10B is a refresh trigger timing chart.

  As shown in FIGS. 10A and 10B, the trigger generator 600B generates a refresh trigger at the timing when the counter value of the reference counter 610B is “0”, “19”, “24”. Occur.

  Note that the three comparison values held by the three match detection units 631 are not limited to “0”, “19”, and “24”. When M comparison values are arranged in order from the smallest value, the absolute value of the difference between the two consecutive comparison values may be different from each other. For example, the three comparison values held by the three match detection units 631 may be “0”, “17”, and “35”, respectively.

  With the above operation, the frequency peak of the refresh noise can be shifted to an arbitrary position by setting the comparison value held by the M coincidence detection units 631 to an arbitrary value.

  Hereinafter, a signal composed of a plurality of refresh triggers having a variable cycle, which is generated by the trigger generation unit 600B according to Embodiment 3, is referred to as a variable cycle signal SA3.

  The trigger generator 600B generates a refresh trigger with a variable period. Therefore, according to the refresh control device A3 including the trigger generation unit 600B according to the third embodiment, the level of noise (for example, the maximum level) caused by a plurality of refresh trigger periods constituting the variable period signal SA3 is constant. It can be reduced from the level of noise caused by the refresh trigger that occurs in a cycle. That is, the noise level caused by the trigger cycle for requesting the memory refresh operation can be reduced from the noise level caused by the trigger generated at a constant cycle.

  As described above, in trigger generation unit 600B according to Embodiment 3, the cycle of reference counter 610B is set to a frequency division cycle that is at least twice the cycle that satisfies the refresh rate rule. With this configuration, the frequency shift direction of the refresh trigger cycle can be expanded as compared with the first and second embodiments. For example, when M is 3, the shift amount of the frequency peak of the variable period signal SA3 can be three times the shift amount of the first embodiment.

  Therefore, intensive refreshing of the DRAM 200 is also possible within a range in which adverse effects on memory access can be tolerated. Further, it is possible to realize a frequency shift that does not overlap with a frequency band for receiving a radio signal.

  Note that the comparison value held by the M coincidence detection units 631 may be a fixed value or a variable value that can be set by the CPU 320.

  The trigger generator 600B is not limited to a configuration that generates a refresh trigger with a variable period. For example, the trigger generation unit 600B may have a function of generating a refresh trigger at a constant cycle and a function of generating the refresh trigger at a variable cycle.

  In this case, the refresh control device A3 according to Embodiment 3 has a function of generating a refresh trigger at a constant period and a function of generating a refresh trigger at a variable period.

  Here, in order to cause the trigger generation unit 600B to generate refresh triggers at a constant period, for example, when M comparison values are arranged from a small value, the absolute value of the difference between two consecutive comparison values is obtained. Just make it the same. For example, the three comparison values held by the three match detection units 631 may be “0”, “16”, and “32”, respectively.

  In this case, the rigger generator 600B generates a refresh trigger at a constant cycle. This makes it possible to cause the DRAM 200 to perform a refresh operation at the conventional timing under conditions that do not affect the reception state of the radio signal.

  The reference clock counted by the reference counter 610B is not particularly limited. For example, the reference clock may be a system clock in the memory controller that serves as a reference for access timing with the DRAM. In some cases, a frequency-divided clock may be used as the reference clock in view of the effect of the radio signal reception state.

<Embodiment 4>
Next, a trigger generation unit 600C according to Embodiment 4 of the present invention will be described. Hereinafter, the refresh control device according to the fourth embodiment is referred to as a refresh control device A4. The refresh control device A4 differs from the refresh control device 400 of FIG. 1 only in that a trigger generation unit 600C is provided instead of the trigger generation unit 600. The rest of the configuration of refresh control device A4 is the same as that of refresh control device 400, and therefore detailed description will not be repeated.

  FIG. 11 is a block diagram showing a configuration of trigger generation unit 600C according to Embodiment 4 of the present invention.

  Referring to FIG. 11, trigger generation unit 600C includes a variable cycle counter 610C and a cycle set value generation unit 620C.

  The period setting value generation unit 620C generates a variable period setting value. The cycle setting value is a value for determining the generation timing of the refresh trigger.

  The variable cycle counter 610C performs a count process for counting only the variable cycle set value, and transmits a cycle signal as a trigger (pulse) to the cycle set value generation unit 620C every time the count process ends.

  That is, the variable cycle counter 610C performs a count process for counting only a variable cycle set value, and generates a cycle signal as a trigger each time the count process is completed.

  The period setting value generation unit 620C uses a period upper limit value and a period lower limit value, which will be described later, each time a period signal is received, a different value is used as the period setting value to be counted by the variable period counter 610C. Output to the variable period counter 610C.

  That is, every time the variable cycle counter 610C generates the trigger, the cycle set value generation unit 620C outputs a different value to the variable cycle counter as the cycle set value to be counted by the variable cycle counter 610C. To do.

  Each time the period setting value generation unit 620C receives a period signal, the period setting value generation unit 620C updates the period setting value to be a value within the range of two different period upper limit values and period lower limit values.

  Further, the variable cycle counter 610C also generates the trigger that is generated every time the counting process is completed as the refresh trigger. That is, the variable cycle counter 610C transmits a refresh trigger to the refresh request unit 710 every time the counting process ends.

  Thereby, it is possible to prevent the generation period of the refresh request from satisfying the refresh rate rule and not to be a constant period.

  FIG. 12 is a block diagram showing a configuration of period setting value generation section 620C according to Embodiment 4 of the present invention.

  Referring to FIG. 12, cycle set value generation unit 620C includes cycle set value holding unit 623C, calculation control unit 625C, and calculation unit 626C.

  The variable cycle counter 610C transmits the above-described cycle signal to the cycle set value holding unit 623C and the calculation control unit 625C every time the counting process ends.

  The cycle set value holding unit 623C holds one cycle set value. Every time the period setting value holding unit 623C receives a period signal as a trigger, the period setting value holding unit 623C continues to transmit the latest period setting value held to the variable period counter 610C, the calculation control unit 625C, and the calculation unit 626C.

  That is, the cycle setting value holding unit 623C holds the cycle setting value and outputs the held latest cycle setting value to at least the variable cycle counter 610C each time the variable cycle counter 610C generates a trigger. To do.

  The cycle set value is set to any one from the cycle lower limit value to the cycle upper limit value. That is, the cycle set value output by the cycle set value generation unit 620C is any value from the fourth value (cycle lower limit value) to the fifth value (cycle upper limit value) greater than the fourth value. It is.

  The cycle lower limit value is a value obtained by subtracting a value of 1 / u (an integer of 2 or more) of the specified value from a specified value corresponding to the base cycle that satisfies the refresh rate specification. Here, the prescribed value corresponding to the base period is the number that the counter counts in the above-described base period.

  The cycle upper limit value is a value obtained by adding 1 / u of the specified value to the specified value. That is, the cycle lower limit value and the cycle upper limit value are values calculated centering on a prescribed value corresponding to the base cycle.

  In other words, the cycle lower limit value and the cycle upper limit value are preferably set so that the intermediate value between the cycle lower limit value and the cycle upper limit value is equal to a specified value corresponding to a cycle that satisfies the refresh rate specification. As a result, in accordance with the above-described operation, the average period of the periodic signal output from the variable period counter 610C when the period setting value has been updated can satisfy the refresh rate specification.

  The cycle lower limit value and the cycle upper limit value are not limited to the values set according to the above rules, and may be arbitrarily set values.

  Here, it is assumed that the specified value corresponding to the base period satisfying the refresh rate specification is “16” as an example. The specified value corresponding to the base period that satisfies the refresh rate rule is a cycle setting value that satisfies the refresh rate rule. Further, it is assumed that u = 4. In this case, the cycle lower limit value and the cycle upper limit value are “12” and “20”, respectively.

  The calculation control unit 625C holds the cycle lower limit value and the cycle upper limit value.

  In addition, the calculation control unit 625C determines whether the latest cycle setting value output from the cycle setting value holding unit 623C is the fourth value (cycle lower limit value) or the fifth value (cycle upper limit value). It is the determination part which determines whether or not.

  Although details will be described later, the cycle setting value is updated by adding +1 at each cycle signal output timing until the cycle setting value reaches the cycle upper limit value. In addition, when the period setting value reaches the period upper limit value, the period setting value is updated by adding −1 for each period signal output timing until the period setting value reaches the period lower limit value.

  Although the details will be described later, the calculation unit 626C performs calculation using the cycle setting value every time the latest cycle setting value is output from the cycle setting value holding unit 623C.

  Then, when the latest cycle setting value output from the cycle setting value holding unit 623C is the cycle lower limit value (fourth value), the calculation control unit 625C determines that the cycle setting value is the cycle upper limit value (fifth). The period setting value is incremented by 1 until the value reaches (), and the latest period setting value is transmitted to the period setting value holding unit 623C every time the period setting value is incremented by 1. An instruction to be issued is issued to the calculation unit 626C.

  That is, the calculation control unit 625 serving as a determination unit further sets the cycle setting value to the fifth value when the cycle setting value held in the cycle setting value holding unit 623C is the fourth value. A process of incrementing the period setting value by 1 until the period setting value is reached, and a process of transmitting the latest period setting value to the period setting value holding unit 623C every time the period setting value is incremented by one. To run.

  In this case, the calculation unit 626C performs calculation processing for incrementing the cycle setting value by 1 for each output timing of the cycle signal until the cycle setting value reaches the cycle upper limit value (fifth value). Each time the set value is incremented by 1, the latest cycle set value is transmitted to the cycle set value holding unit 623C.

  In addition, when the latest cycle setting value output from the cycle setting value holding unit 623C is the cycle upper limit value (fifth value), the calculation control unit 625C determines that the cycle setting value is the cycle lower limit value (fourth value). The period setting value is decremented by 1 until the value reaches the value), and the latest period setting value is transmitted to the period setting value holding unit 623C every time the period setting value is decremented by 1 An instruction to be issued is issued to the calculation unit 626C.

  That is, when the cycle setting value held in the cycle setting value holding unit 623C is the fifth value, the calculation control unit 625 serving as a determination unit until the cycle setting value becomes the fourth value. A process of decrementing the period setting value by 1 and a process of transmitting the latest period setting value to the period setting value holding unit 623C every time the period setting value is decremented by 1 are performed in the arithmetic unit 626C. Let

  In this case, the calculation unit 626C performs a calculation process of decrementing the cycle setting value by 1 for each output timing of the cycle signal until the cycle setting value reaches the cycle lower limit value (fourth value). Each time the set value is decremented by 1, the latest cycle set value is transmitted to the cycle set value holding unit 623C.

  The cycle set value holding unit 623C receives the latest cycle set value transmitted from the calculation unit 626C every time it receives a cycle signal as a trigger from the variable cycle counter 610C, and instead of the held cycle set value. Holds the latest cycle setting. That is, the cycle set value holding unit 623C holds the latest cycle set value transmitted from the calculation unit instead of the held cycle set value every time the variable cycle counter 610C generates a trigger. To do.

  Then, as described above, the cycle set value holding unit 623C, the variable cycle counter 610C, the calculation control unit 625C, and the calculation, stores the latest cycle set value held every time the variable cycle counter 610C generates a trigger. Continue to transmit to the unit 626C.

Then, the variable cycle counter 610C performs a count process for counting only the latest cycle set value, and generates a cycle signal as a trigger each time the count process is completed.
Further, as described above, the variable cycle counter 610C also generates the trigger that is generated every time the counting process is completed as the refresh trigger.

  Note that the period setting value transmitted to the variable period counter 610C is a variable value as described above. Therefore, the trigger generation unit 600C generates a refresh trigger with a variable period. That is, the trigger generation unit 600C generates a refresh trigger at a variable period so as to satisfy the refresh rate rule.

  In the following, a signal composed of a plurality of variable cycle refresh triggers generated by the trigger generation unit 600C according to Embodiment 4 is referred to as a variable cycle signal SA4.

  The trigger generator 600C generates a refresh trigger with a variable period. Therefore, according to the refresh control device A4 including the trigger generation unit 600C according to the fourth embodiment, a refresh trigger that generates, at a constant cycle, the level of noise caused by a plurality of refresh trigger cycles constituting the variable cycle signal SA4. It can be reduced from the level of noise caused by. That is, the noise level caused by the trigger cycle for requesting the memory refresh operation can be reduced from the noise level caused by the trigger generated at a constant cycle.

  FIG. 13 is an example of a timing chart for explaining the operation of the trigger generation unit 600C according to Embodiment 4 of the present invention. The horizontal axis in FIG. 13 indicates time. FIG. 13 is a timing chart in a case where the cycle upper limit value = 12 and the cycle lower limit value = 20.

  Referring to FIG. 13, the timing chart associated with the character string “calculation unit” indicates processing performed by calculation unit 626 </ b> C. The period in which “+1” is indicated is a period in which the calculation unit 626C performs a calculation process of incrementing the cycle setting value by one. The period in which “−1” is indicated is a period in which the calculation unit 626 </ b> C is performing calculation processing for decrementing the cycle setting value by one.

  The “cycle setting value” is a cycle setting value at each timing.

  In FIG. 13, one refresh trigger corresponds to one trigger (pulse).

  As shown in FIG. 13, the refresh trigger cycle is larger as the cycle setting value is larger. That is, the trigger generator 600C generates a refresh trigger with a variable period.

  It should be noted that by increasing the setting range of the cycle upper limit value and the cycle lower limit value, the effect of dispersing the refresh noise peak is enhanced. Here, the set width is a value to be added to or subtracted from the specified value corresponding to the aforementioned base period.

  However, when the cycle set value is updated by the up / down operation, there are places where the refresh operations are concentrated and executed locally.

  For example, by setting the setting range to ± 50% (in the above example, the cycle upper limit value is 24 and the cycle lower limit value is 8), the refresh cycle is locally twice the average rate. In other words, the period upper limit value and the period lower limit value that are optimal for the system may be determined in consideration of the effect on memory access to the DRAM.

  Note that the cycle upper limit value and the cycle lower limit value may be fixed values or variable values that can be set by the CPU 320.

  The trigger generation unit 600C is not limited to a configuration that generates a refresh trigger with a variable period. For example, the trigger generation unit 600C may have a function of generating a refresh trigger at a constant cycle and a function of generating the refresh trigger at a variable cycle.

  In this case, the refresh control device A4 according to the fourth embodiment has a function of generating a refresh trigger at a constant period and a function of generating a refresh trigger at a variable period.

  Here, in order to cause the trigger generation unit 600C to generate the refresh trigger at a constant cycle, for example, the CPU 320 sets the cycle setting value output from the cycle setting value holding unit 623C to a fixed value. What is necessary is just to control 623C.

  In this case, the rigger generator 600B generates a refresh trigger at a constant cycle. This makes it possible to cause the DRAM 200 to perform a refresh operation at the conventional timing under conditions that do not affect the reception state of the radio signal.

<Embodiment 5>
Next, a trigger generation unit 600D according to Embodiment 5 of the present invention will be described. Hereinafter, the refresh control device according to the fifth embodiment is referred to as a refresh control device A5. The refresh control device A5 differs from the refresh control device 400 of FIG. 1 only in that a trigger generation unit 600D is provided instead of the trigger generation unit 600. The rest of the configuration of refresh control device A5 is the same as that of refresh control device 400, and therefore detailed description will not be repeated.

  The trigger generation unit 600D is different from the trigger generation unit 600C in FIG. 3 mainly in that an M-sequence cyclic code generation unit is used. Although details will be described later, the period setting value is updated using the M-sequence cyclic code generated by the M-sequence cyclic code generation unit.

  FIG. 14 is a block diagram showing a configuration of trigger generation unit 600D according to Embodiment 5 of the present invention.

  Referring to FIG. 14, the trigger generation unit 600D is different from the trigger generation unit 600C of FIG. 11 in that it includes a cycle set value generation unit 620D instead of the cycle set value generation unit 620C. The rest of the configuration of trigger generation unit 600D is the same as that of trigger generation unit 600C, so detailed description will not be repeated.

  Similarly to the fourth embodiment, the variable cycle counter 610C performs a count process for counting only a variable cycle set value, and generates a cycle signal as a trigger (pulse) every time the count process ends. It transmits to generation part 620D.

  That is, the variable cycle counter 610C performs a count process for counting only a variable cycle set value, and generates a cycle signal as a trigger each time the count process is completed.

  The period setting value generation unit 620D outputs a random value as a period setting value to the variable period counter 610C every time a period signal is received.

  That is, similar to the cycle setting value generation unit 620C of FIG. 11, the cycle setting value generation unit 620D sets a different value as the cycle setting value to be counted by the variable cycle counter every time a periodic signal is received. Output to the variable period counter 610C.

  That is, every time the variable cycle counter 610C generates the trigger, the cycle set value generation unit 620D outputs a different value to the variable cycle counter as the cycle set value that the variable cycle counter 610C counts. To do.

  Further, the variable cycle counter 610C also generates the trigger that is generated every time the counting process is completed as the refresh trigger.

  Period set value generation section 620D has M-sequence cyclic code generation section 627 and subtraction section 628. The variable period counter 610 </ b> C transmits a period signal as a trigger (pulse) to the M-sequence cyclic code generation unit 627 every time the counting process ends.

  FIG. 15 is a block diagram showing an exemplary configuration of M-sequence cyclic code generation section 627 according to Embodiment 5 of the present invention.

  Referring to FIG. 15, M-sequence cyclic code generator 627 includes a shift register 50 and an EXOR (Exclusive OR) circuit 52.

  The shift register 50 is composed of five flip-flops 51. That is, the shift register 50 includes a five-stage flip-flop 51. The M-sequence cyclic code generator 627 outputs each output value of the five flip-flops 51 as a 5-bit M-sequence cyclic code.

  The operation of the M-sequence cyclic code generation unit 627 is the same as that of a general M-sequence cyclic code generation circuit, and thus will not be described in detail.

  The M-sequence cyclic code generation unit 627 outputs an M-sequence cyclic code, which is a random value, to the subtraction unit 628 every time a periodic signal is received. Specifically, every time a periodic signal is received, the M-sequence cyclic code generator 627 randomly selects one value from “1” to “31” and selects the selected value (M-sequence cyclic code). Is output.

  In the following, the period in which the M-sequence cyclic code generation unit 627 outputs all the values from “1” to “31” is referred to as a random value output period.

  Each time the M-sequence cyclic code is received, the subtraction unit 628 subtracts 1 from the received M-sequence cyclic code as a cycle setting value to be counted by the variable cycle counter 610C to the variable cycle counter 610C. Output.

  Here, the cycle in which the variable cycle counter 610C ends one count process is a cycle in which values from 0 to the cycle set value are counted. Here, as an example, the cycle that satisfies the refresh rate regulation is a cycle in which the variable cycle counter 610C counts 16 times. When the cycle setting value is 15, the variable cycle counter 610C counts 16 times.

  As described above, the M-sequence cyclic code generator 627 randomly selects one value from “1” to “31” one by one and outputs the selected value (M-sequence cyclic code). Therefore, the average value of the 31 M-sequence cyclic codes output from the M-sequence cyclic code generation unit 627 is “16”.

  Therefore, the average period can satisfy the refresh rate rule by setting the value obtained by subtracting “1” from the M-sequence cyclic code output from the M-sequence cyclic code generation unit 627 as the period setting value. That is, the trigger generation unit 600D generates a refresh trigger at a variable period so as to satisfy the refresh rate rule.

  Note that the configuration of the M-sequence cyclic code generation unit 627 is not limited to the configuration illustrated in FIG. 15, and may be another configuration as long as the circuit outputs a random value.

  FIG. 16 is an example of a timing chart for explaining the operation of trigger generation unit 600D according to the fifth embodiment. The horizontal axis in FIG. 16 indicates time.

  Referring to FIG. 16, “M-sequence cyclic code” is a value indicated by an M-sequence cyclic code at each timing.

  The “cycle setting value” is a cycle setting value at each timing.

  In FIG. 16, one refresh trigger corresponds to one trigger (pulse).

  For an average period of 16 (period setting value = 15), the value of the M-sequence cyclic code is updated in the range from “1” to “31”. Further, the variable period counter 610C performs a count process according to the period setting value obtained by subtracting “1” from the M-sequence cyclic code.

  As shown in FIG. 16, the larger the cycle setting value, the longer the refresh trigger cycle. That is, the trigger generator 600D generates a refresh trigger with a variable period. The variable cycle refresh trigger is transmitted to the refresh request unit 710 described above.

  Thereby, it is possible to prevent the generation period of the refresh request from satisfying the refresh rate rule and not to be a constant period. That is, the trigger generation unit 600A generates a refresh trigger at a variable period so as to satisfy the refresh rate rule.

  In the following, a signal composed of a plurality of variable period refresh triggers generated by the trigger generation unit 600D according to the fifth embodiment is referred to as a variable period signal SA5.

  The trigger generator 600D generates a refresh trigger at a variable cycle. Therefore, according to the refresh control device A5 including the trigger generation unit 600D according to the fifth embodiment, the refresh trigger that generates the noise level due to the cycles of the plurality of refresh triggers constituting the variable cycle signal SA5 at a constant cycle. It can be reduced from the level of noise caused by. That is, the noise level caused by the trigger cycle for requesting the memory refresh operation can be reduced from the noise level caused by the trigger generated at a constant cycle.

  Note that, depending on the configuration of the M-sequence cyclic code generation unit 627 or the range of values indicated by the M-sequence cyclic code, the configuration of the trigger generation unit 600D may be configured without the subtraction unit 628. In this case, every time a periodic signal is received, the M-sequence cyclic code generator 627 outputs the M-sequence cyclic code to the variable period counter 610C as a period setting value.

  That is, every time the variable period counter 610C generates a trigger, the M-sequence cyclic code generation unit 627 uses the M-sequence cyclic code having a different value as the period setting value to be counted by the variable period counter 610C. Output to the variable period counter 610C.

  The trigger generation unit 600D is not limited to a configuration that generates a refresh trigger with a variable period. For example, the trigger generation unit 600D may have a function of generating a refresh trigger at a constant cycle and a function of generating the refresh trigger at a variable cycle.

  In this case, the refresh control device A5 according to the fifth embodiment has a function of generating a refresh trigger at a constant cycle and a function of generating a refresh trigger at a variable cycle.

  Here, in order for the trigger generation unit 600D to generate a refresh trigger at a constant cycle, for example, the cycle set value generation unit 620D outputs a cycle output by the cycle set value generation unit 620D in response to an instruction from the external CPU 320. The set value may be a fixed value.

<Embodiment 6>
Next, Embodiment 6 of the present invention will be described with reference to the drawings.

  FIG. 17 is a diagram showing a configuration of radio receiver 1000 according to Embodiment 6 of the present invention.

  Referring to FIG. 17, the configuration of radio receiver 1000 is the same as that of radio receiver 1000 in FIG. 1, and therefore detailed description will not be repeated.

  Each component included in the wireless receiver 1000 is disposed on the substrate 60. That is, the tuner unit 311, the volatile memory (DRAM 200), and the refresh control device 400 are disposed on the same substrate 60.

  Here, a refresh control device having a configuration for generating a refresh trigger at a constant cycle is referred to as a refresh control device J.

  The trigger generation unit 600 generates a refresh trigger with a variable period. Therefore, the level of refresh noise generated during the refresh operation of the DRAM 200 can be reduced as compared with the refresh control device J that generates a refresh trigger at a constant period. Therefore, the refresh noise can be prevented from directly affecting the tuner unit 311.

  Here, the wireless receiver including the refresh control device J is assumed to be the wireless receiver 5000 of FIG. 19 as an example. The refresh control device J is assumed to be included in the memory controller 10. The wireless receiver 5000 includes a refresh control device J that generates a refresh trigger at a constant cycle.

  Therefore, as measures against refresh noise, a configuration in which a decoupling circuit is provided between the tuner unit 31 and the GND line in the wireless receiver 5000 and a configuration in which the tuner unit 31 is covered with an electromagnetic shield can be considered.

  That is, the wireless receiver 1000 does not need to provide expensive noise countermeasure parts such as an electromagnetic shield and a decoupling circuit that the wireless receiver 5000 has required as countermeasures for refresh noise.

  Therefore, the tuner unit 311 can be arranged on a common printed circuit board with the DRAM and other digital circuits. As a result, it is possible to reduce the price, weight, and size of the wireless receiver.

  Instead of the refresh control device 400, any of the above-described refresh control devices A2, A3, A4, and A5 may be disposed on the substrate 60. That is, the wireless receiver 1000 may include any of the refresh control devices A2, A3, A4, and A5 described above instead of the refresh control device 400.

  That is, the wireless receiver 1000 according to the sixth embodiment of the present invention includes a refresh control device, a tuner unit 311 that receives a wireless signal, and a volatile memory (DRAM 200) for holding data. The refresh control device generates a refresh trigger for requesting the volatile memory (DRAM 200) to execute the refresh operation at a variable cycle.

<Embodiment 7>
Next, Embodiment 7 of the present invention will be described with reference to the drawings.

  FIG. 18 is a diagram showing a configuration of a semiconductor integrated circuit 2000 according to the seventh embodiment of the present invention. 18 also shows the wireless receiver 1000 of FIG.

  The configuration of radio receiver 1000 in FIG. 18 is the same as that of radio receiver 1000 in FIG. 1, and therefore detailed description will not be repeated.

  The semiconductor integrated circuit 2000 includes a tuner unit 311, a CPU 320, and a memory controller 100 among a plurality of components included in the wireless receiver 1000.

  The memory controller 100 includes a refresh control device 400.

  That is, the semiconductor integrated circuit 2000 includes a refresh control device 400 and a tuner unit 311 that receives a radio signal.

  With the recent CMOS technology, it is possible to mount a tuner unit in the same semiconductor integrated circuit using a monolithic configuration of a tuner unit and a digital circuit. At this time, the influence on the reception state of the radio signal due to the noise propagation in the silicon and the semiconductor package can be considered.

  However, the semiconductor integrated circuit 2000 includes the trigger generation unit 600 that generates the refresh trigger at a variable period instead of the trigger generation unit that generates the refresh trigger at a constant period, thereby suppressing the influence of the reception state of the radio signal. Can do. Thereby, further miniaturization and cost reduction of the semiconductor integrated circuit can be realized.

  In the semiconductor integrated circuit 2000, any of the above-described refresh control devices A2, A3, A4, and A5 may be arranged instead of the refresh control device 400.

  In the semiconductor integrated circuit, the semiconductor of the tuner unit and the semiconductor of the digital circuit may be mounted in the same semiconductor package in a multichip configuration.

  Further, the DRAM 200 may be mixedly mounted on the semiconductor integrated circuit 2000. Even in this configuration, the semiconductor integrated circuit can be further reduced in size and price.

  As described above, the refresh control device according to the present invention has been described based on the embodiments. However, the present invention is not limited to these embodiments. Unless it deviates from the meaning of this invention, the form which carried out various deformation | transformation which those skilled in the art can think to this embodiment, or the structure constructed | assembled combining the component in different embodiment is also contained in the scope of the present invention. .

  In addition, all or some of the plurality of components constituting the refresh control device according to the present invention may be configured by hardware.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The present invention relates to a refresh control device that performs processing on a volatile memory that requires a refresh operation. In particular, since the wireless receiver has an effect of preventing interference of refresh noise with wireless reception, the present invention is suitable in the field of consumer audio and car audio products equipped with a radio tuner.

  Further, not only wireless reception but also a product field having a problem affected by digital noise in an analog circuit, an improvement effect can be expected by using the refresh control device of the present invention, and its application range is wide.

10,100 Memory controller 20,200 DRAM
30, 310 Antenna 31, 311 Tuner 32, 320 CPU
50 shift register 51 flip-flop 52 EXOR circuit 60 substrate 400 refresh control device 500 driver unit 600, 600A, 600B, 600C, 600D trigger generation unit 610 base cycle counter 610B reference counter 610C variable cycle counter 620, 620A comparison value generation unit 620B detection Unit 620C, 620D period setting value generation unit 621 comparison value holding unit 622 addition unit 623, 623A addition value holding unit 623C period setting value holding unit 624 limit processing unit 625, 625C operation control unit 626, 626C operation unit 627 M-sequence cyclic code Generation unit 628 Subtraction unit 630, 631 Match detection unit 640 OR operation unit 700 Arbitration function unit 710 Refresh request unit 720 Arbitration unit 1000, 5000 Wireless receiver 2000 Semiconductor integrated circuit

Claims (11)

An arbitration function unit that arbitrates a memory access request to a volatile memory that requires a refresh operation to hold data and a refresh trigger for requesting execution of the refresh operation;
Generation of a trigger for generating the refresh trigger at a non-constant period so as to satisfy a refresh rate rule that defines the number of times the refresh operation needs to be performed per predetermined time, which is a rule for the volatile memory to hold data With
The trigger generator is
A base period counter that sequentially indicates from a first value to a second value that is greater than the first value in a base period that satisfies the refresh rate rule, and that indicates the same value for each base period A counter,
A comparison value generating unit that outputs a value that is any value from the first value to the second value and that is different for each base period as a comparison value for each base period;
A coincidence detection unit that detects a coincidence timing at which a value indicated by the base period counter coincides with a latest comparison value output from the comparison value generation unit, and generates a refresh trigger at the coincidence timing; Includes refresh controller. The arbitration function unit
A refresh request unit that outputs a refresh request for requesting execution of the refresh operation based on the refresh trigger generated by the trigger generation unit;
The refresh control device according to claim 1, further comprising: an arbitration unit that arbitrates the refresh request output from the refresh request unit and the access request. The comparison value generator is
A comparison value holding unit that holds the comparison value and outputs the held comparison value;
An addition unit that performs an addition process of adding an addition value to the comparison value held in the comparison value holding unit for each base period;
A limit processing unit that determines whether or not the first calculation value calculated by the addition process is greater than the second value each time the addition unit performs the addition process;
The limit processing unit further includes:
When the first calculated value is larger than the second value, a limit process is performed to subtract the number from the first value to the second value from the first calculated value, and the limit process The calculated second calculated value is transmitted to the comparison value holding unit as the latest comparison value,
When the first calculated value is less than or equal to the second value, the first calculated value is transmitted as the latest comparison value to the comparison value holding unit,
The refresh control device according to claim 1, wherein the comparison value holding unit holds the latest comparison value transmitted from the limit processing unit instead of the held comparison value for each base period. The comparison value generator is
A comparison value holding unit that holds the comparison value and outputs the held comparison value;
An addition value holding unit that holds an addition value and outputs the latest addition value held for each base period;
An addition unit that performs an addition process of adding the latest addition value held by the addition value holding unit to the comparison value held by the comparison value holding unit for each base period;
A first determination unit that determines whether or not a first calculated value calculated by the addition process is greater than the second value each time the addition unit performs the addition process;
A second determination unit that determines whether the latest addition value output by the addition value holding unit is the first value or the second value;
Each time the latest addition value is output from the addition value holding unit, the calculation unit calculates using the addition value,
The second determination unit further includes:
When the addition value held in the addition value holding unit is the first value, a process of incrementing the addition value by 1 for each base period until the addition value becomes the second value; Each time the addition value is incremented by 1, the processing unit transmits the latest addition value to the addition value holding unit.
When the added value held in the added value holding unit is the second value, a process of decrementing the added value by 1 for each base period until the added value becomes the first value; Each time the addition value is decremented by 1, the processing unit transmits the latest addition value to the addition value holding unit.
The refresh control device according to claim 1, wherein the addition value holding unit holds the latest addition value transmitted from the arithmetic unit instead of the held addition value for each base period. The first determination unit further includes:
When the first calculated value is larger than the second value, a limit process is performed to subtract the number from the first value to the second value from the first calculated value, and the limit process The calculated second calculated value is transmitted to the comparison value holding unit as the latest comparison value,
When the first calculated value is less than or equal to the second value, the first calculated value is transmitted as the latest comparison value to the comparison value holding unit,
The refresh control device according to claim 4, wherein the comparison value holding unit holds the latest comparison value transmitted from the first determination unit instead of the held comparison value for each base period. An arbitration function unit that arbitrates a memory access request to a volatile memory that requires a refresh operation to hold data and a refresh trigger for requesting execution of the refresh operation;
Generation of a trigger for generating the refresh trigger at a non-constant period so as to satisfy a refresh rate rule that defines the number of times the refresh operation needs to be performed per predetermined time, which is a rule for the volatile memory to hold data With
The trigger generator is
A variable period counter that performs a counting process that counts only a variable period setting value for determining the generation timing of the refresh trigger, and that generates a trigger each time the counting process ends;
A period setting value generation unit that outputs a different value to the variable period counter as the period setting value to be counted by the variable period counter every time the variable period counter generates the trigger;
The variable cycle counter also generates the trigger that occurs every time the counting process ends as the refresh trigger. The cycle setting value output by the cycle setting value generation unit is any value from a fourth value to a fifth value greater than the fourth value,
The fourth value is a value obtained by subtracting a value of 1 / u (an integer greater than or equal to 2) of the specified value from a specified value corresponding to a base period that satisfies the refresh rate specification.
The fifth value is a value obtained by adding 1 / u of the specified value to the specified value.
The period set value generation unit
While holding the cycle setting value, each time the variable cycle counter generates a trigger, a cycle setting value holding unit that outputs at least the latest cycle setting value held to the variable cycle counter;
A determination unit that determines whether or not the latest cycle setting value output by the cycle setting value holding unit is the fourth value or the fifth value;
Each time the latest cycle setting value is output from the cycle setting value holding unit, the calculation unit calculates using the cycle setting value,
The determination unit further includes:
When the cycle setting value held in the cycle setting value holding unit is the fourth value, a process of incrementing the cycle setting value by 1 until the cycle setting value becomes the fifth value; Each time the cycle setting value is incremented by 1, the processing unit transmits the latest cycle setting value to the cycle setting value holding unit, and
When the cycle setting value held in the cycle setting value holding unit is the fifth value, a process of decrementing the cycle setting value by 1 until the cycle setting value becomes the fourth value; Each time the cycle set value is decremented by 1, the processing unit transmits the latest cycle set value to the cycle set value holding unit.
The cycle setting value holding unit holds the latest cycle setting value transmitted from the calculation unit instead of the held cycle setting value every time the variable cycle counter generates a trigger. The refresh control device according to 1. The period set value generation unit
The code generation unit that outputs an M-sequence cyclic code having a different value to the variable period counter as the period setting value to be counted by the variable period counter every time the variable period counter generates a trigger. 7. The refresh control device according to 6. The refresh control device
The refresh control device according to claim 1, further comprising a function of generating the refresh trigger at a constant period and a function of generating the refresh trigger at a non-constant period. The refresh control device according to any one of claims 1 to 9,
A tuner unit for receiving radio signals;
With volatile memory to hold data,
The said refresh control apparatus is a radio | wireless receiver which generate | occur | produces the refresh trigger for requesting | requiring execution of a refresh operation | movement to the said volatile memory with a fixed period. The refresh control device according to any one of claims 1 to 9,
A semiconductor integrated circuit comprising a tuner unit for receiving a radio signal.

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