JP5643553B2 - Nitride semiconductor microstructure manufacturing method, surface emitting laser and manufacturing method thereof - Google Patents

Description

The present invention relates to a method for manufacturing a microstructure of a nitride semiconductor, a surface emitting laser using a two-dimensional photonic crystal, and a method for manufacturing the same.
In particular, the present invention relates to a manufacturing method for forming a fine structure inside a nitride semiconductor, and relates to a technique used for a manufacturing method of a light emitting element using a photonic crystal.

As a surface emitting laser, a surface emitting laser using a two-dimensional photonic crystal as a reflecting mirror is known.
In particular, surface-emitting lasers using two-dimensional photonic crystals are difficult because it is difficult to fabricate distributed Bragg reflectors that are commonly used in surface-emitting lasers that use nitride semiconductors that can emit light in the near ultraviolet to green region. Has been actively studied.
A photonic crystal is a fine structure whose refractive index is modulated with a period equal to or shorter than the wavelength of light. Among these, a photonic crystal that functions in the visible range is composed of a plurality of fine holes having a size of several tens to hundreds of tens of nanometers.
When the photonic crystal has a structure embedded in a semiconductor, advanced manufacturing technology is required.
On the other hand, since it is possible to stack other semiconductor layers and electrodes on the semiconductor layer sandwiching the embedded photonic crystal, a photonic crystal optical device capable of current injection in the stacking direction is realized. There is an advantage that you can.

Patent Document 1 discloses a technique for forming fine vacancies in a nitride semiconductor using a mass transport phenomenon, and a method for manufacturing a surface emitting laser using a nitride semiconductor photonic crystal. ing.
The specific method is as follows.
First, holes are formed in the surface of the nitride semiconductor by EB lithography and dry etching.
In dry etching, a SiO ₂ hard mask is used.
Next, after forming the holes, the hard mask is removed and heat treatment is performed at 1000 ° C. in an atmosphere containing nitrogen.
As a result, mass transport of surface atoms occurs, and finally, the upper part of the hole is closed and a hole is formed.
A laser structure including an active layer is epitaxially grown on the photonic crystal to produce a nitride semiconductor surface emitting laser.
Further, a multilayer film of gallium nitride (GaN) and aluminum gallium nitride (AlGaN), which is less likely to cause a mass transport phenomenon than GaN, is used.
In patent document 1, the method of improving the positional accuracy of the depth direction in which a hole is formed by these is taken.

JP 2004-111766 A

The optical properties of photonic crystals depend on the size and shape of the holes.
To obtain a photonic crystal device with designed characteristics, it is necessary to control the size and shape of the holes with high accuracy.
That is, it is difficult to obtain a photonic crystal having good optical characteristics if the size of the hole varies greatly during the manufacturing process.
Semiconductor etching technology in the etching process for forming holes in the semiconductor surface has been established, and in this manufacturing process, the size of holes and in-plane variations can be accurately controlled.

  However, the technique disclosed in Patent Document 1 has a problem that the size of the hole becomes larger than the size of the hole before the heat treatment step after the heat treatment step following the etching step for forming the hole on the semiconductor surface. Yes.

  In view of the above problems, the present invention provides a fine structure including pores inside a semiconductor without greatly changing the size of the holes formed by precisely controlling the semiconductor etching process even after the heat treatment process. It is an object of the present invention to provide a method for manufacturing a microstructure of a nitride semiconductor that can be formed, a surface emitting laser using a two-dimensional photonic crystal, and a method for manufacturing the same.

The nitride semiconductor microstructure manufacturing method of the present invention is a nitride semiconductor microstructure manufacturing method,
On the main surface of the first semiconductor layer made of a group III nitride semiconductor excluding Al, a second semiconductor layer made of a group III nitride semiconductor containing at least Al is formed,
A first step of preparing a semiconductor structure having pores formed in the first semiconductor layer, the first semiconductor layer penetrating the second semiconductor layer;
After the first step, the semiconductor structure is heat-treated in an atmosphere containing a nitrogen element, and at least part of the sidewalls of the pores formed in the first semiconductor layer, the first semiconductor layer includes the first semiconductor layer. A second step of forming a group III nitride semiconductor crystal plane excluding Al;
After the second step, a third step of forming a third semiconductor layer made of a group III nitride semiconductor on the second semiconductor layer and closing the upper part of the pores;
It is characterized by having.
In addition, the method of manufacturing a surface emitting laser using a two-dimensional photonic crystal according to the present invention is characterized by being manufactured using a photonic crystal by the above-described nitride semiconductor microstructure manufacturing method.
The surface-emitting laser using the two-dimensional photonic crystal according to the present invention includes an active layer, and a photonic crystal formed by arranging a medium having different refractive indexes of a semiconductor layer and a hole in a two-dimensional cycle. A surface emitting laser using a two-dimensional photonic crystal,
The semiconductor layer is composed of a high refractive index semiconductor layer made of a group III nitride semiconductor excluding Al and a low refractive index semiconductor layer made of a group III nitride semiconductor containing at least Al, and the high refractive index semiconductor The layer is arranged on the side close to the active layer,
The crystal plane of the high refractive index semiconductor layer is formed on at least a part of the side wall of the hole.

According to the present invention, the size of the hole formed by precisely controlling the semiconductor etching process is not greatly changed even after the heat treatment process,
It is possible to realize a nitride semiconductor microstructure manufacturing method, a surface emitting laser using a two-dimensional photonic crystal, and a manufacturing method thereof, which enables formation of a microstructure including vacancies inside the semiconductor.

3 is a diagram for explaining a method for manufacturing a microstructure of a nitride semiconductor according to Embodiment 1. FIG. 3 is a perspective view of holes formed by the manufacturing method according to Embodiment 1. FIG. 6 is a cross-sectional view illustrating an example of a manufacturing process in Embodiment 2. FIG. In Embodiment 2, the light absorption α of the p electrode and the light confinement coefficient Γ of the active layer are calculated using the film thickness of the second semiconductor layer as a parameter. FIG. 4A is a schematic diagram of the structure used for the calculation. FIG. 4B shows the result of calculating α. FIG. 4C shows the result of calculating Γ. It is sectional drawing explaining the modification of the manufacturing process in Embodiment 3. It is sectional drawing explaining the example of the manufacturing process of the 1st process in Embodiment 4. 6 is a cross-sectional view illustrating an example of a manufacturing method in Example 1. FIG.

Next, a method for manufacturing a microstructure of a nitride semiconductor in an embodiment of the present invention will be described.
[Embodiment 1]
A method for manufacturing a microstructure of a nitride semiconductor according to Embodiment 1 to which the present invention is applied will be described with reference to FIG.
(First step)
First, the first step, which is a step of preparing a semiconductor structure having pores, will be described.
As shown in FIG. 1A, a first semiconductor layer 102 made of a group III nitride semiconductor excluding Al is stacked on a substrate 101.
Subsequently, a second semiconductor layer 104 made of a group III nitride semiconductor containing at least Al is stacked on the main surface 103 of the first semiconductor layer 102.
The substrate 101 is, for example, a hexagonal crystal, and more specifically, is preferably any one of GaN, sapphire, and SiC.
The first semiconductor layer 102 is, for example, a nitride semiconductor of GaN, GaInN, or InN.
Further, the second semiconductor layer 104 is a nitride semiconductor of any one of AlN, AlInN, AlGaInN, and AlGaN, for example.
In the present embodiment, the substrate 101 is a GaN substrate, the first semiconductor layer 102 is GaN, and the second semiconductor layer 104 is AlGaN.
The first semiconductor layer 102 and the second semiconductor layer 104 are grown by, for example, a metal organic vapor deposition (MOVPE) method. In the present embodiment, the main surface 103 of the first semiconductor layer 102 is a (0001) plane.

Next, a process for forming an etching mask for forming the pores will be described.
FIG. 1B is a diagram illustrating a process of forming an etching mask 106 for forming the pore 107 in the main surface 105 of the second semiconductor layer 104 following the process of FIG. .
Hereinafter, the process of FIG.1 (b) is demonstrated in order.
The material of the etching mask 106 is formed on the main surface 105 of the second semiconductor layer 104 by plasma CVD (Chemical Vapor Deposition).
The material of the etching mask 106 is preferably, for example, any one of silicon oxide, silicon nitride, and silicon oxynitride that can be easily processed.
In this embodiment, silicon oxide is used as a material for the etching mask 106.
Further, the film formation method of the etching mask may be sputtering or electron beam evaporation.
Subsequently, an opening 108 is formed in the etching mask 106. The opening 108 is formed using photolithography and etching.
The lithography may be electron beam lithography or nanoimprint lithography.
The etching of the opening 108 may be either wet etching or dry etching, but in order to improve the size controllability of the opening 108, dry etching by ICP (Inductively Coupled Plasma) is preferable.
Note that the opening 108 in the present embodiment is a circle having a diameter of 1 μm.

Next, the pore forming process will be described.
FIG. 1C illustrates a process of forming the pores 107 by etching the first semiconductor layer 102 through the second semiconductor layer 104 following the process of FIG. It is.
The step of forming the pore 107 may be either wet etching or dry etching, but in order to improve the controllability of the size of the pore 107, dry etching by ICP is preferable.
The plasma composition used in the dry etching process for forming the pores 107 includes, for example, any element of Cl, Br, and I.
More specifically, it is preferably a mixed gas plasma of any gas of Cl ₂ , BCl ₃ , HBr, HI, and HCl and any gas of He, Ar, Xe, and N ₂ .
After the step of forming the pores 107, the etching mask 106 is removed.
Through the steps from FIG. 1A to FIG. 1C, the second semiconductor layer 104 is provided on the main surface 103 of the first semiconductor layer 102 and penetrates through the second semiconductor layer 104. Thus, a semiconductor structure 100 having pores 107 formed in the first semiconductor layer 102 can be prepared.
Note that the pore 107 in the present embodiment has a circular shape with a diameter of 1 μm at the top and a depth of 2.5 μm.

(Second step)
Next, the second process, which is the heat treatment process shown in FIG. FIG. 1D is a diagram for explaining a second step of heat-treating the semiconductor structure 100 in an atmosphere containing a nitrogen element that is a group V following the step of FIG.
In the step of FIG. 1D, mass transport is generated on the side wall 109 in the region of the first semiconductor layer 102 of the pore 107, and nitridation that forms the first semiconductor layer 102 on at least a part of the side wall 109. A crystal plane 110 of the physical semiconductor is formed.
Note that mass transport is a phenomenon in which atoms are desorbed from a surface by thermal energy and then re-adsorbed at a position where the surface energy becomes small after being transported. While maintaining the composition of the semiconductor, the surface shape can be changed and the crystal plane can be formed.

Next, the atmosphere of the second process, which is a heat treatment process, will be described.
The second step is performed in an atmosphere containing a nitrogen element that is a group V, for example, in an atmosphere containing N ₂ or NH ₃ .
The reason for performing the heat treatment in the group V atmosphere is that the group V element is more easily desorbed than the group III element. By performing the heat treatment in the atmosphere in which the group V element is supplied, the first semiconductor layer 102 is heated. This prevents the reduction of V group elements.

Next, crystal plane formation by the second step will be described.
In this embodiment, since the main surface 103 of the first semiconductor layer 102 is a (0001) plane, the side wall 109 after the second step has the following (1-10n (where n is 0 to 4). An integer))) surface is formed.
That is, a crystal plane 110 equivalent to the (1-100) plane perpendicular to the main surface 103 is formed on the side wall 109 after the second step.
Or a (1-101) plane inclined about 62 degrees, a (1-102) plane inclined about 43 degrees, a (1-103) plane inclined about 32 degrees, a (1-104) plane inclined about 25 degrees, Any crystal plane 110 equivalent to is formed.
Note that when the main surface 103 of the first semiconductor layer 102 is a (1-100) plane, a crystal plane 110 equivalent to the (0001) plane is formed on the side wall 109.
Alternatively, any one of the following (1-10n (where n is an integer from 1 to 4)) surfaces is formed.
That is, any crystal plane 110 equivalent to the (1-101) plane, the (1-102) plane, the (1-103) plane, and the (1-104) plane is formed.
In the second step, the formation of the crystal face 110 means that the crystallinity of the surface of the pore 107 is improved.
For example, when the pore 107 is formed by dry etching, a number of atomic level defects are generated on the surface of the pore 107 due to ion bombardment in plasma.
However, when the crystal plane 110 is formed by mass transport, the atoms are rearranged so that these defects are repaired, and as a result, a surface with better crystallinity than before the heat treatment is obtained.
Further, if the crystal plane 110 perpendicular to the main surface 103 is formed by the mass transport in the second step, it can be used for shaping the pore 107 formed by dry etching.
That is, during dry etching, the plasma ion attraction voltage is lowered to sacrifice the verticality of the side wall 109 and suppress the generation of defects due to ion bombardment.
Next, in the second step, the verticality of the side wall 109 is obtained, and at the same time, defect repair of the surface is performed, so that the verticality of the pore 107 and the crystallinity of the side wall 109 are more than the state immediately after dry etching. Can be in good condition.

Next, the function of the second semiconductor layer made of a group III nitride semiconductor containing at least Al in the second step will be described.
In the second step shown in FIG. 1D, the main surface 103 of the first semiconductor layer 102 other than the pores 107 is covered with the second semiconductor layer 104.
Here, as disclosed in Patent Document 1, AlGaN is less likely to cause a mass transport phenomenon than GaN.
For this reason, the second semiconductor layer 104 suppresses a large size variation of the pore 107 caused by an excessive mass transport of the first semiconductor layer 102.
That is, if the main surface 103 of the first semiconductor layer 102 other than the pore 107 is not covered with the second semiconductor layer 104, atoms desorbed on the surface of the first semiconductor layer 102 enter the inside of the pore 107. After that, it adsorbs to the side wall 109. As a result, the pore diameter or depth of the pore 107 is reduced.
In this embodiment, with respect to the diameter of the opening 108 of 1 μm, the hole diameter of the pores 107 after the second step (the distance between the opposing side wall surfaces) is approximately 1 μm without changing substantially.

(Third step)
Next, the third step of closing the upper portion of the pore will be described.
FIG. 1E is a diagram for explaining a third step of closing the upper portion of the pore 107 following the step of FIG.
Following the second step, a third semiconductor layer 111 made of a group III nitride semiconductor is formed on the second semiconductor layer 104 by crystal growth so as to close the upper portion of the pore 107.
The third semiconductor layer 111 is formed of, for example, a nitride semiconductor of GaN, GaInN, InN, AlN, AlGaN, AlInN, or AlGaInN. In the present embodiment, the third semiconductor layer 111 is made of GaN.

Next, the effect of the crystal plane formed in the second step in the third step will be described.
In the third step, the crystal plane 110 formed on the side wall 109 in the second step functions effectively.
That is, since the crystal face 110 is formed on the side wall 109, the crystal growth rate can be controlled.
For example, in a state where the crystal plane 110 formed on the side wall 109 is a (1-100) plane, the growth rate of the (1-100) plane rather than the (0001) plane or the (1-101) plane in the third step. When the crystal grows under slow conditions, the pores can be blocked as follows.
That is, the upper portion of the pore 107 can be blocked with the third semiconductor layer 111 without greatly changing the pore diameter of the pore 107 (the interval between the opposing side wall surfaces).
Further, for example, in a state where the crystal plane 110 formed on the side wall 109 is the (1-101) plane, the (1-101) plane is more than the (0001) plane or the (1-100) plane in the third step. Even when the crystal grows under slow growth conditions, the pores can be blocked as follows.
That is, the upper portion of the pore 107 can be blocked with the third semiconductor layer 111 without greatly changing the depth of the pore 107.
In the present embodiment, the diameter of the upper portion of the pore 107 is 1 μm. However, in order to close the upper portion of the pore 107, the depth of the pore 107 is a depth such that the aspect ratio is 2 or more. Is preferred.
Further, when the diameter of the upper portion of the pore 107 is 1 μm or less, for example, if it is 300 nm or less, the upper portion of the pore 107 can be blocked even if the depth of the pore 107 is 2 or less in aspect ratio.
In order to reduce the fluctuation amount of the pore diameter (interval between the side wall surfaces facing each other) of the pore 107 before and after the third step, the diameter of the upper portion of the pore 107 before the third step is preferably 150 nm or less. .
The growth rate is controlled mainly by optimizing the temperature parameter of the atmosphere. In particular, since the first semiconductor layer 102 and the third semiconductor layer 111 have the same composition in this embodiment, the temperature optimization is performed. Can be arbitrary.
By sequentially performing the steps of FIG. 1A to FIG. 1E, it is possible to form the pores 120 whose size is precisely controlled inside the nitride semiconductor.

Here, as compared with Patent Document 1, the process of closing the upper part of the pore to form the pore is different.
In Patent Document 1, the mass transport of the GaN layer formed below the AlGaN layer is greatly promoted by only one heat treatment step, and mass transfer is caused from the GaN layer to the AlGaN layer. A hole is formed by closing the upper part of the substrate.
That is, since GaN forming the side walls of the pores of the GaN layer is mass transferred to the AlGaN layer, the size of the pores is increased.
On the other hand, in the present embodiment, the mass transport is used in the second step to form a crystal plane on at least a part of the side wall of the pore, and closes the top of the pore to provide a void. The step of forming is performed by crystal growth of the third semiconductor layer in the third step.
Thus, in Patent Document 1, the size of the pores is greatly increased by a large mass transport, whereas in the present embodiment, a crystal plane is formed on at least a part of the side wall surface of the pores. Because the mass transport is used only for this, there is no significant change in size.
That is, compared with Patent Document 1, in this embodiment, it is possible to form vacancies in the semiconductor layer while maintaining the size of the pores formed by etching.

Next, the outline of the pores after the second step will be described.
When the main surface 103 of the first semiconductor layer 102 is a (0001) plane, the pore 107 formed after the second step is a polyhedron including one of the crystal planes 110 equivalent to the next plane.
That is, it is a polyhedron including any crystal plane 110 equivalent to the (1-100) plane, (1-101) plane, (1-102) plane, (1-103) plane, or (1-104) plane. .
For example, FIG. 2 is a diagram illustrating an example of the pores 107 formed after the second step.
In FIG. 2 (a), the pore 107 has a lower end portion of a hexagonal column 201 composed of six crystal planes 110 equivalent to the (1-100) plane and six crystals equivalent to the (1-101) plane. The hexagonal weight 202 including the surface 110 is connected.
When the depth of the pore 107 is shallow, the hexagonal column 201 does not exist and the hexagonal weight 202 is directly connected.
In addition, each vertex constituting the pore 107 is not necessarily acute but may be rounded.
Further, by adjusting the temperature and atmosphere in the second step, the hexagonal pyramid 202 has any crystal plane 110 equivalent to the (1-102) plane, the (1-103) plane, and the (1-104) plane. It is also possible to make a polyhedron that includes
For example, depending on the conditions after the second step, the pores 107 having the shape shown in FIG. 2B are formed. In FIG. 2B, a hexagonal weight 202 including six crystal planes equivalent to the (1-103) plane is formed on the lower side (substrate side) of the hexagonal column 201.

[Embodiment 2]
In the second embodiment, an example of a manufacturing process of a photonic crystal configured by arranging a plurality of the above-described pores using the process of the first embodiment will be described.
In the present embodiment, the first semiconductor layer 102 is GaN, the second semiconductor layer 104 is AlGaN, and the third semiconductor layer 111 that closes the upper portion of the pore 107 is GaN.
The main surface 103 of the first semiconductor layer 102 is a (0001) plane.
Note that the first semiconductor layer 102 may be either GaInN or InN, and the third semiconductor layer 111 may be any one of AlN, AlGaN, GaInN, InN, AlInN, and AlGaInN.

Next, an etching mask forming process will be described.
As shown in FIG. 3A, the photonic crystal is formed by periodically forming a plurality of openings 108 in the step of patterning the openings 108 of the etching mask 106.
In this embodiment, circular openings 108 having a diameter of 120 nm are patterned in a square lattice pattern with a period of 300 nm in the surface of the etching mask 106.
Next, a pore forming step is performed.
Here, following the step of FIG. 3A, as shown in FIG. 3B, the plurality of pores 107 serving as lattice points of the photonic crystal are dry-etched to form the second semiconductor layer 104. And is formed in the first semiconductor layer 102.
Subsequently, the etching mask 106 is removed.

Next, the second step is performed.
That is, as shown in FIG. 3C, the second step of heat treatment is performed using the second semiconductor layer 104 as a mask for suppressing mass transport.
As a result, without greatly changing the hole diameter (interval of the opposite side wall surface) or hole depth of the pore 107 before and after the heat treatment,
By mass transport, a (1-100) plane perpendicular to the main surface 103 (0001) plane of the first semiconductor layer 102 is formed on the side wall 109 of the pore 107 forming the photonic crystal.
Next, as shown in FIG. 3D, a third step is performed.
That is, the third semiconductor layer 111 is formed by crystal growth on the second semiconductor layer 104 so as to close the upper portion of the pore 107.
As a result, holes are not formed inside the first semiconductor layer 102 and the second semiconductor layer 104 without greatly changing the hole diameter (interval between side wall surfaces facing each other) or the hole depth of the holes 107 formed by etching. 120 can be formed.
In this embodiment, the hole diameter after the third step (the distance between the opposing side wall surfaces) was about 105 nm. The fluctuation of the hole size is suppressed to 15 nm because of the effect of forming the crystal face 110 in the second step.
In particular, in the case of a photonic crystal, the size of the pores 107 (holes 120) is an important parameter for determining the magnitude of diffraction efficiency, and the size of the pores 107 is not greatly changed during the manufacturing process. This is a necessary condition for accurately producing a photonic crystal as designed.

Here, in the case where a surface emitting laser is manufactured by a method of manufacturing a surface emitting laser using a two-dimensional photonic crystal using the process of this embodiment, the influence of this embodiment on the optical characteristics of the surface emitting laser will be described. To do.
When a surface emitting laser using a two-dimensional photonic crystal is manufactured by using the process of this embodiment, the two-dimensional photonic crystal is arranged in a two-dimensional cycle with media having different refractive indexes due to semiconductor layers and holes. Configured.
Here, the semiconductor layer has a laminated structure of a high refractive index semiconductor made of a group III nitride semiconductor excluding Al and a low refractive index semiconductor made of a group III nitride semiconductor containing at least Al.
Further, when the two-dimensional photonic crystal is formed on the active layer, the low refraction made of a group III nitride semiconductor containing Al that functions as a mask for suppressing mass transport on the side far from the active layer. Rate semiconductors are formed.

FIG. 4A is a schematic diagram of the structure used for the calculation of the light absorption coefficient α of the p electrode and the light confinement coefficient Γ of the active layer in the surface emitting laser using the two-dimensional photonic crystal to which the present embodiment is applied. Show.
Based on the structure shown in FIG. 4A, in order to confirm the influence of the present embodiment on the optical characteristics of the surface emitting laser, the light absorption coefficient α of the electrode 407 in the surface emitting laser 400 and the active layer 403 Calculations were made for the optical confinement factor Γ.
In this calculation, the thickness of the lower light guide layer 402 is 100 nm, and the thickness of the active layer 403 is 22.5 nm.
In addition, the upper light guide layer 404 including a part of the two-dimensional photonic crystal 408 corresponding to the first semiconductor layer of Embodiment 1 and the semiconductor functioning as a mask for suppressing mass transport corresponding to the second semiconductor layer The total thickness of the layers 405 was 300 nm.
Further, the thickness of the upper light guide layer 406 corresponding to the third semiconductor layer located above the hole 409 is 100 nm, the thickness of the p-type electrode 407 is 50 nm, and the thickness of the lower cladding layer 401 is infinite. did.
The distance from the active layer 403 to the bottom of the hole 409 forming the two-dimensional photonic crystal 408 was set to 100 nm.
The calculation was performed assuming that the refractive index of the lower cladding layer 401 and the second semiconductor layer 405 functioning as a mask for suppressing mass transport is 2.48 corresponding to the refractive index of AlGaN having an Al composition of 10%.
In addition, the refractive index of the lower light guide layer 402, the upper light guide layer 404 including a part of the two-dimensional photonic crystal 408, and the refractive index of the upper light guide layer 406 positioned above the holes forming the two-dimensional photonic crystal 408 are set. The calculation was performed as 2.55 corresponding to the refractive index of GaN.
In addition, the refractive index of the active layer 403 is 2.62, and the p-type electrode 407 having a thickness of 50 nm is calculated by setting the refractive index of the lower 10 nm to 1.61 and the refractive index of the upper 40 nm to 1.66.
Also, the calculation is performed assuming that the lattice constant of the two-dimensional photonic crystal 408 composed of a square lattice is 160 nm, the diameter of the cylindrical hole forming the dimensional photonic crystal 408 is 64 nm, and the depth of the cylindrical hole is 200 nm. It was.
The calculation was performed with the emission wavelength set at 400 nm.

FIG. 4B shows the result of calculating the light absorption coefficient α at the p-type electrode 407 with respect to the thickness d of the semiconductor layer 405 functioning as a mask for suppressing mass transport corresponding to the second semiconductor layer. .
As d increases, α decreases.
This is because when the thickness d of the second semiconductor layer 405 having a low refractive index is increased, the average refractive index of the two-dimensional photonic crystal 408 is decreased, and introduction of light into the electrode 407 is suppressed. Is attributed.
FIG. 4C shows the result of calculating the optical confinement coefficient Γ in the active layer 403 with respect to the thickness d of the semiconductor layer 405 functioning as a mask for suppressing mass transport corresponding to the second semiconductor layer. is there.
Until d is 160 nm, Γ monotonically increases as d increases.
However, when d exceeds 160 nm, Γ turns from monotonic increase to monotonic decrease.
The reason why d increases monotonously up to 160 nm is due to the suppression of the spread of light above the two-dimensional photonic crystal 408 due to the decrease in the average refractive index of the two-dimensional photonic crystal 408, as in the case of α described above. Therefore, the light confinement in the active layer 403 is further increased accordingly.
On the other hand, if d exceeds 160 nm, the average refractive index of the two-dimensional photonic crystal 408 decreases too much, and the peak of the light distribution shifts below the active layer 403, thereby reducing light confinement in the active layer 403. To do.
Therefore, the thickness of the second semiconductor layer is preferably 160 nm or less.
As described above, when a surface-emitting laser using a two-dimensional photonic crystal is manufactured using the process of this embodiment, it is possible to suppress light absorption at the p-type electrode and increase light confinement in the active layer. The optical characteristics of the surface emitting laser can be improved.

[Embodiment 3]
In Embodiment Mode 3, a case where at least one side of the upper surface shape of the opening of the etching mask 106 is formed using an etching mask having one side parallel to the crystal surface 110 of the first semiconductor layer 102 will be described. .
In the second step of the present invention, the crystal plane 110 of the first semiconductor layer 102 is formed on the side wall 109 of the pore 107 by mass transport.
In this embodiment, since the main surface 103 of the first semiconductor layer 102 is the (0001) plane, the (1-100) plane perpendicular to the main surface 103 is formed on the side wall 109 in the second step. It is formed.
That is, as shown in FIG. 5 (a), even if the top surface shape of the pores 107 is circular 501 before the second step, as shown in FIG. 5 (b) after the first heat treatment step. The upper surface shape is transformed into a hexagon 502.
The diameter of the pores 107 (the distance between the opposing side wall surfaces) varies considerably when deformed from the circle 501 to the hexagon 502.
In FIG. 5B, the dotted line indicates the size of the original circle 501.
Therefore, in the present embodiment, in order to reduce the amount of fluctuation before and after the heat treatment as much as possible, a top surface shape of the pores 107 is prepared in advance before the second step.

The process will be described below.
The shape of the opening 108 of the etching mask 106 is transferred as the shape of the upper surface of the pore 107 before the second step.
Therefore, in the step of patterning the opening 108, patterning may be performed so that the shape of the upper surface of the opening 108 is constituted by a side parallel to the crystal plane 110 of the first semiconductor layer 102.
In the present embodiment, since the main surface 103 is a (0001) plane, the regular hexagon 503 constituted by sides parallel to a plane equivalent to the (1-100) plane is patterned.
The sides parallel to the plane equivalent to the (1-100) plane are the [1-100] direction, the [10-10] direction, the [01-10] direction, the [-1100] direction, It is a side parallel to either the [−1010] direction or the [0−110] direction.

Note that the sides constituting the regular hexagon 503 do not have to be completely parallel to the crystal plane 110 of the first semiconductor layer 102, and a deviation of ± 10 ° is allowed.
Note that it is preferable that the apex of the regular hexagon 503 to be patterned be on the crystal axis (a-axis) of the first semiconductor layer 102.
Further, each vertex of the regular hexagon 503 is not necessarily acute.
The pores 107 formed in this way are regular hexagons 503 formed by a plane parallel to the crystal plane 110 of the first semiconductor layer 102 as shown in FIG. 5C before the second step. .
Even after the second step, as shown in FIG. 5D, the shape of the upper surface of the pore 107 becomes a hexagon 504, and the shape and size hardly change.

The manufacturing process of this embodiment is an effective process that can form the holes 120 inside the semiconductor without changing the hole diameter of the pores 107 after the etching process (interval between opposing side wall surfaces) as much as possible.
In the present embodiment, the case where the main surface 103 of the first semiconductor layer 102 is the (0001) plane has been described. However, when the main surface 103 is the (1-100) plane, the opening 108 has a rectangular shape. do it.
That is, it is a quadrangle composed of sides parallel to the (0001) plane and a plane equivalent to the (10-10) plane.
The (0001) plane and the side parallel to the plane equivalent to the (10-10) plane are sides parallel to either the <0001> direction or the <10-10> direction.

[Embodiment 4]
In the present embodiment, a case will be described in which the pores 107 are formed by crystal growth instead of etching in the first step.
The process will be described below.
First, the first semiconductor layer 102 is formed with a thickness corresponding to the height of the bottom surface of the pore 107.
Next, as shown in FIG. 6A, a crystal growth suppression mask 601 made of, for example, silicon oxide or the like is formed on the first semiconductor layer 102 using, for example, an electron beam evaporation apparatus or a sputtering apparatus. The film is formed with a film thickness exceeding the height of the hole 120.
Then, as shown in FIG. 6B, a resist 602 is formed at a place where the pore 107 on the crystal growth suppression mask 601 is formed by electron beam exposure after film formation.
Subsequently, the crystal growth suppressing mask 601 is dry-etched using the resist 602 as a mask.
Thereafter, by removing the resist 602, as shown in FIG. 6C, a columnar crystal growth suppression mask 610 having the shape of the pore 107 is formed.
The etching of the crystal growth suppression mask 601 may be either wet etching or dry etching, but in order to improve the size controllability of the columnar crystal growth suppression mask 610, dry etching by ICP is preferable. Next, as shown in FIG. 6D, on the first semiconductor layer 102 on which the columnar crystal growth suppression mask 610 is formed,
The first semiconductor layer 102 and the second semiconductor layer 104 are formed in this order at a predetermined film thickness corresponding to the height of the hole 120 from a portion where the columnar crystal growth suppression mask 610 is not provided. To do.
Subsequently, the columnar crystal growth suppression mask 610 is removed.
Thereby, as shown in FIG. 6E, the second semiconductor layer 104 is provided on the main surface 103 of the first semiconductor layer 102 and penetrates through the second semiconductor layer 104. A semiconductor structure 100 having pores 107 formed in one semiconductor layer 102 can be prepared.

Here, silicon oxide can be dry-etched with lower power than GaN.
For this reason, the damage to the layer disposed under the layer to be dry etched is smaller in the silicon oxide etching than in the GaN etching.
Therefore, for example, in a surface emitting laser in which a photonic crystal layer is formed on an active layer, compared to the case where the photonic crystal layer is formed by dry etching an epitaxial layer made of GaN,
In this embodiment, dry etching can be performed with low power, and damage to the active layer can be reduced.
As described above, according to the present embodiment, by forming a hole by crystal growth using a crystal growth suppression mask that can be dry-etched with low power compared to GaN, a layer for forming a hole is formed. Damage to the lower layer due to dry etching can be reduced.

Next, examples of the present invention will be described.
In this embodiment, a surface emitting laser including a two-dimensional photonic crystal configured by applying the present invention will be described with reference to FIG.
(First step)
The first step in this embodiment will be described with reference to FIGS. 7 (a) to 7 (c).
First, the nitride semiconductor layer crystal growth step included in the first step of this embodiment will be described with reference to FIG.
As shown in FIG. 7A, the following layers are grown on the GaN substrate 701 by the MOVPE method in the following order.
That is, the n-type cladding layer 702 is n-type Al _0.09 Ga _0.91 N, the n-type guide layer 703 is n-type GaN, the active layer 704, the p-type guide layer 705 is p-type GaN, and the mass transport suppression layer 706. A certain p-type Al _0.1 Ga _0.9 N is grown in this order.
Here, the p-type guide layer 705 corresponds to the first semiconductor layer 102 shown in the first embodiment, and its main surface 707 is a (0001) plane. The mass transport suppression layer 706 corresponds to the second semiconductor layer 104 described in Embodiment 1.
The film thickness of p-type Al _0.1 Ga _0.9 N is 100 nm.
The growth temperature T1 of p-type GaN is 1100 ° C., and the growth temperature T2 of p-type Al _0.1 Ga _0.9 N is 1150 ° C.
The active layer 704 forms a multi-quantum well structure with three periods, and the material is In _0.09 Ga _0.91 N for the well layer and GaN for the barrier layer.
Note that the second semiconductor layer in this embodiment is not particularly limited to the above-described 100 nm-thickness p-type Al _0.1 Ga _0.9 N. If the second semiconductor layer functions as a mask for suppressing mass transport, other Al layers may be used. It may be a composition or a film thickness.
Here, when AlGaN is crystal-grown on GaN, if the Al composition is increased, crystal cracking (cracks) occurs due to the effect of lattice distortion, which increases the possibility of adversely affecting the device characteristics.
Similarly, when the film thickness of AlGaN is increased, crystal cracking (cracks) occurs due to the effect of lattice distortion, which increases the possibility of adversely affecting the device characteristics.
In addition, the p-type AlGaN in this example also functions as a p-type conductive layer, but if the Al composition becomes high, the electric conduction characteristics may be deteriorated.
On the other hand, as described above, since AlGaN has a lower refractive index than GaN, in this embodiment, it is possible to suppress light absorption at the p-type electrode and increase light confinement in the active layer.
Therefore, in the case of p-type Al _0.1 Ga _0.9 N in this example, the film thickness is preferably 160 nm or less.

Next, an etching mask forming step included in the first step in this embodiment will be described.
FIG. 7B shows the mass transport suppressing layer 706 penetrating the p-type Al _0.1 Ga _0.9 N.
The p-type GaN in the a p-type Al _0.1 Ga _0.9 and the guide layer 705, for forming a two-dimensional photonic crystal is a diagram for explaining a step of forming an etching mask 708.
Hereafter, the process of FIG.7 (b) is demonstrated in order.
First, a SiOx film having a thickness of 150 nm is formed on the mass transport suppression layer 706 by plasma CVD.
Subsequently, a two-dimensional photonic crystal pattern including a plurality of openings 709 is formed on the SiOx film by electron beam lithography and ICP etching.
The apertures 709 have a hole diameter of 60 nm and are arranged in a square lattice pattern with a period of 160 nm in the in-plane direction.

Next, a process for forming a two-dimensional photonic crystal included in the first process in the present embodiment will be described.
FIG. 7C shows an etching mask 708 (SiOx film) following the process of FIG.
The figure explaining the process of removing this etching mask 708, after penetrating the mass transport suppression layer 706 and etching the p-type guide layer 705 to form a two-dimensional photonic crystal composed of a plurality of pores 710. is there.
The two-dimensional photonic crystal is formed by dry etching using ICP.
The gas composition of ICP is a mixed gas plasma of Cl ₂ and Ar. The depth of the pores 710 of the two-dimensional photonic crystal after the etching is 100 nm.

(Second step)
Next, the second step in the present embodiment will be described.
FIG. 7D is a diagram for explaining a second step following the step of FIG.
That is, in this second step, heat treatment is performed in an atmosphere containing a nitrogen element that is a group V, and mass transport is generated in the p-type GaN that is the p-type guide layer 705 using the mass transport suppression layer 706 as a mask. .
Then, a p-type GaN crystal plane 712 that is a material of the p-type guide layer 705 is formed on the side wall 711 of the pore 710 constituting the two-dimensional photonic crystal.
The atmosphere of the second step is an N ₂ flow rate of 10 slm (standard litter per minute), an NH ₃ flow rate of 5 slm, and a heat treatment temperature T3 of 1025 ° C.
The N ₂ flow rate of 10 slm is 0.45 mol / min, and the NH ₃ flow rate of 5 slm corresponds to 0.22 mol / min.
In the second step of the present embodiment, CP ₂ Mg does not flow a p-type dopant raw material, in terms of the optimization of the heat treatment step, may be flowed CP ₂ Mg. Since the main surface 707 of p-type GaN which is the p-type guide layer 705 is the (0001) plane, the side wall 711 is inclined by the mass transport with the (1-100) plane perpendicular to the main surface 707, (1-103) plane is formed.
Here, as described above, the purpose of the second step is to form the p-type GaN that is the material of the p-type guide layer 705 on the side wall 711 of the pore 710 formed in the p-type GaN that is the p-type guide layer 705. Forming a crystal plane 712 of.
For this reason, the relationship between the growth temperature T1 of the first semiconductor layer, the growth temperature T2 of the second semiconductor layer, and the heat treatment temperature T3 is such that a great mass transport as in Patent Document 1 does not occur.
In order to satisfy the relationship of T3 ≦ T1, T2, T3 = 1025 ° C. and the holding time is 4 minutes.

(Third step)
Next, the third step in the present embodiment will be described.
FIG. 7E is a diagram for explaining a third step following the step of FIG.
That is, in this third step, the upper part of the pores 710 of the two-dimensional photonic crystal is closed with the p-type GaN cap layer 713 by crystal growth, and the p-type GaN layer and the p-type Al _0.1 Ga _0.9 N inside. Embed a two-dimensional photonic crystal.
Note that in this example, the cap layer 713 corresponds to the third semiconductor layer 111 described in Embodiment 1.
As a result of the third step, the upper portion of the two-dimensional photonic crystal is closed with the cap layer 713 without substantially changing the hole diameter of the pores 710 of the two-dimensional photonic crystal (the distance between the opposing side wall surfaces). Could be formed.

Next, as shown in FIG. 7F, on the cap layer 713 (p-type GaN), p-type Al _0.1 Ga _0.9 N which is a p-type cladding layer 715, and p-type GaN which is a p-type contact layer 716. Are sequentially grown by the MOVPE method.

Next, a Ti / Al n-side electrode is formed on the back surface of the GaN substrate 701, and a Ti / Au p-side electrode 717 is formed on the p-type contact layer surface by photolithography, electron beam evaporation, and lift-off.
Through the above steps, a two-dimensional photonic crystal surface emitting laser that is driven in a wavelength band of 400 nm can be manufactured.

100: Semiconductor structure 101: Substrate 102: First semiconductor layer 103: Main surface 104 of the first semiconductor layer: Second semiconductor layer 105: Main surface 106 of the second semiconductor layer 106: Etching mask 107: Pore 108 : Opening 109: Side wall 110: Crystal plane 111: Third semiconductor layer 120: Hole

Claims (11)

A method of manufacturing a microstructure of a nitride semiconductor,
On the main surface of the first semiconductor layer made of a group III nitride semiconductor excluding Al, a second semiconductor layer made of a group III nitride semiconductor containing at least Al is formed,
A first step of preparing a semiconductor structure having a second semiconductor layer formed by penetration of said first semiconductor layer hole formed,
After said first step, said semiconductor structure is heat-treated in an atmosphere containing nitrogen element, at least a portion of a sidewall of the first semiconductor layer in the hole formed, the in the first semiconductor layer Al A second step of forming a crystal plane of the group III nitride semiconductor excluding
After the second step, a third step of closing the on the second semiconductor layer to form a third semiconductor layer made of a Group III nitride semiconductor, the upper portion of the front Kiana,
A method for producing a microstructure of a nitride semiconductor, comprising: When the temperature at the time of forming the first semiconductor layer is T1, the temperature at the time of forming the second semiconductor layer is T2, and the temperature of the heat treatment in the second step is T3, each of these temperatures Relationship
The method for manufacturing a microstructure of a nitride semiconductor according to claim 1, wherein the relationship of T3≤T1, T2 is satisfied. The first step includes
After forming the second semiconductor layer on the main surface of the first semiconductor layer,
Wherein the second semiconductor layer through to said first semiconductor layer to Ru formed hole, a nitride semiconductor fine according to claim 1 or claim 2, characterized in that it comprises a step of forming by etching Structure manufacturing method. In forming the pre Kiana by the etching, and wherein at least one side of the upper surface shape of the opening is, an etching mask having one side which is parallel to the crystal plane of the first semiconductor layer is used A method for manufacturing a microstructure of a nitride semiconductor according to claim 3. The first step includes
Wherein on the surface of the first semiconductor layer, said first semiconductor layer and the second is the mask for suppressing crystal growth of the semiconductor layer, the crystal growth suppression mask in the shape of a pre Kiana Forming a step;
After the step of forming the crystal growth suppression mask, in a region on the main surface of the first semiconductor layer where the crystal growth suppression mask is not formed,
Laminating the same semiconductor layer as the first semiconductor layer, and further laminating the second semiconductor layer thereon,
A step of laminating the same semiconductor layer as the first semiconductor layer and further laminating the second semiconductor layer thereon, and thereafter removing the mask for suppressing crystal growth;
The method of manufacturing a microstructure of a nitride semiconductor according to claim 1 or 2, characterized in that Before Kiana The manufacturing method of the nitride semiconductor microstructure according to any one of claims 1 to 5 intervals of the side wall surface facing the hole is equal to or is 1μm or less. Manufacturing method of the nitride semiconductor microstructure according to any one of claims 1 to 6, characterized in that before forming a plurality arranged so it consists photonic crystal Kiana. And the active layer, the photonic crystal is manufactured me by the manufacturing method of the nitride semiconductor microstructure according to claim 7 A method for manufacturing a surface emitting laser and a two-dimensional photonic crystal method for manufacturing a surface-emitting laser you characterized. An active layer, a surface emitting laser and a secondary Motofu photonic crystal,
The two-dimensional photonic crystal includes a first semiconductor layer, the side close to the second semiconductor layer made of a Group III nitride semiconductor, the said active layer comprising at least Al formed of a Group III nitride semiconductor except for Al It has in order from a plurality of holes, through said second semiconductor layer, is formed on the first semiconductor layer,
At least in part on the first surface emitting laser characterized in that the crystal face of the semiconductor layer is formed of a side wall of the front Kiana. The surface emitting laser according to claim 9, wherein the second semiconductor layer is made of AlGaN, and the first semiconductor layer is made of GaN. 11. The surface emitting laser according to claim 10, wherein the AlGaN has an Al composition of 10% and a thickness of the AlGaN of 160 nm or less.

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