JP5636886B2 - Dielectric breakdown lifetime simulation method and silicon wafer surface quality evaluation method - Google Patents

Dielectric breakdown lifetime simulation method and silicon wafer surface quality evaluation method Download PDF

Info

Publication number
JP5636886B2
JP5636886B2 JP2010249919A JP2010249919A JP5636886B2 JP 5636886 B2 JP5636886 B2 JP 5636886B2 JP 2010249919 A JP2010249919 A JP 2010249919A JP 2010249919 A JP2010249919 A JP 2010249919A JP 5636886 B2 JP5636886 B2 JP 5636886B2
Authority
JP
Japan
Prior art keywords
insulating film
silicon wafer
dielectric breakdown
simulation
defects
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2010249919A
Other languages
Japanese (ja)
Other versions
JP2012104561A (en
Inventor
大槻 剛
剛 大槻
Original Assignee
信越半導体株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 信越半導体株式会社 filed Critical 信越半導体株式会社
Priority to JP2010249919A priority Critical patent/JP5636886B2/en
Publication of JP2012104561A publication Critical patent/JP2012104561A/en
Application granted granted Critical
Publication of JP5636886B2 publication Critical patent/JP5636886B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Description

  The present invention relates to a dielectric breakdown lifetime simulation method and a quality evaluation method for a silicon wafer surface, for example, performed at the time of quality evaluation of a MOS device or the like.

In semiconductor devices such as MOS (Metal Oxide Semiconductor) transistors and MOS capacitors, the quality of an insulating thin film (hereinafter also referred to as an insulating film) greatly affects the dielectric breakdown lifetime in long-term reliability.
Therefore, for example, TZDB (Time Zero Dielectric Breakdown) or TDDB (TimeDB) is performed by an acceleration test under an electric field stress in which the voltage applied to the insulating film is higher than the actual device operation or a temperature stress at a higher temperature than that during the operation. Dependent Dielectric Breakdown) measurement is performed, and the insulating film is evaluated. Among them, the TDDB measurement is used for evaluating wafers in recent years because it evaluates reliability (life) and applies a higher stress than TZDB.

Up to now, many physical models have been studied and proposed for dielectric breakdown of an insulating film such as a silicon oxide film formed on a silicon wafer. Among them, the injection of electrons from the electrode of the metal electrode (M) or the substrate (silicon wafer) (S) due to the electric field and temperature into the insulating film, the current mechanism in the insulating film, etc. are investigated in detail. It has been found that the holes generated by the above and the injection and accumulation of the holes into the film greatly affect the dielectric breakdown (for example, see Non-Patent Documents 1 and 2).
By the way, in the TDDB measurement of the MOS capacitor widely used for the reliability evaluation of the insulating film, the dielectric breakdown of the insulating film occurs stochastically. This is mainly due to non-uniform distribution of so-called weak spots, pinholes, holes or electron charge traps, and impurities such as hydrogen, which are defects in the insulating film, in the film.

  Therefore, a stochastic model has been proposed in which the breakdown of the insulating film is regarded as a stochastic process, and simulation is predicted mathematically and statistically. As the model, there is a percolation model (seepage 3). This is because, for example, a silicon oxide film is divided into a mesh structure to form minute cells, and assuming the probability that each cell will break, dielectric breakdown occurs when the broken cells form a line in the thickness direction of the oxide film. Is a probabilistic model that

  In the above probability model, it is known that when the insulating film is thick, the deviation from the actually measured value is large, and when the insulating film is thin, the measured value is well matched. Therefore, the dielectric breakdown simulation prediction of the insulating film using this probability model is useful when the thickness of the insulating film is thin to some extent. For this reason, for adaptation to a thick oxide film, for example, a proposal has been made to model the presence of traps in the film (see, for example, Non-Patent Document 4).

JP 2010-62346 A

"International Journal of High Speed Electronics and Systems", Vol. 11, no. 3 (2001), pp. 849-886 "IEEE Transactions on Electron Devices", Vol. 36, no. 11 (1989) pp. 11-11. 2462-2465 "International Journal of High Speed Electronics and Systems", Vol. 11, no. 3 (2001), pp. 789-848 "Fuji Times" Vol 80 (6), 2007. pp. 457-460

However, when an insulating film such as a silicon oxide film becomes thinner, the dielectric breakdown is greatly influenced by the quality of the surface of the silicon wafer that is a semiconductor device substrate.
In Patent Document 1, in consideration of the quality state (defect amount, defect size, microroughness) of the surface of the silicon wafer, specifically, the surface failure of the silicon wafer is determined by a dielectric breakdown lifetime simulation method based on a Monte Carlo computer simulation. This can be dealt with by cutting into a cell on the wafer as a defect that destroys the cell.

However, an actual silicon wafer is manufactured through a manufacturing process of various processes such as lapping, etching, mirror polishing, and washing after a silicon single crystal ingot that has been pulled and grown is sliced into a thin disk shape. On the surface of the silicon wafer produced in this way, there is a grow-in defect generated during the pulling and growing of the single crystal ingot. Further, in pulling growth, defects such as precipitates of interstitial oxygen (BMD: Bulk Micro Defect) that are taken in from a quartz crucible into a silicon single crystal ingot and are dissolved are present even if they are minute. Further, unevenness at the atomic level (hereinafter referred to as microroughness or simply roughness) remains on the wafer surface. Further, in these wafer manufacturing processes, the occurrence of contamination is always a concern, and it is fully conceivable that metal contamination affects the insulating film also in the device manufacturing process.
Therefore, in the simulation, if only the substrate / insulating film interface is considered, the matching with the actual dielectric breakdown affected by the metal contamination and roughness described above is insufficient.

  In the conventional dielectric breakdown lifetime simulation prediction as described above, the actual situation around the insulating film has not been sufficiently considered.

  The present invention has been made in view of the above problems, and by performing accurate simulation suitable for the dielectric breakdown life of an actual device and obtaining the accurate dielectric breakdown lifetime of the insulating film, It is an object of the present invention to provide a dielectric breakdown lifetime simulation method and a silicon wafer surface quality evaluation method capable of accurately analyzing defect types, defect sizes, and the like.

  In order to achieve the above object, the present invention regards a dielectric breakdown of the insulating film as a stochastic process in a structure having a silicon wafer, an insulating film on the silicon wafer, and a metal electrode on the insulating film, A computer that generates a random number of defects in the insulating film, and that the insulating film breaks down when the generated defect is connected from the interface of the insulating film with the silicon wafer to the interface with the metal electrode. A simulation method for obtaining a dielectric breakdown lifetime of the insulating film by simulation, in the structure to be simulated, at an interface between the silicon wafer and the insulating film and an interface between the insulating film and the metal electrode, and / or In the structure in which defects are incorporated in the insulating film in advance and the defects are incorporated, defects are generated in the insulating film with random numbers. Thereby providing a dielectric breakdown lifetime simulation method characterized by determining the dielectric breakdown lifetime of the insulating film.

  As described above, in the structure to be simulated, a defect is previously incorporated in the interface between the silicon wafer and the insulating film and the interface between the insulating film and the metal electrode and / or in the insulating film. By generating defects with random numbers and determining the dielectric breakdown lifetime of the insulation film, we perform accurate simulations that incorporate the defects in the insulation film that affect the dielectric breakdown and the wafer surface quality, and provide insulation close to that of the actual device. Destruction life can be determined. For this reason, the quality of the actual device and the quality of the silicon wafer surface can be evaluated with high accuracy using the simulation of the present invention.

At this time, it is preferable that the size, density, or position of the defect to be incorporated in advance is an assumed value that predicts a defect in an actual silicon wafer, an insulating film, a metal electrode, or an interface thereof.
As described above, in the simulation of the present invention, the size, density, or position of the defects to be incorporated in advance is assumed to be a hypothetical value that predicts the defects at the actual silicon wafer, insulating film, metal electrode, or their interface, thereby providing more accuracy. In addition, the amount of defects in the actual device can be accurately evaluated based on the simulation result.

At this time, it is preferable to set the size or position of the defect to be incorporated in advance based on the Poisson distribution.
Thus, in the simulation of the present invention, a more accurate simulation can be performed by setting the size or position of the defect to be incorporated in advance based on the Poisson distribution.

At this time, the thickness of the insulating film for simulating the dielectric breakdown lifetime can be 10 nm or less.
As described above, when the thickness of the insulating film for simulating the dielectric breakdown lifetime is 10 nm or less, the present invention can perform a simulation in consideration of the quality of the surface of the silicon wafer. Therefore, it is possible to obtain an accurate dielectric breakdown lifetime in conformity with the device.

  The present invention also relates to a method for evaluating the quality of a silicon wafer surface, wherein measured data of TDDB of a plurality of MOS capacitors fabricated by forming an insulating film and a metal electrode on the silicon wafer is measured. In the dielectric breakdown lifetime simulation method, the same conditions as the MOS capacitor are set, TDDB indicating the dielectric breakdown lifetime of the insulating film is obtained, and the TDDB obtained in the simulation is compared with the measured data of the TDDB, There is provided a quality evaluation method for a surface of a silicon wafer, characterized by evaluating a surface defect of the silicon wafer based on a set value of a defect previously incorporated in the simulation.

  With such a quality evaluation method for the surface of a silicon wafer, the actual amount of silicon wafer defects can be determined based on the defects set in the simulation by comparing the TDDB accurately obtained by the simulation method of the present invention with the measured data. Roughness etc. can be accurately evaluated.

  As described above, according to the present invention, simulation suitable for the dielectric breakdown of an actual device can be performed, the dielectric breakdown lifetime can be obtained accurately, and the surface quality of an actual silicon wafer can be accurately evaluated. it can.

It is a flowchart which shows an example of the embodiment of the dielectric breakdown simulation method of this invention. It is explanatory drawing which shows the example of arrangement | positioning of the defect integrated previously in the dielectric breakdown simulation method of this invention. It is a Weibull plot of TDDB calculated | required by simulation in Example 1 and Comparative Example 1, and TDDB calculated | required by actual measurement. It is a Weibull plot of TDDB calculated | required by simulation in Example 2 and Comparative Example 2, and TDDB calculated | required by actual measurement.

Hereinafter, the present invention will be described in detail as an example of an embodiment with reference to the drawings, but the present invention is not limited thereto.
FIG. 1 is a flowchart showing an example of an embodiment of the dielectric breakdown simulation method of the present invention. FIG. 2 is an explanatory diagram showing an example of arrangement of defects incorporated in advance in the dielectric breakdown simulation method of the present invention.

First, in the present invention, the dielectric breakdown lifetime of, for example, the MOS structure 10 having the insulating film 12 and the metal film 11 on the silicon wafer 13 as shown in FIG. 1A is obtained by the following simulation of the present invention.
The thickness and the like of the insulating film 12 of the MOS structure 10 can be set as appropriate according to the evaluation target. For example, in the method of the present invention, a simulation incorporating the influence of defects on the surface of the silicon wafer 13 is performed. Therefore, even if the insulating film 12 has a thickness of 10 nm or less, a highly accurate simulation can be performed.

  In the simulation method of the present invention, a MOS structure 10 'as shown in FIG. The assumed MOS structure 10 ′ includes an insulating film 12, an interface 14 between the insulating film 12 and the metal film 11, and an interface 15 between the insulating film 12 and the silicon wafer 13.

Then, as shown in FIG. 1C, the defect 16 is previously incorporated in the MOS structure 10 ′.
At this time, as shown in FIG. 1C and FIG. 2A, the defect 16 is incorporated into the interface 14 of the insulating film 12 with the metal film 11 and the interface 15 of the insulating film 12 with the silicon wafer 13 or FIG. As shown in FIG. 2B, the defect 16 is incorporated in the insulating film 12, or as shown in FIG. 2C, the defect 16 is incorporated in the interfaces 14, 15 and the insulating film 12.

It is preferable that the size, density, or position of the defect to be incorporated is an assumed value that predicts a defect of an actual silicon wafer, an insulating film, a metal electrode, or an interface thereof.
In this setting of the assumed value, for example, the size is assumed to be a Poisson distribution, and the influence of the size can be examined by moving in at a certain density. Then, after determining the size, the simulation is repeated by changing the density.
In this way, in accordance with the actual situation, the assumed value predicting the defect type existing in the interface of the insulating film of the actual MOS structure, in the insulating film, the silicon wafer surface, etc. is determined and incorporated, and obtained by simulation. The value and the measured value can be compared with higher accuracy, and accurate defect evaluation can be performed.

For example, as shown in FIGS. 1C and 2A, by incorporating defects at equal intervals in the interfaces 14 and 15, the roughness of the silicon wafer surface in an actual device can be reproduced, and the influence of the roughness Can be simulated.
Also, as shown in FIG. 2B, when defects are incorporated in the insulating film, for example, the defect density in the insulating film can be assumed and incorporated. Also, in this case, defects, traps, etc. existing in the actual insulating film can be reproduced by arranging defects on the interface 15 side with the silicon wafer 13.

Also, the size of the defect to be incorporated may be two or more, and can be determined according to the actual device.
The size and arrangement of defects to be incorporated are preferably set statistically based on a Poisson distribution, for example, according to actual defects. However, the size and coordinate position can be arbitrarily designated and arranged.

Then, the film thickness, gate length, etc. of the insulating film 12 are set, the dielectric breakdown of the insulating film 12 is regarded as a stochastic process, and defects 17 are randomly generated in the insulating film 12 (FIG. 1D). A simulation is performed in which the insulating film breaks when 16 and 17 are connected from the interface 15 with the silicon wafer 13 of the insulating film 12 to the interface 14 with the metal electrode 11 (FIG. 1E).
The dielectric breakdown lifetime of the MOS structure 10 can be obtained by using the number of trials until the dielectric breakdown (the number of times the defect 17 is generated by random numbers) as the time until the dielectric breakdown.

Note that when the number of trials is converted into the time until dielectric breakdown, for example, a converted value can be obtained from a comparison with an actually measured value when there is no defect on the surface of the silicon wafer 13 or the insulating film 12. However, if you want to evaluate the influence of defects such as silicon wafer surface on dielectric breakdown, a strict conversion value is not always necessary, and it is possible to have a sufficient discussion even in relative data comparison using any conversion value. .
In addition, by repeating the simulation up to the breakdown for a predetermined number of MOS structures formed on an actual silicon wafer (for example, 100 times or more), a Weibull plot obtained by TDDB measurement of the actual MOS structure is constructed. can do.

In the simulation method of the present invention, it is preferable to use an S-PLUS function that is closer to the image of the actual defect than the method of dividing with a mesh like the Monte Carlo method.
The insulating film 12 that can be simulated by the present invention is not limited to a silicon oxide film, but may be a silicon oxynitride film, a composite film of a silicon oxide film and a silicon oxynitride film, a refractory metal oxide film, or a silicate film. . Depending on the type of the insulating film 12, the size of a defect generated in a simulation or the size, position, etc. of a defect to be incorporated in advance can be set as appropriate.

  With the simulation method of the present invention based on the percolation model as described above, the surface defects on the surface of the actual silicon wafer, the influence of the quality state such as microroughness that could not be captured in the conventional dielectric breakdown model, and further, in the insulating film These defects can be easily incorporated and simulated, and the dielectric breakdown life can be obtained with high accuracy. Thereby, based on the measured value of TDDB such as a silicon oxide film formed on the actual silicon wafer surface, the quality evaluation of the MOS structure and the silicon wafer surface can be easily performed with high accuracy.

As a method for evaluating the quality of a silicon wafer surface using the simulation method of the present invention, first, measured data of TDDB of a plurality of MOS capacitors produced by forming an insulating film and a metal electrode on a silicon wafer is measured. . On the other hand, in the dielectric breakdown lifetime simulation method of the present invention, the same conditions (insulating film thickness, gate length, etc.) as those of the actually measured MOS capacitor are set, and TDDB indicating the dielectric breakdown lifetime of the insulating film is obtained.
Then, the surface defect of the silicon wafer is evaluated based on the set value of the defect previously incorporated in the simulation of the present invention by comparing the TDDB obtained by the simulation with the measured data of the TDDB.

  Specifically, for example, a defect to be incorporated in advance in the simulation is set to 0, and a simulation TDDB in the case where there is no defect on the silicon wafer surface is obtained to construct a Weibull plot. On the other hand, a simulation is performed with a structure in which defects of an assumed value predicted based on actual defects on the actual silicon wafer surface and surface roughness are incorporated in advance, and a Weibull plot is constructed by obtaining a simulation TDDB in which the defects are incorporated. . Then, a Weibull plot of measured data of TDDB can be constructed and relatively evaluated by comparison with the two Weibull plots of the simulation. If the Weibull plot of the measured data is closer to the Weibull plot of the simulation TDDB in which the defect is 0 than the Weibull plot of the simulation TDDB incorporating the predicted defect, there are fewer defects than the predicted assumption and the surface is good. It can be evaluated that there is.

EXAMPLES Hereinafter, although an Example and a comparative example are shown and this invention is demonstrated more concretely, this invention is not limited to these.
(Example 1, Comparative Example 1)
In a MOS structure in which a silicon wafer is used as the material and the oxide film thickness is set to 5 nm and the gate length is set to 2 mm, the size of defects that are randomly generated in the oxide film at random with time is assumed to be 0.5 nm. Then, the set defect is randomly generated by the software produced in the S-PLUS language (FIG. 1 (d)), and when the defect is connected between the electrode / wafer (FIG. 1 (e)), the dielectric breakdown occurs. And the number of trials up to this time was calculated as the time until failure (lifetime). This simulation was performed 100 times to prepare a Weibull plot.

  The number of simulations is not limited, but considering the relationship with the actual measurement, it is better to perform the simulation more than 100 times. Further, the size of the defect generated randomly is not limited to 5 nm, but as a general size, for example, Non-Patent Document 4 also describes that it is about 1 nm.

Here, in Example 1, before a defect was generated with a random number as described above, a defect was previously incorporated at both the wafer / oxide film and oxide film / electrode interfaces. At this time, as shown in FIG. 2A, defects are set at both interfaces in advance so that the period is about 2 nm. This represents roughness on the surface of the silicon wafer.
On the other hand, in Comparative Example 1, simulation was performed without incorporating defects in advance.

  FIG. 3A shows a graph in which the horizontal axis represents the number of trials until a defect is connected in the simulation of Example 1 and Comparative Example 1, and the vertical axis represents 100 times of data.

  For comparison, the actual measurement data is shown in FIG. This is a result of evaluating a sample having roughness and a sample having no roughness (very small) with a gate oxide film of 5 nm.

From FIG. 3A, it can be seen that the time until dielectric breakdown is shorter in Example 1 than in the conventional method. Also, from FIG. 3B, in the measured data, the data without roughness has a long time to breakdown (charge amount Qbd), and the data with roughness has a short time to breakdown (Qbd). That is, the measured data corresponds to Comparative Example 1 in which the roughness is not considered and Example 1 in which the roughness is considered.
As described above, the measured data and the simulation are in good agreement with respect to the presence / absence of the interface roughness, and the present invention makes it possible to perform a highly accurate simulation that incorporates the influence of the interface roughness.

(Example 2, comparative example 2)
In a MOS structure in which a silicon wafer is used as the material and the oxide film thickness is set to 15 nm and the gate length is set to 2 mm, the size of defects generated randomly and over time in the oxide film is assumed to be 0.5 nm. , It is assumed that the set defects are generated randomly by software created in the S-PLUS language, and the dielectric breakdown occurs when the defects are connected between the electrode / wafer. The number of trials up to this time Life). This simulation was performed 100 times to prepare a Weibull plot.

Here, in Example 2, before a defect was generated with a random number as described above, the defect was previously incorporated in the oxide film. At this time, as shown in FIG. 2B, defects having a size of 2 nm were previously arranged in the oxide film with a density of 0.001 / nm 2 using random numbers. This represents a defect in the oxide film.
On the other hand, in Comparative Example 2, simulation was performed without incorporating defects in advance.

  FIG. 4A shows a graph in which the number of trials until a defect is connected in the simulation of Example 2 and Comparative Example 2 is plotted on the horizontal axis in arbitrary time units, and the vertical axis represents 100 times of data.

  For comparison, actual measurement data is shown in FIG. This is a result of evaluation of a sample having defects in the film and a sample having no (very few) defects in the film at a gate oxide film of 15 nm.

FIG. 4A shows that the time until the dielectric breakdown in the simulation is shorter in Example 2 than in Comparative Example 2 of the conventional method. Also, from FIG. 4B, in the measured data, in the case of no defect in the film, the time to breakdown (charge amount Qbd) is long, and in the case of the defect in the film, the time to breakdown (Qbd) is short. Yes. That is, the measured data corresponds to Comparative Example 2 in which no defects in the film are considered and Example 2 in which defects in the film are considered.
As described above, the measured data and the simulation are in good agreement with respect to the presence / absence of defects in the oxide film, and the present invention makes it possible to perform a highly accurate simulation that incorporates the effects of defects in the film.

  In the above examples and comparative examples, the breakdown life was expressed by the Weibull plot, but there is no problem even if statistical processing is performed by the cumulative failure rate of the breakdown instead of the Weibull plot of the breakdown. It should be chosen by the party.

  The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.

10, 10 '... MOS structure, 11 ... Metal electrode, 12 ... Insulating film,
13 ... Silicon wafer, 14 ... Interface between insulating film and metal electrode,
15 ... Interface between insulating film and silicon wafer 16, 16 ... Defect,

Claims (4)

  1. In a structure having a silicon wafer, an insulating film on the silicon wafer, and a metal electrode on the insulating film, the dielectric breakdown of the insulating film is regarded as a stochastic process, and defects are generated in the insulating film with random numbers. The dielectric breakdown lifetime of the insulating film is obtained by computer simulation in which the insulating film breaks down when the generated defect is connected from the interface with the silicon wafer to the interface with the metal electrode. A simulation method comprising:
    In the structure to be simulated, defects are incorporated in advance in the interface between the silicon wafer and the insulating film and the interface between the insulating film and the metal electrode and / or in the insulating film, and the size and density of the defects incorporated in advance. Or, the position is assumed to be a predicted value of defects in an actual silicon wafer, insulating film, metal electrode or their interface, and in the structure incorporating the defects, defects are generated in the insulating film by random numbers and the insulation is performed. A dielectric breakdown lifetime simulation method characterized by obtaining a dielectric breakdown lifetime of a film.
  2. 2. The dielectric breakdown lifetime simulation method according to claim 1 , wherein the size or position of the defect to be incorporated in advance is set based on a Poisson distribution.
  3. Dielectric breakdown lifetime simulation method according to claim 1 or claim 2, characterized in that the thickness of the insulating film to simulate the dielectric breakdown lifetime, and 10nm or less.
  4. A method for evaluating the quality of a silicon wafer surface,
    Measure actual data of TDDB of a plurality of MOS capacitors produced by forming an insulating film and a metal electrode on the silicon wafer,
    In the dielectric breakdown lifetime simulation method according to any one of claims 1 to 3, the same conditions as the MOS capacitor are set, and TDDB indicating the dielectric breakdown lifetime of the insulating film is obtained.
    The silicon wafer surface characterized in that the surface defect of the silicon wafer is evaluated based on the set value of the defect previously incorporated in the simulation by comparing the TDDB obtained by the simulation with the measured data of the TDDB. Quality evaluation method.
JP2010249919A 2010-11-08 2010-11-08 Dielectric breakdown lifetime simulation method and silicon wafer surface quality evaluation method Active JP5636886B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2010249919A JP5636886B2 (en) 2010-11-08 2010-11-08 Dielectric breakdown lifetime simulation method and silicon wafer surface quality evaluation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010249919A JP5636886B2 (en) 2010-11-08 2010-11-08 Dielectric breakdown lifetime simulation method and silicon wafer surface quality evaluation method

Publications (2)

Publication Number Publication Date
JP2012104561A JP2012104561A (en) 2012-05-31
JP5636886B2 true JP5636886B2 (en) 2014-12-10

Family

ID=46394648

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2010249919A Active JP5636886B2 (en) 2010-11-08 2010-11-08 Dielectric breakdown lifetime simulation method and silicon wafer surface quality evaluation method

Country Status (1)

Country Link
JP (1) JP5636886B2 (en)

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05267421A (en) * 1992-03-17 1993-10-15 Hitachi Ltd Semiconductor device simulation method
JP3333325B2 (en) * 1993-08-26 2002-10-15 株式会社東芝 Semiconductor device, semiconductor device simulation method, and semiconductor device simulator
JP2001267260A (en) * 2000-03-22 2001-09-28 Oki Electric Ind Co Ltd Method for modeling semiconductor
JP2005019885A (en) * 2003-06-27 2005-01-20 Semiconductor Leading Edge Technologies Inc Semiconductor device and manufacturing method therefor
JP4970979B2 (en) * 2007-02-20 2012-07-11 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2010062346A (en) * 2008-09-04 2010-03-18 Covalent Materials Corp Dielectric breakdown life simulation method, and silicon wafer surface quality evaluation method and program

Also Published As

Publication number Publication date
JP2012104561A (en) 2012-05-31

Similar Documents

Publication Publication Date Title
Lombardo et al. Dielectric breakdown mechanisms in gate oxides
US8741713B2 (en) Reliable physical unclonable function for device authentication
Green et al. Ultrathin (< 4 nm) SiO 2 and Si–O–N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits
Hu Gate oxide scaling limits and projection
Hu et al. A unified gate oxide reliability model
Nigam et al. Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks
US7921401B2 (en) Stress analysis method, wiring structure design method, program, and semiconductor device production method
John et al. Porous silicon: theoretical studies
Chen et al. Addressing Cu/low-$ k $ dielectric TDDB-reliability challenges for advanced CMOS technologies
Wirth et al. Statistical model for MOSFET bias temperature instability component due to charge trapping
Grasser et al. NBTI in nanoscale MOSFETs—The ultimate modeling benchmark
Wu et al. Power-law voltage acceleration: A key element for ultra-thin gate oxide reliability
US8594827B2 (en) Method of controlling semiconductor device fabrication
Wu et al. Experimental evidence of T/sub BD/power-law for voltage dependence of oxide breakdown in ultrathin gate oxides
TWI310971B (en) Method and apparatus for predicting device electrical parameters during fabrication
KR101442385B1 (en) Qualitative fault detection and classification system for tool condition monitoring and associated methods
US6873932B1 (en) Method and apparatus for predicting semiconductor device lifetime
Pobegen et al. On the distribution of NBTI time constants on a long, temperature-accelerated time scale
CN101702005B (en) Time dependent dielectric breakdown parallel testing circuit
US9620338B2 (en) System, method, and program for predicting processing shape by plasma process
JP6204036B2 (en) Evaluation method of oxide semiconductor thin film and quality control method of oxide semiconductor thin film
Padovani et al. A microscopic mechanism of dielectric breakdown in SiO2 films: An insight from multi-scale modeling
US7579859B2 (en) Method for determining time dependent dielectric breakdown
De Messemaeker et al. Impact of post-plating anneal and through-silicon via dimensions on Cu pumping
Chen et al. Cu/low-k dielectric TDDB reliability issues for advanced CMOS technologies

Legal Events

Date Code Title Description
A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20121219

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20140401

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140513

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20140924

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20141007

R150 Certificate of patent or registration of utility model

Ref document number: 5636886

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250